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ARM: enable XScale/iWMMXT in linux-user mode
[qemu/ar7.git] / target-arm / helper.c
blob94aef393e2c881455d8eab2fe9e260370799daa9
1 #include <stdio.h>
2 #include <stdlib.h>
3 #include <string.h>
4
5 #include "cpu.h"
6 #include "exec-all.h"
7 #include "gdbstub.h"
8 #include "helpers.h"
9 #include "qemu-common.h"
10 #include "host-utils.h"
11 #if !defined(CONFIG_USER_ONLY)
12 #include "hw/loader.h"
13 #endif
14
15 static uint32_t cortexa9_cp15_c0_c1[8] =
16 { 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
17
18 static uint32_t cortexa9_cp15_c0_c2[8] =
19 { 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
20
21 static uint32_t cortexa8_cp15_c0_c1[8] =
22 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
23
24 static uint32_t cortexa8_cp15_c0_c2[8] =
25 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
26
27 static uint32_t mpcore_cp15_c0_c1[8] =
28 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
29
30 static uint32_t mpcore_cp15_c0_c2[8] =
31 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
32
33 static uint32_t arm1136_cp15_c0_c1[8] =
34 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
35
36 static uint32_t arm1136_cp15_c0_c2[8] =
37 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
38
39 static uint32_t cpu_arm_find_by_name(const char *name);
40
41 static inline void set_feature(CPUARMState *env, int feature)
42 {
43 env->features |= 1u << feature;
44 }
45
46 static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
47 {
48 env->cp15.c0_cpuid = id;
49 switch (id) {
50 case ARM_CPUID_ARM926:
51 set_feature(env, ARM_FEATURE_VFP);
52 env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
53 env->cp15.c0_cachetype = 0x1dd20d2;
54 env->cp15.c1_sys = 0x00090078;
55 break;
56 case ARM_CPUID_ARM946:
57 set_feature(env, ARM_FEATURE_MPU);
58 env->cp15.c0_cachetype = 0x0f004006;
59 env->cp15.c1_sys = 0x00000078;
60 break;
61 case ARM_CPUID_ARM1026:
62 set_feature(env, ARM_FEATURE_VFP);
63 set_feature(env, ARM_FEATURE_AUXCR);
64 env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
65 env->cp15.c0_cachetype = 0x1dd20d2;
66 env->cp15.c1_sys = 0x00090078;
67 break;
68 case ARM_CPUID_ARM1136_R2:
69 case ARM_CPUID_ARM1136:
70 set_feature(env, ARM_FEATURE_V6);
71 set_feature(env, ARM_FEATURE_VFP);
72 set_feature(env, ARM_FEATURE_AUXCR);
73 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
74 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
75 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
76 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
77 memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
78 env->cp15.c0_cachetype = 0x1dd20d2;
79 break;
80 case ARM_CPUID_ARM11MPCORE:
81 set_feature(env, ARM_FEATURE_V6);
82 set_feature(env, ARM_FEATURE_V6K);
83 set_feature(env, ARM_FEATURE_VFP);
84 set_feature(env, ARM_FEATURE_AUXCR);
85 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
86 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
87 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
88 memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
89 memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
90 env->cp15.c0_cachetype = 0x1dd20d2;
91 break;
92 case ARM_CPUID_CORTEXA8:
93 set_feature(env, ARM_FEATURE_V6);
94 set_feature(env, ARM_FEATURE_V6K);
95 set_feature(env, ARM_FEATURE_V7);
96 set_feature(env, ARM_FEATURE_AUXCR);
97 set_feature(env, ARM_FEATURE_THUMB2);
98 set_feature(env, ARM_FEATURE_VFP);
99 set_feature(env, ARM_FEATURE_VFP3);
100 set_feature(env, ARM_FEATURE_NEON);
101 set_feature(env, ARM_FEATURE_THUMB2EE);
102 env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
103 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
104 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
105 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
106 memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
107 env->cp15.c0_cachetype = 0x82048004;
108 env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
109 env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
110 env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
111 env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
112 break;
113 case ARM_CPUID_CORTEXA9:
114 set_feature(env, ARM_FEATURE_V6);
115 set_feature(env, ARM_FEATURE_V6K);
116 set_feature(env, ARM_FEATURE_V7);
117 set_feature(env, ARM_FEATURE_AUXCR);
118 set_feature(env, ARM_FEATURE_THUMB2);
119 set_feature(env, ARM_FEATURE_VFP);
120 set_feature(env, ARM_FEATURE_VFP3);
121 set_feature(env, ARM_FEATURE_VFP_FP16);
122 set_feature(env, ARM_FEATURE_NEON);
123 set_feature(env, ARM_FEATURE_THUMB2EE);
124 env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
125 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
126 env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
127 memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
128 memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
129 env->cp15.c0_cachetype = 0x80038003;
130 env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
131 env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
132 env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
133 break;
134 case ARM_CPUID_CORTEXM3:
135 set_feature(env, ARM_FEATURE_V6);
136 set_feature(env, ARM_FEATURE_THUMB2);
137 set_feature(env, ARM_FEATURE_V7);
138 set_feature(env, ARM_FEATURE_M);
139 set_feature(env, ARM_FEATURE_DIV);
140 break;
141 case ARM_CPUID_ANY: /* For userspace emulation. */
142 set_feature(env, ARM_FEATURE_V6);
143 set_feature(env, ARM_FEATURE_V6K);
144 set_feature(env, ARM_FEATURE_V7);
145 set_feature(env, ARM_FEATURE_THUMB2);
146 set_feature(env, ARM_FEATURE_VFP);
147 set_feature(env, ARM_FEATURE_VFP3);
148 set_feature(env, ARM_FEATURE_VFP_FP16);
149 set_feature(env, ARM_FEATURE_NEON);
150 set_feature(env, ARM_FEATURE_THUMB2EE);
151 set_feature(env, ARM_FEATURE_DIV);
152 break;
153 case ARM_CPUID_TI915T:
154 case ARM_CPUID_TI925T:
155 set_feature(env, ARM_FEATURE_OMAPCP);
156 env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
157 env->cp15.c0_cachetype = 0x5109149;
158 env->cp15.c1_sys = 0x00000070;
159 env->cp15.c15_i_max = 0x000;
160 env->cp15.c15_i_min = 0xff0;
161 break;
162 case ARM_CPUID_PXA250:
163 case ARM_CPUID_PXA255:
164 case ARM_CPUID_PXA260:
165 case ARM_CPUID_PXA261:
166 case ARM_CPUID_PXA262:
167 set_feature(env, ARM_FEATURE_XSCALE);
168 /* JTAG_ID is ((id << 28) | 0x09265013) */
169 env->cp15.c0_cachetype = 0xd172172;
170 env->cp15.c1_sys = 0x00000078;
171 break;
172 case ARM_CPUID_PXA270_A0:
173 case ARM_CPUID_PXA270_A1:
174 case ARM_CPUID_PXA270_B0:
175 case ARM_CPUID_PXA270_B1:
176 case ARM_CPUID_PXA270_C0:
177 case ARM_CPUID_PXA270_C5:
178 set_feature(env, ARM_FEATURE_XSCALE);
179 /* JTAG_ID is ((id << 28) | 0x09265013) */
180 set_feature(env, ARM_FEATURE_IWMMXT);
181 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
182 env->cp15.c0_cachetype = 0xd172172;
183 env->cp15.c1_sys = 0x00000078;
184 break;
185 default:
186 cpu_abort(env, "Bad CPU ID: %x\n", id);
187 break;
188 }
189 }
190
191 void cpu_reset(CPUARMState *env)
192 {
193 uint32_t id;
194
195 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
196 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
197 log_cpu_state(env, 0);
198 }
199
200 id = env->cp15.c0_cpuid;
201 memset(env, 0, offsetof(CPUARMState, breakpoints));
202 if (id)
203 cpu_reset_model_id(env, id);
204 #if defined (CONFIG_USER_ONLY)
205 env->uncached_cpsr = ARM_CPU_MODE_USR;
206 /* For user mode we must enable access to coprocessors */
207 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
208 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
209 env->cp15.c15_cpar = 3;
210 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
211 env->cp15.c15_cpar = 1;
212 }
213 #else
214 /* SVC mode with interrupts disabled. */
215 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
216 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
217 clear at reset. Initial SP and PC are loaded from ROM. */
218 if (IS_M(env)) {
219 uint32_t pc;
220 uint8_t *rom;
221 env->uncached_cpsr &= ~CPSR_I;
222 rom = rom_ptr(0);
223 if (rom) {
224 /* We should really use ldl_phys here, in case the guest
225 modified flash and reset itself. However images
226 loaded via -kenrel have not been copied yet, so load the
227 values directly from there. */
228 env->regs[13] = ldl_p(rom);
229 pc = ldl_p(rom + 4);
230 env->thumb = pc & 1;
231 env->regs[15] = pc & ~1;
232 }
233 }
234 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
235 env->cp15.c2_base_mask = 0xffffc000u;
236 #endif
237 tlb_flush(env, 1);
238 }
239
240 static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
241 {
242 int nregs;
243
244 /* VFP data registers are always little-endian. */
245 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
246 if (reg < nregs) {
247 stfq_le_p(buf, env->vfp.regs[reg]);
248 return 8;
249 }
250 if (arm_feature(env, ARM_FEATURE_NEON)) {
251 /* Aliases for Q regs. */
252 nregs += 16;
253 if (reg < nregs) {
254 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
255 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
256 return 16;
257 }
258 }
259 switch (reg - nregs) {
260 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
261 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
262 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
263 }
264 return 0;
265 }
266
267 static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
268 {
269 int nregs;
270
271 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
272 if (reg < nregs) {
273 env->vfp.regs[reg] = ldfq_le_p(buf);
274 return 8;
275 }
276 if (arm_feature(env, ARM_FEATURE_NEON)) {
277 nregs += 16;
278 if (reg < nregs) {
279 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
280 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
281 return 16;
282 }
283 }
284 switch (reg - nregs) {
285 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
286 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
287 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
288 }
289 return 0;
290 }
291
292 CPUARMState *cpu_arm_init(const char *cpu_model)
293 {
294 CPUARMState *env;
295 uint32_t id;
296 static int inited = 0;
297
298 id = cpu_arm_find_by_name(cpu_model);
299 if (id == 0)
300 return NULL;
301 env = qemu_mallocz(sizeof(CPUARMState));
302 cpu_exec_init(env);
303 if (!inited) {
304 inited = 1;
305 arm_translate_init();
306 }
307
308 env->cpu_model_str = cpu_model;
309 env->cp15.c0_cpuid = id;
310 cpu_reset(env);
311 if (arm_feature(env, ARM_FEATURE_NEON)) {
312 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
313 51, "arm-neon.xml", 0);
314 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
315 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
316 35, "arm-vfp3.xml", 0);
317 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
318 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
319 19, "arm-vfp.xml", 0);
320 }
321 qemu_init_vcpu(env);
322 return env;
323 }
324
325 struct arm_cpu_t {
326 uint32_t id;
327 const char *name;
328 };
329
330 static const struct arm_cpu_t arm_cpu_names[] = {
331 { ARM_CPUID_ARM926, "arm926"},
332 { ARM_CPUID_ARM946, "arm946"},
333 { ARM_CPUID_ARM1026, "arm1026"},
334 { ARM_CPUID_ARM1136, "arm1136"},
335 { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
336 { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
337 { ARM_CPUID_CORTEXM3, "cortex-m3"},
338 { ARM_CPUID_CORTEXA8, "cortex-a8"},
339 { ARM_CPUID_CORTEXA9, "cortex-a9"},
340 { ARM_CPUID_TI925T, "ti925t" },
341 { ARM_CPUID_PXA250, "pxa250" },
342 { ARM_CPUID_PXA255, "pxa255" },
343 { ARM_CPUID_PXA260, "pxa260" },
344 { ARM_CPUID_PXA261, "pxa261" },
345 { ARM_CPUID_PXA262, "pxa262" },
346 { ARM_CPUID_PXA270, "pxa270" },
347 { ARM_CPUID_PXA270_A0, "pxa270-a0" },
348 { ARM_CPUID_PXA270_A1, "pxa270-a1" },
349 { ARM_CPUID_PXA270_B0, "pxa270-b0" },
350 { ARM_CPUID_PXA270_B1, "pxa270-b1" },
351 { ARM_CPUID_PXA270_C0, "pxa270-c0" },
352 { ARM_CPUID_PXA270_C5, "pxa270-c5" },
353 { ARM_CPUID_ANY, "any"},
354 { 0, NULL}
355 };
356
357 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
358 {
359 int i;
360
361 (*cpu_fprintf)(f, "Available CPUs:\n");
362 for (i = 0; arm_cpu_names[i].name; i++) {
363 (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
364 }
365 }
366
367 /* return 0 if not found */
368 static uint32_t cpu_arm_find_by_name(const char *name)
369 {
370 int i;
371 uint32_t id;
372
373 id = 0;
374 for (i = 0; arm_cpu_names[i].name; i++) {
375 if (strcmp(name, arm_cpu_names[i].name) == 0) {
376 id = arm_cpu_names[i].id;
377 break;
378 }
379 }
380 return id;
381 }
382
383 void cpu_arm_close(CPUARMState *env)
384 {
385 free(env);
386 }
387
388 uint32_t cpsr_read(CPUARMState *env)
389 {
390 int ZF;
391 ZF = (env->ZF == 0);
392 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
393 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
394 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
395 | ((env->condexec_bits & 0xfc) << 8)
396 | (env->GE << 16);
397 }
398
399 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
400 {
401 if (mask & CPSR_NZCV) {
402 env->ZF = (~val) & CPSR_Z;
403 env->NF = val;
404 env->CF = (val >> 29) & 1;
405 env->VF = (val << 3) & 0x80000000;
406 }
407 if (mask & CPSR_Q)
408 env->QF = ((val & CPSR_Q) != 0);
409 if (mask & CPSR_T)
410 env->thumb = ((val & CPSR_T) != 0);
411 if (mask & CPSR_IT_0_1) {
412 env->condexec_bits &= ~3;
413 env->condexec_bits |= (val >> 25) & 3;
414 }
415 if (mask & CPSR_IT_2_7) {
416 env->condexec_bits &= 3;
417 env->condexec_bits |= (val >> 8) & 0xfc;
418 }
419 if (mask & CPSR_GE) {
420 env->GE = (val >> 16) & 0xf;
421 }
422
423 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
424 switch_mode(env, val & CPSR_M);
425 }
426 mask &= ~CACHED_CPSR_BITS;
427 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
428 }
429
430 /* Sign/zero extend */
431 uint32_t HELPER(sxtb16)(uint32_t x)
432 {
433 uint32_t res;
434 res = (uint16_t)(int8_t)x;
435 res |= (uint32_t)(int8_t)(x >> 16) << 16;
436 return res;
437 }
438
439 uint32_t HELPER(uxtb16)(uint32_t x)
440 {
441 uint32_t res;
442 res = (uint16_t)(uint8_t)x;
443 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
444 return res;
445 }
446
447 uint32_t HELPER(clz)(uint32_t x)
448 {
449 return clz32(x);
450 }
451
452 int32_t HELPER(sdiv)(int32_t num, int32_t den)
453 {
454 if (den == 0)
455 return 0;
456 if (num == INT_MIN && den == -1)
457 return INT_MIN;
458 return num / den;
459 }
460
461 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
462 {
463 if (den == 0)
464 return 0;
465 return num / den;
466 }
467
468 uint32_t HELPER(rbit)(uint32_t x)
469 {
470 x = ((x & 0xff000000) >> 24)
471 | ((x & 0x00ff0000) >> 8)
472 | ((x & 0x0000ff00) << 8)
473 | ((x & 0x000000ff) << 24);
474 x = ((x & 0xf0f0f0f0) >> 4)
475 | ((x & 0x0f0f0f0f) << 4);
476 x = ((x & 0x88888888) >> 3)
477 | ((x & 0x44444444) >> 1)
478 | ((x & 0x22222222) << 1)
479 | ((x & 0x11111111) << 3);
480 return x;
481 }
482
483 uint32_t HELPER(abs)(uint32_t x)
484 {
485 return ((int32_t)x < 0) ? -x : x;
486 }
487
488 #if defined(CONFIG_USER_ONLY)
489
490 void do_interrupt (CPUState *env)
491 {
492 env->exception_index = -1;
493 }
494
495 int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
496 int mmu_idx, int is_softmmu)
497 {
498 if (rw == 2) {
499 env->exception_index = EXCP_PREFETCH_ABORT;
500 env->cp15.c6_insn = address;
501 } else {
502 env->exception_index = EXCP_DATA_ABORT;
503 env->cp15.c6_data = address;
504 }
505 return 1;
506 }
507
508 /* These should probably raise undefined insn exceptions. */
509 void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
510 {
511 int op1 = (insn >> 8) & 0xf;
512 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
513 return;
514 }
515
516 uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
517 {
518 int op1 = (insn >> 8) & 0xf;
519 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
520 return 0;
521 }
522
523 void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
524 {
525 cpu_abort(env, "cp15 insn %08x\n", insn);
526 }
527
528 uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
529 {
530 cpu_abort(env, "cp15 insn %08x\n", insn);
531 }
532
533 /* These should probably raise undefined insn exceptions. */
534 void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
535 {
536 cpu_abort(env, "v7m_mrs %d\n", reg);
537 }
538
539 uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
540 {
541 cpu_abort(env, "v7m_mrs %d\n", reg);
542 return 0;
543 }
544
545 void switch_mode(CPUState *env, int mode)
546 {
547 if (mode != ARM_CPU_MODE_USR)
548 cpu_abort(env, "Tried to switch out of user mode\n");
549 }
550
551 void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
552 {
553 cpu_abort(env, "banked r13 write\n");
554 }
555
556 uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
557 {
558 cpu_abort(env, "banked r13 read\n");
559 return 0;
560 }
561
562 #else
563
564 extern int semihosting_enabled;
565
566 /* Map CPU modes onto saved register banks. */
567 static inline int bank_number (int mode)
568 {
569 switch (mode) {
570 case ARM_CPU_MODE_USR:
571 case ARM_CPU_MODE_SYS:
572 return 0;
573 case ARM_CPU_MODE_SVC:
574 return 1;
575 case ARM_CPU_MODE_ABT:
576 return 2;
577 case ARM_CPU_MODE_UND:
578 return 3;
579 case ARM_CPU_MODE_IRQ:
580 return 4;
581 case ARM_CPU_MODE_FIQ:
582 return 5;
583 }
584 cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
585 return -1;
586 }
587
588 void switch_mode(CPUState *env, int mode)
589 {
590 int old_mode;
591 int i;
592
593 old_mode = env->uncached_cpsr & CPSR_M;
594 if (mode == old_mode)
595 return;
596
597 if (old_mode == ARM_CPU_MODE_FIQ) {
598 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
599 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
600 } else if (mode == ARM_CPU_MODE_FIQ) {
601 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
602 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
603 }
604
605 i = bank_number(old_mode);
606 env->banked_r13[i] = env->regs[13];
607 env->banked_r14[i] = env->regs[14];
608 env->banked_spsr[i] = env->spsr;
609
610 i = bank_number(mode);
611 env->regs[13] = env->banked_r13[i];
612 env->regs[14] = env->banked_r14[i];
613 env->spsr = env->banked_spsr[i];
614 }
615
616 static void v7m_push(CPUARMState *env, uint32_t val)
617 {
618 env->regs[13] -= 4;
619 stl_phys(env->regs[13], val);
620 }
621
622 static uint32_t v7m_pop(CPUARMState *env)
623 {
624 uint32_t val;
625 val = ldl_phys(env->regs[13]);
626 env->regs[13] += 4;
627 return val;
628 }
629
630 /* Switch to V7M main or process stack pointer. */
631 static void switch_v7m_sp(CPUARMState *env, int process)
632 {
633 uint32_t tmp;
634 if (env->v7m.current_sp != process) {
635 tmp = env->v7m.other_sp;
636 env->v7m.other_sp = env->regs[13];
637 env->regs[13] = tmp;
638 env->v7m.current_sp = process;
639 }
640 }
641
642 static void do_v7m_exception_exit(CPUARMState *env)
643 {
644 uint32_t type;
645 uint32_t xpsr;
646
647 type = env->regs[15];
648 if (env->v7m.exception != 0)
649 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
650
651 /* Switch to the target stack. */
652 switch_v7m_sp(env, (type & 4) != 0);
653 /* Pop registers. */
654 env->regs[0] = v7m_pop(env);
655 env->regs[1] = v7m_pop(env);
656 env->regs[2] = v7m_pop(env);
657 env->regs[3] = v7m_pop(env);
658 env->regs[12] = v7m_pop(env);
659 env->regs[14] = v7m_pop(env);
660 env->regs[15] = v7m_pop(env);
661 xpsr = v7m_pop(env);
662 xpsr_write(env, xpsr, 0xfffffdff);
663 /* Undo stack alignment. */
664 if (xpsr & 0x200)
665 env->regs[13] |= 4;
666 /* ??? The exception return type specifies Thread/Handler mode. However
667 this is also implied by the xPSR value. Not sure what to do
668 if there is a mismatch. */
669 /* ??? Likewise for mismatches between the CONTROL register and the stack
670 pointer. */
671 }
672
673 static void do_interrupt_v7m(CPUARMState *env)
674 {
675 uint32_t xpsr = xpsr_read(env);
676 uint32_t lr;
677 uint32_t addr;
678
679 lr = 0xfffffff1;
680 if (env->v7m.current_sp)
681 lr |= 4;
682 if (env->v7m.exception == 0)
683 lr |= 8;
684
685 /* For exceptions we just mark as pending on the NVIC, and let that
686 handle it. */
687 /* TODO: Need to escalate if the current priority is higher than the
688 one we're raising. */
689 switch (env->exception_index) {
690 case EXCP_UDEF:
691 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
692 return;
693 case EXCP_SWI:
694 env->regs[15] += 2;
695 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
696 return;
697 case EXCP_PREFETCH_ABORT:
698 case EXCP_DATA_ABORT:
699 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
700 return;
701 case EXCP_BKPT:
702 if (semihosting_enabled) {
703 int nr;
704 nr = lduw_code(env->regs[15]) & 0xff;
705 if (nr == 0xab) {
706 env->regs[15] += 2;
707 env->regs[0] = do_arm_semihosting(env);
708 return;
709 }
710 }
711 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
712 return;
713 case EXCP_IRQ:
714 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
715 break;
716 case EXCP_EXCEPTION_EXIT:
717 do_v7m_exception_exit(env);
718 return;
719 default:
720 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
721 return; /* Never happens. Keep compiler happy. */
722 }
723
724 /* Align stack pointer. */
725 /* ??? Should only do this if Configuration Control Register
726 STACKALIGN bit is set. */
727 if (env->regs[13] & 4) {
728 env->regs[13] -= 4;
729 xpsr |= 0x200;
730 }
731 /* Switch to the handler mode. */
732 v7m_push(env, xpsr);
733 v7m_push(env, env->regs[15]);
734 v7m_push(env, env->regs[14]);
735 v7m_push(env, env->regs[12]);
736 v7m_push(env, env->regs[3]);
737 v7m_push(env, env->regs[2]);
738 v7m_push(env, env->regs[1]);
739 v7m_push(env, env->regs[0]);
740 switch_v7m_sp(env, 0);
741 env->uncached_cpsr &= ~CPSR_IT;
742 env->regs[14] = lr;
743 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
744 env->regs[15] = addr & 0xfffffffe;
745 env->thumb = addr & 1;
746 }
747
748 /* Handle a CPU exception. */
749 void do_interrupt(CPUARMState *env)
750 {
751 uint32_t addr;
752 uint32_t mask;
753 int new_mode;
754 uint32_t offset;
755
756 if (IS_M(env)) {
757 do_interrupt_v7m(env);
758 return;
759 }
760 /* TODO: Vectored interrupt controller. */
761 switch (env->exception_index) {
762 case EXCP_UDEF:
763 new_mode = ARM_CPU_MODE_UND;
764 addr = 0x04;
765 mask = CPSR_I;
766 if (env->thumb)
767 offset = 2;
768 else
769 offset = 4;
770 break;
771 case EXCP_SWI:
772 if (semihosting_enabled) {
773 /* Check for semihosting interrupt. */
774 if (env->thumb) {
775 mask = lduw_code(env->regs[15] - 2) & 0xff;
776 } else {
777 mask = ldl_code(env->regs[15] - 4) & 0xffffff;
778 }
779 /* Only intercept calls from privileged modes, to provide some
780 semblance of security. */
781 if (((mask == 0x123456 && !env->thumb)
782 || (mask == 0xab && env->thumb))
783 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
784 env->regs[0] = do_arm_semihosting(env);
785 return;
786 }
787 }
788 new_mode = ARM_CPU_MODE_SVC;
789 addr = 0x08;
790 mask = CPSR_I;
791 /* The PC already points to the next instruction. */
792 offset = 0;
793 break;
794 case EXCP_BKPT:
795 /* See if this is a semihosting syscall. */
796 if (env->thumb && semihosting_enabled) {
797 mask = lduw_code(env->regs[15]) & 0xff;
798 if (mask == 0xab
799 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
800 env->regs[15] += 2;
801 env->regs[0] = do_arm_semihosting(env);
802 return;
803 }
804 }
805 /* Fall through to prefetch abort. */
806 case EXCP_PREFETCH_ABORT:
807 new_mode = ARM_CPU_MODE_ABT;
808 addr = 0x0c;
809 mask = CPSR_A | CPSR_I;
810 offset = 4;
811 break;
812 case EXCP_DATA_ABORT:
813 new_mode = ARM_CPU_MODE_ABT;
814 addr = 0x10;
815 mask = CPSR_A | CPSR_I;
816 offset = 8;
817 break;
818 case EXCP_IRQ:
819 new_mode = ARM_CPU_MODE_IRQ;
820 addr = 0x18;
821 /* Disable IRQ and imprecise data aborts. */
822 mask = CPSR_A | CPSR_I;
823 offset = 4;
824 break;
825 case EXCP_FIQ:
826 new_mode = ARM_CPU_MODE_FIQ;
827 addr = 0x1c;
828 /* Disable FIQ, IRQ and imprecise data aborts. */
829 mask = CPSR_A | CPSR_I | CPSR_F;
830 offset = 4;
831 break;
832 default:
833 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
834 return; /* Never happens. Keep compiler happy. */
835 }
836 /* High vectors. */
837 if (env->cp15.c1_sys & (1 << 13)) {
838 addr += 0xffff0000;
839 }
840 switch_mode (env, new_mode);
841 env->spsr = cpsr_read(env);
842 /* Clear IT bits. */
843 env->condexec_bits = 0;
844 /* Switch to the new mode, and to the correct instruction set. */
845 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
846 env->uncached_cpsr |= mask;
847 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
848 env->regs[14] = env->regs[15] + offset;
849 env->regs[15] = addr;
850 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
851 }
852
853 /* Check section/page access permissions.
854 Returns the page protection flags, or zero if the access is not
855 permitted. */
856 static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
857 int is_user)
858 {
859 int prot_ro;
860
861 if (domain == 3)
862 return PAGE_READ | PAGE_WRITE;
863
864 if (access_type == 1)
865 prot_ro = 0;
866 else
867 prot_ro = PAGE_READ;
868
869 switch (ap) {
870 case 0:
871 if (access_type == 1)
872 return 0;
873 switch ((env->cp15.c1_sys >> 8) & 3) {
874 case 1:
875 return is_user ? 0 : PAGE_READ;
876 case 2:
877 return PAGE_READ;
878 default:
879 return 0;
880 }
881 case 1:
882 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
883 case 2:
884 if (is_user)
885 return prot_ro;
886 else
887 return PAGE_READ | PAGE_WRITE;
888 case 3:
889 return PAGE_READ | PAGE_WRITE;
890 case 4: /* Reserved. */
891 return 0;
892 case 5:
893 return is_user ? 0 : prot_ro;
894 case 6:
895 return prot_ro;
896 case 7:
897 if (!arm_feature (env, ARM_FEATURE_V7))
898 return 0;
899 return prot_ro;
900 default:
901 abort();
902 }
903 }
904
905 static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
906 {
907 uint32_t table;
908
909 if (address & env->cp15.c2_mask)
910 table = env->cp15.c2_base1 & 0xffffc000;
911 else
912 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
913
914 table |= (address >> 18) & 0x3ffc;
915 return table;
916 }
917
918 static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
919 int is_user, uint32_t *phys_ptr, int *prot,
920 target_ulong *page_size)
921 {
922 int code;
923 uint32_t table;
924 uint32_t desc;
925 int type;
926 int ap;
927 int domain;
928 uint32_t phys_addr;
929
930 /* Pagetable walk. */
931 /* Lookup l1 descriptor. */
932 table = get_level1_table_address(env, address);
933 desc = ldl_phys(table);
934 type = (desc & 3);
935 domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
936 if (type == 0) {
937 /* Section translation fault. */
938 code = 5;
939 goto do_fault;
940 }
941 if (domain == 0 || domain == 2) {
942 if (type == 2)
943 code = 9; /* Section domain fault. */
944 else
945 code = 11; /* Page domain fault. */
946 goto do_fault;
947 }
948 if (type == 2) {
949 /* 1Mb section. */
950 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
951 ap = (desc >> 10) & 3;
952 code = 13;
953 *page_size = 1024 * 1024;
954 } else {
955 /* Lookup l2 entry. */
956 if (type == 1) {
957 /* Coarse pagetable. */
958 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
959 } else {
960 /* Fine pagetable. */
961 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
962 }
963 desc = ldl_phys(table);
964 switch (desc & 3) {
965 case 0: /* Page translation fault. */
966 code = 7;
967 goto do_fault;
968 case 1: /* 64k page. */
969 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
970 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
971 *page_size = 0x10000;
972 break;
973 case 2: /* 4k page. */
974 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
975 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
976 *page_size = 0x1000;
977 break;
978 case 3: /* 1k page. */
979 if (type == 1) {
980 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
981 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
982 } else {
983 /* Page translation fault. */
984 code = 7;
985 goto do_fault;
986 }
987 } else {
988 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
989 }
990 ap = (desc >> 4) & 3;
991 *page_size = 0x400;
992 break;
993 default:
994 /* Never happens, but compiler isn't smart enough to tell. */
995 abort();
996 }
997 code = 15;
998 }
999 *prot = check_ap(env, ap, domain, access_type, is_user);
1000 if (!*prot) {
1001 /* Access permission fault. */
1002 goto do_fault;
1003 }
1004 *prot |= PAGE_EXEC;
1005 *phys_ptr = phys_addr;
1006 return 0;
1007 do_fault:
1008 return code | (domain << 4);
1009 }
1010
1011 static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
1012 int is_user, uint32_t *phys_ptr, int *prot,
1013 target_ulong *page_size)
1014 {
1015 int code;
1016 uint32_t table;
1017 uint32_t desc;
1018 uint32_t xn;
1019 int type;
1020 int ap;
1021 int domain;
1022 uint32_t phys_addr;
1023
1024 /* Pagetable walk. */
1025 /* Lookup l1 descriptor. */
1026 table = get_level1_table_address(env, address);
1027 desc = ldl_phys(table);
1028 type = (desc & 3);
1029 if (type == 0) {
1030 /* Section translation fault. */
1031 code = 5;
1032 domain = 0;
1033 goto do_fault;
1034 } else if (type == 2 && (desc & (1 << 18))) {
1035 /* Supersection. */
1036 domain = 0;
1037 } else {
1038 /* Section or page. */
1039 domain = (desc >> 4) & 0x1e;
1040 }
1041 domain = (env->cp15.c3 >> domain) & 3;
1042 if (domain == 0 || domain == 2) {
1043 if (type == 2)
1044 code = 9; /* Section domain fault. */
1045 else
1046 code = 11; /* Page domain fault. */
1047 goto do_fault;
1048 }
1049 if (type == 2) {
1050 if (desc & (1 << 18)) {
1051 /* Supersection. */
1052 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
1053 *page_size = 0x1000000;
1054 } else {
1055 /* Section. */
1056 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
1057 *page_size = 0x100000;
1058 }
1059 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1060 xn = desc & (1 << 4);
1061 code = 13;
1062 } else {
1063 /* Lookup l2 entry. */
1064 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1065 desc = ldl_phys(table);
1066 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1067 switch (desc & 3) {
1068 case 0: /* Page translation fault. */
1069 code = 7;
1070 goto do_fault;
1071 case 1: /* 64k page. */
1072 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1073 xn = desc & (1 << 15);
1074 *page_size = 0x10000;
1075 break;
1076 case 2: case 3: /* 4k page. */
1077 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1078 xn = desc & 1;
1079 *page_size = 0x1000;
1080 break;
1081 default:
1082 /* Never happens, but compiler isn't smart enough to tell. */
1083 abort();
1084 }
1085 code = 15;
1086 }
1087 if (xn && access_type == 2)
1088 goto do_fault;
1089
1090 /* The simplified model uses AP[0] as an access control bit. */
1091 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1092 /* Access flag fault. */
1093 code = (code == 15) ? 6 : 3;
1094 goto do_fault;
1095 }
1096 *prot = check_ap(env, ap, domain, access_type, is_user);
1097 if (!*prot) {
1098 /* Access permission fault. */
1099 goto do_fault;
1100 }
1101 if (!xn) {
1102 *prot |= PAGE_EXEC;
1103 }
1104 *phys_ptr = phys_addr;
1105 return 0;
1106 do_fault:
1107 return code | (domain << 4);
1108 }
1109
1110 static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
1111 int is_user, uint32_t *phys_ptr, int *prot)
1112 {
1113 int n;
1114 uint32_t mask;
1115 uint32_t base;
1116
1117 *phys_ptr = address;
1118 for (n = 7; n >= 0; n--) {
1119 base = env->cp15.c6_region[n];
1120 if ((base & 1) == 0)
1121 continue;
1122 mask = 1 << ((base >> 1) & 0x1f);
1123 /* Keep this shift separate from the above to avoid an
1124 (undefined) << 32. */
1125 mask = (mask << 1) - 1;
1126 if (((base ^ address) & ~mask) == 0)
1127 break;
1128 }
1129 if (n < 0)
1130 return 2;
1131
1132 if (access_type == 2) {
1133 mask = env->cp15.c5_insn;
1134 } else {
1135 mask = env->cp15.c5_data;
1136 }
1137 mask = (mask >> (n * 4)) & 0xf;
1138 switch (mask) {
1139 case 0:
1140 return 1;
1141 case 1:
1142 if (is_user)
1143 return 1;
1144 *prot = PAGE_READ | PAGE_WRITE;
1145 break;
1146 case 2:
1147 *prot = PAGE_READ;
1148 if (!is_user)
1149 *prot |= PAGE_WRITE;
1150 break;
1151 case 3:
1152 *prot = PAGE_READ | PAGE_WRITE;
1153 break;
1154 case 5:
1155 if (is_user)
1156 return 1;
1157 *prot = PAGE_READ;
1158 break;
1159 case 6:
1160 *prot = PAGE_READ;
1161 break;
1162 default:
1163 /* Bad permission. */
1164 return 1;
1165 }
1166 *prot |= PAGE_EXEC;
1167 return 0;
1168 }
1169
1170 static inline int get_phys_addr(CPUState *env, uint32_t address,
1171 int access_type, int is_user,
1172 uint32_t *phys_ptr, int *prot,
1173 target_ulong *page_size)
1174 {
1175 /* Fast Context Switch Extension. */
1176 if (address < 0x02000000)
1177 address += env->cp15.c13_fcse;
1178
1179 if ((env->cp15.c1_sys & 1) == 0) {
1180 /* MMU/MPU disabled. */
1181 *phys_ptr = address;
1182 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1183 *page_size = TARGET_PAGE_SIZE;
1184 return 0;
1185 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
1186 *page_size = TARGET_PAGE_SIZE;
1187 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1188 prot);
1189 } else if (env->cp15.c1_sys & (1 << 23)) {
1190 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
1191 prot, page_size);
1192 } else {
1193 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
1194 prot, page_size);
1195 }
1196 }
1197
1198 int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
1199 int access_type, int mmu_idx, int is_softmmu)
1200 {
1201 uint32_t phys_addr;
1202 target_ulong page_size;
1203 int prot;
1204 int ret, is_user;
1205
1206 is_user = mmu_idx == MMU_USER_IDX;
1207 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
1208 &page_size);
1209 if (ret == 0) {
1210 /* Map a single [sub]page. */
1211 phys_addr &= ~(uint32_t)0x3ff;
1212 address &= ~(uint32_t)0x3ff;
1213 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
1214 return 0;
1215 }
1216
1217 if (access_type == 2) {
1218 env->cp15.c5_insn = ret;
1219 env->cp15.c6_insn = address;
1220 env->exception_index = EXCP_PREFETCH_ABORT;
1221 } else {
1222 env->cp15.c5_data = ret;
1223 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1224 env->cp15.c5_data |= (1 << 11);
1225 env->cp15.c6_data = address;
1226 env->exception_index = EXCP_DATA_ABORT;
1227 }
1228 return 1;
1229 }
1230
1231 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1232 {
1233 uint32_t phys_addr;
1234 target_ulong page_size;
1235 int prot;
1236 int ret;
1237
1238 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
1239
1240 if (ret != 0)
1241 return -1;
1242
1243 return phys_addr;
1244 }
1245
1246 void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
1247 {
1248 int cp_num = (insn >> 8) & 0xf;
1249 int cp_info = (insn >> 5) & 7;
1250 int src = (insn >> 16) & 0xf;
1251 int operand = insn & 0xf;
1252
1253 if (env->cp[cp_num].cp_write)
1254 env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
1255 cp_info, src, operand, val);
1256 }
1257
1258 uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
1259 {
1260 int cp_num = (insn >> 8) & 0xf;
1261 int cp_info = (insn >> 5) & 7;
1262 int dest = (insn >> 16) & 0xf;
1263 int operand = insn & 0xf;
1264
1265 if (env->cp[cp_num].cp_read)
1266 return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
1267 cp_info, dest, operand);
1268 return 0;
1269 }
1270
1271 /* Return basic MPU access permission bits. */
1272 static uint32_t simple_mpu_ap_bits(uint32_t val)
1273 {
1274 uint32_t ret;
1275 uint32_t mask;
1276 int i;
1277 ret = 0;
1278 mask = 3;
1279 for (i = 0; i < 16; i += 2) {
1280 ret |= (val >> i) & mask;
1281 mask <<= 2;
1282 }
1283 return ret;
1284 }
1285
1286 /* Pad basic MPU access permission bits to extended format. */
1287 static uint32_t extended_mpu_ap_bits(uint32_t val)
1288 {
1289 uint32_t ret;
1290 uint32_t mask;
1291 int i;
1292 ret = 0;
1293 mask = 3;
1294 for (i = 0; i < 16; i += 2) {
1295 ret |= (val & mask) << i;
1296 mask <<= 2;
1297 }
1298 return ret;
1299 }
1300
1301 void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
1302 {
1303 int op1;
1304 int op2;
1305 int crm;
1306
1307 op1 = (insn >> 21) & 7;
1308 op2 = (insn >> 5) & 7;
1309 crm = insn & 0xf;
1310 switch ((insn >> 16) & 0xf) {
1311 case 0:
1312 /* ID codes. */
1313 if (arm_feature(env, ARM_FEATURE_XSCALE))
1314 break;
1315 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1316 break;
1317 if (arm_feature(env, ARM_FEATURE_V7)
1318 && op1 == 2 && crm == 0 && op2 == 0) {
1319 env->cp15.c0_cssel = val & 0xf;
1320 break;
1321 }
1322 goto bad_reg;
1323 case 1: /* System configuration. */
1324 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1325 op2 = 0;
1326 switch (op2) {
1327 case 0:
1328 if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
1329 env->cp15.c1_sys = val;
1330 /* ??? Lots of these bits are not implemented. */
1331 /* This may enable/disable the MMU, so do a TLB flush. */
1332 tlb_flush(env, 1);
1333 break;
1334 case 1: /* Auxiliary cotrol register. */
1335 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1336 env->cp15.c1_xscaleauxcr = val;
1337 break;
1338 }
1339 /* Not implemented. */
1340 break;
1341 case 2:
1342 if (arm_feature(env, ARM_FEATURE_XSCALE))
1343 goto bad_reg;
1344 if (env->cp15.c1_coproc != val) {
1345 env->cp15.c1_coproc = val;
1346 /* ??? Is this safe when called from within a TB? */
1347 tb_flush(env);
1348 }
1349 break;
1350 default:
1351 goto bad_reg;
1352 }
1353 break;
1354 case 2: /* MMU Page table control / MPU cache control. */
1355 if (arm_feature(env, ARM_FEATURE_MPU)) {
1356 switch (op2) {
1357 case 0:
1358 env->cp15.c2_data = val;
1359 break;
1360 case 1:
1361 env->cp15.c2_insn = val;
1362 break;
1363 default:
1364 goto bad_reg;
1365 }
1366 } else {
1367 switch (op2) {
1368 case 0:
1369 env->cp15.c2_base0 = val;
1370 break;
1371 case 1:
1372 env->cp15.c2_base1 = val;
1373 break;
1374 case 2:
1375 val &= 7;
1376 env->cp15.c2_control = val;
1377 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
1378 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
1379 break;
1380 default:
1381 goto bad_reg;
1382 }
1383 }
1384 break;
1385 case 3: /* MMU Domain access control / MPU write buffer control. */
1386 env->cp15.c3 = val;
1387 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
1388 break;
1389 case 4: /* Reserved. */
1390 goto bad_reg;
1391 case 5: /* MMU Fault status / MPU access permission. */
1392 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1393 op2 = 0;
1394 switch (op2) {
1395 case 0:
1396 if (arm_feature(env, ARM_FEATURE_MPU))
1397 val = extended_mpu_ap_bits(val);
1398 env->cp15.c5_data = val;
1399 break;
1400 case 1:
1401 if (arm_feature(env, ARM_FEATURE_MPU))
1402 val = extended_mpu_ap_bits(val);
1403 env->cp15.c5_insn = val;
1404 break;
1405 case 2:
1406 if (!arm_feature(env, ARM_FEATURE_MPU))
1407 goto bad_reg;
1408 env->cp15.c5_data = val;
1409 break;
1410 case 3:
1411 if (!arm_feature(env, ARM_FEATURE_MPU))
1412 goto bad_reg;
1413 env->cp15.c5_insn = val;
1414 break;
1415 default:
1416 goto bad_reg;
1417 }
1418 break;
1419 case 6: /* MMU Fault address / MPU base/size. */
1420 if (arm_feature(env, ARM_FEATURE_MPU)) {
1421 if (crm >= 8)
1422 goto bad_reg;
1423 env->cp15.c6_region[crm] = val;
1424 } else {
1425 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1426 op2 = 0;
1427 switch (op2) {
1428 case 0:
1429 env->cp15.c6_data = val;
1430 break;
1431 case 1: /* ??? This is WFAR on armv6 */
1432 case 2:
1433 env->cp15.c6_insn = val;
1434 break;
1435 default:
1436 goto bad_reg;
1437 }
1438 }
1439 break;
1440 case 7: /* Cache control. */
1441 env->cp15.c15_i_max = 0x000;
1442 env->cp15.c15_i_min = 0xff0;
1443 /* No cache, so nothing to do. */
1444 /* ??? MPCore has VA to PA translation functions. */
1445 break;
1446 case 8: /* MMU TLB control. */
1447 switch (op2) {
1448 case 0: /* Invalidate all. */
1449 tlb_flush(env, 0);
1450 break;
1451 case 1: /* Invalidate single TLB entry. */
1452 tlb_flush_page(env, val & TARGET_PAGE_MASK);
1453 break;
1454 case 2: /* Invalidate on ASID. */
1455 tlb_flush(env, val == 0);
1456 break;
1457 case 3: /* Invalidate single entry on MVA. */
1458 /* ??? This is like case 1, but ignores ASID. */
1459 tlb_flush(env, 1);
1460 break;
1461 default:
1462 goto bad_reg;
1463 }
1464 break;
1465 case 9:
1466 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1467 break;
1468 switch (crm) {
1469 case 0: /* Cache lockdown. */
1470 switch (op1) {
1471 case 0: /* L1 cache. */
1472 switch (op2) {
1473 case 0:
1474 env->cp15.c9_data = val;
1475 break;
1476 case 1:
1477 env->cp15.c9_insn = val;
1478 break;
1479 default:
1480 goto bad_reg;
1481 }
1482 break;
1483 case 1: /* L2 cache. */
1484 /* Ignore writes to L2 lockdown/auxiliary registers. */
1485 break;
1486 default:
1487 goto bad_reg;
1488 }
1489 break;
1490 case 1: /* TCM memory region registers. */
1491 /* Not implemented. */
1492 goto bad_reg;
1493 default:
1494 goto bad_reg;
1495 }
1496 break;
1497 case 10: /* MMU TLB lockdown. */
1498 /* ??? TLB lockdown not implemented. */
1499 break;
1500 case 12: /* Reserved. */
1501 goto bad_reg;
1502 case 13: /* Process ID. */
1503 switch (op2) {
1504 case 0:
1505 /* Unlike real hardware the qemu TLB uses virtual addresses,
1506 not modified virtual addresses, so this causes a TLB flush.
1507 */
1508 if (env->cp15.c13_fcse != val)
1509 tlb_flush(env, 1);
1510 env->cp15.c13_fcse = val;
1511 break;
1512 case 1:
1513 /* This changes the ASID, so do a TLB flush. */
1514 if (env->cp15.c13_context != val
1515 && !arm_feature(env, ARM_FEATURE_MPU))
1516 tlb_flush(env, 0);
1517 env->cp15.c13_context = val;
1518 break;
1519 default:
1520 goto bad_reg;
1521 }
1522 break;
1523 case 14: /* Reserved. */
1524 goto bad_reg;
1525 case 15: /* Implementation specific. */
1526 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1527 if (op2 == 0 && crm == 1) {
1528 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1529 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1530 tb_flush(env);
1531 env->cp15.c15_cpar = val & 0x3fff;
1532 }
1533 break;
1534 }
1535 goto bad_reg;
1536 }
1537 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1538 switch (crm) {
1539 case 0:
1540 break;
1541 case 1: /* Set TI925T configuration. */
1542 env->cp15.c15_ticonfig = val & 0xe7;
1543 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1544 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1545 break;
1546 case 2: /* Set I_max. */
1547 env->cp15.c15_i_max = val;
1548 break;
1549 case 3: /* Set I_min. */
1550 env->cp15.c15_i_min = val;
1551 break;
1552 case 4: /* Set thread-ID. */
1553 env->cp15.c15_threadid = val & 0xffff;
1554 break;
1555 case 8: /* Wait-for-interrupt (deprecated). */
1556 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1557 break;
1558 default:
1559 goto bad_reg;
1560 }
1561 }
1562 break;
1563 }
1564 return;
1565 bad_reg:
1566 /* ??? For debugging only. Should raise illegal instruction exception. */
1567 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1568 (insn >> 16) & 0xf, crm, op1, op2);
1569 }
1570
1571 uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
1572 {
1573 int op1;
1574 int op2;
1575 int crm;
1576
1577 op1 = (insn >> 21) & 7;
1578 op2 = (insn >> 5) & 7;
1579 crm = insn & 0xf;
1580 switch ((insn >> 16) & 0xf) {
1581 case 0: /* ID codes. */
1582 switch (op1) {
1583 case 0:
1584 switch (crm) {
1585 case 0:
1586 switch (op2) {
1587 case 0: /* Device ID. */
1588 return env->cp15.c0_cpuid;
1589 case 1: /* Cache Type. */
1590 return env->cp15.c0_cachetype;
1591 case 2: /* TCM status. */
1592 return 0;
1593 case 3: /* TLB type register. */
1594 return 0; /* No lockable TLB entries. */
1595 case 5: /* CPU ID */
1596 if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
1597 return env->cpu_index | 0x80000900;
1598 } else {
1599 return env->cpu_index;
1600 }
1601 default:
1602 goto bad_reg;
1603 }
1604 case 1:
1605 if (!arm_feature(env, ARM_FEATURE_V6))
1606 goto bad_reg;
1607 return env->cp15.c0_c1[op2];
1608 case 2:
1609 if (!arm_feature(env, ARM_FEATURE_V6))
1610 goto bad_reg;
1611 return env->cp15.c0_c2[op2];
1612 case 3: case 4: case 5: case 6: case 7:
1613 return 0;
1614 default:
1615 goto bad_reg;
1616 }
1617 case 1:
1618 /* These registers aren't documented on arm11 cores. However
1619 Linux looks at them anyway. */
1620 if (!arm_feature(env, ARM_FEATURE_V6))
1621 goto bad_reg;
1622 if (crm != 0)
1623 goto bad_reg;
1624 if (!arm_feature(env, ARM_FEATURE_V7))
1625 return 0;
1626
1627 switch (op2) {
1628 case 0:
1629 return env->cp15.c0_ccsid[env->cp15.c0_cssel];
1630 case 1:
1631 return env->cp15.c0_clid;
1632 case 7:
1633 return 0;
1634 }
1635 goto bad_reg;
1636 case 2:
1637 if (op2 != 0 || crm != 0)
1638 goto bad_reg;
1639 return env->cp15.c0_cssel;
1640 default:
1641 goto bad_reg;
1642 }
1643 case 1: /* System configuration. */
1644 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1645 op2 = 0;
1646 switch (op2) {
1647 case 0: /* Control register. */
1648 return env->cp15.c1_sys;
1649 case 1: /* Auxiliary control register. */
1650 if (arm_feature(env, ARM_FEATURE_XSCALE))
1651 return env->cp15.c1_xscaleauxcr;
1652 if (!arm_feature(env, ARM_FEATURE_AUXCR))
1653 goto bad_reg;
1654 switch (ARM_CPUID(env)) {
1655 case ARM_CPUID_ARM1026:
1656 return 1;
1657 case ARM_CPUID_ARM1136:
1658 case ARM_CPUID_ARM1136_R2:
1659 return 7;
1660 case ARM_CPUID_ARM11MPCORE:
1661 return 1;
1662 case ARM_CPUID_CORTEXA8:
1663 return 2;
1664 case ARM_CPUID_CORTEXA9:
1665 return 0;
1666 default:
1667 goto bad_reg;
1668 }
1669 case 2: /* Coprocessor access register. */
1670 if (arm_feature(env, ARM_FEATURE_XSCALE))
1671 goto bad_reg;
1672 return env->cp15.c1_coproc;
1673 default:
1674 goto bad_reg;
1675 }
1676 case 2: /* MMU Page table control / MPU cache control. */
1677 if (arm_feature(env, ARM_FEATURE_MPU)) {
1678 switch (op2) {
1679 case 0:
1680 return env->cp15.c2_data;
1681 break;
1682 case 1:
1683 return env->cp15.c2_insn;
1684 break;
1685 default:
1686 goto bad_reg;
1687 }
1688 } else {
1689 switch (op2) {
1690 case 0:
1691 return env->cp15.c2_base0;
1692 case 1:
1693 return env->cp15.c2_base1;
1694 case 2:
1695 return env->cp15.c2_control;
1696 default:
1697 goto bad_reg;
1698 }
1699 }
1700 case 3: /* MMU Domain access control / MPU write buffer control. */
1701 return env->cp15.c3;
1702 case 4: /* Reserved. */
1703 goto bad_reg;
1704 case 5: /* MMU Fault status / MPU access permission. */
1705 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1706 op2 = 0;
1707 switch (op2) {
1708 case 0:
1709 if (arm_feature(env, ARM_FEATURE_MPU))
1710 return simple_mpu_ap_bits(env->cp15.c5_data);
1711 return env->cp15.c5_data;
1712 case 1:
1713 if (arm_feature(env, ARM_FEATURE_MPU))
1714 return simple_mpu_ap_bits(env->cp15.c5_data);
1715 return env->cp15.c5_insn;
1716 case 2:
1717 if (!arm_feature(env, ARM_FEATURE_MPU))
1718 goto bad_reg;
1719 return env->cp15.c5_data;
1720 case 3:
1721 if (!arm_feature(env, ARM_FEATURE_MPU))
1722 goto bad_reg;
1723 return env->cp15.c5_insn;
1724 default:
1725 goto bad_reg;
1726 }
1727 case 6: /* MMU Fault address. */
1728 if (arm_feature(env, ARM_FEATURE_MPU)) {
1729 if (crm >= 8)
1730 goto bad_reg;
1731 return env->cp15.c6_region[crm];
1732 } else {
1733 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1734 op2 = 0;
1735 switch (op2) {
1736 case 0:
1737 return env->cp15.c6_data;
1738 case 1:
1739 if (arm_feature(env, ARM_FEATURE_V6)) {
1740 /* Watchpoint Fault Adrress. */
1741 return 0; /* Not implemented. */
1742 } else {
1743 /* Instruction Fault Adrress. */
1744 /* Arm9 doesn't have an IFAR, but implementing it anyway
1745 shouldn't do any harm. */
1746 return env->cp15.c6_insn;
1747 }
1748 case 2:
1749 if (arm_feature(env, ARM_FEATURE_V6)) {
1750 /* Instruction Fault Adrress. */
1751 return env->cp15.c6_insn;
1752 } else {
1753 goto bad_reg;
1754 }
1755 default:
1756 goto bad_reg;
1757 }
1758 }
1759 case 7: /* Cache control. */
1760 /* FIXME: Should only clear Z flag if destination is r15. */
1761 env->ZF = 0;
1762 return 0;
1763 case 8: /* MMU TLB control. */
1764 goto bad_reg;
1765 case 9: /* Cache lockdown. */
1766 switch (op1) {
1767 case 0: /* L1 cache. */
1768 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1769 return 0;
1770 switch (op2) {
1771 case 0:
1772 return env->cp15.c9_data;
1773 case 1:
1774 return env->cp15.c9_insn;
1775 default:
1776 goto bad_reg;
1777 }
1778 case 1: /* L2 cache */
1779 if (crm != 0)
1780 goto bad_reg;
1781 /* L2 Lockdown and Auxiliary control. */
1782 return 0;
1783 default:
1784 goto bad_reg;
1785 }
1786 case 10: /* MMU TLB lockdown. */
1787 /* ??? TLB lockdown not implemented. */
1788 return 0;
1789 case 11: /* TCM DMA control. */
1790 case 12: /* Reserved. */
1791 goto bad_reg;
1792 case 13: /* Process ID. */
1793 switch (op2) {
1794 case 0:
1795 return env->cp15.c13_fcse;
1796 case 1:
1797 return env->cp15.c13_context;
1798 default:
1799 goto bad_reg;
1800 }
1801 case 14: /* Reserved. */
1802 goto bad_reg;
1803 case 15: /* Implementation specific. */
1804 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1805 if (op2 == 0 && crm == 1)
1806 return env->cp15.c15_cpar;
1807
1808 goto bad_reg;
1809 }
1810 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1811 switch (crm) {
1812 case 0:
1813 return 0;
1814 case 1: /* Read TI925T configuration. */
1815 return env->cp15.c15_ticonfig;
1816 case 2: /* Read I_max. */
1817 return env->cp15.c15_i_max;
1818 case 3: /* Read I_min. */
1819 return env->cp15.c15_i_min;
1820 case 4: /* Read thread-ID. */
1821 return env->cp15.c15_threadid;
1822 case 8: /* TI925T_status */
1823 return 0;
1824 }
1825 /* TODO: Peripheral port remap register:
1826 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
1827 * controller base address at $rn & ~0xfff and map size of
1828 * 0x200 << ($rn & 0xfff), when MMU is off. */
1829 goto bad_reg;
1830 }
1831 return 0;
1832 }
1833 bad_reg:
1834 /* ??? For debugging only. Should raise illegal instruction exception. */
1835 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1836 (insn >> 16) & 0xf, crm, op1, op2);
1837 return 0;
1838 }
1839
1840 void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
1841 {
1842 env->banked_r13[bank_number(mode)] = val;
1843 }
1844
1845 uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
1846 {
1847 return env->banked_r13[bank_number(mode)];
1848 }
1849
1850 uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
1851 {
1852 switch (reg) {
1853 case 0: /* APSR */
1854 return xpsr_read(env) & 0xf8000000;
1855 case 1: /* IAPSR */
1856 return xpsr_read(env) & 0xf80001ff;
1857 case 2: /* EAPSR */
1858 return xpsr_read(env) & 0xff00fc00;
1859 case 3: /* xPSR */
1860 return xpsr_read(env) & 0xff00fdff;
1861 case 5: /* IPSR */
1862 return xpsr_read(env) & 0x000001ff;
1863 case 6: /* EPSR */
1864 return xpsr_read(env) & 0x0700fc00;
1865 case 7: /* IEPSR */
1866 return xpsr_read(env) & 0x0700edff;
1867 case 8: /* MSP */
1868 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
1869 case 9: /* PSP */
1870 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
1871 case 16: /* PRIMASK */
1872 return (env->uncached_cpsr & CPSR_I) != 0;
1873 case 17: /* FAULTMASK */
1874 return (env->uncached_cpsr & CPSR_F) != 0;
1875 case 18: /* BASEPRI */
1876 case 19: /* BASEPRI_MAX */
1877 return env->v7m.basepri;
1878 case 20: /* CONTROL */
1879 return env->v7m.control;
1880 default:
1881 /* ??? For debugging only. */
1882 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
1883 return 0;
1884 }
1885 }
1886
1887 void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
1888 {
1889 switch (reg) {
1890 case 0: /* APSR */
1891 xpsr_write(env, val, 0xf8000000);
1892 break;
1893 case 1: /* IAPSR */
1894 xpsr_write(env, val, 0xf8000000);
1895 break;
1896 case 2: /* EAPSR */
1897 xpsr_write(env, val, 0xfe00fc00);
1898 break;
1899 case 3: /* xPSR */
1900 xpsr_write(env, val, 0xfe00fc00);
1901 break;
1902 case 5: /* IPSR */
1903 /* IPSR bits are readonly. */
1904 break;
1905 case 6: /* EPSR */
1906 xpsr_write(env, val, 0x0600fc00);
1907 break;
1908 case 7: /* IEPSR */
1909 xpsr_write(env, val, 0x0600fc00);
1910 break;
1911 case 8: /* MSP */
1912 if (env->v7m.current_sp)
1913 env->v7m.other_sp = val;
1914 else
1915 env->regs[13] = val;
1916 break;
1917 case 9: /* PSP */
1918 if (env->v7m.current_sp)
1919 env->regs[13] = val;
1920 else
1921 env->v7m.other_sp = val;
1922 break;
1923 case 16: /* PRIMASK */
1924 if (val & 1)
1925 env->uncached_cpsr |= CPSR_I;
1926 else
1927 env->uncached_cpsr &= ~CPSR_I;
1928 break;
1929 case 17: /* FAULTMASK */
1930 if (val & 1)
1931 env->uncached_cpsr |= CPSR_F;
1932 else
1933 env->uncached_cpsr &= ~CPSR_F;
1934 break;
1935 case 18: /* BASEPRI */
1936 env->v7m.basepri = val & 0xff;
1937 break;
1938 case 19: /* BASEPRI_MAX */
1939 val &= 0xff;
1940 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
1941 env->v7m.basepri = val;
1942 break;
1943 case 20: /* CONTROL */
1944 env->v7m.control = val & 3;
1945 switch_v7m_sp(env, (val & 2) != 0);
1946 break;
1947 default:
1948 /* ??? For debugging only. */
1949 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
1950 return;
1951 }
1952 }
1953
1954 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
1955 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
1956 void *opaque)
1957 {
1958 if (cpnum < 0 || cpnum > 14) {
1959 cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
1960 return;
1961 }
1962
1963 env->cp[cpnum].cp_read = cp_read;
1964 env->cp[cpnum].cp_write = cp_write;
1965 env->cp[cpnum].opaque = opaque;
1966 }
1967
1968 #endif
1969
1970 /* Note that signed overflow is undefined in C. The following routines are
1971 careful to use unsigned types where modulo arithmetic is required.
1972 Failure to do so _will_ break on newer gcc. */
1973
1974 /* Signed saturating arithmetic. */
1975
1976 /* Perform 16-bit signed saturating addition. */
1977 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
1978 {
1979 uint16_t res;
1980
1981 res = a + b;
1982 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
1983 if (a & 0x8000)
1984 res = 0x8000;
1985 else
1986 res = 0x7fff;
1987 }
1988 return res;
1989 }
1990
1991 /* Perform 8-bit signed saturating addition. */
1992 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
1993 {
1994 uint8_t res;
1995
1996 res = a + b;
1997 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
1998 if (a & 0x80)
1999 res = 0x80;
2000 else
2001 res = 0x7f;
2002 }
2003 return res;
2004 }
2005
2006 /* Perform 16-bit signed saturating subtraction. */
2007 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2008 {
2009 uint16_t res;
2010
2011 res = a - b;
2012 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2013 if (a & 0x8000)
2014 res = 0x8000;
2015 else
2016 res = 0x7fff;
2017 }
2018 return res;
2019 }
2020
2021 /* Perform 8-bit signed saturating subtraction. */
2022 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2023 {
2024 uint8_t res;
2025
2026 res = a - b;
2027 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2028 if (a & 0x80)
2029 res = 0x80;
2030 else
2031 res = 0x7f;
2032 }
2033 return res;
2034 }
2035
2036 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2037 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2038 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2039 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2040 #define PFX q
2041
2042 #include "op_addsub.h"
2043
2044 /* Unsigned saturating arithmetic. */
2045 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
2046 {
2047 uint16_t res;
2048 res = a + b;
2049 if (res < a)
2050 res = 0xffff;
2051 return res;
2052 }
2053
2054 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
2055 {
2056 if (a > b)
2057 return a - b;
2058 else
2059 return 0;
2060 }
2061
2062 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2063 {
2064 uint8_t res;
2065 res = a + b;
2066 if (res < a)
2067 res = 0xff;
2068 return res;
2069 }
2070
2071 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2072 {
2073 if (a > b)
2074 return a - b;
2075 else
2076 return 0;
2077 }
2078
2079 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2080 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2081 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2082 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2083 #define PFX uq
2084
2085 #include "op_addsub.h"
2086
2087 /* Signed modulo arithmetic. */
2088 #define SARITH16(a, b, n, op) do { \
2089 int32_t sum; \
2090 sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \
2091 RESULT(sum, n, 16); \
2092 if (sum >= 0) \
2093 ge |= 3 << (n * 2); \
2094 } while(0)
2095
2096 #define SARITH8(a, b, n, op) do { \
2097 int32_t sum; \
2098 sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \
2099 RESULT(sum, n, 8); \
2100 if (sum >= 0) \
2101 ge |= 1 << n; \
2102 } while(0)
2103
2104
2105 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2106 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2107 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2108 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2109 #define PFX s
2110 #define ARITH_GE
2111
2112 #include "op_addsub.h"
2113
2114 /* Unsigned modulo arithmetic. */
2115 #define ADD16(a, b, n) do { \
2116 uint32_t sum; \
2117 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2118 RESULT(sum, n, 16); \
2119 if ((sum >> 16) == 1) \
2120 ge |= 3 << (n * 2); \
2121 } while(0)
2122
2123 #define ADD8(a, b, n) do { \
2124 uint32_t sum; \
2125 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2126 RESULT(sum, n, 8); \
2127 if ((sum >> 8) == 1) \
2128 ge |= 1 << n; \
2129 } while(0)
2130
2131 #define SUB16(a, b, n) do { \
2132 uint32_t sum; \
2133 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2134 RESULT(sum, n, 16); \
2135 if ((sum >> 16) == 0) \
2136 ge |= 3 << (n * 2); \
2137 } while(0)
2138
2139 #define SUB8(a, b, n) do { \
2140 uint32_t sum; \
2141 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2142 RESULT(sum, n, 8); \
2143 if ((sum >> 8) == 0) \
2144 ge |= 1 << n; \
2145 } while(0)
2146
2147 #define PFX u
2148 #define ARITH_GE
2149
2150 #include "op_addsub.h"
2151
2152 /* Halved signed arithmetic. */
2153 #define ADD16(a, b, n) \
2154 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2155 #define SUB16(a, b, n) \
2156 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2157 #define ADD8(a, b, n) \
2158 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2159 #define SUB8(a, b, n) \
2160 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2161 #define PFX sh
2162
2163 #include "op_addsub.h"
2164
2165 /* Halved unsigned arithmetic. */
2166 #define ADD16(a, b, n) \
2167 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2168 #define SUB16(a, b, n) \
2169 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2170 #define ADD8(a, b, n) \
2171 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2172 #define SUB8(a, b, n) \
2173 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2174 #define PFX uh
2175
2176 #include "op_addsub.h"
2177
2178 static inline uint8_t do_usad(uint8_t a, uint8_t b)
2179 {
2180 if (a > b)
2181 return a - b;
2182 else
2183 return b - a;
2184 }
2185
2186 /* Unsigned sum of absolute byte differences. */
2187 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2188 {
2189 uint32_t sum;
2190 sum = do_usad(a, b);
2191 sum += do_usad(a >> 8, b >> 8);
2192 sum += do_usad(a >> 16, b >>16);
2193 sum += do_usad(a >> 24, b >> 24);
2194 return sum;
2195 }
2196
2197 /* For ARMv6 SEL instruction. */
2198 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2199 {
2200 uint32_t mask;
2201
2202 mask = 0;
2203 if (flags & 1)
2204 mask |= 0xff;
2205 if (flags & 2)
2206 mask |= 0xff00;
2207 if (flags & 4)
2208 mask |= 0xff0000;
2209 if (flags & 8)
2210 mask |= 0xff000000;
2211 return (a & mask) | (b & ~mask);
2212 }
2213
2214 uint32_t HELPER(logicq_cc)(uint64_t val)
2215 {
2216 return (val >> 32) | (val != 0);
2217 }
2218
2219 /* VFP support. We follow the convention used for VFP instrunctions:
2220 Single precition routines have a "s" suffix, double precision a
2221 "d" suffix. */
2222
2223 /* Convert host exception flags to vfp form. */
2224 static inline int vfp_exceptbits_from_host(int host_bits)
2225 {
2226 int target_bits = 0;
2227
2228 if (host_bits & float_flag_invalid)
2229 target_bits |= 1;
2230 if (host_bits & float_flag_divbyzero)
2231 target_bits |= 2;
2232 if (host_bits & float_flag_overflow)
2233 target_bits |= 4;
2234 if (host_bits & float_flag_underflow)
2235 target_bits |= 8;
2236 if (host_bits & float_flag_inexact)
2237 target_bits |= 0x10;
2238 return target_bits;
2239 }
2240
2241 uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
2242 {
2243 int i;
2244 uint32_t fpscr;
2245
2246 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2247 | (env->vfp.vec_len << 16)
2248 | (env->vfp.vec_stride << 20);
2249 i = get_float_exception_flags(&env->vfp.fp_status);
2250 fpscr |= vfp_exceptbits_from_host(i);
2251 return fpscr;
2252 }
2253
2254 /* Convert vfp exception flags to target form. */
2255 static inline int vfp_exceptbits_to_host(int target_bits)
2256 {
2257 int host_bits = 0;
2258
2259 if (target_bits & 1)
2260 host_bits |= float_flag_invalid;
2261 if (target_bits & 2)
2262 host_bits |= float_flag_divbyzero;
2263 if (target_bits & 4)
2264 host_bits |= float_flag_overflow;
2265 if (target_bits & 8)
2266 host_bits |= float_flag_underflow;
2267 if (target_bits & 0x10)
2268 host_bits |= float_flag_inexact;
2269 return host_bits;
2270 }
2271
2272 void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
2273 {
2274 int i;
2275 uint32_t changed;
2276
2277 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2278 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2279 env->vfp.vec_len = (val >> 16) & 7;
2280 env->vfp.vec_stride = (val >> 20) & 3;
2281
2282 changed ^= val;
2283 if (changed & (3 << 22)) {
2284 i = (val >> 22) & 3;
2285 switch (i) {
2286 case 0:
2287 i = float_round_nearest_even;
2288 break;
2289 case 1:
2290 i = float_round_up;
2291 break;
2292 case 2:
2293 i = float_round_down;
2294 break;
2295 case 3:
2296 i = float_round_to_zero;
2297 break;
2298 }
2299 set_float_rounding_mode(i, &env->vfp.fp_status);
2300 }
2301 if (changed & (1 << 24))
2302 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2303 if (changed & (1 << 25))
2304 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
2305
2306 i = vfp_exceptbits_to_host((val >> 8) & 0x1f);
2307 set_float_exception_flags(i, &env->vfp.fp_status);
2308 }
2309
2310 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2311
2312 #define VFP_BINOP(name) \
2313 float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2314 { \
2315 return float32_ ## name (a, b, &env->vfp.fp_status); \
2316 } \
2317 float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2318 { \
2319 return float64_ ## name (a, b, &env->vfp.fp_status); \
2320 }
2321 VFP_BINOP(add)
2322 VFP_BINOP(sub)
2323 VFP_BINOP(mul)
2324 VFP_BINOP(div)
2325 #undef VFP_BINOP
2326
2327 float32 VFP_HELPER(neg, s)(float32 a)
2328 {
2329 return float32_chs(a);
2330 }
2331
2332 float64 VFP_HELPER(neg, d)(float64 a)
2333 {
2334 return float64_chs(a);
2335 }
2336
2337 float32 VFP_HELPER(abs, s)(float32 a)
2338 {
2339 return float32_abs(a);
2340 }
2341
2342 float64 VFP_HELPER(abs, d)(float64 a)
2343 {
2344 return float64_abs(a);
2345 }
2346
2347 float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env)
2348 {
2349 return float32_sqrt(a, &env->vfp.fp_status);
2350 }
2351
2352 float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env)
2353 {
2354 return float64_sqrt(a, &env->vfp.fp_status);
2355 }
2356
2357 /* XXX: check quiet/signaling case */
2358 #define DO_VFP_cmp(p, type) \
2359 void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2360 { \
2361 uint32_t flags; \
2362 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2363 case 0: flags = 0x6; break; \
2364 case -1: flags = 0x8; break; \
2365 case 1: flags = 0x2; break; \
2366 default: case 2: flags = 0x3; break; \
2367 } \
2368 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2369 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2370 } \
2371 void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2372 { \
2373 uint32_t flags; \
2374 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2375 case 0: flags = 0x6; break; \
2376 case -1: flags = 0x8; break; \
2377 case 1: flags = 0x2; break; \
2378 default: case 2: flags = 0x3; break; \
2379 } \
2380 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2381 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2382 }
2383 DO_VFP_cmp(s, float32)
2384 DO_VFP_cmp(d, float64)
2385 #undef DO_VFP_cmp
2386
2387 /* Helper routines to perform bitwise copies between float and int. */
2388 static inline float32 vfp_itos(uint32_t i)
2389 {
2390 union {
2391 uint32_t i;
2392 float32 s;
2393 } v;
2394
2395 v.i = i;
2396 return v.s;
2397 }
2398
2399 static inline uint32_t vfp_stoi(float32 s)
2400 {
2401 union {
2402 uint32_t i;
2403 float32 s;
2404 } v;
2405
2406 v.s = s;
2407 return v.i;
2408 }
2409
2410 static inline float64 vfp_itod(uint64_t i)
2411 {
2412 union {
2413 uint64_t i;
2414 float64 d;
2415 } v;
2416
2417 v.i = i;
2418 return v.d;
2419 }
2420
2421 static inline uint64_t vfp_dtoi(float64 d)
2422 {
2423 union {
2424 uint64_t i;
2425 float64 d;
2426 } v;
2427
2428 v.d = d;
2429 return v.i;
2430 }
2431
2432 /* Integer to float conversion. */
2433 float32 VFP_HELPER(uito, s)(float32 x, CPUState *env)
2434 {
2435 return uint32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
2436 }
2437
2438 float64 VFP_HELPER(uito, d)(float32 x, CPUState *env)
2439 {
2440 return uint32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
2441 }
2442
2443 float32 VFP_HELPER(sito, s)(float32 x, CPUState *env)
2444 {
2445 return int32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
2446 }
2447
2448 float64 VFP_HELPER(sito, d)(float32 x, CPUState *env)
2449 {
2450 return int32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
2451 }
2452
2453 /* Float to integer conversion. */
2454 float32 VFP_HELPER(toui, s)(float32 x, CPUState *env)
2455 {
2456 return vfp_itos(float32_to_uint32(x, &env->vfp.fp_status));
2457 }
2458
2459 float32 VFP_HELPER(toui, d)(float64 x, CPUState *env)
2460 {
2461 return vfp_itos(float64_to_uint32(x, &env->vfp.fp_status));
2462 }
2463
2464 float32 VFP_HELPER(tosi, s)(float32 x, CPUState *env)
2465 {
2466 return vfp_itos(float32_to_int32(x, &env->vfp.fp_status));
2467 }
2468
2469 float32 VFP_HELPER(tosi, d)(float64 x, CPUState *env)
2470 {
2471 return vfp_itos(float64_to_int32(x, &env->vfp.fp_status));
2472 }
2473
2474 float32 VFP_HELPER(touiz, s)(float32 x, CPUState *env)
2475 {
2476 return vfp_itos(float32_to_uint32_round_to_zero(x, &env->vfp.fp_status));
2477 }
2478
2479 float32 VFP_HELPER(touiz, d)(float64 x, CPUState *env)
2480 {
2481 return vfp_itos(float64_to_uint32_round_to_zero(x, &env->vfp.fp_status));
2482 }
2483
2484 float32 VFP_HELPER(tosiz, s)(float32 x, CPUState *env)
2485 {
2486 return vfp_itos(float32_to_int32_round_to_zero(x, &env->vfp.fp_status));
2487 }
2488
2489 float32 VFP_HELPER(tosiz, d)(float64 x, CPUState *env)
2490 {
2491 return vfp_itos(float64_to_int32_round_to_zero(x, &env->vfp.fp_status));
2492 }
2493
2494 /* floating point conversion */
2495 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
2496 {
2497 return float32_to_float64(x, &env->vfp.fp_status);
2498 }
2499
2500 float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env)
2501 {
2502 return float64_to_float32(x, &env->vfp.fp_status);
2503 }
2504
2505 /* VFP3 fixed point conversion. */
2506 #define VFP_CONV_FIX(name, p, ftype, itype, sign) \
2507 ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \
2508 { \
2509 ftype tmp; \
2510 tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(x), \
2511 &env->vfp.fp_status); \
2512 return ftype##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \
2513 } \
2514 ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \
2515 { \
2516 ftype tmp; \
2517 tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \
2518 return vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \
2519 &env->vfp.fp_status)); \
2520 }
2521
2522 VFP_CONV_FIX(sh, d, float64, int16, )
2523 VFP_CONV_FIX(sl, d, float64, int32, )
2524 VFP_CONV_FIX(uh, d, float64, uint16, u)
2525 VFP_CONV_FIX(ul, d, float64, uint32, u)
2526 VFP_CONV_FIX(sh, s, float32, int16, )
2527 VFP_CONV_FIX(sl, s, float32, int32, )
2528 VFP_CONV_FIX(uh, s, float32, uint16, u)
2529 VFP_CONV_FIX(ul, s, float32, uint32, u)
2530 #undef VFP_CONV_FIX
2531
2532 /* Half precision conversions. */
2533 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
2534 {
2535 float_status *s = &env->vfp.fp_status;
2536 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
2537 return float16_to_float32(a, ieee, s);
2538 }
2539
2540 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env)
2541 {
2542 float_status *s = &env->vfp.fp_status;
2543 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
2544 return float32_to_float16(a, ieee, s);
2545 }
2546
2547 float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
2548 {
2549 float_status *s = &env->vfp.fp_status;
2550 float32 two = int32_to_float32(2, s);
2551 return float32_sub(two, float32_mul(a, b, s), s);
2552 }
2553
2554 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
2555 {
2556 float_status *s = &env->vfp.fp_status;
2557 float32 three = int32_to_float32(3, s);
2558 return float32_sub(three, float32_mul(a, b, s), s);
2559 }
2560
2561 /* NEON helpers. */
2562
2563 /* TODO: The architecture specifies the value that the estimate functions
2564 should return. We return the exact reciprocal/root instead. */
2565 float32 HELPER(recpe_f32)(float32 a, CPUState *env)
2566 {
2567 float_status *s = &env->vfp.fp_status;
2568 float32 one = int32_to_float32(1, s);
2569 return float32_div(one, a, s);
2570 }
2571
2572 float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
2573 {
2574 float_status *s = &env->vfp.fp_status;
2575 float32 one = int32_to_float32(1, s);
2576 return float32_div(one, float32_sqrt(a, s), s);
2577 }
2578
2579 uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
2580 {
2581 float_status *s = &env->vfp.fp_status;
2582 float32 tmp;
2583 tmp = int32_to_float32(a, s);
2584 tmp = float32_scalbn(tmp, -32, s);
2585 tmp = helper_recpe_f32(tmp, env);
2586 tmp = float32_scalbn(tmp, 31, s);
2587 return float32_to_int32(tmp, s);
2588 }
2589
2590 uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
2591 {
2592 float_status *s = &env->vfp.fp_status;
2593 float32 tmp;
2594 tmp = int32_to_float32(a, s);
2595 tmp = float32_scalbn(tmp, -32, s);
2596 tmp = helper_rsqrte_f32(tmp, env);
2597 tmp = float32_scalbn(tmp, 31, s);
2598 return float32_to_int32(tmp, s);
2599 }
2600
2601 void HELPER(set_teecr)(CPUState *env, uint32_t val)
2602 {
2603 val &= 1;
2604 if (env->teecr != val) {
2605 env->teecr = val;
2606 tb_flush(env);
2607 }
2608 }
AR7 emulation for QEMU