hw/intc/ibex_plic.c

   1 /*
   2  * QEMU RISC-V lowRISC Ibex PLIC
   3  *
   4  * Copyright (c) 2020 Western Digital
   5  *
   6  * Documentation avaliable: https://docs.opentitan.org/hw/ip/rv_plic/doc/
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/log.h"
  23 #include "hw/qdev-properties.h"
  24 #include "hw/core/cpu.h"
  25 #include "hw/boards.h"
  26 #include "hw/pci/msi.h"
  27 #include "target/riscv/cpu_bits.h"
  28 #include "target/riscv/cpu.h"
  29 #include "hw/intc/ibex_plic.h"
  30
  31 static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
  32 {
  33     uint32_t end = base + (num * 0x04);
  34
  35     if (addr >= base && addr < end) {
  36         return true;
  37     }
  38
  39     return false;
  40 }
  41
  42 static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
  43 {
  44     int pending_num = irq / 32;
  45
  46     if (!level) {
  47         /*
  48          * If the level is low make sure we clear the hidden_pending.
  49          */
  50         s->hidden_pending[pending_num] &= ~(1 << (irq % 32));
  51     }
  52
  53     if (s->claimed[pending_num] & 1 << (irq % 32)) {
  54         /*
  55          * The interrupt has been claimed, but not completed.
  56          * The pending bit can't be set.
  57          * Save the pending level for after the interrupt is completed.
  58          */
  59         s->hidden_pending[pending_num] |= level << (irq % 32);
  60     } else {
  61         s->pending[pending_num] |= level << (irq % 32);
  62     }
  63 }
  64
  65 static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
  66 {
  67     int i;
  68     uint32_t max_irq = 0;
  69     uint32_t max_prio = s->threshold;
  70
  71     for (i = 0; i < s->pending_num; i++) {
  72         uint32_t irq_num = ctz64(s->pending[i]) + (i * 32);
  73
  74         if (!(s->pending[i] & s->enable[i])) {
  75             /* No pending and enabled IRQ */
  76             continue;
  77         }
  78
  79         if (s->priority[irq_num] > max_prio) {
  80             max_irq = irq_num;
  81             max_prio = s->priority[irq_num];
  82         }
  83     }
  84
  85     if (max_irq) {
  86         s->claim = max_irq;
  87         return true;
  88     }
  89
  90     return false;
  91 }
  92
  93 static void ibex_plic_update(IbexPlicState *s)
  94 {
  95     CPUState *cpu;
  96     int level, i;
  97
  98     for (i = 0; i < s->num_cpus; i++) {
  99         cpu = qemu_get_cpu(i);
 100
 101         if (!cpu) {
 102             continue;
 103         }
 104
 105         level = ibex_plic_irqs_pending(s, 0);
 106
 107         riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
 108     }
 109 }
 110
 111 static void ibex_plic_reset(DeviceState *dev)
 112 {
 113     IbexPlicState *s = IBEX_PLIC(dev);
 114
 115     s->threshold = 0x00000000;
 116     s->claim = 0x00000000;
 117 }
 118
 119 static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
 120                                unsigned int size)
 121 {
 122     IbexPlicState *s = opaque;
 123     int offset;
 124     uint32_t ret = 0;
 125
 126     if (addr_between(addr, s->pending_base, s->pending_num)) {
 127         offset = (addr - s->pending_base) / 4;
 128         ret = s->pending[offset];
 129     } else if (addr_between(addr, s->source_base, s->source_num)) {
 130         qemu_log_mask(LOG_UNIMP,
 131                       "%s: Interrupt source mode not supported\n", __func__);
 132     } else if (addr_between(addr, s->priority_base, s->priority_num)) {
 133         offset = (addr - s->priority_base) / 4;
 134         ret = s->priority[offset];
 135     } else if (addr_between(addr, s->enable_base, s->enable_num)) {
 136         offset = (addr - s->enable_base) / 4;
 137         ret = s->enable[offset];
 138     } else if (addr_between(addr, s->threshold_base, 1)) {
 139         ret = s->threshold;
 140     } else if (addr_between(addr, s->claim_base, 1)) {
 141         int pending_num = s->claim / 32;
 142         s->pending[pending_num] &= ~(1 << (s->claim % 32));
 143
 144         /* Set the interrupt as claimed, but not completed */
 145         s->claimed[pending_num] |= 1 << (s->claim % 32);
 146
 147         /* Return the current claimed interrupt */
 148         ret = s->claim;
 149
 150         /* Clear the claimed interrupt */
 151         s->claim = 0x00000000;
 152
 153         /* Update the interrupt status after the claim */
 154         ibex_plic_update(s);
 155     }
 156
 157     return ret;
 158 }
 159
 160 static void ibex_plic_write(void *opaque, hwaddr addr,
 161                             uint64_t value, unsigned int size)
 162 {
 163     IbexPlicState *s = opaque;
 164
 165     if (addr_between(addr, s->pending_base, s->pending_num)) {
 166         qemu_log_mask(LOG_GUEST_ERROR,
 167                       "%s: Pending registers are read only\n", __func__);
 168     } else if (addr_between(addr, s->source_base, s->source_num)) {
 169         qemu_log_mask(LOG_UNIMP,
 170                       "%s: Interrupt source mode not supported\n", __func__);
 171     } else if (addr_between(addr, s->priority_base, s->priority_num)) {
 172         uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
 173         s->priority[irq] = value & 7;
 174         ibex_plic_update(s);
 175     } else if (addr_between(addr, s->enable_base, s->enable_num)) {
 176         uint32_t enable_reg = (addr - s->enable_base) / 4;
 177
 178         s->enable[enable_reg] = value;
 179     } else if (addr_between(addr, s->threshold_base, 1)) {
 180         s->threshold = value & 3;
 181     } else if (addr_between(addr, s->claim_base, 1)) {
 182         if (s->claim == value) {
 183             /* Interrupt was completed */
 184             s->claim = 0;
 185         }
 186         if (s->claimed[value / 32] & 1 << (value % 32)) {
 187             int pending_num = value / 32;
 188
 189             /* This value was already claimed, clear it. */
 190             s->claimed[pending_num] &= ~(1 << (value % 32));
 191
 192             if (s->hidden_pending[pending_num] & (1 << (value % 32))) {
 193                 /*
 194                  * If the bit in hidden_pending is set then that means we
 195                  * received an interrupt between claiming and completing
 196                  * the interrupt that hasn't since been de-asserted.
 197                  * On hardware this would trigger an interrupt, so let's
 198                  * trigger one here as well.
 199                  */
 200                 s->pending[pending_num] |= 1 << (value % 32);
 201             }
 202         }
 203     }
 204
 205     ibex_plic_update(s);
 206 }
 207
 208 static const MemoryRegionOps ibex_plic_ops = {
 209     .read = ibex_plic_read,
 210     .write = ibex_plic_write,
 211     .endianness = DEVICE_NATIVE_ENDIAN,
 212     .valid = {
 213         .min_access_size = 4,
 214         .max_access_size = 4
 215     }
 216 };
 217
 218 static void ibex_plic_irq_request(void *opaque, int irq, int level)
 219 {
 220     IbexPlicState *s = opaque;
 221
 222     ibex_plic_irqs_set_pending(s, irq, level > 0);
 223     ibex_plic_update(s);
 224 }
 225
 226 static Property ibex_plic_properties[] = {
 227     DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
 228     DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 80),
 229
 230     DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
 231     DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 3),
 232
 233     DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x0c),
 234     DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 3),
 235
 236     DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x18),
 237     DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 80),
 238
 239     DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x200),
 240     DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 3),
 241
 242     DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x20c),
 243
 244     DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x210),
 245     DEFINE_PROP_END_OF_LIST(),
 246 };
 247
 248 static void ibex_plic_init(Object *obj)
 249 {
 250     IbexPlicState *s = IBEX_PLIC(obj);
 251
 252     memory_region_init_io(&s->mmio, obj, &ibex_plic_ops, s,
 253                           TYPE_IBEX_PLIC, 0x400);
 254     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 255 }
 256
 257 static void ibex_plic_realize(DeviceState *dev, Error **errp)
 258 {
 259     IbexPlicState *s = IBEX_PLIC(dev);
 260     int i;
 261
 262     s->pending = g_new0(uint32_t, s->pending_num);
 263     s->hidden_pending = g_new0(uint32_t, s->pending_num);
 264     s->claimed = g_new0(uint32_t, s->pending_num);
 265     s->source = g_new0(uint32_t, s->source_num);
 266     s->priority = g_new0(uint32_t, s->priority_num);
 267     s->enable = g_new0(uint32_t, s->enable_num);
 268
 269     qdev_init_gpio_in(dev, ibex_plic_irq_request, s->num_sources);
 270
 271     /*
 272      * We can't allow the supervisor to control SEIP as this would allow the
 273      * supervisor to clear a pending external interrupt which will result in
 274      * a lost interrupt in the case a PLIC is attached. The SEIP bit must be
 275      * hardware controlled when a PLIC is attached.
 276      */
 277     MachineState *ms = MACHINE(qdev_get_machine());
 278     unsigned int smp_cpus = ms->smp.cpus;
 279     for (i = 0; i < smp_cpus; i++) {
 280         RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
 281         if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
 282             error_report("SEIP already claimed");
 283             exit(1);
 284         }
 285     }
 286
 287     msi_nonbroken = true;
 288 }
 289
 290 static void ibex_plic_class_init(ObjectClass *klass, void *data)
 291 {
 292     DeviceClass *dc = DEVICE_CLASS(klass);
 293
 294     dc->reset = ibex_plic_reset;
 295     device_class_set_props(dc, ibex_plic_properties);
 296     dc->realize = ibex_plic_realize;
 297 }
 298
 299 static const TypeInfo ibex_plic_info = {
 300     .name          = TYPE_IBEX_PLIC,
 301     .parent        = TYPE_SYS_BUS_DEVICE,
 302     .instance_size = sizeof(IbexPlicState),
 303     .instance_init = ibex_plic_init,
 304     .class_init    = ibex_plic_class_init,
 305 };
 306
 307 static void ibex_plic_register_types(void)
 308 {
 309     type_register_static(&ibex_plic_info);
 310 }
 311
 312 type_init(ibex_plic_register_types)