2 * ARM Generic Interrupt Controller using KVM in-kernel support
4 * Copyright (c) 2012 Linaro Limited
5 * Written by Peter Maydell
6 * Save/Restore logic added by Christoffer Dall.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "qemu/module.h"
26 #include "hw/sysbus.h"
27 #include "migration/blocker.h"
28 #include "sysemu/kvm.h"
30 #include "gic_internal.h"
31 #include "vgic_common.h"
32 #include "qom/object.h"
34 #define TYPE_KVM_ARM_GIC "kvm-arm-gic"
35 typedef struct KVMARMGICClass KVMARMGICClass
;
36 /* This is reusing the GICState typedef from ARM_GIC_COMMON */
37 DECLARE_OBJ_CHECKERS(GICState
, KVMARMGICClass
,
38 KVM_ARM_GIC
, TYPE_KVM_ARM_GIC
)
40 struct KVMARMGICClass
{
41 ARMGICCommonClass parent_class
;
42 DeviceRealize parent_realize
;
43 void (*parent_reset
)(DeviceState
*dev
);
46 void kvm_arm_gic_set_irq(uint32_t num_irq
, int irq
, int level
)
48 /* Meaning of the 'irq' parameter:
49 * [0..N-1] : external interrupts
50 * [N..N+31] : PPI (internal) interrupts for CPU 0
51 * [N+32..N+63] : PPI (internal interrupts for CPU 1
53 * Convert this to the kernel's desired encoding, which
54 * has separate fields in the irq number for type,
55 * CPU number and interrupt number.
59 if (irq
< (num_irq
- GIC_INTERNAL
)) {
60 /* External interrupt. The kernel numbers these like the GIC
61 * hardware, with external interrupt IDs starting after the
64 irqtype
= KVM_ARM_IRQ_TYPE_SPI
;
68 /* Internal interrupt: decode into (cpu, interrupt id) */
69 irqtype
= KVM_ARM_IRQ_TYPE_PPI
;
70 irq
-= (num_irq
- GIC_INTERNAL
);
71 cpu
= irq
/ GIC_INTERNAL
;
74 kvm_arm_set_irq(cpu
, irqtype
, irq
, !!level
);
77 static void kvm_arm_gicv2_set_irq(void *opaque
, int irq
, int level
)
79 GICState
*s
= (GICState
*)opaque
;
81 kvm_arm_gic_set_irq(s
->num_irq
, irq
, level
);
84 static bool kvm_arm_gic_can_save_restore(GICState
*s
)
86 return s
->dev_fd
>= 0;
89 #define KVM_VGIC_ATTR(offset, cpu) \
90 ((((uint64_t)(cpu) << KVM_DEV_ARM_VGIC_CPUID_SHIFT) & \
91 KVM_DEV_ARM_VGIC_CPUID_MASK) | \
92 (((uint64_t)(offset) << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) & \
93 KVM_DEV_ARM_VGIC_OFFSET_MASK))
95 static void kvm_gicd_access(GICState
*s
, int offset
, int cpu
,
96 uint32_t *val
, bool write
)
98 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_DIST_REGS
,
99 KVM_VGIC_ATTR(offset
, cpu
), val
, write
, &error_abort
);
102 static void kvm_gicc_access(GICState
*s
, int offset
, int cpu
,
103 uint32_t *val
, bool write
)
105 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_CPU_REGS
,
106 KVM_VGIC_ATTR(offset
, cpu
), val
, write
, &error_abort
);
109 #define for_each_irq_reg(_ctr, _max_irq, _field_width) \
110 for (_ctr = 0; _ctr < ((_max_irq) / (32 / (_field_width))); _ctr++)
113 * Translate from the in-kernel field for an IRQ value to/from the qemu
116 typedef void (*vgic_translate_fn
)(GICState
*s
, int irq
, int cpu
,
117 uint32_t *field
, bool to_kernel
);
119 /* synthetic translate function used for clear/set registers to completely
120 * clear a setting using a clear-register before setting the remaining bits
121 * using a set-register */
122 static void translate_clear(GICState
*s
, int irq
, int cpu
,
123 uint32_t *field
, bool to_kernel
)
128 /* does not make sense: qemu model doesn't use set/clear regs */
133 static void translate_group(GICState
*s
, int irq
, int cpu
,
134 uint32_t *field
, bool to_kernel
)
136 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
139 *field
= GIC_DIST_TEST_GROUP(irq
, cm
);
142 GIC_DIST_SET_GROUP(irq
, cm
);
147 static void translate_enabled(GICState
*s
, int irq
, int cpu
,
148 uint32_t *field
, bool to_kernel
)
150 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
153 *field
= GIC_DIST_TEST_ENABLED(irq
, cm
);
156 GIC_DIST_SET_ENABLED(irq
, cm
);
161 static void translate_pending(GICState
*s
, int irq
, int cpu
,
162 uint32_t *field
, bool to_kernel
)
164 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
167 *field
= gic_test_pending(s
, irq
, cm
);
170 GIC_DIST_SET_PENDING(irq
, cm
);
171 /* TODO: Capture is level-line is held high in the kernel */
176 static void translate_active(GICState
*s
, int irq
, int cpu
,
177 uint32_t *field
, bool to_kernel
)
179 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
182 *field
= GIC_DIST_TEST_ACTIVE(irq
, cm
);
185 GIC_DIST_SET_ACTIVE(irq
, cm
);
190 static void translate_trigger(GICState
*s
, int irq
, int cpu
,
191 uint32_t *field
, bool to_kernel
)
194 *field
= (GIC_DIST_TEST_EDGE_TRIGGER(irq
)) ? 0x2 : 0x0;
197 GIC_DIST_SET_EDGE_TRIGGER(irq
);
202 static void translate_priority(GICState
*s
, int irq
, int cpu
,
203 uint32_t *field
, bool to_kernel
)
206 *field
= GIC_DIST_GET_PRIORITY(irq
, cpu
) & 0xff;
208 gic_dist_set_priority(s
, cpu
, irq
,
209 *field
& 0xff, MEMTXATTRS_UNSPECIFIED
);
213 static void translate_targets(GICState
*s
, int irq
, int cpu
,
214 uint32_t *field
, bool to_kernel
)
217 *field
= s
->irq_target
[irq
] & 0xff;
219 s
->irq_target
[irq
] = *field
& 0xff;
223 static void translate_sgisource(GICState
*s
, int irq
, int cpu
,
224 uint32_t *field
, bool to_kernel
)
227 *field
= s
->sgi_pending
[irq
][cpu
] & 0xff;
229 s
->sgi_pending
[irq
][cpu
] = *field
& 0xff;
233 /* Read a register group from the kernel VGIC */
234 static void kvm_dist_get(GICState
*s
, uint32_t offset
, int width
,
235 int maxirq
, vgic_translate_fn translate_fn
)
242 int regsz
= 32 / width
; /* irqs per kernel register */
245 for_each_irq_reg(i
, maxirq
, width
) {
248 while ((cpu
< s
->num_cpu
&& irq
< GIC_INTERNAL
) || cpu
== 0) {
249 kvm_gicd_access(s
, offset
, cpu
, ®
, false);
250 for (j
= 0; j
< regsz
; j
++) {
251 field
= extract32(reg
, j
* width
, width
);
252 translate_fn(s
, irq
+ j
, cpu
, &field
, false);
261 /* Write a register group to the kernel VGIC */
262 static void kvm_dist_put(GICState
*s
, uint32_t offset
, int width
,
263 int maxirq
, vgic_translate_fn translate_fn
)
270 int regsz
= 32 / width
; /* irqs per kernel register */
273 for_each_irq_reg(i
, maxirq
, width
) {
276 while ((cpu
< s
->num_cpu
&& irq
< GIC_INTERNAL
) || cpu
== 0) {
278 for (j
= 0; j
< regsz
; j
++) {
279 translate_fn(s
, irq
+ j
, cpu
, &field
, true);
280 reg
= deposit32(reg
, j
* width
, width
, field
);
282 kvm_gicd_access(s
, offset
, cpu
, ®
, true);
290 static void kvm_arm_gic_put(GICState
*s
)
298 /* Note: We do the restore in a slightly different order than the save
299 * (where the order doesn't matter and is simply ordered according to the
300 * register offset values */
302 /*****************************************************************
306 /* s->ctlr -> GICD_CTLR */
308 kvm_gicd_access(s
, 0x0, 0, ®
, true);
310 /* Sanity checking on GICD_TYPER and s->num_irq, s->num_cpu */
311 kvm_gicd_access(s
, 0x4, 0, ®
, false);
312 num_irq
= ((reg
& 0x1f) + 1) * 32;
313 num_cpu
= ((reg
& 0xe0) >> 5) + 1;
315 if (num_irq
< s
->num_irq
) {
316 fprintf(stderr
, "Restoring %u IRQs, but kernel supports max %d\n",
317 s
->num_irq
, num_irq
);
319 } else if (num_cpu
!= s
->num_cpu
) {
320 fprintf(stderr
, "Restoring %u CPU interfaces, kernel only has %d\n",
321 s
->num_cpu
, num_cpu
);
322 /* Did we not create the VCPUs in the kernel yet? */
326 /* TODO: Consider checking compatibility with the IIDR ? */
328 /* irq_state[n].enabled -> GICD_ISENABLERn */
329 kvm_dist_put(s
, 0x180, 1, s
->num_irq
, translate_clear
);
330 kvm_dist_put(s
, 0x100, 1, s
->num_irq
, translate_enabled
);
332 /* irq_state[n].group -> GICD_IGROUPRn */
333 kvm_dist_put(s
, 0x80, 1, s
->num_irq
, translate_group
);
335 /* s->irq_target[irq] -> GICD_ITARGETSRn
336 * (restore targets before pending to ensure the pending state is set on
337 * the appropriate CPU interfaces in the kernel) */
338 kvm_dist_put(s
, 0x800, 8, s
->num_irq
, translate_targets
);
340 /* irq_state[n].trigger -> GICD_ICFGRn
341 * (restore configuration registers before pending IRQs so we treat
342 * level/edge correctly) */
343 kvm_dist_put(s
, 0xc00, 2, s
->num_irq
, translate_trigger
);
345 /* irq_state[n].pending + irq_state[n].level -> GICD_ISPENDRn */
346 kvm_dist_put(s
, 0x280, 1, s
->num_irq
, translate_clear
);
347 kvm_dist_put(s
, 0x200, 1, s
->num_irq
, translate_pending
);
349 /* irq_state[n].active -> GICD_ISACTIVERn */
350 kvm_dist_put(s
, 0x380, 1, s
->num_irq
, translate_clear
);
351 kvm_dist_put(s
, 0x300, 1, s
->num_irq
, translate_active
);
354 /* s->priorityX[irq] -> ICD_IPRIORITYRn */
355 kvm_dist_put(s
, 0x400, 8, s
->num_irq
, translate_priority
);
357 /* s->sgi_pending -> ICD_CPENDSGIRn */
358 kvm_dist_put(s
, 0xf10, 8, GIC_NR_SGIS
, translate_clear
);
359 kvm_dist_put(s
, 0xf20, 8, GIC_NR_SGIS
, translate_sgisource
);
362 /*****************************************************************
363 * CPU Interface(s) State
366 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
367 /* s->cpu_ctlr[cpu] -> GICC_CTLR */
368 reg
= s
->cpu_ctlr
[cpu
];
369 kvm_gicc_access(s
, 0x00, cpu
, ®
, true);
371 /* s->priority_mask[cpu] -> GICC_PMR */
372 reg
= (s
->priority_mask
[cpu
] & 0xff);
373 kvm_gicc_access(s
, 0x04, cpu
, ®
, true);
375 /* s->bpr[cpu] -> GICC_BPR */
376 reg
= (s
->bpr
[cpu
] & 0x7);
377 kvm_gicc_access(s
, 0x08, cpu
, ®
, true);
379 /* s->abpr[cpu] -> GICC_ABPR */
380 reg
= (s
->abpr
[cpu
] & 0x7);
381 kvm_gicc_access(s
, 0x1c, cpu
, ®
, true);
383 /* s->apr[n][cpu] -> GICC_APRn */
384 for (i
= 0; i
< 4; i
++) {
385 reg
= s
->apr
[i
][cpu
];
386 kvm_gicc_access(s
, 0xd0 + i
* 4, cpu
, ®
, true);
391 static void kvm_arm_gic_get(GICState
*s
)
397 /*****************************************************************
401 /* GICD_CTLR -> s->ctlr */
402 kvm_gicd_access(s
, 0x0, 0, ®
, false);
405 /* Sanity checking on GICD_TYPER -> s->num_irq, s->num_cpu */
406 kvm_gicd_access(s
, 0x4, 0, ®
, false);
407 s
->num_irq
= ((reg
& 0x1f) + 1) * 32;
408 s
->num_cpu
= ((reg
& 0xe0) >> 5) + 1;
410 if (s
->num_irq
> GIC_MAXIRQ
) {
411 fprintf(stderr
, "Too many IRQs reported from the kernel: %d\n",
417 kvm_gicd_access(s
, 0x8, 0, ®
, false);
419 /* Clear all the IRQ settings */
420 for (i
= 0; i
< s
->num_irq
; i
++) {
421 memset(&s
->irq_state
[i
], 0, sizeof(s
->irq_state
[0]));
424 /* GICD_IGROUPRn -> irq_state[n].group */
425 kvm_dist_get(s
, 0x80, 1, s
->num_irq
, translate_group
);
427 /* GICD_ISENABLERn -> irq_state[n].enabled */
428 kvm_dist_get(s
, 0x100, 1, s
->num_irq
, translate_enabled
);
430 /* GICD_ISPENDRn -> irq_state[n].pending + irq_state[n].level */
431 kvm_dist_get(s
, 0x200, 1, s
->num_irq
, translate_pending
);
433 /* GICD_ISACTIVERn -> irq_state[n].active */
434 kvm_dist_get(s
, 0x300, 1, s
->num_irq
, translate_active
);
436 /* GICD_ICFRn -> irq_state[n].trigger */
437 kvm_dist_get(s
, 0xc00, 2, s
->num_irq
, translate_trigger
);
439 /* GICD_IPRIORITYRn -> s->priorityX[irq] */
440 kvm_dist_get(s
, 0x400, 8, s
->num_irq
, translate_priority
);
442 /* GICD_ITARGETSRn -> s->irq_target[irq] */
443 kvm_dist_get(s
, 0x800, 8, s
->num_irq
, translate_targets
);
445 /* GICD_CPENDSGIRn -> s->sgi_pending */
446 kvm_dist_get(s
, 0xf10, 8, GIC_NR_SGIS
, translate_sgisource
);
449 /*****************************************************************
450 * CPU Interface(s) State
453 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
454 /* GICC_CTLR -> s->cpu_ctlr[cpu] */
455 kvm_gicc_access(s
, 0x00, cpu
, ®
, false);
456 s
->cpu_ctlr
[cpu
] = reg
;
458 /* GICC_PMR -> s->priority_mask[cpu] */
459 kvm_gicc_access(s
, 0x04, cpu
, ®
, false);
460 s
->priority_mask
[cpu
] = (reg
& 0xff);
462 /* GICC_BPR -> s->bpr[cpu] */
463 kvm_gicc_access(s
, 0x08, cpu
, ®
, false);
464 s
->bpr
[cpu
] = (reg
& 0x7);
466 /* GICC_ABPR -> s->abpr[cpu] */
467 kvm_gicc_access(s
, 0x1c, cpu
, ®
, false);
468 s
->abpr
[cpu
] = (reg
& 0x7);
470 /* GICC_APRn -> s->apr[n][cpu] */
471 for (i
= 0; i
< 4; i
++) {
472 kvm_gicc_access(s
, 0xd0 + i
* 4, cpu
, ®
, false);
473 s
->apr
[i
][cpu
] = reg
;
478 static void kvm_arm_gic_reset(DeviceState
*dev
)
480 GICState
*s
= ARM_GIC_COMMON(dev
);
481 KVMARMGICClass
*kgc
= KVM_ARM_GIC_GET_CLASS(s
);
483 kgc
->parent_reset(dev
);
485 if (kvm_arm_gic_can_save_restore(s
)) {
490 static void kvm_arm_gic_realize(DeviceState
*dev
, Error
**errp
)
493 GICState
*s
= KVM_ARM_GIC(dev
);
494 KVMARMGICClass
*kgc
= KVM_ARM_GIC_GET_CLASS(s
);
495 Error
*local_err
= NULL
;
498 kgc
->parent_realize(dev
, &local_err
);
500 error_propagate(errp
, local_err
);
504 if (s
->security_extn
) {
505 error_setg(errp
, "the in-kernel VGIC does not implement the "
506 "security extensions");
511 error_setg(errp
, "the in-kernel VGIC does not implement the "
512 "virtualization extensions");
516 if (!kvm_arm_gic_can_save_restore(s
)) {
517 error_setg(&s
->migration_blocker
, "This operating system kernel does "
518 "not support vGICv2 migration");
519 if (migrate_add_blocker(s
->migration_blocker
, errp
) < 0) {
520 error_free(s
->migration_blocker
);
525 gic_init_irqs_and_mmio(s
, kvm_arm_gicv2_set_irq
, NULL
, NULL
);
527 for (i
= 0; i
< s
->num_irq
- GIC_INTERNAL
; i
++) {
528 qemu_irq irq
= qdev_get_gpio_in(dev
, i
);
529 kvm_irqchip_set_qemuirq_gsi(kvm_state
, irq
, i
);
532 /* Try to create the device via the device control API */
534 ret
= kvm_create_device(kvm_state
, KVM_DEV_TYPE_ARM_VGIC_V2
, false);
538 /* Newstyle API is used, we may have attributes */
539 if (kvm_device_check_attr(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_NR_IRQS
, 0)) {
540 uint32_t numirqs
= s
->num_irq
;
541 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_NR_IRQS
, 0,
542 &numirqs
, true, &error_abort
);
544 /* Tell the kernel to complete VGIC initialization now */
545 if (kvm_device_check_attr(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_CTRL
,
546 KVM_DEV_ARM_VGIC_CTRL_INIT
)) {
547 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_CTRL
,
548 KVM_DEV_ARM_VGIC_CTRL_INIT
, NULL
, true,
551 } else if (kvm_check_extension(kvm_state
, KVM_CAP_DEVICE_CTRL
)) {
552 error_setg_errno(errp
, -ret
, "error creating in-kernel VGIC");
553 error_append_hint(errp
,
554 "Perhaps the host CPU does not support GICv2?\n");
555 } else if (ret
!= -ENODEV
&& ret
!= -ENOTSUP
) {
557 * Very ancient kernel without KVM_CAP_DEVICE_CTRL: assume that
558 * ENODEV or ENOTSUP mean "can't create GICv2 with KVM_CREATE_DEVICE",
559 * and that we will get a GICv2 via KVM_CREATE_IRQCHIP.
561 error_setg_errno(errp
, -ret
, "error creating in-kernel VGIC");
566 kvm_arm_register_device(&s
->iomem
,
567 (KVM_ARM_DEVICE_VGIC_V2
<< KVM_ARM_DEVICE_ID_SHIFT
)
568 | KVM_VGIC_V2_ADDR_TYPE_DIST
,
569 KVM_DEV_ARM_VGIC_GRP_ADDR
,
570 KVM_VGIC_V2_ADDR_TYPE_DIST
,
572 /* CPU interface for current core. Unlike arm_gic, we don't
573 * provide the "interface for core #N" memory regions, because
574 * cores with a VGIC don't have those.
576 kvm_arm_register_device(&s
->cpuiomem
[0],
577 (KVM_ARM_DEVICE_VGIC_V2
<< KVM_ARM_DEVICE_ID_SHIFT
)
578 | KVM_VGIC_V2_ADDR_TYPE_CPU
,
579 KVM_DEV_ARM_VGIC_GRP_ADDR
,
580 KVM_VGIC_V2_ADDR_TYPE_CPU
,
583 if (kvm_has_gsi_routing()) {
584 /* set up irq routing */
585 for (i
= 0; i
< s
->num_irq
- GIC_INTERNAL
; ++i
) {
586 kvm_irqchip_add_irq_route(kvm_state
, i
, 0, i
);
589 kvm_gsi_routing_allowed
= true;
591 kvm_irqchip_commit_routes(kvm_state
);
595 static void kvm_arm_gic_class_init(ObjectClass
*klass
, void *data
)
597 DeviceClass
*dc
= DEVICE_CLASS(klass
);
598 ARMGICCommonClass
*agcc
= ARM_GIC_COMMON_CLASS(klass
);
599 KVMARMGICClass
*kgc
= KVM_ARM_GIC_CLASS(klass
);
601 agcc
->pre_save
= kvm_arm_gic_get
;
602 agcc
->post_load
= kvm_arm_gic_put
;
603 device_class_set_parent_realize(dc
, kvm_arm_gic_realize
,
604 &kgc
->parent_realize
);
605 device_class_set_parent_reset(dc
, kvm_arm_gic_reset
, &kgc
->parent_reset
);
608 static const TypeInfo kvm_arm_gic_info
= {
609 .name
= TYPE_KVM_ARM_GIC
,
610 .parent
= TYPE_ARM_GIC_COMMON
,
611 .instance_size
= sizeof(GICState
),
612 .class_init
= kvm_arm_gic_class_init
,
613 .class_size
= sizeof(KVMARMGICClass
),
616 static void kvm_arm_gic_register_types(void)
618 type_register_static(&kvm_arm_gic_info
);
621 type_init(kvm_arm_gic_register_types
)