include/hw/dma/pl080.h

   1 /*
   2  * ARM PrimeCell PL080/PL081 DMA controller
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Copyright (c) 2018 Linaro Limited
   6  * Written by Paul Brook, Peter Maydell
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 or
  10  * (at your option) any later version.
  11  */
  12
  13 /*
  14  * This is a model of the Arm PrimeCell PL080/PL081 DMA controller:
  15  * The PL080 TRM is:
  16  * https://developer.arm.com/documentation/ddi0196/latest
  17  * and the PL081 TRM is:
  18  * https://developer.arm.com/documentation/ddi0218/latest
  19  *
  20  * QEMU interface:
  21  * + sysbus IRQ 0: DMACINTR combined interrupt line
  22  * + sysbus IRQ 1: DMACINTERR error interrupt request
  23  * + sysbus IRQ 2: DMACINTTC count interrupt request
  24  * + sysbus MMIO region 0: MemoryRegion for the device's registers
  25  * + QOM property "downstream": MemoryRegion defining where DMA
  26  *   bus master transactions are made
  27  */
  28
  29 #ifndef HW_DMA_PL080_H
  30 #define HW_DMA_PL080_H
  31
  32 #include "hw/sysbus.h"
  33 #include "qom/object.h"
  34
  35 #define PL080_MAX_CHANNELS 8
  36
  37 typedef struct {
  38     uint32_t src;
  39     uint32_t dest;
  40     uint32_t lli;
  41     uint32_t ctrl;
  42     uint32_t conf;
  43 } pl080_channel;
  44
  45 #define TYPE_PL080 "pl080"
  46 #define TYPE_PL081 "pl081"
  47 OBJECT_DECLARE_SIMPLE_TYPE(PL080State, PL080)
  48
  49 struct PL080State {
  50     SysBusDevice parent_obj;
  51
  52     MemoryRegion iomem;
  53     uint8_t tc_int;
  54     uint8_t tc_mask;
  55     uint8_t err_int;
  56     uint8_t err_mask;
  57     uint32_t conf;
  58     uint32_t sync;
  59     uint32_t req_single;
  60     uint32_t req_burst;
  61     pl080_channel chan[PL080_MAX_CHANNELS];
  62     int nchannels;
  63     /* Flag to avoid recursive DMA invocations.  */
  64     int running;
  65     qemu_irq irq;
  66     qemu_irq interr;
  67     qemu_irq inttc;
  68
  69     MemoryRegion *downstream;
  70     AddressSpace downstream_as;
  71 };
  72
  73 #endif