target-ppc/mmu-hash64.c

   1 /*
   2  *  PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *  Copyright (c) 2013 David Gibson, IBM Corporation
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "exec/helper-proto.h"
  23 #include "sysemu/kvm.h"
  24 #include "kvm_ppc.h"
  25 #include "mmu-hash64.h"
  26
  27 //#define DEBUG_SLB
  28
  29 #ifdef DEBUG_SLB
  30 #  define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
  31 #else
  32 #  define LOG_SLB(...) do { } while (0)
  33 #endif
  34
  35 /*
  36  * Used to indicate whether we have allocated htab in the
  37  * host kernel
  38  */
  39 bool kvmppc_kern_htab;
  40 /*
  41  * SLB handling
  42  */
  43
  44 static ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr)
  45 {
  46     uint64_t esid_256M, esid_1T;
  47     int n;
  48
  49     LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
  50
  51     esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
  52     esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
  53
  54     for (n = 0; n < env->slb_nr; n++) {
  55         ppc_slb_t *slb = &env->slb[n];
  56
  57         LOG_SLB("%s: slot %d %016" PRIx64 " %016"
  58                     PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
  59         /* We check for 1T matches on all MMUs here - if the MMU
  60          * doesn't have 1T segment support, we will have prevented 1T
  61          * entries from being inserted in the slbmte code. */
  62         if (((slb->esid == esid_256M) &&
  63              ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
  64             || ((slb->esid == esid_1T) &&
  65                 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
  66             return slb;
  67         }
  68     }
  69
  70     return NULL;
  71 }
  72
  73 void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
  74 {
  75     int i;
  76     uint64_t slbe, slbv;
  77
  78     cpu_synchronize_state(CPU(ppc_env_get_cpu(env)));
  79
  80     cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
  81     for (i = 0; i < env->slb_nr; i++) {
  82         slbe = env->slb[i].esid;
  83         slbv = env->slb[i].vsid;
  84         if (slbe == 0 && slbv == 0) {
  85             continue;
  86         }
  87         cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
  88                     i, slbe, slbv);
  89     }
  90 }
  91
  92 void helper_slbia(CPUPPCState *env)
  93 {
  94     PowerPCCPU *cpu = ppc_env_get_cpu(env);
  95     int n, do_invalidate;
  96
  97     do_invalidate = 0;
  98     /* XXX: Warning: slbia never invalidates the first segment */
  99     for (n = 1; n < env->slb_nr; n++) {
 100         ppc_slb_t *slb = &env->slb[n];
 101
 102         if (slb->esid & SLB_ESID_V) {
 103             slb->esid &= ~SLB_ESID_V;
 104             /* XXX: given the fact that segment size is 256 MB or 1TB,
 105              *      and we still don't have a tlb_flush_mask(env, n, mask)
 106              *      in QEMU, we just invalidate all TLBs
 107              */
 108             do_invalidate = 1;
 109         }
 110     }
 111     if (do_invalidate) {
 112         tlb_flush(CPU(cpu), 1);
 113     }
 114 }
 115
 116 void helper_slbie(CPUPPCState *env, target_ulong addr)
 117 {
 118     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 119     ppc_slb_t *slb;
 120
 121     slb = slb_lookup(env, addr);
 122     if (!slb) {
 123         return;
 124     }
 125
 126     if (slb->esid & SLB_ESID_V) {
 127         slb->esid &= ~SLB_ESID_V;
 128
 129         /* XXX: given the fact that segment size is 256 MB or 1TB,
 130          *      and we still don't have a tlb_flush_mask(env, n, mask)
 131          *      in QEMU, we just invalidate all TLBs
 132          */
 133         tlb_flush(CPU(cpu), 1);
 134     }
 135 }
 136
 137 int ppc_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
 138 {
 139     int slot = rb & 0xfff;
 140     ppc_slb_t *slb = &env->slb[slot];
 141
 142     if (rb & (0x1000 - env->slb_nr)) {
 143         return -1; /* Reserved bits set or slot too high */
 144     }
 145     if (rs & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
 146         return -1; /* Bad segment size */
 147     }
 148     if ((rs & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
 149         return -1; /* 1T segment on MMU that doesn't support it */
 150     }
 151
 152     /* Mask out the slot number as we store the entry */
 153     slb->esid = rb & (SLB_ESID_ESID | SLB_ESID_V);
 154     slb->vsid = rs;
 155
 156     LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
 157             " %016" PRIx64 "\n", __func__, slot, rb, rs,
 158             slb->esid, slb->vsid);
 159
 160     return 0;
 161 }
 162
 163 static int ppc_load_slb_esid(CPUPPCState *env, target_ulong rb,
 164                              target_ulong *rt)
 165 {
 166     int slot = rb & 0xfff;
 167     ppc_slb_t *slb = &env->slb[slot];
 168
 169     if (slot >= env->slb_nr) {
 170         return -1;
 171     }
 172
 173     *rt = slb->esid;
 174     return 0;
 175 }
 176
 177 static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,
 178                              target_ulong *rt)
 179 {
 180     int slot = rb & 0xfff;
 181     ppc_slb_t *slb = &env->slb[slot];
 182
 183     if (slot >= env->slb_nr) {
 184         return -1;
 185     }
 186
 187     *rt = slb->vsid;
 188     return 0;
 189 }
 190
 191 void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
 192 {
 193     if (ppc_store_slb(env, rb, rs) < 0) {
 194         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 195                                    POWERPC_EXCP_INVAL);
 196     }
 197 }
 198
 199 target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
 200 {
 201     target_ulong rt = 0;
 202
 203     if (ppc_load_slb_esid(env, rb, &rt) < 0) {
 204         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 205                                    POWERPC_EXCP_INVAL);
 206     }
 207     return rt;
 208 }
 209
 210 target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
 211 {
 212     target_ulong rt = 0;
 213
 214     if (ppc_load_slb_vsid(env, rb, &rt) < 0) {
 215         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 216                                    POWERPC_EXCP_INVAL);
 217     }
 218     return rt;
 219 }
 220
 221 /*
 222  * 64-bit hash table MMU handling
 223  */
 224
 225 static int ppc_hash64_pte_prot(CPUPPCState *env,
 226                                ppc_slb_t *slb, ppc_hash_pte64_t pte)
 227 {
 228     unsigned pp, key;
 229     /* Some pp bit combinations have undefined behaviour, so default
 230      * to no access in those cases */
 231     int prot = 0;
 232
 233     key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
 234              : (slb->vsid & SLB_VSID_KS));
 235     pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61);
 236
 237     if (key == 0) {
 238         switch (pp) {
 239         case 0x0:
 240         case 0x1:
 241         case 0x2:
 242             prot = PAGE_READ | PAGE_WRITE;
 243             break;
 244
 245         case 0x3:
 246         case 0x6:
 247             prot = PAGE_READ;
 248             break;
 249         }
 250     } else {
 251         switch (pp) {
 252         case 0x0:
 253         case 0x6:
 254             prot = 0;
 255             break;
 256
 257         case 0x1:
 258         case 0x3:
 259             prot = PAGE_READ;
 260             break;
 261
 262         case 0x2:
 263             prot = PAGE_READ | PAGE_WRITE;
 264             break;
 265         }
 266     }
 267
 268     /* No execute if either noexec or guarded bits set */
 269     if (!(pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G)
 270         || (slb->vsid & SLB_VSID_N)) {
 271         prot |= PAGE_EXEC;
 272     }
 273
 274     return prot;
 275 }
 276
 277 static int ppc_hash64_amr_prot(CPUPPCState *env, ppc_hash_pte64_t pte)
 278 {
 279     int key, amrbits;
 280     int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 281
 282
 283     /* Only recent MMUs implement Virtual Page Class Key Protection */
 284     if (!(env->mmu_model & POWERPC_MMU_AMR)) {
 285         return prot;
 286     }
 287
 288     key = HPTE64_R_KEY(pte.pte1);
 289     amrbits = (env->spr[SPR_AMR] >> 2*(31 - key)) & 0x3;
 290
 291     /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */
 292     /*         env->spr[SPR_AMR]); */
 293
 294     /*
 295      * A store is permitted if the AMR bit is 0. Remove write
 296      * protection if it is set.
 297      */
 298     if (amrbits & 0x2) {
 299         prot &= ~PAGE_WRITE;
 300     }
 301     /*
 302      * A load is permitted if the AMR bit is 0. Remove read
 303      * protection if it is set.
 304      */
 305     if (amrbits & 0x1) {
 306         prot &= ~PAGE_READ;
 307     }
 308
 309     return prot;
 310 }
 311
 312 uint64_t ppc_hash64_start_access(PowerPCCPU *cpu, target_ulong pte_index)
 313 {
 314     uint64_t token = 0;
 315     hwaddr pte_offset;
 316
 317     pte_offset = pte_index * HASH_PTE_SIZE_64;
 318     if (kvmppc_kern_htab) {
 319         /*
 320          * HTAB is controlled by KVM. Fetch the PTEG into a new buffer.
 321          */
 322         token = kvmppc_hash64_read_pteg(cpu, pte_index);
 323         if (token) {
 324             return token;
 325         }
 326         /*
 327          * pteg read failed, even though we have allocated htab via
 328          * kvmppc_reset_htab.
 329          */
 330         return 0;
 331     }
 332     /*
 333      * HTAB is controlled by QEMU. Just point to the internally
 334      * accessible PTEG.
 335      */
 336     if (cpu->env.external_htab) {
 337         token = (uint64_t)(uintptr_t) cpu->env.external_htab + pte_offset;
 338     } else if (cpu->env.htab_base) {
 339         token = cpu->env.htab_base + pte_offset;
 340     }
 341     return token;
 342 }
 343
 344 void ppc_hash64_stop_access(uint64_t token)
 345 {
 346     if (kvmppc_kern_htab) {
 347         kvmppc_hash64_free_pteg(token);
 348     }
 349 }
 350
 351 static hwaddr ppc_hash64_pteg_search(CPUPPCState *env, hwaddr hash,
 352                                      bool secondary, target_ulong ptem,
 353                                      ppc_hash_pte64_t *pte)
 354 {
 355     int i;
 356     uint64_t token;
 357     target_ulong pte0, pte1;
 358     target_ulong pte_index;
 359
 360     pte_index = (hash & env->htab_mask) * HPTES_PER_GROUP;
 361     token = ppc_hash64_start_access(ppc_env_get_cpu(env), pte_index);
 362     if (!token) {
 363         return -1;
 364     }
 365     for (i = 0; i < HPTES_PER_GROUP; i++) {
 366         pte0 = ppc_hash64_load_hpte0(env, token, i);
 367         pte1 = ppc_hash64_load_hpte1(env, token, i);
 368
 369         if ((pte0 & HPTE64_V_VALID)
 370             && (secondary == !!(pte0 & HPTE64_V_SECONDARY))
 371             && HPTE64_V_COMPARE(pte0, ptem)) {
 372             pte->pte0 = pte0;
 373             pte->pte1 = pte1;
 374             ppc_hash64_stop_access(token);
 375             return (pte_index + i) * HASH_PTE_SIZE_64;
 376         }
 377     }
 378     ppc_hash64_stop_access(token);
 379     /*
 380      * We didn't find a valid entry.
 381      */
 382     return -1;
 383 }
 384
 385 static uint64_t ppc_hash64_page_shift(ppc_slb_t *slb)
 386 {
 387     uint64_t epnshift;
 388
 389     /* Page size according to the SLB, which we use to generate the
 390      * EPN for hash table lookup..  When we implement more recent MMU
 391      * extensions this might be different from the actual page size
 392      * encoded in the PTE */
 393     if ((slb->vsid & SLB_VSID_LLP_MASK) == SLB_VSID_4K) {
 394         epnshift = TARGET_PAGE_BITS;
 395     } else if ((slb->vsid & SLB_VSID_LLP_MASK) == SLB_VSID_64K) {
 396         epnshift = TARGET_PAGE_BITS_64K;
 397     } else {
 398         epnshift = TARGET_PAGE_BITS_16M;
 399     }
 400     return epnshift;
 401 }
 402
 403 static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env,
 404                                      ppc_slb_t *slb, target_ulong eaddr,
 405                                      ppc_hash_pte64_t *pte)
 406 {
 407     hwaddr pte_offset;
 408     hwaddr hash;
 409     uint64_t vsid, epnshift, epnmask, epn, ptem;
 410
 411     epnshift = ppc_hash64_page_shift(slb);
 412     epnmask = ~((1ULL << epnshift) - 1);
 413
 414     if (slb->vsid & SLB_VSID_B) {
 415         /* 1TB segment */
 416         vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
 417         epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask;
 418         hash = vsid ^ (vsid << 25) ^ (epn >> epnshift);
 419     } else {
 420         /* 256M segment */
 421         vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
 422         epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
 423         hash = vsid ^ (epn >> epnshift);
 424     }
 425     ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
 426
 427     /* Page address translation */
 428     qemu_log_mask(CPU_LOG_MMU,
 429             "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
 430             " hash " TARGET_FMT_plx "\n",
 431             env->htab_base, env->htab_mask, hash);
 432
 433     /* Primary PTEG lookup */
 434     qemu_log_mask(CPU_LOG_MMU,
 435             "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 436             " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
 437             " hash=" TARGET_FMT_plx "\n",
 438             env->htab_base, env->htab_mask, vsid, ptem,  hash);
 439     pte_offset = ppc_hash64_pteg_search(env, hash, 0, ptem, pte);
 440
 441     if (pte_offset == -1) {
 442         /* Secondary PTEG lookup */
 443         qemu_log_mask(CPU_LOG_MMU,
 444                 "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 445                 " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
 446                 " hash=" TARGET_FMT_plx "\n", env->htab_base,
 447                 env->htab_mask, vsid, ptem, ~hash);
 448
 449         pte_offset = ppc_hash64_pteg_search(env, ~hash, 1, ptem, pte);
 450     }
 451
 452     return pte_offset;
 453 }
 454
 455 static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb, ppc_hash_pte64_t pte,
 456                                    target_ulong eaddr)
 457 {
 458     hwaddr mask;
 459     int target_page_bits;
 460     hwaddr rpn = pte.pte1 & HPTE64_R_RPN;
 461     /*
 462      * We support 4K, 64K and 16M now
 463      */
 464     target_page_bits = ppc_hash64_page_shift(slb);
 465     mask = (1ULL << target_page_bits) - 1;
 466     return (rpn & ~mask) | (eaddr & mask);
 467 }
 468
 469 int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
 470                                 int rwx, int mmu_idx)
 471 {
 472     CPUState *cs = CPU(cpu);
 473     CPUPPCState *env = &cpu->env;
 474     ppc_slb_t *slb;
 475     hwaddr pte_offset;
 476     ppc_hash_pte64_t pte;
 477     int pp_prot, amr_prot, prot;
 478     uint64_t new_pte1;
 479     const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
 480     hwaddr raddr;
 481
 482     assert((rwx == 0) || (rwx == 1) || (rwx == 2));
 483
 484     /* 1. Handle real mode accesses */
 485     if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
 486         /* Translation is off */
 487         /* In real mode the top 4 effective address bits are ignored */
 488         raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
 489         tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
 490                      PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
 491                      TARGET_PAGE_SIZE);
 492         return 0;
 493     }
 494
 495     /* 2. Translation is on, so look up the SLB */
 496     slb = slb_lookup(env, eaddr);
 497
 498     if (!slb) {
 499         if (rwx == 2) {
 500             cs->exception_index = POWERPC_EXCP_ISEG;
 501             env->error_code = 0;
 502         } else {
 503             cs->exception_index = POWERPC_EXCP_DSEG;
 504             env->error_code = 0;
 505             env->spr[SPR_DAR] = eaddr;
 506         }
 507         return 1;
 508     }
 509
 510     /* 3. Check for segment level no-execute violation */
 511     if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
 512         cs->exception_index = POWERPC_EXCP_ISI;
 513         env->error_code = 0x10000000;
 514         return 1;
 515     }
 516
 517     /* 4. Locate the PTE in the hash table */
 518     pte_offset = ppc_hash64_htab_lookup(env, slb, eaddr, &pte);
 519     if (pte_offset == -1) {
 520         if (rwx == 2) {
 521             cs->exception_index = POWERPC_EXCP_ISI;
 522             env->error_code = 0x40000000;
 523         } else {
 524             cs->exception_index = POWERPC_EXCP_DSI;
 525             env->error_code = 0;
 526             env->spr[SPR_DAR] = eaddr;
 527             if (rwx == 1) {
 528                 env->spr[SPR_DSISR] = 0x42000000;
 529             } else {
 530                 env->spr[SPR_DSISR] = 0x40000000;
 531             }
 532         }
 533         return 1;
 534     }
 535     qemu_log_mask(CPU_LOG_MMU,
 536                 "found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
 537
 538     /* 5. Check access permissions */
 539
 540     pp_prot = ppc_hash64_pte_prot(env, slb, pte);
 541     amr_prot = ppc_hash64_amr_prot(env, pte);
 542     prot = pp_prot & amr_prot;
 543
 544     if ((need_prot[rwx] & ~prot) != 0) {
 545         /* Access right violation */
 546         qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
 547         if (rwx == 2) {
 548             cs->exception_index = POWERPC_EXCP_ISI;
 549             env->error_code = 0x08000000;
 550         } else {
 551             target_ulong dsisr = 0;
 552
 553             cs->exception_index = POWERPC_EXCP_DSI;
 554             env->error_code = 0;
 555             env->spr[SPR_DAR] = eaddr;
 556             if (need_prot[rwx] & ~pp_prot) {
 557                 dsisr |= 0x08000000;
 558             }
 559             if (rwx == 1) {
 560                 dsisr |= 0x02000000;
 561             }
 562             if (need_prot[rwx] & ~amr_prot) {
 563                 dsisr |= 0x00200000;
 564             }
 565             env->spr[SPR_DSISR] = dsisr;
 566         }
 567         return 1;
 568     }
 569
 570     qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
 571
 572     /* 6. Update PTE referenced and changed bits if necessary */
 573
 574     new_pte1 = pte.pte1 | HPTE64_R_R; /* set referenced bit */
 575     if (rwx == 1) {
 576         new_pte1 |= HPTE64_R_C; /* set changed (dirty) bit */
 577     } else {
 578         /* Treat the page as read-only for now, so that a later write
 579          * will pass through this function again to set the C bit */
 580         prot &= ~PAGE_WRITE;
 581     }
 582
 583     if (new_pte1 != pte.pte1) {
 584         ppc_hash64_store_hpte(env, pte_offset / HASH_PTE_SIZE_64,
 585                               pte.pte0, new_pte1);
 586     }
 587
 588     /* 7. Determine the real address from the PTE */
 589
 590     raddr = ppc_hash64_pte_raddr(slb, pte, eaddr);
 591
 592     tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
 593                  prot, mmu_idx, TARGET_PAGE_SIZE);
 594
 595     return 0;
 596 }
 597
 598 hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
 599 {
 600     ppc_slb_t *slb;
 601     hwaddr pte_offset;
 602     ppc_hash_pte64_t pte;
 603
 604     if (msr_dr == 0) {
 605         /* In real mode the top 4 effective address bits are ignored */
 606         return addr & 0x0FFFFFFFFFFFFFFFULL;
 607     }
 608
 609     slb = slb_lookup(env, addr);
 610     if (!slb) {
 611         return -1;
 612     }
 613
 614     pte_offset = ppc_hash64_htab_lookup(env, slb, addr, &pte);
 615     if (pte_offset == -1) {
 616         return -1;
 617     }
 618
 619     return ppc_hash64_pte_raddr(slb, pte, addr) & TARGET_PAGE_MASK;
 620 }
 621
 622 void ppc_hash64_store_hpte(CPUPPCState *env,
 623                            target_ulong pte_index,
 624                            target_ulong pte0, target_ulong pte1)
 625 {
 626     CPUState *cs = CPU(ppc_env_get_cpu(env));
 627
 628     if (kvmppc_kern_htab) {
 629         kvmppc_hash64_write_pte(env, pte_index, pte0, pte1);
 630         return;
 631     }
 632
 633     pte_index *= HASH_PTE_SIZE_64;
 634     if (env->external_htab) {
 635         stq_p(env->external_htab + pte_index, pte0);
 636         stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64/2, pte1);
 637     } else {
 638         stq_phys(cs->as, env->htab_base + pte_index, pte0);
 639         stq_phys(cs->as, env->htab_base + pte_index + HASH_PTE_SIZE_64/2, pte1);
 640     }
 641 }