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Introduce Xen PCI Passthrough, MSI
[qemu/ar7.git] / hw / xen_pt_config_init.c
blob00eb3d997d3c34325f9c565878830ccbfee01f53
1 /*
2 * Copyright (c) 2007, Neocleus Corporation.
3 * Copyright (c) 2007, Intel Corporation.
4 *
5 * This work is licensed under the terms of the GNU GPL, version 2. See
6 * the COPYING file in the top-level directory.
7 *
8 * Alex Novik <alex@neocleus.com>
9 * Allen Kay <allen.m.kay@intel.com>
10 * Guy Zana <guy@neocleus.com>
11 *
12 * This file implements direct PCI assignment to a HVM guest
13 */
14
15 #include "qemu-timer.h"
16 #include "xen_backend.h"
17 #include "xen_pt.h"
18
19 #define XEN_PT_MERGE_VALUE(value, data, val_mask) \
20 (((value) & (val_mask)) | ((data) & ~(val_mask)))
21
22 #define XEN_PT_INVALID_REG 0xFFFFFFFF /* invalid register value */
23
24 /* prototype */
25
26 static int xen_pt_ptr_reg_init(XenPCIPassthroughState *s, XenPTRegInfo *reg,
27 uint32_t real_offset, uint32_t *data);
28
29
30 /* helper */
31
32 /* A return value of 1 means the capability should NOT be exposed to guest. */
33 static int xen_pt_hide_dev_cap(const XenHostPCIDevice *d, uint8_t grp_id)
34 {
35 switch (grp_id) {
36 case PCI_CAP_ID_EXP:
37 /* The PCI Express Capability Structure of the VF of Intel 82599 10GbE
38 * Controller looks trivial, e.g., the PCI Express Capabilities
39 * Register is 0. We should not try to expose it to guest.
40 *
41 * The datasheet is available at
42 * http://download.intel.com/design/network/datashts/82599_datasheet.pdf
43 *
44 * See 'Table 9.7. VF PCIe Configuration Space' of the datasheet, the
45 * PCI Express Capability Structure of the VF of Intel 82599 10GbE
46 * Controller looks trivial, e.g., the PCI Express Capabilities
47 * Register is 0, so the Capability Version is 0 and
48 * xen_pt_pcie_size_init() would fail.
49 */
50 if (d->vendor_id == PCI_VENDOR_ID_INTEL &&
51 d->device_id == PCI_DEVICE_ID_INTEL_82599_SFP_VF) {
52 return 1;
53 }
54 break;
55 }
56 return 0;
57 }
58
59 /* find emulate register group entry */
60 XenPTRegGroup *xen_pt_find_reg_grp(XenPCIPassthroughState *s, uint32_t address)
61 {
62 XenPTRegGroup *entry = NULL;
63
64 /* find register group entry */
65 QLIST_FOREACH(entry, &s->reg_grps, entries) {
66 /* check address */
67 if ((entry->base_offset <= address)
68 && ((entry->base_offset + entry->size) > address)) {
69 return entry;
70 }
71 }
72
73 /* group entry not found */
74 return NULL;
75 }
76
77 /* find emulate register entry */
78 XenPTReg *xen_pt_find_reg(XenPTRegGroup *reg_grp, uint32_t address)
79 {
80 XenPTReg *reg_entry = NULL;
81 XenPTRegInfo *reg = NULL;
82 uint32_t real_offset = 0;
83
84 /* find register entry */
85 QLIST_FOREACH(reg_entry, &reg_grp->reg_tbl_list, entries) {
86 reg = reg_entry->reg;
87 real_offset = reg_grp->base_offset + reg->offset;
88 /* check address */
89 if ((real_offset <= address)
90 && ((real_offset + reg->size) > address)) {
91 return reg_entry;
92 }
93 }
94
95 return NULL;
96 }
97
98
99 /****************
100 * general register functions
101 */
102
103 /* register initialization function */
104
105 static int xen_pt_common_reg_init(XenPCIPassthroughState *s,
106 XenPTRegInfo *reg, uint32_t real_offset,
107 uint32_t *data)
108 {
109 *data = reg->init_val;
110 return 0;
111 }
112
113 /* Read register functions */
114
115 static int xen_pt_byte_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
116 uint8_t *value, uint8_t valid_mask)
117 {
118 XenPTRegInfo *reg = cfg_entry->reg;
119 uint8_t valid_emu_mask = 0;
120
121 /* emulate byte register */
122 valid_emu_mask = reg->emu_mask & valid_mask;
123 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
124
125 return 0;
126 }
127 static int xen_pt_word_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
128 uint16_t *value, uint16_t valid_mask)
129 {
130 XenPTRegInfo *reg = cfg_entry->reg;
131 uint16_t valid_emu_mask = 0;
132
133 /* emulate word register */
134 valid_emu_mask = reg->emu_mask & valid_mask;
135 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
136
137 return 0;
138 }
139 static int xen_pt_long_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
140 uint32_t *value, uint32_t valid_mask)
141 {
142 XenPTRegInfo *reg = cfg_entry->reg;
143 uint32_t valid_emu_mask = 0;
144
145 /* emulate long register */
146 valid_emu_mask = reg->emu_mask & valid_mask;
147 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
148
149 return 0;
150 }
151
152 /* Write register functions */
153
154 static int xen_pt_byte_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
155 uint8_t *val, uint8_t dev_value,
156 uint8_t valid_mask)
157 {
158 XenPTRegInfo *reg = cfg_entry->reg;
159 uint8_t writable_mask = 0;
160 uint8_t throughable_mask = 0;
161
162 /* modify emulate register */
163 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
164 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
165
166 /* create value for writing to I/O device register */
167 throughable_mask = ~reg->emu_mask & valid_mask;
168 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
169
170 return 0;
171 }
172 static int xen_pt_word_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
173 uint16_t *val, uint16_t dev_value,
174 uint16_t valid_mask)
175 {
176 XenPTRegInfo *reg = cfg_entry->reg;
177 uint16_t writable_mask = 0;
178 uint16_t throughable_mask = 0;
179
180 /* modify emulate register */
181 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
182 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
183
184 /* create value for writing to I/O device register */
185 throughable_mask = ~reg->emu_mask & valid_mask;
186 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
187
188 return 0;
189 }
190 static int xen_pt_long_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
191 uint32_t *val, uint32_t dev_value,
192 uint32_t valid_mask)
193 {
194 XenPTRegInfo *reg = cfg_entry->reg;
195 uint32_t writable_mask = 0;
196 uint32_t throughable_mask = 0;
197
198 /* modify emulate register */
199 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
200 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
201
202 /* create value for writing to I/O device register */
203 throughable_mask = ~reg->emu_mask & valid_mask;
204 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
205
206 return 0;
207 }
208
209
210 /* XenPTRegInfo declaration
211 * - only for emulated register (either a part or whole bit).
212 * - for passthrough register that need special behavior (like interacting with
213 * other component), set emu_mask to all 0 and specify r/w func properly.
214 * - do NOT use ALL F for init_val, otherwise the tbl will not be registered.
215 */
216
217 /********************
218 * Header Type0
219 */
220
221 static int xen_pt_vendor_reg_init(XenPCIPassthroughState *s,
222 XenPTRegInfo *reg, uint32_t real_offset,
223 uint32_t *data)
224 {
225 *data = s->real_device.vendor_id;
226 return 0;
227 }
228 static int xen_pt_device_reg_init(XenPCIPassthroughState *s,
229 XenPTRegInfo *reg, uint32_t real_offset,
230 uint32_t *data)
231 {
232 *data = s->real_device.device_id;
233 return 0;
234 }
235 static int xen_pt_status_reg_init(XenPCIPassthroughState *s,
236 XenPTRegInfo *reg, uint32_t real_offset,
237 uint32_t *data)
238 {
239 XenPTRegGroup *reg_grp_entry = NULL;
240 XenPTReg *reg_entry = NULL;
241 uint32_t reg_field = 0;
242
243 /* find Header register group */
244 reg_grp_entry = xen_pt_find_reg_grp(s, PCI_CAPABILITY_LIST);
245 if (reg_grp_entry) {
246 /* find Capabilities Pointer register */
247 reg_entry = xen_pt_find_reg(reg_grp_entry, PCI_CAPABILITY_LIST);
248 if (reg_entry) {
249 /* check Capabilities Pointer register */
250 if (reg_entry->data) {
251 reg_field |= PCI_STATUS_CAP_LIST;
252 } else {
253 reg_field &= ~PCI_STATUS_CAP_LIST;
254 }
255 } else {
256 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTReg*"
257 " for Capabilities Pointer register."
258 " (%s)\n", __func__);
259 return -1;
260 }
261 } else {
262 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTRegGroup"
263 " for Header. (%s)\n", __func__);
264 return -1;
265 }
266
267 *data = reg_field;
268 return 0;
269 }
270 static int xen_pt_header_type_reg_init(XenPCIPassthroughState *s,
271 XenPTRegInfo *reg, uint32_t real_offset,
272 uint32_t *data)
273 {
274 /* read PCI_HEADER_TYPE */
275 *data = reg->init_val | 0x80;
276 return 0;
277 }
278
279 /* initialize Interrupt Pin register */
280 static int xen_pt_irqpin_reg_init(XenPCIPassthroughState *s,
281 XenPTRegInfo *reg, uint32_t real_offset,
282 uint32_t *data)
283 {
284 *data = xen_pt_pci_read_intx(s);
285 return 0;
286 }
287
288 /* Command register */
289 static int xen_pt_cmd_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
290 uint16_t *value, uint16_t valid_mask)
291 {
292 XenPTRegInfo *reg = cfg_entry->reg;
293 uint16_t valid_emu_mask = 0;
294 uint16_t emu_mask = reg->emu_mask;
295
296 if (s->is_virtfn) {
297 emu_mask |= PCI_COMMAND_MEMORY;
298 }
299
300 /* emulate word register */
301 valid_emu_mask = emu_mask & valid_mask;
302 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
303
304 return 0;
305 }
306 static int xen_pt_cmd_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
307 uint16_t *val, uint16_t dev_value,
308 uint16_t valid_mask)
309 {
310 XenPTRegInfo *reg = cfg_entry->reg;
311 uint16_t writable_mask = 0;
312 uint16_t throughable_mask = 0;
313 uint16_t emu_mask = reg->emu_mask;
314
315 if (s->is_virtfn) {
316 emu_mask |= PCI_COMMAND_MEMORY;
317 }
318
319 /* modify emulate register */
320 writable_mask = ~reg->ro_mask & valid_mask;
321 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
322
323 /* create value for writing to I/O device register */
324 throughable_mask = ~emu_mask & valid_mask;
325
326 if (*val & PCI_COMMAND_INTX_DISABLE) {
327 throughable_mask |= PCI_COMMAND_INTX_DISABLE;
328 } else {
329 if (s->machine_irq) {
330 throughable_mask |= PCI_COMMAND_INTX_DISABLE;
331 }
332 }
333
334 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
335
336 return 0;
337 }
338
339 /* BAR */
340 #define XEN_PT_BAR_MEM_RO_MASK 0x0000000F /* BAR ReadOnly mask(Memory) */
341 #define XEN_PT_BAR_MEM_EMU_MASK 0xFFFFFFF0 /* BAR emul mask(Memory) */
342 #define XEN_PT_BAR_IO_RO_MASK 0x00000003 /* BAR ReadOnly mask(I/O) */
343 #define XEN_PT_BAR_IO_EMU_MASK 0xFFFFFFFC /* BAR emul mask(I/O) */
344
345 static XenPTBarFlag xen_pt_bar_reg_parse(XenPCIPassthroughState *s,
346 XenPTRegInfo *reg)
347 {
348 PCIDevice *d = &s->dev;
349 XenPTRegion *region = NULL;
350 PCIIORegion *r;
351 int index = 0;
352
353 /* check 64bit BAR */
354 index = xen_pt_bar_offset_to_index(reg->offset);
355 if ((0 < index) && (index < PCI_ROM_SLOT)) {
356 int type = s->real_device.io_regions[index - 1].type;
357
358 if ((type & XEN_HOST_PCI_REGION_TYPE_MEM)
359 && (type & XEN_HOST_PCI_REGION_TYPE_MEM_64)) {
360 region = &s->bases[index - 1];
361 if (region->bar_flag != XEN_PT_BAR_FLAG_UPPER) {
362 return XEN_PT_BAR_FLAG_UPPER;
363 }
364 }
365 }
366
367 /* check unused BAR */
368 r = &d->io_regions[index];
369 if (r->size == 0) {
370 return XEN_PT_BAR_FLAG_UNUSED;
371 }
372
373 /* for ExpROM BAR */
374 if (index == PCI_ROM_SLOT) {
375 return XEN_PT_BAR_FLAG_MEM;
376 }
377
378 /* check BAR I/O indicator */
379 if (s->real_device.io_regions[index].type & XEN_HOST_PCI_REGION_TYPE_IO) {
380 return XEN_PT_BAR_FLAG_IO;
381 } else {
382 return XEN_PT_BAR_FLAG_MEM;
383 }
384 }
385
386 static inline uint32_t base_address_with_flags(XenHostPCIIORegion *hr)
387 {
388 if (hr->type & XEN_HOST_PCI_REGION_TYPE_IO) {
389 return hr->base_addr | (hr->bus_flags & ~PCI_BASE_ADDRESS_IO_MASK);
390 } else {
391 return hr->base_addr | (hr->bus_flags & ~PCI_BASE_ADDRESS_MEM_MASK);
392 }
393 }
394
395 static int xen_pt_bar_reg_init(XenPCIPassthroughState *s, XenPTRegInfo *reg,
396 uint32_t real_offset, uint32_t *data)
397 {
398 uint32_t reg_field = 0;
399 int index;
400
401 index = xen_pt_bar_offset_to_index(reg->offset);
402 if (index < 0 || index >= PCI_NUM_REGIONS) {
403 XEN_PT_ERR(&s->dev, "Internal error: Invalid BAR index [%d].\n", index);
404 return -1;
405 }
406
407 /* set BAR flag */
408 s->bases[index].bar_flag = xen_pt_bar_reg_parse(s, reg);
409 if (s->bases[index].bar_flag == XEN_PT_BAR_FLAG_UNUSED) {
410 reg_field = XEN_PT_INVALID_REG;
411 }
412
413 *data = reg_field;
414 return 0;
415 }
416 static int xen_pt_bar_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
417 uint32_t *value, uint32_t valid_mask)
418 {
419 XenPTRegInfo *reg = cfg_entry->reg;
420 uint32_t valid_emu_mask = 0;
421 uint32_t bar_emu_mask = 0;
422 int index;
423
424 /* get BAR index */
425 index = xen_pt_bar_offset_to_index(reg->offset);
426 if (index < 0 || index >= PCI_NUM_REGIONS) {
427 XEN_PT_ERR(&s->dev, "Internal error: Invalid BAR index [%d].\n", index);
428 return -1;
429 }
430
431 /* use fixed-up value from kernel sysfs */
432 *value = base_address_with_flags(&s->real_device.io_regions[index]);
433
434 /* set emulate mask depend on BAR flag */
435 switch (s->bases[index].bar_flag) {
436 case XEN_PT_BAR_FLAG_MEM:
437 bar_emu_mask = XEN_PT_BAR_MEM_EMU_MASK;
438 break;
439 case XEN_PT_BAR_FLAG_IO:
440 bar_emu_mask = XEN_PT_BAR_IO_EMU_MASK;
441 break;
442 case XEN_PT_BAR_FLAG_UPPER:
443 bar_emu_mask = XEN_PT_BAR_ALLF;
444 break;
445 default:
446 break;
447 }
448
449 /* emulate BAR */
450 valid_emu_mask = bar_emu_mask & valid_mask;
451 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
452
453 return 0;
454 }
455 static int xen_pt_bar_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
456 uint32_t *val, uint32_t dev_value,
457 uint32_t valid_mask)
458 {
459 XenPTRegInfo *reg = cfg_entry->reg;
460 XenPTRegion *base = NULL;
461 PCIDevice *d = &s->dev;
462 const PCIIORegion *r;
463 uint32_t writable_mask = 0;
464 uint32_t throughable_mask = 0;
465 uint32_t bar_emu_mask = 0;
466 uint32_t bar_ro_mask = 0;
467 uint32_t r_size = 0;
468 int index = 0;
469
470 index = xen_pt_bar_offset_to_index(reg->offset);
471 if (index < 0 || index >= PCI_NUM_REGIONS) {
472 XEN_PT_ERR(d, "Internal error: Invalid BAR index [%d].\n", index);
473 return -1;
474 }
475
476 r = &d->io_regions[index];
477 base = &s->bases[index];
478 r_size = xen_pt_get_emul_size(base->bar_flag, r->size);
479
480 /* set emulate mask and read-only mask values depend on the BAR flag */
481 switch (s->bases[index].bar_flag) {
482 case XEN_PT_BAR_FLAG_MEM:
483 bar_emu_mask = XEN_PT_BAR_MEM_EMU_MASK;
484 bar_ro_mask = XEN_PT_BAR_MEM_RO_MASK | (r_size - 1);
485 break;
486 case XEN_PT_BAR_FLAG_IO:
487 bar_emu_mask = XEN_PT_BAR_IO_EMU_MASK;
488 bar_ro_mask = XEN_PT_BAR_IO_RO_MASK | (r_size - 1);
489 break;
490 case XEN_PT_BAR_FLAG_UPPER:
491 bar_emu_mask = XEN_PT_BAR_ALLF;
492 bar_ro_mask = 0; /* all upper 32bit are R/W */
493 break;
494 default:
495 break;
496 }
497
498 /* modify emulate register */
499 writable_mask = bar_emu_mask & ~bar_ro_mask & valid_mask;
500 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
501
502 /* check whether we need to update the virtual region address or not */
503 switch (s->bases[index].bar_flag) {
504 case XEN_PT_BAR_FLAG_MEM:
505 /* nothing to do */
506 break;
507 case XEN_PT_BAR_FLAG_IO:
508 /* nothing to do */
509 break;
510 case XEN_PT_BAR_FLAG_UPPER:
511 if (cfg_entry->data) {
512 if (cfg_entry->data != (XEN_PT_BAR_ALLF & ~bar_ro_mask)) {
513 XEN_PT_WARN(d, "Guest attempt to set high MMIO Base Address. "
514 "Ignore mapping. "
515 "(offset: 0x%02x, high address: 0x%08x)\n",
516 reg->offset, cfg_entry->data);
517 }
518 }
519 break;
520 default:
521 break;
522 }
523
524 /* create value for writing to I/O device register */
525 throughable_mask = ~bar_emu_mask & valid_mask;
526 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
527
528 return 0;
529 }
530
531 /* write Exp ROM BAR */
532 static int xen_pt_exp_rom_bar_reg_write(XenPCIPassthroughState *s,
533 XenPTReg *cfg_entry, uint32_t *val,
534 uint32_t dev_value, uint32_t valid_mask)
535 {
536 XenPTRegInfo *reg = cfg_entry->reg;
537 XenPTRegion *base = NULL;
538 PCIDevice *d = (PCIDevice *)&s->dev;
539 uint32_t writable_mask = 0;
540 uint32_t throughable_mask = 0;
541 pcibus_t r_size = 0;
542 uint32_t bar_emu_mask = 0;
543 uint32_t bar_ro_mask = 0;
544
545 r_size = d->io_regions[PCI_ROM_SLOT].size;
546 base = &s->bases[PCI_ROM_SLOT];
547 /* align memory type resource size */
548 r_size = xen_pt_get_emul_size(base->bar_flag, r_size);
549
550 /* set emulate mask and read-only mask */
551 bar_emu_mask = reg->emu_mask;
552 bar_ro_mask = (reg->ro_mask | (r_size - 1)) & ~PCI_ROM_ADDRESS_ENABLE;
553
554 /* modify emulate register */
555 writable_mask = ~bar_ro_mask & valid_mask;
556 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
557
558 /* create value for writing to I/O device register */
559 throughable_mask = ~bar_emu_mask & valid_mask;
560 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
561
562 return 0;
563 }
564
565 /* Header Type0 reg static infomation table */
566 static XenPTRegInfo xen_pt_emu_reg_header0[] = {
567 /* Vendor ID reg */
568 {
569 .offset = PCI_VENDOR_ID,
570 .size = 2,
571 .init_val = 0x0000,
572 .ro_mask = 0xFFFF,
573 .emu_mask = 0xFFFF,
574 .init = xen_pt_vendor_reg_init,
575 .u.w.read = xen_pt_word_reg_read,
576 .u.w.write = xen_pt_word_reg_write,
577 },
578 /* Device ID reg */
579 {
580 .offset = PCI_DEVICE_ID,
581 .size = 2,
582 .init_val = 0x0000,
583 .ro_mask = 0xFFFF,
584 .emu_mask = 0xFFFF,
585 .init = xen_pt_device_reg_init,
586 .u.w.read = xen_pt_word_reg_read,
587 .u.w.write = xen_pt_word_reg_write,
588 },
589 /* Command reg */
590 {
591 .offset = PCI_COMMAND,
592 .size = 2,
593 .init_val = 0x0000,
594 .ro_mask = 0xF880,
595 .emu_mask = 0x0740,
596 .init = xen_pt_common_reg_init,
597 .u.w.read = xen_pt_cmd_reg_read,
598 .u.w.write = xen_pt_cmd_reg_write,
599 },
600 /* Capabilities Pointer reg */
601 {
602 .offset = PCI_CAPABILITY_LIST,
603 .size = 1,
604 .init_val = 0x00,
605 .ro_mask = 0xFF,
606 .emu_mask = 0xFF,
607 .init = xen_pt_ptr_reg_init,
608 .u.b.read = xen_pt_byte_reg_read,
609 .u.b.write = xen_pt_byte_reg_write,
610 },
611 /* Status reg */
612 /* use emulated Cap Ptr value to initialize,
613 * so need to be declared after Cap Ptr reg
614 */
615 {
616 .offset = PCI_STATUS,
617 .size = 2,
618 .init_val = 0x0000,
619 .ro_mask = 0x06FF,
620 .emu_mask = 0x0010,
621 .init = xen_pt_status_reg_init,
622 .u.w.read = xen_pt_word_reg_read,
623 .u.w.write = xen_pt_word_reg_write,
624 },
625 /* Cache Line Size reg */
626 {
627 .offset = PCI_CACHE_LINE_SIZE,
628 .size = 1,
629 .init_val = 0x00,
630 .ro_mask = 0x00,
631 .emu_mask = 0xFF,
632 .init = xen_pt_common_reg_init,
633 .u.b.read = xen_pt_byte_reg_read,
634 .u.b.write = xen_pt_byte_reg_write,
635 },
636 /* Latency Timer reg */
637 {
638 .offset = PCI_LATENCY_TIMER,
639 .size = 1,
640 .init_val = 0x00,
641 .ro_mask = 0x00,
642 .emu_mask = 0xFF,
643 .init = xen_pt_common_reg_init,
644 .u.b.read = xen_pt_byte_reg_read,
645 .u.b.write = xen_pt_byte_reg_write,
646 },
647 /* Header Type reg */
648 {
649 .offset = PCI_HEADER_TYPE,
650 .size = 1,
651 .init_val = 0x00,
652 .ro_mask = 0xFF,
653 .emu_mask = 0x00,
654 .init = xen_pt_header_type_reg_init,
655 .u.b.read = xen_pt_byte_reg_read,
656 .u.b.write = xen_pt_byte_reg_write,
657 },
658 /* Interrupt Line reg */
659 {
660 .offset = PCI_INTERRUPT_LINE,
661 .size = 1,
662 .init_val = 0x00,
663 .ro_mask = 0x00,
664 .emu_mask = 0xFF,
665 .init = xen_pt_common_reg_init,
666 .u.b.read = xen_pt_byte_reg_read,
667 .u.b.write = xen_pt_byte_reg_write,
668 },
669 /* Interrupt Pin reg */
670 {
671 .offset = PCI_INTERRUPT_PIN,
672 .size = 1,
673 .init_val = 0x00,
674 .ro_mask = 0xFF,
675 .emu_mask = 0xFF,
676 .init = xen_pt_irqpin_reg_init,
677 .u.b.read = xen_pt_byte_reg_read,
678 .u.b.write = xen_pt_byte_reg_write,
679 },
680 /* BAR 0 reg */
681 /* mask of BAR need to be decided later, depends on IO/MEM type */
682 {
683 .offset = PCI_BASE_ADDRESS_0,
684 .size = 4,
685 .init_val = 0x00000000,
686 .init = xen_pt_bar_reg_init,
687 .u.dw.read = xen_pt_bar_reg_read,
688 .u.dw.write = xen_pt_bar_reg_write,
689 },
690 /* BAR 1 reg */
691 {
692 .offset = PCI_BASE_ADDRESS_1,
693 .size = 4,
694 .init_val = 0x00000000,
695 .init = xen_pt_bar_reg_init,
696 .u.dw.read = xen_pt_bar_reg_read,
697 .u.dw.write = xen_pt_bar_reg_write,
698 },
699 /* BAR 2 reg */
700 {
701 .offset = PCI_BASE_ADDRESS_2,
702 .size = 4,
703 .init_val = 0x00000000,
704 .init = xen_pt_bar_reg_init,
705 .u.dw.read = xen_pt_bar_reg_read,
706 .u.dw.write = xen_pt_bar_reg_write,
707 },
708 /* BAR 3 reg */
709 {
710 .offset = PCI_BASE_ADDRESS_3,
711 .size = 4,
712 .init_val = 0x00000000,
713 .init = xen_pt_bar_reg_init,
714 .u.dw.read = xen_pt_bar_reg_read,
715 .u.dw.write = xen_pt_bar_reg_write,
716 },
717 /* BAR 4 reg */
718 {
719 .offset = PCI_BASE_ADDRESS_4,
720 .size = 4,
721 .init_val = 0x00000000,
722 .init = xen_pt_bar_reg_init,
723 .u.dw.read = xen_pt_bar_reg_read,
724 .u.dw.write = xen_pt_bar_reg_write,
725 },
726 /* BAR 5 reg */
727 {
728 .offset = PCI_BASE_ADDRESS_5,
729 .size = 4,
730 .init_val = 0x00000000,
731 .init = xen_pt_bar_reg_init,
732 .u.dw.read = xen_pt_bar_reg_read,
733 .u.dw.write = xen_pt_bar_reg_write,
734 },
735 /* Expansion ROM BAR reg */
736 {
737 .offset = PCI_ROM_ADDRESS,
738 .size = 4,
739 .init_val = 0x00000000,
740 .ro_mask = 0x000007FE,
741 .emu_mask = 0xFFFFF800,
742 .init = xen_pt_bar_reg_init,
743 .u.dw.read = xen_pt_long_reg_read,
744 .u.dw.write = xen_pt_exp_rom_bar_reg_write,
745 },
746 {
747 .size = 0,
748 },
749 };
750
751
752 /*********************************
753 * Vital Product Data Capability
754 */
755
756 /* Vital Product Data Capability Structure reg static infomation table */
757 static XenPTRegInfo xen_pt_emu_reg_vpd[] = {
758 {
759 .offset = PCI_CAP_LIST_NEXT,
760 .size = 1,
761 .init_val = 0x00,
762 .ro_mask = 0xFF,
763 .emu_mask = 0xFF,
764 .init = xen_pt_ptr_reg_init,
765 .u.b.read = xen_pt_byte_reg_read,
766 .u.b.write = xen_pt_byte_reg_write,
767 },
768 {
769 .size = 0,
770 },
771 };
772
773
774 /**************************************
775 * Vendor Specific Capability
776 */
777
778 /* Vendor Specific Capability Structure reg static infomation table */
779 static XenPTRegInfo xen_pt_emu_reg_vendor[] = {
780 {
781 .offset = PCI_CAP_LIST_NEXT,
782 .size = 1,
783 .init_val = 0x00,
784 .ro_mask = 0xFF,
785 .emu_mask = 0xFF,
786 .init = xen_pt_ptr_reg_init,
787 .u.b.read = xen_pt_byte_reg_read,
788 .u.b.write = xen_pt_byte_reg_write,
789 },
790 {
791 .size = 0,
792 },
793 };
794
795
796 /*****************************
797 * PCI Express Capability
798 */
799
800 static inline uint8_t get_capability_version(XenPCIPassthroughState *s,
801 uint32_t offset)
802 {
803 uint8_t flags = pci_get_byte(s->dev.config + offset + PCI_EXP_FLAGS);
804 return flags & PCI_EXP_FLAGS_VERS;
805 }
806
807 static inline uint8_t get_device_type(XenPCIPassthroughState *s,
808 uint32_t offset)
809 {
810 uint8_t flags = pci_get_byte(s->dev.config + offset + PCI_EXP_FLAGS);
811 return (flags & PCI_EXP_FLAGS_TYPE) >> 4;
812 }
813
814 /* initialize Link Control register */
815 static int xen_pt_linkctrl_reg_init(XenPCIPassthroughState *s,
816 XenPTRegInfo *reg, uint32_t real_offset,
817 uint32_t *data)
818 {
819 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
820 uint8_t dev_type = get_device_type(s, real_offset - reg->offset);
821
822 /* no need to initialize in case of Root Complex Integrated Endpoint
823 * with cap_ver 1.x
824 */
825 if ((dev_type == PCI_EXP_TYPE_RC_END) && (cap_ver == 1)) {
826 *data = XEN_PT_INVALID_REG;
827 }
828
829 *data = reg->init_val;
830 return 0;
831 }
832 /* initialize Device Control 2 register */
833 static int xen_pt_devctrl2_reg_init(XenPCIPassthroughState *s,
834 XenPTRegInfo *reg, uint32_t real_offset,
835 uint32_t *data)
836 {
837 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
838
839 /* no need to initialize in case of cap_ver 1.x */
840 if (cap_ver == 1) {
841 *data = XEN_PT_INVALID_REG;
842 }
843
844 *data = reg->init_val;
845 return 0;
846 }
847 /* initialize Link Control 2 register */
848 static int xen_pt_linkctrl2_reg_init(XenPCIPassthroughState *s,
849 XenPTRegInfo *reg, uint32_t real_offset,
850 uint32_t *data)
851 {
852 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
853 uint32_t reg_field = 0;
854
855 /* no need to initialize in case of cap_ver 1.x */
856 if (cap_ver == 1) {
857 reg_field = XEN_PT_INVALID_REG;
858 } else {
859 /* set Supported Link Speed */
860 uint8_t lnkcap = pci_get_byte(s->dev.config + real_offset - reg->offset
861 + PCI_EXP_LNKCAP);
862 reg_field |= PCI_EXP_LNKCAP_SLS & lnkcap;
863 }
864
865 *data = reg_field;
866 return 0;
867 }
868
869 /* PCI Express Capability Structure reg static infomation table */
870 static XenPTRegInfo xen_pt_emu_reg_pcie[] = {
871 /* Next Pointer reg */
872 {
873 .offset = PCI_CAP_LIST_NEXT,
874 .size = 1,
875 .init_val = 0x00,
876 .ro_mask = 0xFF,
877 .emu_mask = 0xFF,
878 .init = xen_pt_ptr_reg_init,
879 .u.b.read = xen_pt_byte_reg_read,
880 .u.b.write = xen_pt_byte_reg_write,
881 },
882 /* Device Capabilities reg */
883 {
884 .offset = PCI_EXP_DEVCAP,
885 .size = 4,
886 .init_val = 0x00000000,
887 .ro_mask = 0x1FFCFFFF,
888 .emu_mask = 0x10000000,
889 .init = xen_pt_common_reg_init,
890 .u.dw.read = xen_pt_long_reg_read,
891 .u.dw.write = xen_pt_long_reg_write,
892 },
893 /* Device Control reg */
894 {
895 .offset = PCI_EXP_DEVCTL,
896 .size = 2,
897 .init_val = 0x2810,
898 .ro_mask = 0x8400,
899 .emu_mask = 0xFFFF,
900 .init = xen_pt_common_reg_init,
901 .u.w.read = xen_pt_word_reg_read,
902 .u.w.write = xen_pt_word_reg_write,
903 },
904 /* Link Control reg */
905 {
906 .offset = PCI_EXP_LNKCTL,
907 .size = 2,
908 .init_val = 0x0000,
909 .ro_mask = 0xFC34,
910 .emu_mask = 0xFFFF,
911 .init = xen_pt_linkctrl_reg_init,
912 .u.w.read = xen_pt_word_reg_read,
913 .u.w.write = xen_pt_word_reg_write,
914 },
915 /* Device Control 2 reg */
916 {
917 .offset = 0x28,
918 .size = 2,
919 .init_val = 0x0000,
920 .ro_mask = 0xFFE0,
921 .emu_mask = 0xFFFF,
922 .init = xen_pt_devctrl2_reg_init,
923 .u.w.read = xen_pt_word_reg_read,
924 .u.w.write = xen_pt_word_reg_write,
925 },
926 /* Link Control 2 reg */
927 {
928 .offset = 0x30,
929 .size = 2,
930 .init_val = 0x0000,
931 .ro_mask = 0xE040,
932 .emu_mask = 0xFFFF,
933 .init = xen_pt_linkctrl2_reg_init,
934 .u.w.read = xen_pt_word_reg_read,
935 .u.w.write = xen_pt_word_reg_write,
936 },
937 {
938 .size = 0,
939 },
940 };
941
942
943 /*********************************
944 * Power Management Capability
945 */
946
947 /* read Power Management Control/Status register */
948 static int xen_pt_pmcsr_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
949 uint16_t *value, uint16_t valid_mask)
950 {
951 XenPTRegInfo *reg = cfg_entry->reg;
952 uint16_t valid_emu_mask = reg->emu_mask;
953
954 valid_emu_mask |= PCI_PM_CTRL_STATE_MASK | PCI_PM_CTRL_NO_SOFT_RESET;
955
956 valid_emu_mask = valid_emu_mask & valid_mask;
957 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
958
959 return 0;
960 }
961 /* write Power Management Control/Status register */
962 static int xen_pt_pmcsr_reg_write(XenPCIPassthroughState *s,
963 XenPTReg *cfg_entry, uint16_t *val,
964 uint16_t dev_value, uint16_t valid_mask)
965 {
966 XenPTRegInfo *reg = cfg_entry->reg;
967 uint16_t emu_mask = reg->emu_mask;
968 uint16_t writable_mask = 0;
969 uint16_t throughable_mask = 0;
970
971 emu_mask |= PCI_PM_CTRL_STATE_MASK | PCI_PM_CTRL_NO_SOFT_RESET;
972
973 /* modify emulate register */
974 writable_mask = emu_mask & ~reg->ro_mask & valid_mask;
975 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
976
977 /* create value for writing to I/O device register */
978 throughable_mask = ~emu_mask & valid_mask;
979 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
980
981 return 0;
982 }
983
984 /* Power Management Capability reg static infomation table */
985 static XenPTRegInfo xen_pt_emu_reg_pm[] = {
986 /* Next Pointer reg */
987 {
988 .offset = PCI_CAP_LIST_NEXT,
989 .size = 1,
990 .init_val = 0x00,
991 .ro_mask = 0xFF,
992 .emu_mask = 0xFF,
993 .init = xen_pt_ptr_reg_init,
994 .u.b.read = xen_pt_byte_reg_read,
995 .u.b.write = xen_pt_byte_reg_write,
996 },
997 /* Power Management Capabilities reg */
998 {
999 .offset = PCI_CAP_FLAGS,
1000 .size = 2,
1001 .init_val = 0x0000,
1002 .ro_mask = 0xFFFF,
1003 .emu_mask = 0xF9C8,
1004 .init = xen_pt_common_reg_init,
1005 .u.w.read = xen_pt_word_reg_read,
1006 .u.w.write = xen_pt_word_reg_write,
1007 },
1008 /* PCI Power Management Control/Status reg */
1009 {
1010 .offset = PCI_PM_CTRL,
1011 .size = 2,
1012 .init_val = 0x0008,
1013 .ro_mask = 0xE1FC,
1014 .emu_mask = 0x8100,
1015 .init = xen_pt_common_reg_init,
1016 .u.w.read = xen_pt_pmcsr_reg_read,
1017 .u.w.write = xen_pt_pmcsr_reg_write,
1018 },
1019 {
1020 .size = 0,
1021 },
1022 };
1023
1024
1025 /********************************
1026 * MSI Capability
1027 */
1028
1029 /* Helper */
1030 static bool xen_pt_msgdata_check_type(uint32_t offset, uint16_t flags)
1031 {
1032 /* check the offset whether matches the type or not */
1033 bool is_32 = (offset == PCI_MSI_DATA_32) && !(flags & PCI_MSI_FLAGS_64BIT);
1034 bool is_64 = (offset == PCI_MSI_DATA_64) && (flags & PCI_MSI_FLAGS_64BIT);
1035 return is_32 || is_64;
1036 }
1037
1038 /* Message Control register */
1039 static int xen_pt_msgctrl_reg_init(XenPCIPassthroughState *s,
1040 XenPTRegInfo *reg, uint32_t real_offset,
1041 uint32_t *data)
1042 {
1043 PCIDevice *d = &s->dev;
1044 XenPTMSI *msi = s->msi;
1045 uint16_t reg_field = 0;
1046
1047 /* use I/O device register's value as initial value */
1048 reg_field = pci_get_word(d->config + real_offset);
1049
1050 if (reg_field & PCI_MSI_FLAGS_ENABLE) {
1051 XEN_PT_LOG(&s->dev, "MSI already enabled, disabling it first\n");
1052 xen_host_pci_set_word(&s->real_device, real_offset,
1053 reg_field & ~PCI_MSI_FLAGS_ENABLE);
1054 }
1055 msi->flags |= reg_field;
1056 msi->ctrl_offset = real_offset;
1057 msi->initialized = false;
1058 msi->mapped = false;
1059
1060 *data = reg->init_val;
1061 return 0;
1062 }
1063 static int xen_pt_msgctrl_reg_write(XenPCIPassthroughState *s,
1064 XenPTReg *cfg_entry, uint16_t *val,
1065 uint16_t dev_value, uint16_t valid_mask)
1066 {
1067 XenPTRegInfo *reg = cfg_entry->reg;
1068 XenPTMSI *msi = s->msi;
1069 uint16_t writable_mask = 0;
1070 uint16_t throughable_mask = 0;
1071 uint16_t raw_val;
1072
1073 /* Currently no support for multi-vector */
1074 if (*val & PCI_MSI_FLAGS_QSIZE) {
1075 XEN_PT_WARN(&s->dev, "Tries to set more than 1 vector ctrl %x\n", *val);
1076 }
1077
1078 /* modify emulate register */
1079 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1080 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1081 msi->flags |= cfg_entry->data & ~PCI_MSI_FLAGS_ENABLE;
1082
1083 /* create value for writing to I/O device register */
1084 raw_val = *val;
1085 throughable_mask = ~reg->emu_mask & valid_mask;
1086 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1087
1088 /* update MSI */
1089 if (raw_val & PCI_MSI_FLAGS_ENABLE) {
1090 /* setup MSI pirq for the first time */
1091 if (!msi->initialized) {
1092 /* Init physical one */
1093 XEN_PT_LOG(&s->dev, "setup MSI\n");
1094 if (xen_pt_msi_setup(s)) {
1095 /* We do not broadcast the error to the framework code, so
1096 * that MSI errors are contained in MSI emulation code and
1097 * QEMU can go on running.
1098 * Guest MSI would be actually not working.
1099 */
1100 *val &= ~PCI_MSI_FLAGS_ENABLE;
1101 XEN_PT_WARN(&s->dev, "Can not map MSI.\n");
1102 return 0;
1103 }
1104 if (xen_pt_msi_update(s)) {
1105 *val &= ~PCI_MSI_FLAGS_ENABLE;
1106 XEN_PT_WARN(&s->dev, "Can not bind MSI\n");
1107 return 0;
1108 }
1109 msi->initialized = true;
1110 msi->mapped = true;
1111 }
1112 msi->flags |= PCI_MSI_FLAGS_ENABLE;
1113 } else {
1114 msi->flags &= ~PCI_MSI_FLAGS_ENABLE;
1115 }
1116
1117 /* pass through MSI_ENABLE bit */
1118 *val &= ~PCI_MSI_FLAGS_ENABLE;
1119 *val |= raw_val & PCI_MSI_FLAGS_ENABLE;
1120
1121 return 0;
1122 }
1123
1124 /* initialize Message Upper Address register */
1125 static int xen_pt_msgaddr64_reg_init(XenPCIPassthroughState *s,
1126 XenPTRegInfo *reg, uint32_t real_offset,
1127 uint32_t *data)
1128 {
1129 /* no need to initialize in case of 32 bit type */
1130 if (!(s->msi->flags & PCI_MSI_FLAGS_64BIT)) {
1131 *data = XEN_PT_INVALID_REG;
1132 } else {
1133 *data = reg->init_val;
1134 }
1135
1136 return 0;
1137 }
1138 /* this function will be called twice (for 32 bit and 64 bit type) */
1139 /* initialize Message Data register */
1140 static int xen_pt_msgdata_reg_init(XenPCIPassthroughState *s,
1141 XenPTRegInfo *reg, uint32_t real_offset,
1142 uint32_t *data)
1143 {
1144 uint32_t flags = s->msi->flags;
1145 uint32_t offset = reg->offset;
1146
1147 /* check the offset whether matches the type or not */
1148 if (xen_pt_msgdata_check_type(offset, flags)) {
1149 *data = reg->init_val;
1150 } else {
1151 *data = XEN_PT_INVALID_REG;
1152 }
1153 return 0;
1154 }
1155
1156 /* write Message Address register */
1157 static int xen_pt_msgaddr32_reg_write(XenPCIPassthroughState *s,
1158 XenPTReg *cfg_entry, uint32_t *val,
1159 uint32_t dev_value, uint32_t valid_mask)
1160 {
1161 XenPTRegInfo *reg = cfg_entry->reg;
1162 uint32_t writable_mask = 0;
1163 uint32_t throughable_mask = 0;
1164 uint32_t old_addr = cfg_entry->data;
1165
1166 /* modify emulate register */
1167 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1168 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1169 s->msi->addr_lo = cfg_entry->data;
1170
1171 /* create value for writing to I/O device register */
1172 throughable_mask = ~reg->emu_mask & valid_mask;
1173 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1174
1175 /* update MSI */
1176 if (cfg_entry->data != old_addr) {
1177 if (s->msi->mapped) {
1178 xen_pt_msi_update(s);
1179 }
1180 }
1181
1182 return 0;
1183 }
1184 /* write Message Upper Address register */
1185 static int xen_pt_msgaddr64_reg_write(XenPCIPassthroughState *s,
1186 XenPTReg *cfg_entry, uint32_t *val,
1187 uint32_t dev_value, uint32_t valid_mask)
1188 {
1189 XenPTRegInfo *reg = cfg_entry->reg;
1190 uint32_t writable_mask = 0;
1191 uint32_t throughable_mask = 0;
1192 uint32_t old_addr = cfg_entry->data;
1193
1194 /* check whether the type is 64 bit or not */
1195 if (!(s->msi->flags & PCI_MSI_FLAGS_64BIT)) {
1196 XEN_PT_ERR(&s->dev,
1197 "Can't write to the upper address without 64 bit support\n");
1198 return -1;
1199 }
1200
1201 /* modify emulate register */
1202 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1203 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1204 /* update the msi_info too */
1205 s->msi->addr_hi = cfg_entry->data;
1206
1207 /* create value for writing to I/O device register */
1208 throughable_mask = ~reg->emu_mask & valid_mask;
1209 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1210
1211 /* update MSI */
1212 if (cfg_entry->data != old_addr) {
1213 if (s->msi->mapped) {
1214 xen_pt_msi_update(s);
1215 }
1216 }
1217
1218 return 0;
1219 }
1220
1221
1222 /* this function will be called twice (for 32 bit and 64 bit type) */
1223 /* write Message Data register */
1224 static int xen_pt_msgdata_reg_write(XenPCIPassthroughState *s,
1225 XenPTReg *cfg_entry, uint16_t *val,
1226 uint16_t dev_value, uint16_t valid_mask)
1227 {
1228 XenPTRegInfo *reg = cfg_entry->reg;
1229 XenPTMSI *msi = s->msi;
1230 uint16_t writable_mask = 0;
1231 uint16_t throughable_mask = 0;
1232 uint16_t old_data = cfg_entry->data;
1233 uint32_t offset = reg->offset;
1234
1235 /* check the offset whether matches the type or not */
1236 if (!xen_pt_msgdata_check_type(offset, msi->flags)) {
1237 /* exit I/O emulator */
1238 XEN_PT_ERR(&s->dev, "the offset does not match the 32/64 bit type!\n");
1239 return -1;
1240 }
1241
1242 /* modify emulate register */
1243 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1244 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1245 /* update the msi_info too */
1246 msi->data = cfg_entry->data;
1247
1248 /* create value for writing to I/O device register */
1249 throughable_mask = ~reg->emu_mask & valid_mask;
1250 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1251
1252 /* update MSI */
1253 if (cfg_entry->data != old_data) {
1254 if (msi->mapped) {
1255 xen_pt_msi_update(s);
1256 }
1257 }
1258
1259 return 0;
1260 }
1261
1262 /* MSI Capability Structure reg static infomation table */
1263 static XenPTRegInfo xen_pt_emu_reg_msi[] = {
1264 /* Next Pointer reg */
1265 {
1266 .offset = PCI_CAP_LIST_NEXT,
1267 .size = 1,
1268 .init_val = 0x00,
1269 .ro_mask = 0xFF,
1270 .emu_mask = 0xFF,
1271 .init = xen_pt_ptr_reg_init,
1272 .u.b.read = xen_pt_byte_reg_read,
1273 .u.b.write = xen_pt_byte_reg_write,
1274 },
1275 /* Message Control reg */
1276 {
1277 .offset = PCI_MSI_FLAGS,
1278 .size = 2,
1279 .init_val = 0x0000,
1280 .ro_mask = 0xFF8E,
1281 .emu_mask = 0x007F,
1282 .init = xen_pt_msgctrl_reg_init,
1283 .u.w.read = xen_pt_word_reg_read,
1284 .u.w.write = xen_pt_msgctrl_reg_write,
1285 },
1286 /* Message Address reg */
1287 {
1288 .offset = PCI_MSI_ADDRESS_LO,
1289 .size = 4,
1290 .init_val = 0x00000000,
1291 .ro_mask = 0x00000003,
1292 .emu_mask = 0xFFFFFFFF,
1293 .no_wb = 1,
1294 .init = xen_pt_common_reg_init,
1295 .u.dw.read = xen_pt_long_reg_read,
1296 .u.dw.write = xen_pt_msgaddr32_reg_write,
1297 },
1298 /* Message Upper Address reg (if PCI_MSI_FLAGS_64BIT set) */
1299 {
1300 .offset = PCI_MSI_ADDRESS_HI,
1301 .size = 4,
1302 .init_val = 0x00000000,
1303 .ro_mask = 0x00000000,
1304 .emu_mask = 0xFFFFFFFF,
1305 .no_wb = 1,
1306 .init = xen_pt_msgaddr64_reg_init,
1307 .u.dw.read = xen_pt_long_reg_read,
1308 .u.dw.write = xen_pt_msgaddr64_reg_write,
1309 },
1310 /* Message Data reg (16 bits of data for 32-bit devices) */
1311 {
1312 .offset = PCI_MSI_DATA_32,
1313 .size = 2,
1314 .init_val = 0x0000,
1315 .ro_mask = 0x0000,
1316 .emu_mask = 0xFFFF,
1317 .no_wb = 1,
1318 .init = xen_pt_msgdata_reg_init,
1319 .u.w.read = xen_pt_word_reg_read,
1320 .u.w.write = xen_pt_msgdata_reg_write,
1321 },
1322 /* Message Data reg (16 bits of data for 64-bit devices) */
1323 {
1324 .offset = PCI_MSI_DATA_64,
1325 .size = 2,
1326 .init_val = 0x0000,
1327 .ro_mask = 0x0000,
1328 .emu_mask = 0xFFFF,
1329 .no_wb = 1,
1330 .init = xen_pt_msgdata_reg_init,
1331 .u.w.read = xen_pt_word_reg_read,
1332 .u.w.write = xen_pt_msgdata_reg_write,
1333 },
1334 {
1335 .size = 0,
1336 },
1337 };
1338
1339
1340 /**************************************
1341 * MSI-X Capability
1342 */
1343
1344 /* Message Control register for MSI-X */
1345 static int xen_pt_msixctrl_reg_init(XenPCIPassthroughState *s,
1346 XenPTRegInfo *reg, uint32_t real_offset,
1347 uint32_t *data)
1348 {
1349 PCIDevice *d = &s->dev;
1350 uint16_t reg_field = 0;
1351
1352 /* use I/O device register's value as initial value */
1353 reg_field = pci_get_word(d->config + real_offset);
1354
1355 if (reg_field & PCI_MSIX_FLAGS_ENABLE) {
1356 XEN_PT_LOG(d, "MSIX already enabled, disabling it first\n");
1357 xen_host_pci_set_word(&s->real_device, real_offset,
1358 reg_field & ~PCI_MSIX_FLAGS_ENABLE);
1359 }
1360
1361 s->msix->ctrl_offset = real_offset;
1362
1363 *data = reg->init_val;
1364 return 0;
1365 }
1366 static int xen_pt_msixctrl_reg_write(XenPCIPassthroughState *s,
1367 XenPTReg *cfg_entry, uint16_t *val,
1368 uint16_t dev_value, uint16_t valid_mask)
1369 {
1370 XenPTRegInfo *reg = cfg_entry->reg;
1371 uint16_t writable_mask = 0;
1372 uint16_t throughable_mask = 0;
1373 int debug_msix_enabled_old;
1374
1375 /* modify emulate register */
1376 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1377 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1378
1379 /* create value for writing to I/O device register */
1380 throughable_mask = ~reg->emu_mask & valid_mask;
1381 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1382
1383 /* update MSI-X */
1384 if ((*val & PCI_MSIX_FLAGS_ENABLE)
1385 && !(*val & PCI_MSIX_FLAGS_MASKALL)) {
1386 xen_pt_msix_update(s);
1387 }
1388
1389 debug_msix_enabled_old = s->msix->enabled;
1390 s->msix->enabled = !!(*val & PCI_MSIX_FLAGS_ENABLE);
1391 if (s->msix->enabled != debug_msix_enabled_old) {
1392 XEN_PT_LOG(&s->dev, "%s MSI-X\n",
1393 s->msix->enabled ? "enable" : "disable");
1394 }
1395
1396 return 0;
1397 }
1398
1399 /* MSI-X Capability Structure reg static infomation table */
1400 static XenPTRegInfo xen_pt_emu_reg_msix[] = {
1401 /* Next Pointer reg */
1402 {
1403 .offset = PCI_CAP_LIST_NEXT,
1404 .size = 1,
1405 .init_val = 0x00,
1406 .ro_mask = 0xFF,
1407 .emu_mask = 0xFF,
1408 .init = xen_pt_ptr_reg_init,
1409 .u.b.read = xen_pt_byte_reg_read,
1410 .u.b.write = xen_pt_byte_reg_write,
1411 },
1412 /* Message Control reg */
1413 {
1414 .offset = PCI_MSI_FLAGS,
1415 .size = 2,
1416 .init_val = 0x0000,
1417 .ro_mask = 0x3FFF,
1418 .emu_mask = 0x0000,
1419 .init = xen_pt_msixctrl_reg_init,
1420 .u.w.read = xen_pt_word_reg_read,
1421 .u.w.write = xen_pt_msixctrl_reg_write,
1422 },
1423 {
1424 .size = 0,
1425 },
1426 };
1427
1428
1429 /****************************
1430 * Capabilities
1431 */
1432
1433 /* capability structure register group size functions */
1434
1435 static int xen_pt_reg_grp_size_init(XenPCIPassthroughState *s,
1436 const XenPTRegGroupInfo *grp_reg,
1437 uint32_t base_offset, uint8_t *size)
1438 {
1439 *size = grp_reg->grp_size;
1440 return 0;
1441 }
1442 /* get Vendor Specific Capability Structure register group size */
1443 static int xen_pt_vendor_size_init(XenPCIPassthroughState *s,
1444 const XenPTRegGroupInfo *grp_reg,
1445 uint32_t base_offset, uint8_t *size)
1446 {
1447 *size = pci_get_byte(s->dev.config + base_offset + 0x02);
1448 return 0;
1449 }
1450 /* get PCI Express Capability Structure register group size */
1451 static int xen_pt_pcie_size_init(XenPCIPassthroughState *s,
1452 const XenPTRegGroupInfo *grp_reg,
1453 uint32_t base_offset, uint8_t *size)
1454 {
1455 PCIDevice *d = &s->dev;
1456 uint8_t version = get_capability_version(s, base_offset);
1457 uint8_t type = get_device_type(s, base_offset);
1458 uint8_t pcie_size = 0;
1459
1460
1461 /* calculate size depend on capability version and device/port type */
1462 /* in case of PCI Express Base Specification Rev 1.x */
1463 if (version == 1) {
1464 /* The PCI Express Capabilities, Device Capabilities, and Device
1465 * Status/Control registers are required for all PCI Express devices.
1466 * The Link Capabilities and Link Status/Control are required for all
1467 * Endpoints that are not Root Complex Integrated Endpoints. Endpoints
1468 * are not required to implement registers other than those listed
1469 * above and terminate the capability structure.
1470 */
1471 switch (type) {
1472 case PCI_EXP_TYPE_ENDPOINT:
1473 case PCI_EXP_TYPE_LEG_END:
1474 pcie_size = 0x14;
1475 break;
1476 case PCI_EXP_TYPE_RC_END:
1477 /* has no link */
1478 pcie_size = 0x0C;
1479 break;
1480 /* only EndPoint passthrough is supported */
1481 case PCI_EXP_TYPE_ROOT_PORT:
1482 case PCI_EXP_TYPE_UPSTREAM:
1483 case PCI_EXP_TYPE_DOWNSTREAM:
1484 case PCI_EXP_TYPE_PCI_BRIDGE:
1485 case PCI_EXP_TYPE_PCIE_BRIDGE:
1486 case PCI_EXP_TYPE_RC_EC:
1487 default:
1488 XEN_PT_ERR(d, "Unsupported device/port type %#x.\n", type);
1489 return -1;
1490 }
1491 }
1492 /* in case of PCI Express Base Specification Rev 2.0 */
1493 else if (version == 2) {
1494 switch (type) {
1495 case PCI_EXP_TYPE_ENDPOINT:
1496 case PCI_EXP_TYPE_LEG_END:
1497 case PCI_EXP_TYPE_RC_END:
1498 /* For Functions that do not implement the registers,
1499 * these spaces must be hardwired to 0b.
1500 */
1501 pcie_size = 0x3C;
1502 break;
1503 /* only EndPoint passthrough is supported */
1504 case PCI_EXP_TYPE_ROOT_PORT:
1505 case PCI_EXP_TYPE_UPSTREAM:
1506 case PCI_EXP_TYPE_DOWNSTREAM:
1507 case PCI_EXP_TYPE_PCI_BRIDGE:
1508 case PCI_EXP_TYPE_PCIE_BRIDGE:
1509 case PCI_EXP_TYPE_RC_EC:
1510 default:
1511 XEN_PT_ERR(d, "Unsupported device/port type %#x.\n", type);
1512 return -1;
1513 }
1514 } else {
1515 XEN_PT_ERR(d, "Unsupported capability version %#x.\n", version);
1516 return -1;
1517 }
1518
1519 *size = pcie_size;
1520 return 0;
1521 }
1522 /* get MSI Capability Structure register group size */
1523 static int xen_pt_msi_size_init(XenPCIPassthroughState *s,
1524 const XenPTRegGroupInfo *grp_reg,
1525 uint32_t base_offset, uint8_t *size)
1526 {
1527 PCIDevice *d = &s->dev;
1528 uint16_t msg_ctrl = 0;
1529 uint8_t msi_size = 0xa;
1530
1531 msg_ctrl = pci_get_word(d->config + (base_offset + PCI_MSI_FLAGS));
1532
1533 /* check if 64-bit address is capable of per-vector masking */
1534 if (msg_ctrl & PCI_MSI_FLAGS_64BIT) {
1535 msi_size += 4;
1536 }
1537 if (msg_ctrl & PCI_MSI_FLAGS_MASKBIT) {
1538 msi_size += 10;
1539 }
1540
1541 s->msi = g_new0(XenPTMSI, 1);
1542 s->msi->pirq = XEN_PT_UNASSIGNED_PIRQ;
1543
1544 *size = msi_size;
1545 return 0;
1546 }
1547 /* get MSI-X Capability Structure register group size */
1548 static int xen_pt_msix_size_init(XenPCIPassthroughState *s,
1549 const XenPTRegGroupInfo *grp_reg,
1550 uint32_t base_offset, uint8_t *size)
1551 {
1552 int rc = 0;
1553
1554 rc = xen_pt_msix_init(s, base_offset);
1555
1556 if (rc < 0) {
1557 XEN_PT_ERR(&s->dev, "Internal error: Invalid xen_pt_msix_init.\n");
1558 return rc;
1559 }
1560
1561 *size = grp_reg->grp_size;
1562 return 0;
1563 }
1564
1565
1566 static const XenPTRegGroupInfo xen_pt_emu_reg_grps[] = {
1567 /* Header Type0 reg group */
1568 {
1569 .grp_id = 0xFF,
1570 .grp_type = XEN_PT_GRP_TYPE_EMU,
1571 .grp_size = 0x40,
1572 .size_init = xen_pt_reg_grp_size_init,
1573 .emu_regs = xen_pt_emu_reg_header0,
1574 },
1575 /* PCI PowerManagement Capability reg group */
1576 {
1577 .grp_id = PCI_CAP_ID_PM,
1578 .grp_type = XEN_PT_GRP_TYPE_EMU,
1579 .grp_size = PCI_PM_SIZEOF,
1580 .size_init = xen_pt_reg_grp_size_init,
1581 .emu_regs = xen_pt_emu_reg_pm,
1582 },
1583 /* AGP Capability Structure reg group */
1584 {
1585 .grp_id = PCI_CAP_ID_AGP,
1586 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1587 .grp_size = 0x30,
1588 .size_init = xen_pt_reg_grp_size_init,
1589 },
1590 /* Vital Product Data Capability Structure reg group */
1591 {
1592 .grp_id = PCI_CAP_ID_VPD,
1593 .grp_type = XEN_PT_GRP_TYPE_EMU,
1594 .grp_size = 0x08,
1595 .size_init = xen_pt_reg_grp_size_init,
1596 .emu_regs = xen_pt_emu_reg_vpd,
1597 },
1598 /* Slot Identification reg group */
1599 {
1600 .grp_id = PCI_CAP_ID_SLOTID,
1601 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1602 .grp_size = 0x04,
1603 .size_init = xen_pt_reg_grp_size_init,
1604 },
1605 /* MSI Capability Structure reg group */
1606 {
1607 .grp_id = PCI_CAP_ID_MSI,
1608 .grp_type = XEN_PT_GRP_TYPE_EMU,
1609 .grp_size = 0xFF,
1610 .size_init = xen_pt_msi_size_init,
1611 .emu_regs = xen_pt_emu_reg_msi,
1612 },
1613 /* PCI-X Capabilities List Item reg group */
1614 {
1615 .grp_id = PCI_CAP_ID_PCIX,
1616 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1617 .grp_size = 0x18,
1618 .size_init = xen_pt_reg_grp_size_init,
1619 },
1620 /* Vendor Specific Capability Structure reg group */
1621 {
1622 .grp_id = PCI_CAP_ID_VNDR,
1623 .grp_type = XEN_PT_GRP_TYPE_EMU,
1624 .grp_size = 0xFF,
1625 .size_init = xen_pt_vendor_size_init,
1626 .emu_regs = xen_pt_emu_reg_vendor,
1627 },
1628 /* SHPC Capability List Item reg group */
1629 {
1630 .grp_id = PCI_CAP_ID_SHPC,
1631 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1632 .grp_size = 0x08,
1633 .size_init = xen_pt_reg_grp_size_init,
1634 },
1635 /* Subsystem ID and Subsystem Vendor ID Capability List Item reg group */
1636 {
1637 .grp_id = PCI_CAP_ID_SSVID,
1638 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1639 .grp_size = 0x08,
1640 .size_init = xen_pt_reg_grp_size_init,
1641 },
1642 /* AGP 8x Capability Structure reg group */
1643 {
1644 .grp_id = PCI_CAP_ID_AGP3,
1645 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1646 .grp_size = 0x30,
1647 .size_init = xen_pt_reg_grp_size_init,
1648 },
1649 /* PCI Express Capability Structure reg group */
1650 {
1651 .grp_id = PCI_CAP_ID_EXP,
1652 .grp_type = XEN_PT_GRP_TYPE_EMU,
1653 .grp_size = 0xFF,
1654 .size_init = xen_pt_pcie_size_init,
1655 .emu_regs = xen_pt_emu_reg_pcie,
1656 },
1657 /* MSI-X Capability Structure reg group */
1658 {
1659 .grp_id = PCI_CAP_ID_MSIX,
1660 .grp_type = XEN_PT_GRP_TYPE_EMU,
1661 .grp_size = 0x0C,
1662 .size_init = xen_pt_msix_size_init,
1663 .emu_regs = xen_pt_emu_reg_msix,
1664 },
1665 {
1666 .grp_size = 0,
1667 },
1668 };
1669
1670 /* initialize Capabilities Pointer or Next Pointer register */
1671 static int xen_pt_ptr_reg_init(XenPCIPassthroughState *s,
1672 XenPTRegInfo *reg, uint32_t real_offset,
1673 uint32_t *data)
1674 {
1675 int i;
1676 uint8_t *config = s->dev.config;
1677 uint32_t reg_field = pci_get_byte(config + real_offset);
1678 uint8_t cap_id = 0;
1679
1680 /* find capability offset */
1681 while (reg_field) {
1682 for (i = 0; xen_pt_emu_reg_grps[i].grp_size != 0; i++) {
1683 if (xen_pt_hide_dev_cap(&s->real_device,
1684 xen_pt_emu_reg_grps[i].grp_id)) {
1685 continue;
1686 }
1687
1688 cap_id = pci_get_byte(config + reg_field + PCI_CAP_LIST_ID);
1689 if (xen_pt_emu_reg_grps[i].grp_id == cap_id) {
1690 if (xen_pt_emu_reg_grps[i].grp_type == XEN_PT_GRP_TYPE_EMU) {
1691 goto out;
1692 }
1693 /* ignore the 0 hardwired capability, find next one */
1694 break;
1695 }
1696 }
1697
1698 /* next capability */
1699 reg_field = pci_get_byte(config + reg_field + PCI_CAP_LIST_NEXT);
1700 }
1701
1702 out:
1703 *data = reg_field;
1704 return 0;
1705 }
1706
1707
1708 /*************
1709 * Main
1710 */
1711
1712 static uint8_t find_cap_offset(XenPCIPassthroughState *s, uint8_t cap)
1713 {
1714 uint8_t id;
1715 unsigned max_cap = PCI_CAP_MAX;
1716 uint8_t pos = PCI_CAPABILITY_LIST;
1717 uint8_t status = 0;
1718
1719 if (xen_host_pci_get_byte(&s->real_device, PCI_STATUS, &status)) {
1720 return 0;
1721 }
1722 if ((status & PCI_STATUS_CAP_LIST) == 0) {
1723 return 0;
1724 }
1725
1726 while (max_cap--) {
1727 if (xen_host_pci_get_byte(&s->real_device, pos, &pos)) {
1728 break;
1729 }
1730 if (pos < PCI_CONFIG_HEADER_SIZE) {
1731 break;
1732 }
1733
1734 pos &= ~3;
1735 if (xen_host_pci_get_byte(&s->real_device,
1736 pos + PCI_CAP_LIST_ID, &id)) {
1737 break;
1738 }
1739
1740 if (id == 0xff) {
1741 break;
1742 }
1743 if (id == cap) {
1744 return pos;
1745 }
1746
1747 pos += PCI_CAP_LIST_NEXT;
1748 }
1749 return 0;
1750 }
1751
1752 static int xen_pt_config_reg_init(XenPCIPassthroughState *s,
1753 XenPTRegGroup *reg_grp, XenPTRegInfo *reg)
1754 {
1755 XenPTReg *reg_entry;
1756 uint32_t data = 0;
1757 int rc = 0;
1758
1759 reg_entry = g_new0(XenPTReg, 1);
1760 reg_entry->reg = reg;
1761
1762 if (reg->init) {
1763 /* initialize emulate register */
1764 rc = reg->init(s, reg_entry->reg,
1765 reg_grp->base_offset + reg->offset, &data);
1766 if (rc < 0) {
1767 free(reg_entry);
1768 return rc;
1769 }
1770 if (data == XEN_PT_INVALID_REG) {
1771 /* free unused BAR register entry */
1772 free(reg_entry);
1773 return 0;
1774 }
1775 /* set register value */
1776 reg_entry->data = data;
1777 }
1778 /* list add register entry */
1779 QLIST_INSERT_HEAD(&reg_grp->reg_tbl_list, reg_entry, entries);
1780
1781 return 0;
1782 }
1783
1784 int xen_pt_config_init(XenPCIPassthroughState *s)
1785 {
1786 int i, rc;
1787
1788 QLIST_INIT(&s->reg_grps);
1789
1790 for (i = 0; xen_pt_emu_reg_grps[i].grp_size != 0; i++) {
1791 uint32_t reg_grp_offset = 0;
1792 XenPTRegGroup *reg_grp_entry = NULL;
1793
1794 if (xen_pt_emu_reg_grps[i].grp_id != 0xFF) {
1795 if (xen_pt_hide_dev_cap(&s->real_device,
1796 xen_pt_emu_reg_grps[i].grp_id)) {
1797 continue;
1798 }
1799
1800 reg_grp_offset = find_cap_offset(s, xen_pt_emu_reg_grps[i].grp_id);
1801
1802 if (!reg_grp_offset) {
1803 continue;
1804 }
1805 }
1806
1807 reg_grp_entry = g_new0(XenPTRegGroup, 1);
1808 QLIST_INIT(&reg_grp_entry->reg_tbl_list);
1809 QLIST_INSERT_HEAD(&s->reg_grps, reg_grp_entry, entries);
1810
1811 reg_grp_entry->base_offset = reg_grp_offset;
1812 reg_grp_entry->reg_grp = xen_pt_emu_reg_grps + i;
1813 if (xen_pt_emu_reg_grps[i].size_init) {
1814 /* get register group size */
1815 rc = xen_pt_emu_reg_grps[i].size_init(s, reg_grp_entry->reg_grp,
1816 reg_grp_offset,
1817 &reg_grp_entry->size);
1818 if (rc < 0) {
1819 xen_pt_config_delete(s);
1820 return rc;
1821 }
1822 }
1823
1824 if (xen_pt_emu_reg_grps[i].grp_type == XEN_PT_GRP_TYPE_EMU) {
1825 if (xen_pt_emu_reg_grps[i].emu_regs) {
1826 int j = 0;
1827 XenPTRegInfo *regs = xen_pt_emu_reg_grps[i].emu_regs;
1828 /* initialize capability register */
1829 for (j = 0; regs->size != 0; j++, regs++) {
1830 /* initialize capability register */
1831 rc = xen_pt_config_reg_init(s, reg_grp_entry, regs);
1832 if (rc < 0) {
1833 xen_pt_config_delete(s);
1834 return rc;
1835 }
1836 }
1837 }
1838 }
1839 }
1840
1841 return 0;
1842 }
1843
1844 /* delete all emulate register */
1845 void xen_pt_config_delete(XenPCIPassthroughState *s)
1846 {
1847 struct XenPTRegGroup *reg_group, *next_grp;
1848 struct XenPTReg *reg, *next_reg;
1849
1850 /* free MSI/MSI-X info table */
1851 if (s->msix) {
1852 xen_pt_msix_delete(s);
1853 }
1854 if (s->msi) {
1855 g_free(s->msi);
1856 }
1857
1858 /* free all register group entry */
1859 QLIST_FOREACH_SAFE(reg_group, &s->reg_grps, entries, next_grp) {
1860 /* free all register entry */
1861 QLIST_FOREACH_SAFE(reg, &reg_group->reg_tbl_list, entries, next_reg) {
1862 QLIST_REMOVE(reg, entries);
1863 g_free(reg);
1864 }
1865
1866 QLIST_REMOVE(reg_group, entries);
1867 g_free(reg_group);
1868 }
1869 }
AR7 emulation for QEMU