hw/ioh3420.c

   1 /*
   2  * ioh3420.c
   3  * Intel X58 north bridge IOH
   4  * PCI Express root port device id 3420
   5  *
   6  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   7  *                    VA Linux Systems Japan K.K.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "pci_ids.h"
  24 #include "msi.h"
  25 #include "pcie.h"
  26 #include "ioh3420.h"
  27
  28 #define PCI_DEVICE_ID_IOH_EPORT         0x3420  /* D0:F0 express mode */
  29 #define PCI_DEVICE_ID_IOH_REV           0x2
  30 #define IOH_EP_SSVID_OFFSET             0x40
  31 #define IOH_EP_SSVID_SVID               PCI_VENDOR_ID_INTEL
  32 #define IOH_EP_SSVID_SSID               0
  33 #define IOH_EP_MSI_OFFSET               0x60
  34 #define IOH_EP_MSI_SUPPORTED_FLAGS      PCI_MSI_FLAGS_MASKBIT
  35 #define IOH_EP_MSI_NR_VECTOR            2
  36 #define IOH_EP_EXP_OFFSET               0x90
  37 #define IOH_EP_AER_OFFSET               0x100
  38
  39 /*
  40  * If two MSI vector are allocated, Advanced Error Interrupt Message Number
  41  * is 1. otherwise 0.
  42  * 17.12.5.10 RPERRSTS,  32:27 bit Advanced Error Interrupt Message Number.
  43  */
  44 static uint8_t ioh3420_aer_vector(const PCIDevice *d)
  45 {
  46     switch (msi_nr_vectors_allocated(d)) {
  47     case 1:
  48         return 0;
  49     case 2:
  50         return 1;
  51     case 4:
  52     case 8:
  53     case 16:
  54     case 32:
  55     default:
  56         break;
  57     }
  58     abort();
  59     return 0;
  60 }
  61
  62 static void ioh3420_aer_vector_update(PCIDevice *d)
  63 {
  64     pcie_aer_root_set_vector(d, ioh3420_aer_vector(d));
  65 }
  66
  67 static void ioh3420_write_config(PCIDevice *d,
  68                                    uint32_t address, uint32_t val, int len)
  69 {
  70     uint32_t root_cmd =
  71         pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
  72
  73     pci_bridge_write_config(d, address, val, len);
  74     ioh3420_aer_vector_update(d);
  75     pcie_cap_slot_write_config(d, address, val, len);
  76     pcie_aer_write_config(d, address, val, len);
  77     pcie_aer_root_write_config(d, address, val, len, root_cmd);
  78 }
  79
  80 static void ioh3420_reset(DeviceState *qdev)
  81 {
  82     PCIDevice *d = PCI_DEVICE(qdev);
  83
  84     ioh3420_aer_vector_update(d);
  85     pcie_cap_root_reset(d);
  86     pcie_cap_deverr_reset(d);
  87     pcie_cap_slot_reset(d);
  88     pcie_aer_root_reset(d);
  89     pci_bridge_reset(qdev);
  90     pci_bridge_disable_base_limit(d);
  91 }
  92
  93 static int ioh3420_initfn(PCIDevice *d)
  94 {
  95     PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
  96     PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
  97     PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
  98     int rc;
  99     int tmp;
 100
 101     rc = pci_bridge_initfn(d);
 102     if (rc < 0) {
 103         return rc;
 104     }
 105
 106     pcie_port_init_reg(d);
 107
 108     rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET,
 109                                IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID);
 110     if (rc < 0) {
 111         goto err_bridge;
 112     }
 113     rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR,
 114                   IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
 115                   IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
 116     if (rc < 0) {
 117         goto err_bridge;
 118     }
 119     rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port);
 120     if (rc < 0) {
 121         goto err_msi;
 122     }
 123     pcie_cap_deverr_init(d);
 124     pcie_cap_slot_init(d, s->slot);
 125     pcie_chassis_create(s->chassis);
 126     rc = pcie_chassis_add_slot(s);
 127     if (rc < 0) {
 128         goto err_pcie_cap;
 129         return rc;
 130     }
 131     pcie_cap_root_init(d);
 132     rc = pcie_aer_init(d, IOH_EP_AER_OFFSET);
 133     if (rc < 0) {
 134         goto err;
 135     }
 136     pcie_aer_root_init(d);
 137     ioh3420_aer_vector_update(d);
 138     return 0;
 139
 140 err:
 141     pcie_chassis_del_slot(s);
 142 err_pcie_cap:
 143     pcie_cap_exit(d);
 144 err_msi:
 145     msi_uninit(d);
 146 err_bridge:
 147     tmp = pci_bridge_exitfn(d);
 148     assert(!tmp);
 149     return rc;
 150 }
 151
 152 static int ioh3420_exitfn(PCIDevice *d)
 153 {
 154     PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
 155     PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
 156     PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
 157
 158     pcie_aer_exit(d);
 159     pcie_chassis_del_slot(s);
 160     pcie_cap_exit(d);
 161     msi_uninit(d);
 162     return pci_bridge_exitfn(d);
 163 }
 164
 165 PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction,
 166                          const char *bus_name, pci_map_irq_fn map_irq,
 167                          uint8_t port, uint8_t chassis, uint16_t slot)
 168 {
 169     PCIDevice *d;
 170     PCIBridge *br;
 171     DeviceState *qdev;
 172
 173     d = pci_create_multifunction(bus, devfn, multifunction, "ioh3420");
 174     if (!d) {
 175         return NULL;
 176     }
 177     br = DO_UPCAST(PCIBridge, dev, d);
 178
 179     qdev = &br->dev.qdev;
 180     pci_bridge_map_irq(br, bus_name, map_irq);
 181     qdev_prop_set_uint8(qdev, "port", port);
 182     qdev_prop_set_uint8(qdev, "chassis", chassis);
 183     qdev_prop_set_uint16(qdev, "slot", slot);
 184     qdev_init_nofail(qdev);
 185
 186     return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br));
 187 }
 188
 189 static const VMStateDescription vmstate_ioh3420 = {
 190     .name = "ioh-3240-express-root-port",
 191     .version_id = 1,
 192     .minimum_version_id = 1,
 193     .minimum_version_id_old = 1,
 194     .post_load = pcie_cap_slot_post_load,
 195     .fields = (VMStateField[]) {
 196         VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
 197         VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0,
 198                        vmstate_pcie_aer_log, PCIEAERLog),
 199         VMSTATE_END_OF_LIST()
 200     }
 201 };
 202
 203 static Property ioh3420_properties[] = {
 204     DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
 205     DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
 206     DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
 207     DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
 208     port.br.dev.exp.aer_log.log_max,
 209     PCIE_AER_LOG_MAX_DEFAULT),
 210     DEFINE_PROP_END_OF_LIST(),
 211 };
 212
 213 static void ioh3420_class_init(ObjectClass *klass, void *data)
 214 {
 215     DeviceClass *dc = DEVICE_CLASS(klass);
 216     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 217
 218     k->is_express = 1;
 219     k->is_bridge = 1;
 220     k->config_write = ioh3420_write_config;
 221     k->init = ioh3420_initfn;
 222     k->exit = ioh3420_exitfn;
 223     k->vendor_id = PCI_VENDOR_ID_INTEL;
 224     k->device_id = PCI_DEVICE_ID_IOH_EPORT;
 225     k->revision = PCI_DEVICE_ID_IOH_REV;
 226     dc->desc = "Intel IOH device id 3420 PCIE Root Port";
 227     dc->reset = ioh3420_reset;
 228     dc->vmsd = &vmstate_ioh3420;
 229     dc->props = ioh3420_properties;
 230 }
 231
 232 static TypeInfo ioh3420_info = {
 233     .name          = "ioh3420",
 234     .parent        = TYPE_PCI_DEVICE,
 235     .instance_size = sizeof(PCIESlot),
 236     .class_init    = ioh3420_class_init,
 237 };
 238
 239 static void ioh3420_register_types(void)
 240 {
 241     type_register_static(&ioh3420_info);
 242 }
 243
 244 type_init(ioh3420_register_types)
 245
 246 /*
 247  * Local variables:
 248  *  c-indent-level: 4
 249  *  c-basic-offset: 4
 250  *  tab-width: 8
 251  *  indent-tab-mode: nil
 252  * End:
 253  */