target/ppc/internal.h

   1 /*
   2  *  PowerPC interal definitions for qemu.
   3  *
   4  * This library is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU Lesser General Public
   6  * License as published by the Free Software Foundation; either
   7  * version 2 of the License, or (at your option) any later version.
   8  *
   9  * This library is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * Lesser General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU Lesser General Public
  15  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef PPC_INTERNAL_H
  19 #define PPC_INTERNAL_H
  20
  21 #define FUNC_MASK(name, ret_type, size, max_val)                  \
  22 static inline ret_type name(uint##size##_t start,                 \
  23                               uint##size##_t end)                 \
  24 {                                                                 \
  25     ret_type ret, max_bit = size - 1;                             \
  26                                                                   \
  27     if (likely(start == 0)) {                                     \
  28         ret = max_val << (max_bit - end);                         \
  29     } else if (likely(end == max_bit)) {                          \
  30         ret = max_val >> start;                                   \
  31     } else {                                                      \
  32         ret = (((uint##size##_t)(-1ULL)) >> (start)) ^            \
  33             (((uint##size##_t)(-1ULL) >> (end)) >> 1);            \
  34         if (unlikely(start > end)) {                              \
  35             return ~ret;                                          \
  36         }                                                         \
  37     }                                                             \
  38                                                                   \
  39     return ret;                                                   \
  40 }
  41
  42 #if defined(TARGET_PPC64)
  43 FUNC_MASK(MASK, target_ulong, 64, UINT64_MAX);
  44 #else
  45 FUNC_MASK(MASK, target_ulong, 32, UINT32_MAX);
  46 #endif
  47 FUNC_MASK(mask_u32, uint32_t, 32, UINT32_MAX);
  48 FUNC_MASK(mask_u64, uint64_t, 64, UINT64_MAX);
  49
  50 /*****************************************************************************/
  51 /***                           Instruction decoding                        ***/
  52 #define EXTRACT_HELPER(name, shift, nb)                                       \
  53 static inline uint32_t name(uint32_t opcode)                                  \
  54 {                                                                             \
  55     return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \
  56 }
  57
  58 #define EXTRACT_SHELPER(name, shift, nb)                                      \
  59 static inline int32_t name(uint32_t opcode)                                   \
  60 {                                                                             \
  61     return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \
  62 }
  63
  64 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2)                  \
  65 static inline uint32_t name(uint32_t opcode)                                  \
  66 {                                                                             \
  67     return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) |             \
  68             ((opcode >> (shift2)) & ((1 << (nb2)) - 1));                      \
  69 }
  70
  71 #define EXTRACT_HELPER_SPLIT_3(name,                                          \
  72                               d0_bits, shift_op_d0, shift_d0,                 \
  73                               d1_bits, shift_op_d1, shift_d1,                 \
  74                               d2_bits, shift_op_d2, shift_d2)                 \
  75 static inline int16_t name(uint32_t opcode)                                   \
  76 {                                                                             \
  77     return                                                                    \
  78         (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
  79         (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
  80         (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2));  \
  81 }
  82
  83
  84 /* Opcode part 1 */
  85 EXTRACT_HELPER(opc1, 26, 6);
  86 /* Opcode part 2 */
  87 EXTRACT_HELPER(opc2, 1, 5);
  88 /* Opcode part 3 */
  89 EXTRACT_HELPER(opc3, 6, 5);
  90 /* Opcode part 4 */
  91 EXTRACT_HELPER(opc4, 16, 5);
  92 /* Update Cr0 flags */
  93 EXTRACT_HELPER(Rc, 0, 1);
  94 /* Update Cr6 flags (Altivec) */
  95 EXTRACT_HELPER(Rc21, 10, 1);
  96 /* Destination */
  97 EXTRACT_HELPER(rD, 21, 5);
  98 /* Source */
  99 EXTRACT_HELPER(rS, 21, 5);
 100 /* First operand */
 101 EXTRACT_HELPER(rA, 16, 5);
 102 /* Second operand */
 103 EXTRACT_HELPER(rB, 11, 5);
 104 /* Third operand */
 105 EXTRACT_HELPER(rC, 6, 5);
 106 /***                               Get CRn                                 ***/
 107 EXTRACT_HELPER(crfD, 23, 3);
 108 EXTRACT_HELPER(BF, 23, 3);
 109 EXTRACT_HELPER(crfS, 18, 3);
 110 EXTRACT_HELPER(crbD, 21, 5);
 111 EXTRACT_HELPER(crbA, 16, 5);
 112 EXTRACT_HELPER(crbB, 11, 5);
 113 /* SPR / TBL */
 114 EXTRACT_HELPER(_SPR, 11, 10);
 115 static inline uint32_t SPR(uint32_t opcode)
 116 {
 117     uint32_t sprn = _SPR(opcode);
 118
 119     return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
 120 }
 121 /***                              Get constants                            ***/
 122 /* 16 bits signed immediate value */
 123 EXTRACT_SHELPER(SIMM, 0, 16);
 124 /* 16 bits unsigned immediate value */
 125 EXTRACT_HELPER(UIMM, 0, 16);
 126 /* 5 bits signed immediate value */
 127 EXTRACT_HELPER(SIMM5, 16, 5);
 128 /* 5 bits signed immediate value */
 129 EXTRACT_HELPER(UIMM5, 16, 5);
 130 /* 4 bits unsigned immediate value */
 131 EXTRACT_HELPER(UIMM4, 16, 4);
 132 /* Bit count */
 133 EXTRACT_HELPER(NB, 11, 5);
 134 /* Shift count */
 135 EXTRACT_HELPER(SH, 11, 5);
 136 /* lwat/stwat/ldat/lwat */
 137 EXTRACT_HELPER(FC, 11, 5);
 138 /* Vector shift count */
 139 EXTRACT_HELPER(VSH, 6, 4);
 140 /* Mask start */
 141 EXTRACT_HELPER(MB, 6, 5);
 142 /* Mask end */
 143 EXTRACT_HELPER(ME, 1, 5);
 144 /* Trap operand */
 145 EXTRACT_HELPER(TO, 21, 5);
 146
 147 EXTRACT_HELPER(CRM, 12, 8);
 148
 149 #ifndef CONFIG_USER_ONLY
 150 EXTRACT_HELPER(SR, 16, 4);
 151 #endif
 152
 153 /* mtfsf/mtfsfi */
 154 EXTRACT_HELPER(FPBF, 23, 3);
 155 EXTRACT_HELPER(FPIMM, 12, 4);
 156 EXTRACT_HELPER(FPL, 25, 1);
 157 EXTRACT_HELPER(FPFLM, 17, 8);
 158 EXTRACT_HELPER(FPW, 16, 1);
 159
 160 /* addpcis */
 161 EXTRACT_HELPER_SPLIT_3(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
 162 #if defined(TARGET_PPC64)
 163 /* darn */
 164 EXTRACT_HELPER(L, 16, 2);
 165 #endif
 166
 167 /***                            Jump target decoding                       ***/
 168 /* Immediate address */
 169 static inline target_ulong LI(uint32_t opcode)
 170 {
 171     return (opcode >> 0) & 0x03FFFFFC;
 172 }
 173
 174 static inline uint32_t BD(uint32_t opcode)
 175 {
 176     return (opcode >> 0) & 0xFFFC;
 177 }
 178
 179 EXTRACT_HELPER(BO, 21, 5);
 180 EXTRACT_HELPER(BI, 16, 5);
 181 /* Absolute/relative address */
 182 EXTRACT_HELPER(AA, 1, 1);
 183 /* Link */
 184 EXTRACT_HELPER(LK, 0, 1);
 185
 186 /* DFP Z22-form */
 187 EXTRACT_HELPER(DCM, 10, 6)
 188
 189 /* DFP Z23-form */
 190 EXTRACT_HELPER(RMC, 9, 2)
 191 EXTRACT_HELPER(Rrm, 16, 1)
 192
 193 EXTRACT_HELPER_SPLIT(DQxT, 3, 1, 21, 5);
 194 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
 195 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
 196 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
 197 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
 198 EXTRACT_HELPER_SPLIT(xC, 3, 1,  6, 5);
 199 EXTRACT_HELPER(DM, 8, 2);
 200 EXTRACT_HELPER(UIM, 16, 2);
 201 EXTRACT_HELPER(SHW, 8, 2);
 202 EXTRACT_HELPER(SP, 19, 2);
 203 EXTRACT_HELPER(IMM8, 11, 8);
 204 EXTRACT_HELPER(DCMX, 16, 7);
 205 EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6);
 206
 207 typedef union _ppc_vsr_t {
 208     uint8_t u8[16];
 209     uint16_t u16[8];
 210     uint32_t u32[4];
 211     uint64_t u64[2];
 212     float32 f32[4];
 213     float64 f64[2];
 214     float128 f128;
 215     Int128  s128;
 216 } ppc_vsr_t;
 217
 218 #if defined(HOST_WORDS_BIGENDIAN)
 219 #define VsrB(i) u8[i]
 220 #define VsrH(i) u16[i]
 221 #define VsrW(i) u32[i]
 222 #define VsrD(i) u64[i]
 223 #else
 224 #define VsrB(i) u8[15 - (i)]
 225 #define VsrH(i) u16[7 - (i)]
 226 #define VsrW(i) u32[3 - (i)]
 227 #define VsrD(i) u64[1 - (i)]
 228 #endif
 229
 230 static inline void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
 231 {
 232     if (n < 32) {
 233         vsr->VsrD(0) = env->fpr[n];
 234         vsr->VsrD(1) = env->vsr[n];
 235     } else {
 236         vsr->u64[0] = env->avr[n - 32].u64[0];
 237         vsr->u64[1] = env->avr[n - 32].u64[1];
 238     }
 239 }
 240
 241 static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
 242 {
 243     if (n < 32) {
 244         env->fpr[n] = vsr->VsrD(0);
 245         env->vsr[n] = vsr->VsrD(1);
 246     } else {
 247         env->avr[n - 32].u64[0] = vsr->u64[0];
 248         env->avr[n - 32].u64[1] = vsr->u64[1];
 249     }
 250 }
 251
 252 void helper_compute_fprf_float16(CPUPPCState *env, float16 arg);
 253 void helper_compute_fprf_float32(CPUPPCState *env, float32 arg);
 254 void helper_compute_fprf_float128(CPUPPCState *env, float128 arg);
 255 #endif /* PPC_INTERNAL_H */