raw: Check byte range uniformly
[qemu/ar7.git] / exec.c
blobc30f9055988bdd96339a35f3faef0bc394801c09
1 /*
2 * Virtual page mapping
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
22 #include "qemu/cutils.h"
23 #include "cpu.h"
24 #include "exec/exec-all.h"
25 #include "exec/target_page.h"
26 #include "tcg.h"
27 #include "hw/qdev-core.h"
28 #include "hw/qdev-properties.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/boards.h"
31 #include "hw/xen/xen.h"
32 #endif
33 #include "sysemu/kvm.h"
34 #include "sysemu/sysemu.h"
35 #include "qemu/timer.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #if defined(CONFIG_USER_ONLY)
39 #include "qemu.h"
40 #else /* !CONFIG_USER_ONLY */
41 #include "hw/hw.h"
42 #include "exec/memory.h"
43 #include "exec/ioport.h"
44 #include "sysemu/dma.h"
45 #include "sysemu/numa.h"
46 #include "sysemu/hw_accel.h"
47 #include "exec/address-spaces.h"
48 #include "sysemu/xen-mapcache.h"
49 #include "trace-root.h"
51 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
52 #include <linux/falloc.h>
53 #endif
55 #endif
56 #include "qemu/rcu_queue.h"
57 #include "qemu/main-loop.h"
58 #include "translate-all.h"
59 #include "sysemu/replay.h"
61 #include "exec/memory-internal.h"
62 #include "exec/ram_addr.h"
63 #include "exec/log.h"
65 #include "migration/vmstate.h"
67 #include "qemu/range.h"
68 #ifndef _WIN32
69 #include "qemu/mmap-alloc.h"
70 #endif
72 #include "monitor/monitor.h"
74 //#define DEBUG_SUBPAGE
76 #if !defined(CONFIG_USER_ONLY)
77 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
78 * are protected by the ramlist lock.
80 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
82 static MemoryRegion *system_memory;
83 static MemoryRegion *system_io;
85 AddressSpace address_space_io;
86 AddressSpace address_space_memory;
88 MemoryRegion io_mem_rom, io_mem_notdirty;
89 static MemoryRegion io_mem_unassigned;
91 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
92 #define RAM_PREALLOC (1 << 0)
94 /* RAM is mmap-ed with MAP_SHARED */
95 #define RAM_SHARED (1 << 1)
97 /* Only a portion of RAM (used_length) is actually used, and migrated.
98 * This used_length size can change across reboots.
100 #define RAM_RESIZEABLE (1 << 2)
102 /* UFFDIO_ZEROPAGE is available on this RAMBlock to atomically
103 * zero the page and wake waiting processes.
104 * (Set during postcopy)
106 #define RAM_UF_ZEROPAGE (1 << 3)
107 #endif
109 #ifdef TARGET_PAGE_BITS_VARY
110 int target_page_bits;
111 bool target_page_bits_decided;
112 #endif
114 struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
115 /* current CPU in the current thread. It is only valid inside
116 cpu_exec() */
117 __thread CPUState *current_cpu;
118 /* 0 = Do not count executed instructions.
119 1 = Precise instruction counting.
120 2 = Adaptive rate instruction counting. */
121 int use_icount;
123 uintptr_t qemu_host_page_size;
124 intptr_t qemu_host_page_mask;
126 bool set_preferred_target_page_bits(int bits)
128 /* The target page size is the lowest common denominator for all
129 * the CPUs in the system, so we can only make it smaller, never
130 * larger. And we can't make it smaller once we've committed to
131 * a particular size.
133 #ifdef TARGET_PAGE_BITS_VARY
134 assert(bits >= TARGET_PAGE_BITS_MIN);
135 if (target_page_bits == 0 || target_page_bits > bits) {
136 if (target_page_bits_decided) {
137 return false;
139 target_page_bits = bits;
141 #endif
142 return true;
145 #if !defined(CONFIG_USER_ONLY)
147 static void finalize_target_page_bits(void)
149 #ifdef TARGET_PAGE_BITS_VARY
150 if (target_page_bits == 0) {
151 target_page_bits = TARGET_PAGE_BITS_MIN;
153 target_page_bits_decided = true;
154 #endif
157 typedef struct PhysPageEntry PhysPageEntry;
159 struct PhysPageEntry {
160 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
161 uint32_t skip : 6;
162 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
163 uint32_t ptr : 26;
166 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
168 /* Size of the L2 (and L3, etc) page tables. */
169 #define ADDR_SPACE_BITS 64
171 #define P_L2_BITS 9
172 #define P_L2_SIZE (1 << P_L2_BITS)
174 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
176 typedef PhysPageEntry Node[P_L2_SIZE];
178 typedef struct PhysPageMap {
179 struct rcu_head rcu;
181 unsigned sections_nb;
182 unsigned sections_nb_alloc;
183 unsigned nodes_nb;
184 unsigned nodes_nb_alloc;
185 Node *nodes;
186 MemoryRegionSection *sections;
187 } PhysPageMap;
189 struct AddressSpaceDispatch {
190 MemoryRegionSection *mru_section;
191 /* This is a multi-level map on the physical address space.
192 * The bottom level has pointers to MemoryRegionSections.
194 PhysPageEntry phys_map;
195 PhysPageMap map;
198 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
199 typedef struct subpage_t {
200 MemoryRegion iomem;
201 FlatView *fv;
202 hwaddr base;
203 uint16_t sub_section[];
204 } subpage_t;
206 #define PHYS_SECTION_UNASSIGNED 0
207 #define PHYS_SECTION_NOTDIRTY 1
208 #define PHYS_SECTION_ROM 2
209 #define PHYS_SECTION_WATCH 3
211 static void io_mem_init(void);
212 static void memory_map_init(void);
213 static void tcg_commit(MemoryListener *listener);
215 static MemoryRegion io_mem_watch;
218 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
219 * @cpu: the CPU whose AddressSpace this is
220 * @as: the AddressSpace itself
221 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
222 * @tcg_as_listener: listener for tracking changes to the AddressSpace
224 struct CPUAddressSpace {
225 CPUState *cpu;
226 AddressSpace *as;
227 struct AddressSpaceDispatch *memory_dispatch;
228 MemoryListener tcg_as_listener;
231 struct DirtyBitmapSnapshot {
232 ram_addr_t start;
233 ram_addr_t end;
234 unsigned long dirty[];
237 #endif
239 #if !defined(CONFIG_USER_ONLY)
241 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
243 static unsigned alloc_hint = 16;
244 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
245 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint);
246 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes);
247 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
248 alloc_hint = map->nodes_nb_alloc;
252 static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf)
254 unsigned i;
255 uint32_t ret;
256 PhysPageEntry e;
257 PhysPageEntry *p;
259 ret = map->nodes_nb++;
260 p = map->nodes[ret];
261 assert(ret != PHYS_MAP_NODE_NIL);
262 assert(ret != map->nodes_nb_alloc);
264 e.skip = leaf ? 0 : 1;
265 e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL;
266 for (i = 0; i < P_L2_SIZE; ++i) {
267 memcpy(&p[i], &e, sizeof(e));
269 return ret;
272 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
273 hwaddr *index, hwaddr *nb, uint16_t leaf,
274 int level)
276 PhysPageEntry *p;
277 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
279 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
280 lp->ptr = phys_map_node_alloc(map, level == 0);
282 p = map->nodes[lp->ptr];
283 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
285 while (*nb && lp < &p[P_L2_SIZE]) {
286 if ((*index & (step - 1)) == 0 && *nb >= step) {
287 lp->skip = 0;
288 lp->ptr = leaf;
289 *index += step;
290 *nb -= step;
291 } else {
292 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
294 ++lp;
298 static void phys_page_set(AddressSpaceDispatch *d,
299 hwaddr index, hwaddr nb,
300 uint16_t leaf)
302 /* Wildly overreserve - it doesn't matter much. */
303 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
305 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
308 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
309 * and update our entry so we can skip it and go directly to the destination.
311 static void phys_page_compact(PhysPageEntry *lp, Node *nodes)
313 unsigned valid_ptr = P_L2_SIZE;
314 int valid = 0;
315 PhysPageEntry *p;
316 int i;
318 if (lp->ptr == PHYS_MAP_NODE_NIL) {
319 return;
322 p = nodes[lp->ptr];
323 for (i = 0; i < P_L2_SIZE; i++) {
324 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
325 continue;
328 valid_ptr = i;
329 valid++;
330 if (p[i].skip) {
331 phys_page_compact(&p[i], nodes);
335 /* We can only compress if there's only one child. */
336 if (valid != 1) {
337 return;
340 assert(valid_ptr < P_L2_SIZE);
342 /* Don't compress if it won't fit in the # of bits we have. */
343 if (lp->skip + p[valid_ptr].skip >= (1 << 3)) {
344 return;
347 lp->ptr = p[valid_ptr].ptr;
348 if (!p[valid_ptr].skip) {
349 /* If our only child is a leaf, make this a leaf. */
350 /* By design, we should have made this node a leaf to begin with so we
351 * should never reach here.
352 * But since it's so simple to handle this, let's do it just in case we
353 * change this rule.
355 lp->skip = 0;
356 } else {
357 lp->skip += p[valid_ptr].skip;
361 void address_space_dispatch_compact(AddressSpaceDispatch *d)
363 if (d->phys_map.skip) {
364 phys_page_compact(&d->phys_map, d->map.nodes);
368 static inline bool section_covers_addr(const MemoryRegionSection *section,
369 hwaddr addr)
371 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
372 * the section must cover the entire address space.
374 return int128_gethi(section->size) ||
375 range_covers_byte(section->offset_within_address_space,
376 int128_getlo(section->size), addr);
379 static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr)
381 PhysPageEntry lp = d->phys_map, *p;
382 Node *nodes = d->map.nodes;
383 MemoryRegionSection *sections = d->map.sections;
384 hwaddr index = addr >> TARGET_PAGE_BITS;
385 int i;
387 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
388 if (lp.ptr == PHYS_MAP_NODE_NIL) {
389 return &sections[PHYS_SECTION_UNASSIGNED];
391 p = nodes[lp.ptr];
392 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
395 if (section_covers_addr(&sections[lp.ptr], addr)) {
396 return &sections[lp.ptr];
397 } else {
398 return &sections[PHYS_SECTION_UNASSIGNED];
402 bool memory_region_is_unassigned(MemoryRegion *mr)
404 return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device
405 && mr != &io_mem_watch;
408 /* Called from RCU critical section */
409 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
410 hwaddr addr,
411 bool resolve_subpage)
413 MemoryRegionSection *section = atomic_read(&d->mru_section);
414 subpage_t *subpage;
416 if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] ||
417 !section_covers_addr(section, addr)) {
418 section = phys_page_find(d, addr);
419 atomic_set(&d->mru_section, section);
421 if (resolve_subpage && section->mr->subpage) {
422 subpage = container_of(section->mr, subpage_t, iomem);
423 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
425 return section;
428 /* Called from RCU critical section */
429 static MemoryRegionSection *
430 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
431 hwaddr *plen, bool resolve_subpage)
433 MemoryRegionSection *section;
434 MemoryRegion *mr;
435 Int128 diff;
437 section = address_space_lookup_region(d, addr, resolve_subpage);
438 /* Compute offset within MemoryRegionSection */
439 addr -= section->offset_within_address_space;
441 /* Compute offset within MemoryRegion */
442 *xlat = addr + section->offset_within_region;
444 mr = section->mr;
446 /* MMIO registers can be expected to perform full-width accesses based only
447 * on their address, without considering adjacent registers that could
448 * decode to completely different MemoryRegions. When such registers
449 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
450 * regions overlap wildly. For this reason we cannot clamp the accesses
451 * here.
453 * If the length is small (as is the case for address_space_ldl/stl),
454 * everything works fine. If the incoming length is large, however,
455 * the caller really has to do the clamping through memory_access_size.
457 if (memory_region_is_ram(mr)) {
458 diff = int128_sub(section->size, int128_make64(addr));
459 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
461 return section;
465 * address_space_translate_iommu - translate an address through an IOMMU
466 * memory region and then through the target address space.
468 * @iommu_mr: the IOMMU memory region that we start the translation from
469 * @addr: the address to be translated through the MMU
470 * @xlat: the translated address offset within the destination memory region.
471 * It cannot be %NULL.
472 * @plen_out: valid read/write length of the translated address. It
473 * cannot be %NULL.
474 * @page_mask_out: page mask for the translated address. This
475 * should only be meaningful for IOMMU translated
476 * addresses, since there may be huge pages that this bit
477 * would tell. It can be %NULL if we don't care about it.
478 * @is_write: whether the translation operation is for write
479 * @is_mmio: whether this can be MMIO, set true if it can
480 * @target_as: the address space targeted by the IOMMU
481 * @attrs: transaction attributes
483 * This function is called from RCU critical section. It is the common
484 * part of flatview_do_translate and address_space_translate_cached.
486 static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iommu_mr,
487 hwaddr *xlat,
488 hwaddr *plen_out,
489 hwaddr *page_mask_out,
490 bool is_write,
491 bool is_mmio,
492 AddressSpace **target_as,
493 MemTxAttrs attrs)
495 MemoryRegionSection *section;
496 hwaddr page_mask = (hwaddr)-1;
498 do {
499 hwaddr addr = *xlat;
500 IOMMUMemoryRegionClass *imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
501 IOMMUTLBEntry iotlb = imrc->translate(iommu_mr, addr, is_write ?
502 IOMMU_WO : IOMMU_RO);
504 if (!(iotlb.perm & (1 << is_write))) {
505 goto unassigned;
508 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
509 | (addr & iotlb.addr_mask));
510 page_mask &= iotlb.addr_mask;
511 *plen_out = MIN(*plen_out, (addr | iotlb.addr_mask) - addr + 1);
512 *target_as = iotlb.target_as;
514 section = address_space_translate_internal(
515 address_space_to_dispatch(iotlb.target_as), addr, xlat,
516 plen_out, is_mmio);
518 iommu_mr = memory_region_get_iommu(section->mr);
519 } while (unlikely(iommu_mr));
521 if (page_mask_out) {
522 *page_mask_out = page_mask;
524 return *section;
526 unassigned:
527 return (MemoryRegionSection) { .mr = &io_mem_unassigned };
531 * flatview_do_translate - translate an address in FlatView
533 * @fv: the flat view that we want to translate on
534 * @addr: the address to be translated in above address space
535 * @xlat: the translated address offset within memory region. It
536 * cannot be @NULL.
537 * @plen_out: valid read/write length of the translated address. It
538 * can be @NULL when we don't care about it.
539 * @page_mask_out: page mask for the translated address. This
540 * should only be meaningful for IOMMU translated
541 * addresses, since there may be huge pages that this bit
542 * would tell. It can be @NULL if we don't care about it.
543 * @is_write: whether the translation operation is for write
544 * @is_mmio: whether this can be MMIO, set true if it can
545 * @target_as: the address space targeted by the IOMMU
546 * @attrs: memory transaction attributes
548 * This function is called from RCU critical section
550 static MemoryRegionSection flatview_do_translate(FlatView *fv,
551 hwaddr addr,
552 hwaddr *xlat,
553 hwaddr *plen_out,
554 hwaddr *page_mask_out,
555 bool is_write,
556 bool is_mmio,
557 AddressSpace **target_as,
558 MemTxAttrs attrs)
560 MemoryRegionSection *section;
561 IOMMUMemoryRegion *iommu_mr;
562 hwaddr plen = (hwaddr)(-1);
564 if (!plen_out) {
565 plen_out = &plen;
568 section = address_space_translate_internal(
569 flatview_to_dispatch(fv), addr, xlat,
570 plen_out, is_mmio);
572 iommu_mr = memory_region_get_iommu(section->mr);
573 if (unlikely(iommu_mr)) {
574 return address_space_translate_iommu(iommu_mr, xlat,
575 plen_out, page_mask_out,
576 is_write, is_mmio,
577 target_as, attrs);
579 if (page_mask_out) {
580 /* Not behind an IOMMU, use default page size. */
581 *page_mask_out = ~TARGET_PAGE_MASK;
584 return *section;
587 /* Called from RCU critical section */
588 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
589 bool is_write, MemTxAttrs attrs)
591 MemoryRegionSection section;
592 hwaddr xlat, page_mask;
595 * This can never be MMIO, and we don't really care about plen,
596 * but page mask.
598 section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
599 NULL, &page_mask, is_write, false, &as,
600 attrs);
602 /* Illegal translation */
603 if (section.mr == &io_mem_unassigned) {
604 goto iotlb_fail;
607 /* Convert memory region offset into address space offset */
608 xlat += section.offset_within_address_space -
609 section.offset_within_region;
611 return (IOMMUTLBEntry) {
612 .target_as = as,
613 .iova = addr & ~page_mask,
614 .translated_addr = xlat & ~page_mask,
615 .addr_mask = page_mask,
616 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
617 .perm = IOMMU_RW,
620 iotlb_fail:
621 return (IOMMUTLBEntry) {0};
624 /* Called from RCU critical section */
625 MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
626 hwaddr *plen, bool is_write,
627 MemTxAttrs attrs)
629 MemoryRegion *mr;
630 MemoryRegionSection section;
631 AddressSpace *as = NULL;
633 /* This can be MMIO, so setup MMIO bit. */
634 section = flatview_do_translate(fv, addr, xlat, plen, NULL,
635 is_write, true, &as, attrs);
636 mr = section.mr;
638 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
639 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
640 *plen = MIN(page, *plen);
643 return mr;
646 /* Called from RCU critical section */
647 MemoryRegionSection *
648 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
649 hwaddr *xlat, hwaddr *plen)
651 MemoryRegionSection *section;
652 AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch);
654 section = address_space_translate_internal(d, addr, xlat, plen, false);
656 assert(!memory_region_is_iommu(section->mr));
657 return section;
659 #endif
661 #if !defined(CONFIG_USER_ONLY)
663 static int cpu_common_post_load(void *opaque, int version_id)
665 CPUState *cpu = opaque;
667 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
668 version_id is increased. */
669 cpu->interrupt_request &= ~0x01;
670 tlb_flush(cpu);
672 /* loadvm has just updated the content of RAM, bypassing the
673 * usual mechanisms that ensure we flush TBs for writes to
674 * memory we've translated code from. So we must flush all TBs,
675 * which will now be stale.
677 tb_flush(cpu);
679 return 0;
682 static int cpu_common_pre_load(void *opaque)
684 CPUState *cpu = opaque;
686 cpu->exception_index = -1;
688 return 0;
691 static bool cpu_common_exception_index_needed(void *opaque)
693 CPUState *cpu = opaque;
695 return tcg_enabled() && cpu->exception_index != -1;
698 static const VMStateDescription vmstate_cpu_common_exception_index = {
699 .name = "cpu_common/exception_index",
700 .version_id = 1,
701 .minimum_version_id = 1,
702 .needed = cpu_common_exception_index_needed,
703 .fields = (VMStateField[]) {
704 VMSTATE_INT32(exception_index, CPUState),
705 VMSTATE_END_OF_LIST()
709 static bool cpu_common_crash_occurred_needed(void *opaque)
711 CPUState *cpu = opaque;
713 return cpu->crash_occurred;
716 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
717 .name = "cpu_common/crash_occurred",
718 .version_id = 1,
719 .minimum_version_id = 1,
720 .needed = cpu_common_crash_occurred_needed,
721 .fields = (VMStateField[]) {
722 VMSTATE_BOOL(crash_occurred, CPUState),
723 VMSTATE_END_OF_LIST()
727 const VMStateDescription vmstate_cpu_common = {
728 .name = "cpu_common",
729 .version_id = 1,
730 .minimum_version_id = 1,
731 .pre_load = cpu_common_pre_load,
732 .post_load = cpu_common_post_load,
733 .fields = (VMStateField[]) {
734 VMSTATE_UINT32(halted, CPUState),
735 VMSTATE_UINT32(interrupt_request, CPUState),
736 VMSTATE_END_OF_LIST()
738 .subsections = (const VMStateDescription*[]) {
739 &vmstate_cpu_common_exception_index,
740 &vmstate_cpu_common_crash_occurred,
741 NULL
745 #endif
747 CPUState *qemu_get_cpu(int index)
749 CPUState *cpu;
751 CPU_FOREACH(cpu) {
752 if (cpu->cpu_index == index) {
753 return cpu;
757 return NULL;
760 #if !defined(CONFIG_USER_ONLY)
761 void cpu_address_space_init(CPUState *cpu, int asidx,
762 const char *prefix, MemoryRegion *mr)
764 CPUAddressSpace *newas;
765 AddressSpace *as = g_new0(AddressSpace, 1);
766 char *as_name;
768 assert(mr);
769 as_name = g_strdup_printf("%s-%d", prefix, cpu->cpu_index);
770 address_space_init(as, mr, as_name);
771 g_free(as_name);
773 /* Target code should have set num_ases before calling us */
774 assert(asidx < cpu->num_ases);
776 if (asidx == 0) {
777 /* address space 0 gets the convenience alias */
778 cpu->as = as;
781 /* KVM cannot currently support multiple address spaces. */
782 assert(asidx == 0 || !kvm_enabled());
784 if (!cpu->cpu_ases) {
785 cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases);
788 newas = &cpu->cpu_ases[asidx];
789 newas->cpu = cpu;
790 newas->as = as;
791 if (tcg_enabled()) {
792 newas->tcg_as_listener.commit = tcg_commit;
793 memory_listener_register(&newas->tcg_as_listener, as);
797 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
799 /* Return the AddressSpace corresponding to the specified index */
800 return cpu->cpu_ases[asidx].as;
802 #endif
804 void cpu_exec_unrealizefn(CPUState *cpu)
806 CPUClass *cc = CPU_GET_CLASS(cpu);
808 cpu_list_remove(cpu);
810 if (cc->vmsd != NULL) {
811 vmstate_unregister(NULL, cc->vmsd, cpu);
813 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
814 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
818 Property cpu_common_props[] = {
819 #ifndef CONFIG_USER_ONLY
820 /* Create a memory property for softmmu CPU object,
821 * so users can wire up its memory. (This can't go in qom/cpu.c
822 * because that file is compiled only once for both user-mode
823 * and system builds.) The default if no link is set up is to use
824 * the system address space.
826 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
827 MemoryRegion *),
828 #endif
829 DEFINE_PROP_END_OF_LIST(),
832 void cpu_exec_initfn(CPUState *cpu)
834 cpu->as = NULL;
835 cpu->num_ases = 0;
837 #ifndef CONFIG_USER_ONLY
838 cpu->thread_id = qemu_get_thread_id();
839 cpu->memory = system_memory;
840 object_ref(OBJECT(cpu->memory));
841 #endif
844 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
846 CPUClass *cc = CPU_GET_CLASS(cpu);
847 static bool tcg_target_initialized;
849 cpu_list_add(cpu);
851 if (tcg_enabled() && !tcg_target_initialized) {
852 tcg_target_initialized = true;
853 cc->tcg_initialize();
856 #ifndef CONFIG_USER_ONLY
857 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
858 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
860 if (cc->vmsd != NULL) {
861 vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
863 #endif
866 const char *parse_cpu_model(const char *cpu_model)
868 ObjectClass *oc;
869 CPUClass *cc;
870 gchar **model_pieces;
871 const char *cpu_type;
873 model_pieces = g_strsplit(cpu_model, ",", 2);
875 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
876 if (oc == NULL) {
877 error_report("unable to find CPU model '%s'", model_pieces[0]);
878 g_strfreev(model_pieces);
879 exit(EXIT_FAILURE);
882 cpu_type = object_class_get_name(oc);
883 cc = CPU_CLASS(oc);
884 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
885 g_strfreev(model_pieces);
886 return cpu_type;
889 #if defined(CONFIG_USER_ONLY)
890 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
892 mmap_lock();
893 tb_lock();
894 tb_invalidate_phys_page_range(pc, pc + 1, 0);
895 tb_unlock();
896 mmap_unlock();
898 #else
899 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
901 MemTxAttrs attrs;
902 hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs);
903 int asidx = cpu_asidx_from_attrs(cpu, attrs);
904 if (phys != -1) {
905 /* Locks grabbed by tb_invalidate_phys_addr */
906 tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
907 phys | (pc & ~TARGET_PAGE_MASK), attrs);
910 #endif
912 #if defined(CONFIG_USER_ONLY)
913 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
918 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
919 int flags)
921 return -ENOSYS;
924 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
928 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
929 int flags, CPUWatchpoint **watchpoint)
931 return -ENOSYS;
933 #else
934 /* Add a watchpoint. */
935 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
936 int flags, CPUWatchpoint **watchpoint)
938 CPUWatchpoint *wp;
940 /* forbid ranges which are empty or run off the end of the address space */
941 if (len == 0 || (addr + len - 1) < addr) {
942 error_report("tried to set invalid watchpoint at %"
943 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
944 return -EINVAL;
946 wp = g_malloc(sizeof(*wp));
948 wp->vaddr = addr;
949 wp->len = len;
950 wp->flags = flags;
952 /* keep all GDB-injected watchpoints in front */
953 if (flags & BP_GDB) {
954 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
955 } else {
956 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
959 tlb_flush_page(cpu, addr);
961 if (watchpoint)
962 *watchpoint = wp;
963 return 0;
966 /* Remove a specific watchpoint. */
967 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
968 int flags)
970 CPUWatchpoint *wp;
972 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
973 if (addr == wp->vaddr && len == wp->len
974 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
975 cpu_watchpoint_remove_by_ref(cpu, wp);
976 return 0;
979 return -ENOENT;
982 /* Remove a specific watchpoint by reference. */
983 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
985 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
987 tlb_flush_page(cpu, watchpoint->vaddr);
989 g_free(watchpoint);
992 /* Remove all matching watchpoints. */
993 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
995 CPUWatchpoint *wp, *next;
997 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
998 if (wp->flags & mask) {
999 cpu_watchpoint_remove_by_ref(cpu, wp);
1004 /* Return true if this watchpoint address matches the specified
1005 * access (ie the address range covered by the watchpoint overlaps
1006 * partially or completely with the address range covered by the
1007 * access).
1009 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp,
1010 vaddr addr,
1011 vaddr len)
1013 /* We know the lengths are non-zero, but a little caution is
1014 * required to avoid errors in the case where the range ends
1015 * exactly at the top of the address space and so addr + len
1016 * wraps round to zero.
1018 vaddr wpend = wp->vaddr + wp->len - 1;
1019 vaddr addrend = addr + len - 1;
1021 return !(addr > wpend || wp->vaddr > addrend);
1024 #endif
1026 /* Add a breakpoint. */
1027 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
1028 CPUBreakpoint **breakpoint)
1030 CPUBreakpoint *bp;
1032 bp = g_malloc(sizeof(*bp));
1034 bp->pc = pc;
1035 bp->flags = flags;
1037 /* keep all GDB-injected breakpoints in front */
1038 if (flags & BP_GDB) {
1039 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
1040 } else {
1041 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
1044 breakpoint_invalidate(cpu, pc);
1046 if (breakpoint) {
1047 *breakpoint = bp;
1049 return 0;
1052 /* Remove a specific breakpoint. */
1053 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
1055 CPUBreakpoint *bp;
1057 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
1058 if (bp->pc == pc && bp->flags == flags) {
1059 cpu_breakpoint_remove_by_ref(cpu, bp);
1060 return 0;
1063 return -ENOENT;
1066 /* Remove a specific breakpoint by reference. */
1067 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
1069 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
1071 breakpoint_invalidate(cpu, breakpoint->pc);
1073 g_free(breakpoint);
1076 /* Remove all matching breakpoints. */
1077 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
1079 CPUBreakpoint *bp, *next;
1081 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
1082 if (bp->flags & mask) {
1083 cpu_breakpoint_remove_by_ref(cpu, bp);
1088 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1089 CPU loop after each instruction */
1090 void cpu_single_step(CPUState *cpu, int enabled)
1092 if (cpu->singlestep_enabled != enabled) {
1093 cpu->singlestep_enabled = enabled;
1094 if (kvm_enabled()) {
1095 kvm_update_guest_debug(cpu, 0);
1096 } else {
1097 /* must flush all the translated code to avoid inconsistencies */
1098 /* XXX: only flush what is necessary */
1099 tb_flush(cpu);
1104 void cpu_abort(CPUState *cpu, const char *fmt, ...)
1106 va_list ap;
1107 va_list ap2;
1109 va_start(ap, fmt);
1110 va_copy(ap2, ap);
1111 fprintf(stderr, "qemu: fatal: ");
1112 vfprintf(stderr, fmt, ap);
1113 fprintf(stderr, "\n");
1114 cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1115 if (qemu_log_separate()) {
1116 qemu_log_lock();
1117 qemu_log("qemu: fatal: ");
1118 qemu_log_vprintf(fmt, ap2);
1119 qemu_log("\n");
1120 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1121 qemu_log_flush();
1122 qemu_log_unlock();
1123 qemu_log_close();
1125 va_end(ap2);
1126 va_end(ap);
1127 replay_finish();
1128 #if defined(CONFIG_USER_ONLY)
1130 struct sigaction act;
1131 sigfillset(&act.sa_mask);
1132 act.sa_handler = SIG_DFL;
1133 sigaction(SIGABRT, &act, NULL);
1135 #endif
1136 abort();
1139 #if !defined(CONFIG_USER_ONLY)
1140 /* Called from RCU critical section */
1141 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
1143 RAMBlock *block;
1145 block = atomic_rcu_read(&ram_list.mru_block);
1146 if (block && addr - block->offset < block->max_length) {
1147 return block;
1149 RAMBLOCK_FOREACH(block) {
1150 if (addr - block->offset < block->max_length) {
1151 goto found;
1155 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1156 abort();
1158 found:
1159 /* It is safe to write mru_block outside the iothread lock. This
1160 * is what happens:
1162 * mru_block = xxx
1163 * rcu_read_unlock()
1164 * xxx removed from list
1165 * rcu_read_lock()
1166 * read mru_block
1167 * mru_block = NULL;
1168 * call_rcu(reclaim_ramblock, xxx);
1169 * rcu_read_unlock()
1171 * atomic_rcu_set is not needed here. The block was already published
1172 * when it was placed into the list. Here we're just making an extra
1173 * copy of the pointer.
1175 ram_list.mru_block = block;
1176 return block;
1179 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
1181 CPUState *cpu;
1182 ram_addr_t start1;
1183 RAMBlock *block;
1184 ram_addr_t end;
1186 end = TARGET_PAGE_ALIGN(start + length);
1187 start &= TARGET_PAGE_MASK;
1189 rcu_read_lock();
1190 block = qemu_get_ram_block(start);
1191 assert(block == qemu_get_ram_block(end - 1));
1192 start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
1193 CPU_FOREACH(cpu) {
1194 tlb_reset_dirty(cpu, start1, length);
1196 rcu_read_unlock();
1199 /* Note: start and end must be within the same ram block. */
1200 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start,
1201 ram_addr_t length,
1202 unsigned client)
1204 DirtyMemoryBlocks *blocks;
1205 unsigned long end, page;
1206 bool dirty = false;
1208 if (length == 0) {
1209 return false;
1212 end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
1213 page = start >> TARGET_PAGE_BITS;
1215 rcu_read_lock();
1217 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1219 while (page < end) {
1220 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1221 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1222 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1224 dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx],
1225 offset, num);
1226 page += num;
1229 rcu_read_unlock();
1231 if (dirty && tcg_enabled()) {
1232 tlb_reset_dirty_range_all(start, length);
1235 return dirty;
1238 DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty
1239 (ram_addr_t start, ram_addr_t length, unsigned client)
1241 DirtyMemoryBlocks *blocks;
1242 unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL);
1243 ram_addr_t first = QEMU_ALIGN_DOWN(start, align);
1244 ram_addr_t last = QEMU_ALIGN_UP(start + length, align);
1245 DirtyBitmapSnapshot *snap;
1246 unsigned long page, end, dest;
1248 snap = g_malloc0(sizeof(*snap) +
1249 ((last - first) >> (TARGET_PAGE_BITS + 3)));
1250 snap->start = first;
1251 snap->end = last;
1253 page = first >> TARGET_PAGE_BITS;
1254 end = last >> TARGET_PAGE_BITS;
1255 dest = 0;
1257 rcu_read_lock();
1259 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1261 while (page < end) {
1262 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1263 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1264 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1266 assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL)));
1267 assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL)));
1268 offset >>= BITS_PER_LEVEL;
1270 bitmap_copy_and_clear_atomic(snap->dirty + dest,
1271 blocks->blocks[idx] + offset,
1272 num);
1273 page += num;
1274 dest += num >> BITS_PER_LEVEL;
1277 rcu_read_unlock();
1279 if (tcg_enabled()) {
1280 tlb_reset_dirty_range_all(start, length);
1283 return snap;
1286 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap,
1287 ram_addr_t start,
1288 ram_addr_t length)
1290 unsigned long page, end;
1292 assert(start >= snap->start);
1293 assert(start + length <= snap->end);
1295 end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS;
1296 page = (start - snap->start) >> TARGET_PAGE_BITS;
1298 while (page < end) {
1299 if (test_bit(page, snap->dirty)) {
1300 return true;
1302 page++;
1304 return false;
1307 /* Called from RCU critical section */
1308 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
1309 MemoryRegionSection *section,
1310 target_ulong vaddr,
1311 hwaddr paddr, hwaddr xlat,
1312 int prot,
1313 target_ulong *address)
1315 hwaddr iotlb;
1316 CPUWatchpoint *wp;
1318 if (memory_region_is_ram(section->mr)) {
1319 /* Normal RAM. */
1320 iotlb = memory_region_get_ram_addr(section->mr) + xlat;
1321 if (!section->readonly) {
1322 iotlb |= PHYS_SECTION_NOTDIRTY;
1323 } else {
1324 iotlb |= PHYS_SECTION_ROM;
1326 } else {
1327 AddressSpaceDispatch *d;
1329 d = flatview_to_dispatch(section->fv);
1330 iotlb = section - d->map.sections;
1331 iotlb += xlat;
1334 /* Make accesses to pages with watchpoints go via the
1335 watchpoint trap routines. */
1336 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1337 if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) {
1338 /* Avoid trapping reads of pages with a write breakpoint. */
1339 if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
1340 iotlb = PHYS_SECTION_WATCH + paddr;
1341 *address |= TLB_MMIO;
1342 break;
1347 return iotlb;
1349 #endif /* defined(CONFIG_USER_ONLY) */
1351 #if !defined(CONFIG_USER_ONLY)
1353 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1354 uint16_t section);
1355 static subpage_t *subpage_init(FlatView *fv, hwaddr base);
1357 static void *(*phys_mem_alloc)(size_t size, uint64_t *align, bool shared) =
1358 qemu_anon_ram_alloc;
1361 * Set a custom physical guest memory alloator.
1362 * Accelerators with unusual needs may need this. Hopefully, we can
1363 * get rid of it eventually.
1365 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align, bool shared))
1367 phys_mem_alloc = alloc;
1370 static uint16_t phys_section_add(PhysPageMap *map,
1371 MemoryRegionSection *section)
1373 /* The physical section number is ORed with a page-aligned
1374 * pointer to produce the iotlb entries. Thus it should
1375 * never overflow into the page-aligned value.
1377 assert(map->sections_nb < TARGET_PAGE_SIZE);
1379 if (map->sections_nb == map->sections_nb_alloc) {
1380 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
1381 map->sections = g_renew(MemoryRegionSection, map->sections,
1382 map->sections_nb_alloc);
1384 map->sections[map->sections_nb] = *section;
1385 memory_region_ref(section->mr);
1386 return map->sections_nb++;
1389 static void phys_section_destroy(MemoryRegion *mr)
1391 bool have_sub_page = mr->subpage;
1393 memory_region_unref(mr);
1395 if (have_sub_page) {
1396 subpage_t *subpage = container_of(mr, subpage_t, iomem);
1397 object_unref(OBJECT(&subpage->iomem));
1398 g_free(subpage);
1402 static void phys_sections_free(PhysPageMap *map)
1404 while (map->sections_nb > 0) {
1405 MemoryRegionSection *section = &map->sections[--map->sections_nb];
1406 phys_section_destroy(section->mr);
1408 g_free(map->sections);
1409 g_free(map->nodes);
1412 static void register_subpage(FlatView *fv, MemoryRegionSection *section)
1414 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1415 subpage_t *subpage;
1416 hwaddr base = section->offset_within_address_space
1417 & TARGET_PAGE_MASK;
1418 MemoryRegionSection *existing = phys_page_find(d, base);
1419 MemoryRegionSection subsection = {
1420 .offset_within_address_space = base,
1421 .size = int128_make64(TARGET_PAGE_SIZE),
1423 hwaddr start, end;
1425 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
1427 if (!(existing->mr->subpage)) {
1428 subpage = subpage_init(fv, base);
1429 subsection.fv = fv;
1430 subsection.mr = &subpage->iomem;
1431 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
1432 phys_section_add(&d->map, &subsection));
1433 } else {
1434 subpage = container_of(existing->mr, subpage_t, iomem);
1436 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
1437 end = start + int128_get64(section->size) - 1;
1438 subpage_register(subpage, start, end,
1439 phys_section_add(&d->map, section));
1443 static void register_multipage(FlatView *fv,
1444 MemoryRegionSection *section)
1446 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1447 hwaddr start_addr = section->offset_within_address_space;
1448 uint16_t section_index = phys_section_add(&d->map, section);
1449 uint64_t num_pages = int128_get64(int128_rshift(section->size,
1450 TARGET_PAGE_BITS));
1452 assert(num_pages);
1453 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
1456 void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section)
1458 MemoryRegionSection now = *section, remain = *section;
1459 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
1461 if (now.offset_within_address_space & ~TARGET_PAGE_MASK) {
1462 uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space)
1463 - now.offset_within_address_space;
1465 now.size = int128_min(int128_make64(left), now.size);
1466 register_subpage(fv, &now);
1467 } else {
1468 now.size = int128_zero();
1470 while (int128_ne(remain.size, now.size)) {
1471 remain.size = int128_sub(remain.size, now.size);
1472 remain.offset_within_address_space += int128_get64(now.size);
1473 remain.offset_within_region += int128_get64(now.size);
1474 now = remain;
1475 if (int128_lt(remain.size, page_size)) {
1476 register_subpage(fv, &now);
1477 } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1478 now.size = page_size;
1479 register_subpage(fv, &now);
1480 } else {
1481 now.size = int128_and(now.size, int128_neg(page_size));
1482 register_multipage(fv, &now);
1487 void qemu_flush_coalesced_mmio_buffer(void)
1489 if (kvm_enabled())
1490 kvm_flush_coalesced_mmio_buffer();
1493 void qemu_mutex_lock_ramlist(void)
1495 qemu_mutex_lock(&ram_list.mutex);
1498 void qemu_mutex_unlock_ramlist(void)
1500 qemu_mutex_unlock(&ram_list.mutex);
1503 void ram_block_dump(Monitor *mon)
1505 RAMBlock *block;
1506 char *psize;
1508 rcu_read_lock();
1509 monitor_printf(mon, "%24s %8s %18s %18s %18s\n",
1510 "Block Name", "PSize", "Offset", "Used", "Total");
1511 RAMBLOCK_FOREACH(block) {
1512 psize = size_to_str(block->page_size);
1513 monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64
1514 " 0x%016" PRIx64 "\n", block->idstr, psize,
1515 (uint64_t)block->offset,
1516 (uint64_t)block->used_length,
1517 (uint64_t)block->max_length);
1518 g_free(psize);
1520 rcu_read_unlock();
1523 #ifdef __linux__
1525 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1526 * may or may not name the same files / on the same filesystem now as
1527 * when we actually open and map them. Iterate over the file
1528 * descriptors instead, and use qemu_fd_getpagesize().
1530 static int find_max_supported_pagesize(Object *obj, void *opaque)
1532 long *hpsize_min = opaque;
1534 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1535 long hpsize = host_memory_backend_pagesize(MEMORY_BACKEND(obj));
1537 if (hpsize < *hpsize_min) {
1538 *hpsize_min = hpsize;
1542 return 0;
1545 long qemu_getrampagesize(void)
1547 long hpsize = LONG_MAX;
1548 long mainrampagesize;
1549 Object *memdev_root;
1551 mainrampagesize = qemu_mempath_getpagesize(mem_path);
1553 /* it's possible we have memory-backend objects with
1554 * hugepage-backed RAM. these may get mapped into system
1555 * address space via -numa parameters or memory hotplug
1556 * hooks. we want to take these into account, but we
1557 * also want to make sure these supported hugepage
1558 * sizes are applicable across the entire range of memory
1559 * we may boot from, so we take the min across all
1560 * backends, and assume normal pages in cases where a
1561 * backend isn't backed by hugepages.
1563 memdev_root = object_resolve_path("/objects", NULL);
1564 if (memdev_root) {
1565 object_child_foreach(memdev_root, find_max_supported_pagesize, &hpsize);
1567 if (hpsize == LONG_MAX) {
1568 /* No additional memory regions found ==> Report main RAM page size */
1569 return mainrampagesize;
1572 /* If NUMA is disabled or the NUMA nodes are not backed with a
1573 * memory-backend, then there is at least one node using "normal" RAM,
1574 * so if its page size is smaller we have got to report that size instead.
1576 if (hpsize > mainrampagesize &&
1577 (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) {
1578 static bool warned;
1579 if (!warned) {
1580 error_report("Huge page support disabled (n/a for main memory).");
1581 warned = true;
1583 return mainrampagesize;
1586 return hpsize;
1588 #else
1589 long qemu_getrampagesize(void)
1591 return getpagesize();
1593 #endif
1595 #ifdef __linux__
1596 static int64_t get_file_size(int fd)
1598 int64_t size = lseek(fd, 0, SEEK_END);
1599 if (size < 0) {
1600 return -errno;
1602 return size;
1605 static int file_ram_open(const char *path,
1606 const char *region_name,
1607 bool *created,
1608 Error **errp)
1610 char *filename;
1611 char *sanitized_name;
1612 char *c;
1613 int fd = -1;
1615 *created = false;
1616 for (;;) {
1617 fd = open(path, O_RDWR);
1618 if (fd >= 0) {
1619 /* @path names an existing file, use it */
1620 break;
1622 if (errno == ENOENT) {
1623 /* @path names a file that doesn't exist, create it */
1624 fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644);
1625 if (fd >= 0) {
1626 *created = true;
1627 break;
1629 } else if (errno == EISDIR) {
1630 /* @path names a directory, create a file there */
1631 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1632 sanitized_name = g_strdup(region_name);
1633 for (c = sanitized_name; *c != '\0'; c++) {
1634 if (*c == '/') {
1635 *c = '_';
1639 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1640 sanitized_name);
1641 g_free(sanitized_name);
1643 fd = mkstemp(filename);
1644 if (fd >= 0) {
1645 unlink(filename);
1646 g_free(filename);
1647 break;
1649 g_free(filename);
1651 if (errno != EEXIST && errno != EINTR) {
1652 error_setg_errno(errp, errno,
1653 "can't open backing store %s for guest RAM",
1654 path);
1655 return -1;
1658 * Try again on EINTR and EEXIST. The latter happens when
1659 * something else creates the file between our two open().
1663 return fd;
1666 static void *file_ram_alloc(RAMBlock *block,
1667 ram_addr_t memory,
1668 int fd,
1669 bool truncate,
1670 Error **errp)
1672 void *area;
1674 block->page_size = qemu_fd_getpagesize(fd);
1675 if (block->mr->align % block->page_size) {
1676 error_setg(errp, "alignment 0x%" PRIx64
1677 " must be multiples of page size 0x%zx",
1678 block->mr->align, block->page_size);
1679 return NULL;
1681 block->mr->align = MAX(block->page_size, block->mr->align);
1682 #if defined(__s390x__)
1683 if (kvm_enabled()) {
1684 block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN);
1686 #endif
1688 if (memory < block->page_size) {
1689 error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to "
1690 "or larger than page size 0x%zx",
1691 memory, block->page_size);
1692 return NULL;
1695 memory = ROUND_UP(memory, block->page_size);
1698 * ftruncate is not supported by hugetlbfs in older
1699 * hosts, so don't bother bailing out on errors.
1700 * If anything goes wrong with it under other filesystems,
1701 * mmap will fail.
1703 * Do not truncate the non-empty backend file to avoid corrupting
1704 * the existing data in the file. Disabling shrinking is not
1705 * enough. For example, the current vNVDIMM implementation stores
1706 * the guest NVDIMM labels at the end of the backend file. If the
1707 * backend file is later extended, QEMU will not be able to find
1708 * those labels. Therefore, extending the non-empty backend file
1709 * is disabled as well.
1711 if (truncate && ftruncate(fd, memory)) {
1712 perror("ftruncate");
1715 area = qemu_ram_mmap(fd, memory, block->mr->align,
1716 block->flags & RAM_SHARED);
1717 if (area == MAP_FAILED) {
1718 error_setg_errno(errp, errno,
1719 "unable to map backing store for guest RAM");
1720 return NULL;
1723 if (mem_prealloc) {
1724 os_mem_prealloc(fd, area, memory, smp_cpus, errp);
1725 if (errp && *errp) {
1726 qemu_ram_munmap(area, memory);
1727 return NULL;
1731 block->fd = fd;
1732 return area;
1734 #endif
1736 /* Allocate space within the ram_addr_t space that governs the
1737 * dirty bitmaps.
1738 * Called with the ramlist lock held.
1740 static ram_addr_t find_ram_offset(ram_addr_t size)
1742 RAMBlock *block, *next_block;
1743 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1745 assert(size != 0); /* it would hand out same offset multiple times */
1747 if (QLIST_EMPTY_RCU(&ram_list.blocks)) {
1748 return 0;
1751 RAMBLOCK_FOREACH(block) {
1752 ram_addr_t candidate, next = RAM_ADDR_MAX;
1754 /* Align blocks to start on a 'long' in the bitmap
1755 * which makes the bitmap sync'ing take the fast path.
1757 candidate = block->offset + block->max_length;
1758 candidate = ROUND_UP(candidate, BITS_PER_LONG << TARGET_PAGE_BITS);
1760 /* Search for the closest following block
1761 * and find the gap.
1763 RAMBLOCK_FOREACH(next_block) {
1764 if (next_block->offset >= candidate) {
1765 next = MIN(next, next_block->offset);
1769 /* If it fits remember our place and remember the size
1770 * of gap, but keep going so that we might find a smaller
1771 * gap to fill so avoiding fragmentation.
1773 if (next - candidate >= size && next - candidate < mingap) {
1774 offset = candidate;
1775 mingap = next - candidate;
1778 trace_find_ram_offset_loop(size, candidate, offset, next, mingap);
1781 if (offset == RAM_ADDR_MAX) {
1782 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
1783 (uint64_t)size);
1784 abort();
1787 trace_find_ram_offset(size, offset);
1789 return offset;
1792 unsigned long last_ram_page(void)
1794 RAMBlock *block;
1795 ram_addr_t last = 0;
1797 rcu_read_lock();
1798 RAMBLOCK_FOREACH(block) {
1799 last = MAX(last, block->offset + block->max_length);
1801 rcu_read_unlock();
1802 return last >> TARGET_PAGE_BITS;
1805 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
1807 int ret;
1809 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1810 if (!machine_dump_guest_core(current_machine)) {
1811 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
1812 if (ret) {
1813 perror("qemu_madvise");
1814 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
1815 "but dump_guest_core=off specified\n");
1820 const char *qemu_ram_get_idstr(RAMBlock *rb)
1822 return rb->idstr;
1825 bool qemu_ram_is_shared(RAMBlock *rb)
1827 return rb->flags & RAM_SHARED;
1830 /* Note: Only set at the start of postcopy */
1831 bool qemu_ram_is_uf_zeroable(RAMBlock *rb)
1833 return rb->flags & RAM_UF_ZEROPAGE;
1836 void qemu_ram_set_uf_zeroable(RAMBlock *rb)
1838 rb->flags |= RAM_UF_ZEROPAGE;
1841 /* Called with iothread lock held. */
1842 void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev)
1844 RAMBlock *block;
1846 assert(new_block);
1847 assert(!new_block->idstr[0]);
1849 if (dev) {
1850 char *id = qdev_get_dev_path(dev);
1851 if (id) {
1852 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
1853 g_free(id);
1856 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
1858 rcu_read_lock();
1859 RAMBLOCK_FOREACH(block) {
1860 if (block != new_block &&
1861 !strcmp(block->idstr, new_block->idstr)) {
1862 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
1863 new_block->idstr);
1864 abort();
1867 rcu_read_unlock();
1870 /* Called with iothread lock held. */
1871 void qemu_ram_unset_idstr(RAMBlock *block)
1873 /* FIXME: arch_init.c assumes that this is not called throughout
1874 * migration. Ignore the problem since hot-unplug during migration
1875 * does not work anyway.
1877 if (block) {
1878 memset(block->idstr, 0, sizeof(block->idstr));
1882 size_t qemu_ram_pagesize(RAMBlock *rb)
1884 return rb->page_size;
1887 /* Returns the largest size of page in use */
1888 size_t qemu_ram_pagesize_largest(void)
1890 RAMBlock *block;
1891 size_t largest = 0;
1893 RAMBLOCK_FOREACH(block) {
1894 largest = MAX(largest, qemu_ram_pagesize(block));
1897 return largest;
1900 static int memory_try_enable_merging(void *addr, size_t len)
1902 if (!machine_mem_merge(current_machine)) {
1903 /* disabled by the user */
1904 return 0;
1907 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
1910 /* Only legal before guest might have detected the memory size: e.g. on
1911 * incoming migration, or right after reset.
1913 * As memory core doesn't know how is memory accessed, it is up to
1914 * resize callback to update device state and/or add assertions to detect
1915 * misuse, if necessary.
1917 int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp)
1919 assert(block);
1921 newsize = HOST_PAGE_ALIGN(newsize);
1923 if (block->used_length == newsize) {
1924 return 0;
1927 if (!(block->flags & RAM_RESIZEABLE)) {
1928 error_setg_errno(errp, EINVAL,
1929 "Length mismatch: %s: 0x" RAM_ADDR_FMT
1930 " in != 0x" RAM_ADDR_FMT, block->idstr,
1931 newsize, block->used_length);
1932 return -EINVAL;
1935 if (block->max_length < newsize) {
1936 error_setg_errno(errp, EINVAL,
1937 "Length too large: %s: 0x" RAM_ADDR_FMT
1938 " > 0x" RAM_ADDR_FMT, block->idstr,
1939 newsize, block->max_length);
1940 return -EINVAL;
1943 cpu_physical_memory_clear_dirty_range(block->offset, block->used_length);
1944 block->used_length = newsize;
1945 cpu_physical_memory_set_dirty_range(block->offset, block->used_length,
1946 DIRTY_CLIENTS_ALL);
1947 memory_region_set_size(block->mr, newsize);
1948 if (block->resized) {
1949 block->resized(block->idstr, newsize, block->host);
1951 return 0;
1954 /* Called with ram_list.mutex held */
1955 static void dirty_memory_extend(ram_addr_t old_ram_size,
1956 ram_addr_t new_ram_size)
1958 ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size,
1959 DIRTY_MEMORY_BLOCK_SIZE);
1960 ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size,
1961 DIRTY_MEMORY_BLOCK_SIZE);
1962 int i;
1964 /* Only need to extend if block count increased */
1965 if (new_num_blocks <= old_num_blocks) {
1966 return;
1969 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
1970 DirtyMemoryBlocks *old_blocks;
1971 DirtyMemoryBlocks *new_blocks;
1972 int j;
1974 old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]);
1975 new_blocks = g_malloc(sizeof(*new_blocks) +
1976 sizeof(new_blocks->blocks[0]) * new_num_blocks);
1978 if (old_num_blocks) {
1979 memcpy(new_blocks->blocks, old_blocks->blocks,
1980 old_num_blocks * sizeof(old_blocks->blocks[0]));
1983 for (j = old_num_blocks; j < new_num_blocks; j++) {
1984 new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE);
1987 atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks);
1989 if (old_blocks) {
1990 g_free_rcu(old_blocks, rcu);
1995 static void ram_block_add(RAMBlock *new_block, Error **errp, bool shared)
1997 RAMBlock *block;
1998 RAMBlock *last_block = NULL;
1999 ram_addr_t old_ram_size, new_ram_size;
2000 Error *err = NULL;
2002 old_ram_size = last_ram_page();
2004 qemu_mutex_lock_ramlist();
2005 new_block->offset = find_ram_offset(new_block->max_length);
2007 if (!new_block->host) {
2008 if (xen_enabled()) {
2009 xen_ram_alloc(new_block->offset, new_block->max_length,
2010 new_block->mr, &err);
2011 if (err) {
2012 error_propagate(errp, err);
2013 qemu_mutex_unlock_ramlist();
2014 return;
2016 } else {
2017 new_block->host = phys_mem_alloc(new_block->max_length,
2018 &new_block->mr->align, shared);
2019 if (!new_block->host) {
2020 error_setg_errno(errp, errno,
2021 "cannot set up guest memory '%s'",
2022 memory_region_name(new_block->mr));
2023 qemu_mutex_unlock_ramlist();
2024 return;
2026 memory_try_enable_merging(new_block->host, new_block->max_length);
2030 new_ram_size = MAX(old_ram_size,
2031 (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS);
2032 if (new_ram_size > old_ram_size) {
2033 dirty_memory_extend(old_ram_size, new_ram_size);
2035 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2036 * QLIST (which has an RCU-friendly variant) does not have insertion at
2037 * tail, so save the last element in last_block.
2039 RAMBLOCK_FOREACH(block) {
2040 last_block = block;
2041 if (block->max_length < new_block->max_length) {
2042 break;
2045 if (block) {
2046 QLIST_INSERT_BEFORE_RCU(block, new_block, next);
2047 } else if (last_block) {
2048 QLIST_INSERT_AFTER_RCU(last_block, new_block, next);
2049 } else { /* list is empty */
2050 QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
2052 ram_list.mru_block = NULL;
2054 /* Write list before version */
2055 smp_wmb();
2056 ram_list.version++;
2057 qemu_mutex_unlock_ramlist();
2059 cpu_physical_memory_set_dirty_range(new_block->offset,
2060 new_block->used_length,
2061 DIRTY_CLIENTS_ALL);
2063 if (new_block->host) {
2064 qemu_ram_setup_dump(new_block->host, new_block->max_length);
2065 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
2066 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
2067 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK);
2068 ram_block_notify_add(new_block->host, new_block->max_length);
2072 #ifdef __linux__
2073 RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr,
2074 bool share, int fd,
2075 Error **errp)
2077 RAMBlock *new_block;
2078 Error *local_err = NULL;
2079 int64_t file_size;
2081 if (xen_enabled()) {
2082 error_setg(errp, "-mem-path not supported with Xen");
2083 return NULL;
2086 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2087 error_setg(errp,
2088 "host lacks kvm mmu notifiers, -mem-path unsupported");
2089 return NULL;
2092 if (phys_mem_alloc != qemu_anon_ram_alloc) {
2094 * file_ram_alloc() needs to allocate just like
2095 * phys_mem_alloc, but we haven't bothered to provide
2096 * a hook there.
2098 error_setg(errp,
2099 "-mem-path not supported with this accelerator");
2100 return NULL;
2103 size = HOST_PAGE_ALIGN(size);
2104 file_size = get_file_size(fd);
2105 if (file_size > 0 && file_size < size) {
2106 error_setg(errp, "backing store %s size 0x%" PRIx64
2107 " does not match 'size' option 0x" RAM_ADDR_FMT,
2108 mem_path, file_size, size);
2109 return NULL;
2112 new_block = g_malloc0(sizeof(*new_block));
2113 new_block->mr = mr;
2114 new_block->used_length = size;
2115 new_block->max_length = size;
2116 new_block->flags = share ? RAM_SHARED : 0;
2117 new_block->host = file_ram_alloc(new_block, size, fd, !file_size, errp);
2118 if (!new_block->host) {
2119 g_free(new_block);
2120 return NULL;
2123 ram_block_add(new_block, &local_err, share);
2124 if (local_err) {
2125 g_free(new_block);
2126 error_propagate(errp, local_err);
2127 return NULL;
2129 return new_block;
2134 RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
2135 bool share, const char *mem_path,
2136 Error **errp)
2138 int fd;
2139 bool created;
2140 RAMBlock *block;
2142 fd = file_ram_open(mem_path, memory_region_name(mr), &created, errp);
2143 if (fd < 0) {
2144 return NULL;
2147 block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
2148 if (!block) {
2149 if (created) {
2150 unlink(mem_path);
2152 close(fd);
2153 return NULL;
2156 return block;
2158 #endif
2160 static
2161 RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
2162 void (*resized)(const char*,
2163 uint64_t length,
2164 void *host),
2165 void *host, bool resizeable, bool share,
2166 MemoryRegion *mr, Error **errp)
2168 RAMBlock *new_block;
2169 Error *local_err = NULL;
2171 size = HOST_PAGE_ALIGN(size);
2172 max_size = HOST_PAGE_ALIGN(max_size);
2173 new_block = g_malloc0(sizeof(*new_block));
2174 new_block->mr = mr;
2175 new_block->resized = resized;
2176 new_block->used_length = size;
2177 new_block->max_length = max_size;
2178 assert(max_size >= size);
2179 new_block->fd = -1;
2180 new_block->page_size = getpagesize();
2181 new_block->host = host;
2182 if (host) {
2183 new_block->flags |= RAM_PREALLOC;
2185 if (resizeable) {
2186 new_block->flags |= RAM_RESIZEABLE;
2188 ram_block_add(new_block, &local_err, share);
2189 if (local_err) {
2190 g_free(new_block);
2191 error_propagate(errp, local_err);
2192 return NULL;
2194 return new_block;
2197 RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
2198 MemoryRegion *mr, Error **errp)
2200 return qemu_ram_alloc_internal(size, size, NULL, host, false,
2201 false, mr, errp);
2204 RAMBlock *qemu_ram_alloc(ram_addr_t size, bool share,
2205 MemoryRegion *mr, Error **errp)
2207 return qemu_ram_alloc_internal(size, size, NULL, NULL, false,
2208 share, mr, errp);
2211 RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz,
2212 void (*resized)(const char*,
2213 uint64_t length,
2214 void *host),
2215 MemoryRegion *mr, Error **errp)
2217 return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true,
2218 false, mr, errp);
2221 static void reclaim_ramblock(RAMBlock *block)
2223 if (block->flags & RAM_PREALLOC) {
2225 } else if (xen_enabled()) {
2226 xen_invalidate_map_cache_entry(block->host);
2227 #ifndef _WIN32
2228 } else if (block->fd >= 0) {
2229 qemu_ram_munmap(block->host, block->max_length);
2230 close(block->fd);
2231 #endif
2232 } else {
2233 qemu_anon_ram_free(block->host, block->max_length);
2235 g_free(block);
2238 void qemu_ram_free(RAMBlock *block)
2240 if (!block) {
2241 return;
2244 if (block->host) {
2245 ram_block_notify_remove(block->host, block->max_length);
2248 qemu_mutex_lock_ramlist();
2249 QLIST_REMOVE_RCU(block, next);
2250 ram_list.mru_block = NULL;
2251 /* Write list before version */
2252 smp_wmb();
2253 ram_list.version++;
2254 call_rcu(block, reclaim_ramblock, rcu);
2255 qemu_mutex_unlock_ramlist();
2258 #ifndef _WIN32
2259 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
2261 RAMBlock *block;
2262 ram_addr_t offset;
2263 int flags;
2264 void *area, *vaddr;
2266 RAMBLOCK_FOREACH(block) {
2267 offset = addr - block->offset;
2268 if (offset < block->max_length) {
2269 vaddr = ramblock_ptr(block, offset);
2270 if (block->flags & RAM_PREALLOC) {
2272 } else if (xen_enabled()) {
2273 abort();
2274 } else {
2275 flags = MAP_FIXED;
2276 if (block->fd >= 0) {
2277 flags |= (block->flags & RAM_SHARED ?
2278 MAP_SHARED : MAP_PRIVATE);
2279 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2280 flags, block->fd, offset);
2281 } else {
2283 * Remap needs to match alloc. Accelerators that
2284 * set phys_mem_alloc never remap. If they did,
2285 * we'd need a remap hook here.
2287 assert(phys_mem_alloc == qemu_anon_ram_alloc);
2289 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
2290 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2291 flags, -1, 0);
2293 if (area != vaddr) {
2294 error_report("Could not remap addr: "
2295 RAM_ADDR_FMT "@" RAM_ADDR_FMT "",
2296 length, addr);
2297 exit(1);
2299 memory_try_enable_merging(vaddr, length);
2300 qemu_ram_setup_dump(vaddr, length);
2305 #endif /* !_WIN32 */
2307 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2308 * This should not be used for general purpose DMA. Use address_space_map
2309 * or address_space_rw instead. For local memory (e.g. video ram) that the
2310 * device owns, use memory_region_get_ram_ptr.
2312 * Called within RCU critical section.
2314 void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
2316 RAMBlock *block = ram_block;
2318 if (block == NULL) {
2319 block = qemu_get_ram_block(addr);
2320 addr -= block->offset;
2323 if (xen_enabled() && block->host == NULL) {
2324 /* We need to check if the requested address is in the RAM
2325 * because we don't want to map the entire memory in QEMU.
2326 * In that case just map until the end of the page.
2328 if (block->offset == 0) {
2329 return xen_map_cache(addr, 0, 0, false);
2332 block->host = xen_map_cache(block->offset, block->max_length, 1, false);
2334 return ramblock_ptr(block, addr);
2337 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2338 * but takes a size argument.
2340 * Called within RCU critical section.
2342 static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
2343 hwaddr *size, bool lock)
2345 RAMBlock *block = ram_block;
2346 if (*size == 0) {
2347 return NULL;
2350 if (block == NULL) {
2351 block = qemu_get_ram_block(addr);
2352 addr -= block->offset;
2354 *size = MIN(*size, block->max_length - addr);
2356 if (xen_enabled() && block->host == NULL) {
2357 /* We need to check if the requested address is in the RAM
2358 * because we don't want to map the entire memory in QEMU.
2359 * In that case just map the requested area.
2361 if (block->offset == 0) {
2362 return xen_map_cache(addr, *size, lock, lock);
2365 block->host = xen_map_cache(block->offset, block->max_length, 1, lock);
2368 return ramblock_ptr(block, addr);
2371 /* Return the offset of a hostpointer within a ramblock */
2372 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host)
2374 ram_addr_t res = (uint8_t *)host - (uint8_t *)rb->host;
2375 assert((uintptr_t)host >= (uintptr_t)rb->host);
2376 assert(res < rb->max_length);
2378 return res;
2382 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2383 * in that RAMBlock.
2385 * ptr: Host pointer to look up
2386 * round_offset: If true round the result offset down to a page boundary
2387 * *ram_addr: set to result ram_addr
2388 * *offset: set to result offset within the RAMBlock
2390 * Returns: RAMBlock (or NULL if not found)
2392 * By the time this function returns, the returned pointer is not protected
2393 * by RCU anymore. If the caller is not within an RCU critical section and
2394 * does not hold the iothread lock, it must have other means of protecting the
2395 * pointer, such as a reference to the region that includes the incoming
2396 * ram_addr_t.
2398 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
2399 ram_addr_t *offset)
2401 RAMBlock *block;
2402 uint8_t *host = ptr;
2404 if (xen_enabled()) {
2405 ram_addr_t ram_addr;
2406 rcu_read_lock();
2407 ram_addr = xen_ram_addr_from_mapcache(ptr);
2408 block = qemu_get_ram_block(ram_addr);
2409 if (block) {
2410 *offset = ram_addr - block->offset;
2412 rcu_read_unlock();
2413 return block;
2416 rcu_read_lock();
2417 block = atomic_rcu_read(&ram_list.mru_block);
2418 if (block && block->host && host - block->host < block->max_length) {
2419 goto found;
2422 RAMBLOCK_FOREACH(block) {
2423 /* This case append when the block is not mapped. */
2424 if (block->host == NULL) {
2425 continue;
2427 if (host - block->host < block->max_length) {
2428 goto found;
2432 rcu_read_unlock();
2433 return NULL;
2435 found:
2436 *offset = (host - block->host);
2437 if (round_offset) {
2438 *offset &= TARGET_PAGE_MASK;
2440 rcu_read_unlock();
2441 return block;
2445 * Finds the named RAMBlock
2447 * name: The name of RAMBlock to find
2449 * Returns: RAMBlock (or NULL if not found)
2451 RAMBlock *qemu_ram_block_by_name(const char *name)
2453 RAMBlock *block;
2455 RAMBLOCK_FOREACH(block) {
2456 if (!strcmp(name, block->idstr)) {
2457 return block;
2461 return NULL;
2464 /* Some of the softmmu routines need to translate from a host pointer
2465 (typically a TLB entry) back to a ram offset. */
2466 ram_addr_t qemu_ram_addr_from_host(void *ptr)
2468 RAMBlock *block;
2469 ram_addr_t offset;
2471 block = qemu_ram_block_from_host(ptr, false, &offset);
2472 if (!block) {
2473 return RAM_ADDR_INVALID;
2476 return block->offset + offset;
2479 /* Called within RCU critical section. */
2480 void memory_notdirty_write_prepare(NotDirtyInfo *ndi,
2481 CPUState *cpu,
2482 vaddr mem_vaddr,
2483 ram_addr_t ram_addr,
2484 unsigned size)
2486 ndi->cpu = cpu;
2487 ndi->ram_addr = ram_addr;
2488 ndi->mem_vaddr = mem_vaddr;
2489 ndi->size = size;
2490 ndi->locked = false;
2492 assert(tcg_enabled());
2493 if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) {
2494 ndi->locked = true;
2495 tb_lock();
2496 tb_invalidate_phys_page_fast(ram_addr, size);
2500 /* Called within RCU critical section. */
2501 void memory_notdirty_write_complete(NotDirtyInfo *ndi)
2503 if (ndi->locked) {
2504 tb_unlock();
2507 /* Set both VGA and migration bits for simplicity and to remove
2508 * the notdirty callback faster.
2510 cpu_physical_memory_set_dirty_range(ndi->ram_addr, ndi->size,
2511 DIRTY_CLIENTS_NOCODE);
2512 /* we remove the notdirty callback only if the code has been
2513 flushed */
2514 if (!cpu_physical_memory_is_clean(ndi->ram_addr)) {
2515 tlb_set_dirty(ndi->cpu, ndi->mem_vaddr);
2519 /* Called within RCU critical section. */
2520 static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
2521 uint64_t val, unsigned size)
2523 NotDirtyInfo ndi;
2525 memory_notdirty_write_prepare(&ndi, current_cpu, current_cpu->mem_io_vaddr,
2526 ram_addr, size);
2528 switch (size) {
2529 case 1:
2530 stb_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2531 break;
2532 case 2:
2533 stw_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2534 break;
2535 case 4:
2536 stl_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2537 break;
2538 case 8:
2539 stq_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2540 break;
2541 default:
2542 abort();
2544 memory_notdirty_write_complete(&ndi);
2547 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
2548 unsigned size, bool is_write,
2549 MemTxAttrs attrs)
2551 return is_write;
2554 static const MemoryRegionOps notdirty_mem_ops = {
2555 .write = notdirty_mem_write,
2556 .valid.accepts = notdirty_mem_accepts,
2557 .endianness = DEVICE_NATIVE_ENDIAN,
2558 .valid = {
2559 .min_access_size = 1,
2560 .max_access_size = 8,
2561 .unaligned = false,
2563 .impl = {
2564 .min_access_size = 1,
2565 .max_access_size = 8,
2566 .unaligned = false,
2570 /* Generate a debug exception if a watchpoint has been hit. */
2571 static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
2573 CPUState *cpu = current_cpu;
2574 CPUClass *cc = CPU_GET_CLASS(cpu);
2575 target_ulong vaddr;
2576 CPUWatchpoint *wp;
2578 assert(tcg_enabled());
2579 if (cpu->watchpoint_hit) {
2580 /* We re-entered the check after replacing the TB. Now raise
2581 * the debug interrupt so that is will trigger after the
2582 * current instruction. */
2583 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
2584 return;
2586 vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
2587 vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
2588 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
2589 if (cpu_watchpoint_address_matches(wp, vaddr, len)
2590 && (wp->flags & flags)) {
2591 if (flags == BP_MEM_READ) {
2592 wp->flags |= BP_WATCHPOINT_HIT_READ;
2593 } else {
2594 wp->flags |= BP_WATCHPOINT_HIT_WRITE;
2596 wp->hitaddr = vaddr;
2597 wp->hitattrs = attrs;
2598 if (!cpu->watchpoint_hit) {
2599 if (wp->flags & BP_CPU &&
2600 !cc->debug_check_watchpoint(cpu, wp)) {
2601 wp->flags &= ~BP_WATCHPOINT_HIT;
2602 continue;
2604 cpu->watchpoint_hit = wp;
2606 /* Both tb_lock and iothread_mutex will be reset when
2607 * cpu_loop_exit or cpu_loop_exit_noexc longjmp
2608 * back into the cpu_exec main loop.
2610 tb_lock();
2611 tb_check_watchpoint(cpu);
2612 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2613 cpu->exception_index = EXCP_DEBUG;
2614 cpu_loop_exit(cpu);
2615 } else {
2616 /* Force execution of one insn next time. */
2617 cpu->cflags_next_tb = 1 | curr_cflags();
2618 cpu_loop_exit_noexc(cpu);
2621 } else {
2622 wp->flags &= ~BP_WATCHPOINT_HIT;
2627 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2628 so these check for a hit then pass through to the normal out-of-line
2629 phys routines. */
2630 static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata,
2631 unsigned size, MemTxAttrs attrs)
2633 MemTxResult res;
2634 uint64_t data;
2635 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2636 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2638 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ);
2639 switch (size) {
2640 case 1:
2641 data = address_space_ldub(as, addr, attrs, &res);
2642 break;
2643 case 2:
2644 data = address_space_lduw(as, addr, attrs, &res);
2645 break;
2646 case 4:
2647 data = address_space_ldl(as, addr, attrs, &res);
2648 break;
2649 case 8:
2650 data = address_space_ldq(as, addr, attrs, &res);
2651 break;
2652 default: abort();
2654 *pdata = data;
2655 return res;
2658 static MemTxResult watch_mem_write(void *opaque, hwaddr addr,
2659 uint64_t val, unsigned size,
2660 MemTxAttrs attrs)
2662 MemTxResult res;
2663 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2664 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2666 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE);
2667 switch (size) {
2668 case 1:
2669 address_space_stb(as, addr, val, attrs, &res);
2670 break;
2671 case 2:
2672 address_space_stw(as, addr, val, attrs, &res);
2673 break;
2674 case 4:
2675 address_space_stl(as, addr, val, attrs, &res);
2676 break;
2677 case 8:
2678 address_space_stq(as, addr, val, attrs, &res);
2679 break;
2680 default: abort();
2682 return res;
2685 static const MemoryRegionOps watch_mem_ops = {
2686 .read_with_attrs = watch_mem_read,
2687 .write_with_attrs = watch_mem_write,
2688 .endianness = DEVICE_NATIVE_ENDIAN,
2689 .valid = {
2690 .min_access_size = 1,
2691 .max_access_size = 8,
2692 .unaligned = false,
2694 .impl = {
2695 .min_access_size = 1,
2696 .max_access_size = 8,
2697 .unaligned = false,
2701 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
2702 MemTxAttrs attrs, uint8_t *buf, int len);
2703 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
2704 const uint8_t *buf, int len);
2705 static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
2706 bool is_write, MemTxAttrs attrs);
2708 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
2709 unsigned len, MemTxAttrs attrs)
2711 subpage_t *subpage = opaque;
2712 uint8_t buf[8];
2713 MemTxResult res;
2715 #if defined(DEBUG_SUBPAGE)
2716 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
2717 subpage, len, addr);
2718 #endif
2719 res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len);
2720 if (res) {
2721 return res;
2723 switch (len) {
2724 case 1:
2725 *data = ldub_p(buf);
2726 return MEMTX_OK;
2727 case 2:
2728 *data = lduw_p(buf);
2729 return MEMTX_OK;
2730 case 4:
2731 *data = ldl_p(buf);
2732 return MEMTX_OK;
2733 case 8:
2734 *data = ldq_p(buf);
2735 return MEMTX_OK;
2736 default:
2737 abort();
2741 static MemTxResult subpage_write(void *opaque, hwaddr addr,
2742 uint64_t value, unsigned len, MemTxAttrs attrs)
2744 subpage_t *subpage = opaque;
2745 uint8_t buf[8];
2747 #if defined(DEBUG_SUBPAGE)
2748 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2749 " value %"PRIx64"\n",
2750 __func__, subpage, len, addr, value);
2751 #endif
2752 switch (len) {
2753 case 1:
2754 stb_p(buf, value);
2755 break;
2756 case 2:
2757 stw_p(buf, value);
2758 break;
2759 case 4:
2760 stl_p(buf, value);
2761 break;
2762 case 8:
2763 stq_p(buf, value);
2764 break;
2765 default:
2766 abort();
2768 return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len);
2771 static bool subpage_accepts(void *opaque, hwaddr addr,
2772 unsigned len, bool is_write,
2773 MemTxAttrs attrs)
2775 subpage_t *subpage = opaque;
2776 #if defined(DEBUG_SUBPAGE)
2777 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
2778 __func__, subpage, is_write ? 'w' : 'r', len, addr);
2779 #endif
2781 return flatview_access_valid(subpage->fv, addr + subpage->base,
2782 len, is_write, attrs);
2785 static const MemoryRegionOps subpage_ops = {
2786 .read_with_attrs = subpage_read,
2787 .write_with_attrs = subpage_write,
2788 .impl.min_access_size = 1,
2789 .impl.max_access_size = 8,
2790 .valid.min_access_size = 1,
2791 .valid.max_access_size = 8,
2792 .valid.accepts = subpage_accepts,
2793 .endianness = DEVICE_NATIVE_ENDIAN,
2796 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
2797 uint16_t section)
2799 int idx, eidx;
2801 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2802 return -1;
2803 idx = SUBPAGE_IDX(start);
2804 eidx = SUBPAGE_IDX(end);
2805 #if defined(DEBUG_SUBPAGE)
2806 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2807 __func__, mmio, start, end, idx, eidx, section);
2808 #endif
2809 for (; idx <= eidx; idx++) {
2810 mmio->sub_section[idx] = section;
2813 return 0;
2816 static subpage_t *subpage_init(FlatView *fv, hwaddr base)
2818 subpage_t *mmio;
2820 mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));
2821 mmio->fv = fv;
2822 mmio->base = base;
2823 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
2824 NULL, TARGET_PAGE_SIZE);
2825 mmio->iomem.subpage = true;
2826 #if defined(DEBUG_SUBPAGE)
2827 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
2828 mmio, base, TARGET_PAGE_SIZE);
2829 #endif
2830 subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED);
2832 return mmio;
2835 static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr)
2837 assert(fv);
2838 MemoryRegionSection section = {
2839 .fv = fv,
2840 .mr = mr,
2841 .offset_within_address_space = 0,
2842 .offset_within_region = 0,
2843 .size = int128_2_64(),
2846 return phys_section_add(map, &section);
2849 static void readonly_mem_write(void *opaque, hwaddr addr,
2850 uint64_t val, unsigned size)
2852 /* Ignore any write to ROM. */
2855 static bool readonly_mem_accepts(void *opaque, hwaddr addr,
2856 unsigned size, bool is_write,
2857 MemTxAttrs attrs)
2859 return is_write;
2862 /* This will only be used for writes, because reads are special cased
2863 * to directly access the underlying host ram.
2865 static const MemoryRegionOps readonly_mem_ops = {
2866 .write = readonly_mem_write,
2867 .valid.accepts = readonly_mem_accepts,
2868 .endianness = DEVICE_NATIVE_ENDIAN,
2869 .valid = {
2870 .min_access_size = 1,
2871 .max_access_size = 8,
2872 .unaligned = false,
2874 .impl = {
2875 .min_access_size = 1,
2876 .max_access_size = 8,
2877 .unaligned = false,
2881 MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs)
2883 int asidx = cpu_asidx_from_attrs(cpu, attrs);
2884 CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
2885 AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch);
2886 MemoryRegionSection *sections = d->map.sections;
2888 return sections[index & ~TARGET_PAGE_MASK].mr;
2891 static void io_mem_init(void)
2893 memory_region_init_io(&io_mem_rom, NULL, &readonly_mem_ops,
2894 NULL, NULL, UINT64_MAX);
2895 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
2896 NULL, UINT64_MAX);
2898 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
2899 * which can be called without the iothread mutex.
2901 memory_region_init_io(&io_mem_notdirty, NULL, &notdirty_mem_ops, NULL,
2902 NULL, UINT64_MAX);
2903 memory_region_clear_global_locking(&io_mem_notdirty);
2905 memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL,
2906 NULL, UINT64_MAX);
2909 AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv)
2911 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
2912 uint16_t n;
2914 n = dummy_section(&d->map, fv, &io_mem_unassigned);
2915 assert(n == PHYS_SECTION_UNASSIGNED);
2916 n = dummy_section(&d->map, fv, &io_mem_notdirty);
2917 assert(n == PHYS_SECTION_NOTDIRTY);
2918 n = dummy_section(&d->map, fv, &io_mem_rom);
2919 assert(n == PHYS_SECTION_ROM);
2920 n = dummy_section(&d->map, fv, &io_mem_watch);
2921 assert(n == PHYS_SECTION_WATCH);
2923 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
2925 return d;
2928 void address_space_dispatch_free(AddressSpaceDispatch *d)
2930 phys_sections_free(&d->map);
2931 g_free(d);
2934 static void tcg_commit(MemoryListener *listener)
2936 CPUAddressSpace *cpuas;
2937 AddressSpaceDispatch *d;
2939 /* since each CPU stores ram addresses in its TLB cache, we must
2940 reset the modified entries */
2941 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
2942 cpu_reloading_memory_map();
2943 /* The CPU and TLB are protected by the iothread lock.
2944 * We reload the dispatch pointer now because cpu_reloading_memory_map()
2945 * may have split the RCU critical section.
2947 d = address_space_to_dispatch(cpuas->as);
2948 atomic_rcu_set(&cpuas->memory_dispatch, d);
2949 tlb_flush(cpuas->cpu);
2952 static void memory_map_init(void)
2954 system_memory = g_malloc(sizeof(*system_memory));
2956 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
2957 address_space_init(&address_space_memory, system_memory, "memory");
2959 system_io = g_malloc(sizeof(*system_io));
2960 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
2961 65536);
2962 address_space_init(&address_space_io, system_io, "I/O");
2965 MemoryRegion *get_system_memory(void)
2967 return system_memory;
2970 MemoryRegion *get_system_io(void)
2972 return system_io;
2975 #endif /* !defined(CONFIG_USER_ONLY) */
2977 /* physical memory access (slow version, mainly for debug) */
2978 #if defined(CONFIG_USER_ONLY)
2979 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
2980 uint8_t *buf, int len, int is_write)
2982 int l, flags;
2983 target_ulong page;
2984 void * p;
2986 while (len > 0) {
2987 page = addr & TARGET_PAGE_MASK;
2988 l = (page + TARGET_PAGE_SIZE) - addr;
2989 if (l > len)
2990 l = len;
2991 flags = page_get_flags(page);
2992 if (!(flags & PAGE_VALID))
2993 return -1;
2994 if (is_write) {
2995 if (!(flags & PAGE_WRITE))
2996 return -1;
2997 /* XXX: this code should not depend on lock_user */
2998 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
2999 return -1;
3000 memcpy(p, buf, l);
3001 unlock_user(p, addr, l);
3002 } else {
3003 if (!(flags & PAGE_READ))
3004 return -1;
3005 /* XXX: this code should not depend on lock_user */
3006 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
3007 return -1;
3008 memcpy(buf, p, l);
3009 unlock_user(p, addr, 0);
3011 len -= l;
3012 buf += l;
3013 addr += l;
3015 return 0;
3018 #else
3020 static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
3021 hwaddr length)
3023 uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
3024 addr += memory_region_get_ram_addr(mr);
3026 /* No early return if dirty_log_mask is or becomes 0, because
3027 * cpu_physical_memory_set_dirty_range will still call
3028 * xen_modified_memory.
3030 if (dirty_log_mask) {
3031 dirty_log_mask =
3032 cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask);
3034 if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) {
3035 assert(tcg_enabled());
3036 tb_lock();
3037 tb_invalidate_phys_range(addr, addr + length);
3038 tb_unlock();
3039 dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
3041 cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);
3044 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
3046 unsigned access_size_max = mr->ops->valid.max_access_size;
3048 /* Regions are assumed to support 1-4 byte accesses unless
3049 otherwise specified. */
3050 if (access_size_max == 0) {
3051 access_size_max = 4;
3054 /* Bound the maximum access by the alignment of the address. */
3055 if (!mr->ops->impl.unaligned) {
3056 unsigned align_size_max = addr & -addr;
3057 if (align_size_max != 0 && align_size_max < access_size_max) {
3058 access_size_max = align_size_max;
3062 /* Don't attempt accesses larger than the maximum. */
3063 if (l > access_size_max) {
3064 l = access_size_max;
3066 l = pow2floor(l);
3068 return l;
3071 static bool prepare_mmio_access(MemoryRegion *mr)
3073 bool unlocked = !qemu_mutex_iothread_locked();
3074 bool release_lock = false;
3076 if (unlocked && mr->global_locking) {
3077 qemu_mutex_lock_iothread();
3078 unlocked = false;
3079 release_lock = true;
3081 if (mr->flush_coalesced_mmio) {
3082 if (unlocked) {
3083 qemu_mutex_lock_iothread();
3085 qemu_flush_coalesced_mmio_buffer();
3086 if (unlocked) {
3087 qemu_mutex_unlock_iothread();
3091 return release_lock;
3094 /* Called within RCU critical section. */
3095 static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
3096 MemTxAttrs attrs,
3097 const uint8_t *buf,
3098 int len, hwaddr addr1,
3099 hwaddr l, MemoryRegion *mr)
3101 uint8_t *ptr;
3102 uint64_t val;
3103 MemTxResult result = MEMTX_OK;
3104 bool release_lock = false;
3106 for (;;) {
3107 if (!memory_access_is_direct(mr, true)) {
3108 release_lock |= prepare_mmio_access(mr);
3109 l = memory_access_size(mr, l, addr1);
3110 /* XXX: could force current_cpu to NULL to avoid
3111 potential bugs */
3112 switch (l) {
3113 case 8:
3114 /* 64 bit write access */
3115 val = ldq_p(buf);
3116 result |= memory_region_dispatch_write(mr, addr1, val, 8,
3117 attrs);
3118 break;
3119 case 4:
3120 /* 32 bit write access */
3121 val = (uint32_t)ldl_p(buf);
3122 result |= memory_region_dispatch_write(mr, addr1, val, 4,
3123 attrs);
3124 break;
3125 case 2:
3126 /* 16 bit write access */
3127 val = lduw_p(buf);
3128 result |= memory_region_dispatch_write(mr, addr1, val, 2,
3129 attrs);
3130 break;
3131 case 1:
3132 /* 8 bit write access */
3133 val = ldub_p(buf);
3134 result |= memory_region_dispatch_write(mr, addr1, val, 1,
3135 attrs);
3136 break;
3137 default:
3138 abort();
3140 } else {
3141 /* RAM case */
3142 ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3143 memcpy(ptr, buf, l);
3144 invalidate_and_set_dirty(mr, addr1, l);
3147 if (release_lock) {
3148 qemu_mutex_unlock_iothread();
3149 release_lock = false;
3152 len -= l;
3153 buf += l;
3154 addr += l;
3156 if (!len) {
3157 break;
3160 l = len;
3161 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
3164 return result;
3167 /* Called from RCU critical section. */
3168 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
3169 const uint8_t *buf, int len)
3171 hwaddr l;
3172 hwaddr addr1;
3173 MemoryRegion *mr;
3174 MemTxResult result = MEMTX_OK;
3176 l = len;
3177 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
3178 result = flatview_write_continue(fv, addr, attrs, buf, len,
3179 addr1, l, mr);
3181 return result;
3184 /* Called within RCU critical section. */
3185 MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
3186 MemTxAttrs attrs, uint8_t *buf,
3187 int len, hwaddr addr1, hwaddr l,
3188 MemoryRegion *mr)
3190 uint8_t *ptr;
3191 uint64_t val;
3192 MemTxResult result = MEMTX_OK;
3193 bool release_lock = false;
3195 for (;;) {
3196 if (!memory_access_is_direct(mr, false)) {
3197 /* I/O case */
3198 release_lock |= prepare_mmio_access(mr);
3199 l = memory_access_size(mr, l, addr1);
3200 switch (l) {
3201 case 8:
3202 /* 64 bit read access */
3203 result |= memory_region_dispatch_read(mr, addr1, &val, 8,
3204 attrs);
3205 stq_p(buf, val);
3206 break;
3207 case 4:
3208 /* 32 bit read access */
3209 result |= memory_region_dispatch_read(mr, addr1, &val, 4,
3210 attrs);
3211 stl_p(buf, val);
3212 break;
3213 case 2:
3214 /* 16 bit read access */
3215 result |= memory_region_dispatch_read(mr, addr1, &val, 2,
3216 attrs);
3217 stw_p(buf, val);
3218 break;
3219 case 1:
3220 /* 8 bit read access */
3221 result |= memory_region_dispatch_read(mr, addr1, &val, 1,
3222 attrs);
3223 stb_p(buf, val);
3224 break;
3225 default:
3226 abort();
3228 } else {
3229 /* RAM case */
3230 ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3231 memcpy(buf, ptr, l);
3234 if (release_lock) {
3235 qemu_mutex_unlock_iothread();
3236 release_lock = false;
3239 len -= l;
3240 buf += l;
3241 addr += l;
3243 if (!len) {
3244 break;
3247 l = len;
3248 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
3251 return result;
3254 /* Called from RCU critical section. */
3255 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
3256 MemTxAttrs attrs, uint8_t *buf, int len)
3258 hwaddr l;
3259 hwaddr addr1;
3260 MemoryRegion *mr;
3262 l = len;
3263 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
3264 return flatview_read_continue(fv, addr, attrs, buf, len,
3265 addr1, l, mr);
3268 MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
3269 MemTxAttrs attrs, uint8_t *buf, int len)
3271 MemTxResult result = MEMTX_OK;
3272 FlatView *fv;
3274 if (len > 0) {
3275 rcu_read_lock();
3276 fv = address_space_to_flatview(as);
3277 result = flatview_read(fv, addr, attrs, buf, len);
3278 rcu_read_unlock();
3281 return result;
3284 MemTxResult address_space_write(AddressSpace *as, hwaddr addr,
3285 MemTxAttrs attrs,
3286 const uint8_t *buf, int len)
3288 MemTxResult result = MEMTX_OK;
3289 FlatView *fv;
3291 if (len > 0) {
3292 rcu_read_lock();
3293 fv = address_space_to_flatview(as);
3294 result = flatview_write(fv, addr, attrs, buf, len);
3295 rcu_read_unlock();
3298 return result;
3301 MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
3302 uint8_t *buf, int len, bool is_write)
3304 if (is_write) {
3305 return address_space_write(as, addr, attrs, buf, len);
3306 } else {
3307 return address_space_read_full(as, addr, attrs, buf, len);
3311 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
3312 int len, int is_write)
3314 address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
3315 buf, len, is_write);
3318 enum write_rom_type {
3319 WRITE_DATA,
3320 FLUSH_CACHE,
3323 static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
3324 hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type)
3326 hwaddr l;
3327 uint8_t *ptr;
3328 hwaddr addr1;
3329 MemoryRegion *mr;
3331 rcu_read_lock();
3332 while (len > 0) {
3333 l = len;
3334 mr = address_space_translate(as, addr, &addr1, &l, true,
3335 MEMTXATTRS_UNSPECIFIED);
3337 if (!(memory_region_is_ram(mr) ||
3338 memory_region_is_romd(mr))) {
3339 l = memory_access_size(mr, l, addr1);
3340 } else {
3341 /* ROM/RAM case */
3342 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
3343 switch (type) {
3344 case WRITE_DATA:
3345 memcpy(ptr, buf, l);
3346 invalidate_and_set_dirty(mr, addr1, l);
3347 break;
3348 case FLUSH_CACHE:
3349 flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
3350 break;
3353 len -= l;
3354 buf += l;
3355 addr += l;
3357 rcu_read_unlock();
3360 /* used for ROM loading : can write in RAM and ROM */
3361 void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
3362 const uint8_t *buf, int len)
3364 cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA);
3367 void cpu_flush_icache_range(hwaddr start, int len)
3370 * This function should do the same thing as an icache flush that was
3371 * triggered from within the guest. For TCG we are always cache coherent,
3372 * so there is no need to flush anything. For KVM / Xen we need to flush
3373 * the host's instruction cache at least.
3375 if (tcg_enabled()) {
3376 return;
3379 cpu_physical_memory_write_rom_internal(&address_space_memory,
3380 start, NULL, len, FLUSH_CACHE);
3383 typedef struct {
3384 MemoryRegion *mr;
3385 void *buffer;
3386 hwaddr addr;
3387 hwaddr len;
3388 bool in_use;
3389 } BounceBuffer;
3391 static BounceBuffer bounce;
3393 typedef struct MapClient {
3394 QEMUBH *bh;
3395 QLIST_ENTRY(MapClient) link;
3396 } MapClient;
3398 QemuMutex map_client_list_lock;
3399 static QLIST_HEAD(map_client_list, MapClient) map_client_list
3400 = QLIST_HEAD_INITIALIZER(map_client_list);
3402 static void cpu_unregister_map_client_do(MapClient *client)
3404 QLIST_REMOVE(client, link);
3405 g_free(client);
3408 static void cpu_notify_map_clients_locked(void)
3410 MapClient *client;
3412 while (!QLIST_EMPTY(&map_client_list)) {
3413 client = QLIST_FIRST(&map_client_list);
3414 qemu_bh_schedule(client->bh);
3415 cpu_unregister_map_client_do(client);
3419 void cpu_register_map_client(QEMUBH *bh)
3421 MapClient *client = g_malloc(sizeof(*client));
3423 qemu_mutex_lock(&map_client_list_lock);
3424 client->bh = bh;
3425 QLIST_INSERT_HEAD(&map_client_list, client, link);
3426 if (!atomic_read(&bounce.in_use)) {
3427 cpu_notify_map_clients_locked();
3429 qemu_mutex_unlock(&map_client_list_lock);
3432 void cpu_exec_init_all(void)
3434 qemu_mutex_init(&ram_list.mutex);
3435 /* The data structures we set up here depend on knowing the page size,
3436 * so no more changes can be made after this point.
3437 * In an ideal world, nothing we did before we had finished the
3438 * machine setup would care about the target page size, and we could
3439 * do this much later, rather than requiring board models to state
3440 * up front what their requirements are.
3442 finalize_target_page_bits();
3443 io_mem_init();
3444 memory_map_init();
3445 qemu_mutex_init(&map_client_list_lock);
3448 void cpu_unregister_map_client(QEMUBH *bh)
3450 MapClient *client;
3452 qemu_mutex_lock(&map_client_list_lock);
3453 QLIST_FOREACH(client, &map_client_list, link) {
3454 if (client->bh == bh) {
3455 cpu_unregister_map_client_do(client);
3456 break;
3459 qemu_mutex_unlock(&map_client_list_lock);
3462 static void cpu_notify_map_clients(void)
3464 qemu_mutex_lock(&map_client_list_lock);
3465 cpu_notify_map_clients_locked();
3466 qemu_mutex_unlock(&map_client_list_lock);
3469 static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
3470 bool is_write, MemTxAttrs attrs)
3472 MemoryRegion *mr;
3473 hwaddr l, xlat;
3475 while (len > 0) {
3476 l = len;
3477 mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
3478 if (!memory_access_is_direct(mr, is_write)) {
3479 l = memory_access_size(mr, l, addr);
3480 if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
3481 return false;
3485 len -= l;
3486 addr += l;
3488 return true;
3491 bool address_space_access_valid(AddressSpace *as, hwaddr addr,
3492 int len, bool is_write,
3493 MemTxAttrs attrs)
3495 FlatView *fv;
3496 bool result;
3498 rcu_read_lock();
3499 fv = address_space_to_flatview(as);
3500 result = flatview_access_valid(fv, addr, len, is_write, attrs);
3501 rcu_read_unlock();
3502 return result;
3505 static hwaddr
3506 flatview_extend_translation(FlatView *fv, hwaddr addr,
3507 hwaddr target_len,
3508 MemoryRegion *mr, hwaddr base, hwaddr len,
3509 bool is_write, MemTxAttrs attrs)
3511 hwaddr done = 0;
3512 hwaddr xlat;
3513 MemoryRegion *this_mr;
3515 for (;;) {
3516 target_len -= len;
3517 addr += len;
3518 done += len;
3519 if (target_len == 0) {
3520 return done;
3523 len = target_len;
3524 this_mr = flatview_translate(fv, addr, &xlat,
3525 &len, is_write, attrs);
3526 if (this_mr != mr || xlat != base + done) {
3527 return done;
3532 /* Map a physical memory region into a host virtual address.
3533 * May map a subset of the requested range, given by and returned in *plen.
3534 * May return NULL if resources needed to perform the mapping are exhausted.
3535 * Use only for reads OR writes - not for read-modify-write operations.
3536 * Use cpu_register_map_client() to know when retrying the map operation is
3537 * likely to succeed.
3539 void *address_space_map(AddressSpace *as,
3540 hwaddr addr,
3541 hwaddr *plen,
3542 bool is_write,
3543 MemTxAttrs attrs)
3545 hwaddr len = *plen;
3546 hwaddr l, xlat;
3547 MemoryRegion *mr;
3548 void *ptr;
3549 FlatView *fv;
3551 if (len == 0) {
3552 return NULL;
3555 l = len;
3556 rcu_read_lock();
3557 fv = address_space_to_flatview(as);
3558 mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
3560 if (!memory_access_is_direct(mr, is_write)) {
3561 if (atomic_xchg(&bounce.in_use, true)) {
3562 rcu_read_unlock();
3563 return NULL;
3565 /* Avoid unbounded allocations */
3566 l = MIN(l, TARGET_PAGE_SIZE);
3567 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l);
3568 bounce.addr = addr;
3569 bounce.len = l;
3571 memory_region_ref(mr);
3572 bounce.mr = mr;
3573 if (!is_write) {
3574 flatview_read(fv, addr, MEMTXATTRS_UNSPECIFIED,
3575 bounce.buffer, l);
3578 rcu_read_unlock();
3579 *plen = l;
3580 return bounce.buffer;
3584 memory_region_ref(mr);
3585 *plen = flatview_extend_translation(fv, addr, len, mr, xlat,
3586 l, is_write, attrs);
3587 ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
3588 rcu_read_unlock();
3590 return ptr;
3593 /* Unmaps a memory region previously mapped by address_space_map().
3594 * Will also mark the memory as dirty if is_write == 1. access_len gives
3595 * the amount of memory that was actually read or written by the caller.
3597 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
3598 int is_write, hwaddr access_len)
3600 if (buffer != bounce.buffer) {
3601 MemoryRegion *mr;
3602 ram_addr_t addr1;
3604 mr = memory_region_from_host(buffer, &addr1);
3605 assert(mr != NULL);
3606 if (is_write) {
3607 invalidate_and_set_dirty(mr, addr1, access_len);
3609 if (xen_enabled()) {
3610 xen_invalidate_map_cache_entry(buffer);
3612 memory_region_unref(mr);
3613 return;
3615 if (is_write) {
3616 address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED,
3617 bounce.buffer, access_len);
3619 qemu_vfree(bounce.buffer);
3620 bounce.buffer = NULL;
3621 memory_region_unref(bounce.mr);
3622 atomic_mb_set(&bounce.in_use, false);
3623 cpu_notify_map_clients();
3626 void *cpu_physical_memory_map(hwaddr addr,
3627 hwaddr *plen,
3628 int is_write)
3630 return address_space_map(&address_space_memory, addr, plen, is_write,
3631 MEMTXATTRS_UNSPECIFIED);
3634 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
3635 int is_write, hwaddr access_len)
3637 return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
3640 #define ARG1_DECL AddressSpace *as
3641 #define ARG1 as
3642 #define SUFFIX
3643 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3644 #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write)
3645 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3646 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3647 #define RCU_READ_LOCK(...) rcu_read_lock()
3648 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3649 #include "memory_ldst.inc.c"
3651 int64_t address_space_cache_init(MemoryRegionCache *cache,
3652 AddressSpace *as,
3653 hwaddr addr,
3654 hwaddr len,
3655 bool is_write)
3657 AddressSpaceDispatch *d;
3658 hwaddr l;
3659 MemoryRegion *mr;
3661 assert(len > 0);
3663 l = len;
3664 cache->fv = address_space_get_flatview(as);
3665 d = flatview_to_dispatch(cache->fv);
3666 cache->mrs = *address_space_translate_internal(d, addr, &cache->xlat, &l, true);
3668 mr = cache->mrs.mr;
3669 memory_region_ref(mr);
3670 if (memory_access_is_direct(mr, is_write)) {
3671 /* We don't care about the memory attributes here as we're only
3672 * doing this if we found actual RAM, which behaves the same
3673 * regardless of attributes; so UNSPECIFIED is fine.
3675 l = flatview_extend_translation(cache->fv, addr, len, mr,
3676 cache->xlat, l, is_write,
3677 MEMTXATTRS_UNSPECIFIED);
3678 cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
3679 } else {
3680 cache->ptr = NULL;
3683 cache->len = l;
3684 cache->is_write = is_write;
3685 return l;
3688 void address_space_cache_invalidate(MemoryRegionCache *cache,
3689 hwaddr addr,
3690 hwaddr access_len)
3692 assert(cache->is_write);
3693 if (likely(cache->ptr)) {
3694 invalidate_and_set_dirty(cache->mrs.mr, addr + cache->xlat, access_len);
3698 void address_space_cache_destroy(MemoryRegionCache *cache)
3700 if (!cache->mrs.mr) {
3701 return;
3704 if (xen_enabled()) {
3705 xen_invalidate_map_cache_entry(cache->ptr);
3707 memory_region_unref(cache->mrs.mr);
3708 flatview_unref(cache->fv);
3709 cache->mrs.mr = NULL;
3710 cache->fv = NULL;
3713 /* Called from RCU critical section. This function has the same
3714 * semantics as address_space_translate, but it only works on a
3715 * predefined range of a MemoryRegion that was mapped with
3716 * address_space_cache_init.
3718 static inline MemoryRegion *address_space_translate_cached(
3719 MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
3720 hwaddr *plen, bool is_write, MemTxAttrs attrs)
3722 MemoryRegionSection section;
3723 MemoryRegion *mr;
3724 IOMMUMemoryRegion *iommu_mr;
3725 AddressSpace *target_as;
3727 assert(!cache->ptr);
3728 *xlat = addr + cache->xlat;
3730 mr = cache->mrs.mr;
3731 iommu_mr = memory_region_get_iommu(mr);
3732 if (!iommu_mr) {
3733 /* MMIO region. */
3734 return mr;
3737 section = address_space_translate_iommu(iommu_mr, xlat, plen,
3738 NULL, is_write, true,
3739 &target_as, attrs);
3740 return section.mr;
3743 /* Called from RCU critical section. address_space_read_cached uses this
3744 * out of line function when the target is an MMIO or IOMMU region.
3746 void
3747 address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
3748 void *buf, int len)
3750 hwaddr addr1, l;
3751 MemoryRegion *mr;
3753 l = len;
3754 mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
3755 MEMTXATTRS_UNSPECIFIED);
3756 flatview_read_continue(cache->fv,
3757 addr, MEMTXATTRS_UNSPECIFIED, buf, len,
3758 addr1, l, mr);
3761 /* Called from RCU critical section. address_space_write_cached uses this
3762 * out of line function when the target is an MMIO or IOMMU region.
3764 void
3765 address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
3766 const void *buf, int len)
3768 hwaddr addr1, l;
3769 MemoryRegion *mr;
3771 l = len;
3772 mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
3773 MEMTXATTRS_UNSPECIFIED);
3774 flatview_write_continue(cache->fv,
3775 addr, MEMTXATTRS_UNSPECIFIED, buf, len,
3776 addr1, l, mr);
3779 #define ARG1_DECL MemoryRegionCache *cache
3780 #define ARG1 cache
3781 #define SUFFIX _cached_slow
3782 #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
3783 #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write)
3784 #define MAP_RAM(mr, ofs) (cache->ptr + (ofs - cache->xlat))
3785 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3786 #define RCU_READ_LOCK() ((void)0)
3787 #define RCU_READ_UNLOCK() ((void)0)
3788 #include "memory_ldst.inc.c"
3790 /* virtual memory access for debug (includes writing to ROM) */
3791 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3792 uint8_t *buf, int len, int is_write)
3794 int l;
3795 hwaddr phys_addr;
3796 target_ulong page;
3798 cpu_synchronize_state(cpu);
3799 while (len > 0) {
3800 int asidx;
3801 MemTxAttrs attrs;
3803 page = addr & TARGET_PAGE_MASK;
3804 phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs);
3805 asidx = cpu_asidx_from_attrs(cpu, attrs);
3806 /* if no physical page mapped, return an error */
3807 if (phys_addr == -1)
3808 return -1;
3809 l = (page + TARGET_PAGE_SIZE) - addr;
3810 if (l > len)
3811 l = len;
3812 phys_addr += (addr & ~TARGET_PAGE_MASK);
3813 if (is_write) {
3814 cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as,
3815 phys_addr, buf, l);
3816 } else {
3817 address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
3818 MEMTXATTRS_UNSPECIFIED,
3819 buf, l, 0);
3821 len -= l;
3822 buf += l;
3823 addr += l;
3825 return 0;
3829 * Allows code that needs to deal with migration bitmaps etc to still be built
3830 * target independent.
3832 size_t qemu_target_page_size(void)
3834 return TARGET_PAGE_SIZE;
3837 int qemu_target_page_bits(void)
3839 return TARGET_PAGE_BITS;
3842 int qemu_target_page_bits_min(void)
3844 return TARGET_PAGE_BITS_MIN;
3846 #endif
3849 * A helper function for the _utterly broken_ virtio device model to find out if
3850 * it's running on a big endian machine. Don't do this at home kids!
3852 bool target_words_bigendian(void);
3853 bool target_words_bigendian(void)
3855 #if defined(TARGET_WORDS_BIGENDIAN)
3856 return true;
3857 #else
3858 return false;
3859 #endif
3862 #ifndef CONFIG_USER_ONLY
3863 bool cpu_physical_memory_is_io(hwaddr phys_addr)
3865 MemoryRegion*mr;
3866 hwaddr l = 1;
3867 bool res;
3869 rcu_read_lock();
3870 mr = address_space_translate(&address_space_memory,
3871 phys_addr, &phys_addr, &l, false,
3872 MEMTXATTRS_UNSPECIFIED);
3874 res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
3875 rcu_read_unlock();
3876 return res;
3879 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque)
3881 RAMBlock *block;
3882 int ret = 0;
3884 rcu_read_lock();
3885 RAMBLOCK_FOREACH(block) {
3886 ret = func(block->idstr, block->host, block->offset,
3887 block->used_length, opaque);
3888 if (ret) {
3889 break;
3892 rcu_read_unlock();
3893 return ret;
3897 * Unmap pages of memory from start to start+length such that
3898 * they a) read as 0, b) Trigger whatever fault mechanism
3899 * the OS provides for postcopy.
3900 * The pages must be unmapped by the end of the function.
3901 * Returns: 0 on success, none-0 on failure
3904 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length)
3906 int ret = -1;
3908 uint8_t *host_startaddr = rb->host + start;
3910 if ((uintptr_t)host_startaddr & (rb->page_size - 1)) {
3911 error_report("ram_block_discard_range: Unaligned start address: %p",
3912 host_startaddr);
3913 goto err;
3916 if ((start + length) <= rb->used_length) {
3917 bool need_madvise, need_fallocate;
3918 uint8_t *host_endaddr = host_startaddr + length;
3919 if ((uintptr_t)host_endaddr & (rb->page_size - 1)) {
3920 error_report("ram_block_discard_range: Unaligned end address: %p",
3921 host_endaddr);
3922 goto err;
3925 errno = ENOTSUP; /* If we are missing MADVISE etc */
3927 /* The logic here is messy;
3928 * madvise DONTNEED fails for hugepages
3929 * fallocate works on hugepages and shmem
3931 need_madvise = (rb->page_size == qemu_host_page_size);
3932 need_fallocate = rb->fd != -1;
3933 if (need_fallocate) {
3934 /* For a file, this causes the area of the file to be zero'd
3935 * if read, and for hugetlbfs also causes it to be unmapped
3936 * so a userfault will trigger.
3938 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
3939 ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE,
3940 start, length);
3941 if (ret) {
3942 ret = -errno;
3943 error_report("ram_block_discard_range: Failed to fallocate "
3944 "%s:%" PRIx64 " +%zx (%d)",
3945 rb->idstr, start, length, ret);
3946 goto err;
3948 #else
3949 ret = -ENOSYS;
3950 error_report("ram_block_discard_range: fallocate not available/file"
3951 "%s:%" PRIx64 " +%zx (%d)",
3952 rb->idstr, start, length, ret);
3953 goto err;
3954 #endif
3956 if (need_madvise) {
3957 /* For normal RAM this causes it to be unmapped,
3958 * for shared memory it causes the local mapping to disappear
3959 * and to fall back on the file contents (which we just
3960 * fallocate'd away).
3962 #if defined(CONFIG_MADVISE)
3963 ret = madvise(host_startaddr, length, MADV_DONTNEED);
3964 if (ret) {
3965 ret = -errno;
3966 error_report("ram_block_discard_range: Failed to discard range "
3967 "%s:%" PRIx64 " +%zx (%d)",
3968 rb->idstr, start, length, ret);
3969 goto err;
3971 #else
3972 ret = -ENOSYS;
3973 error_report("ram_block_discard_range: MADVISE not available"
3974 "%s:%" PRIx64 " +%zx (%d)",
3975 rb->idstr, start, length, ret);
3976 goto err;
3977 #endif
3979 trace_ram_block_discard_range(rb->idstr, host_startaddr, length,
3980 need_madvise, need_fallocate, ret);
3981 } else {
3982 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
3983 "/%zx/" RAM_ADDR_FMT")",
3984 rb->idstr, start, length, rb->used_length);
3987 err:
3988 return ret;
3991 #endif
3993 void page_size_init(void)
3995 /* NOTE: we can always suppose that qemu_host_page_size >=
3996 TARGET_PAGE_SIZE */
3997 if (qemu_host_page_size == 0) {
3998 qemu_host_page_size = qemu_real_host_page_size;
4000 if (qemu_host_page_size < TARGET_PAGE_SIZE) {
4001 qemu_host_page_size = TARGET_PAGE_SIZE;
4003 qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
4006 #if !defined(CONFIG_USER_ONLY)
4008 static void mtree_print_phys_entries(fprintf_function mon, void *f,
4009 int start, int end, int skip, int ptr)
4011 if (start == end - 1) {
4012 mon(f, "\t%3d ", start);
4013 } else {
4014 mon(f, "\t%3d..%-3d ", start, end - 1);
4016 mon(f, " skip=%d ", skip);
4017 if (ptr == PHYS_MAP_NODE_NIL) {
4018 mon(f, " ptr=NIL");
4019 } else if (!skip) {
4020 mon(f, " ptr=#%d", ptr);
4021 } else {
4022 mon(f, " ptr=[%d]", ptr);
4024 mon(f, "\n");
4027 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
4028 int128_sub((size), int128_one())) : 0)
4030 void mtree_print_dispatch(fprintf_function mon, void *f,
4031 AddressSpaceDispatch *d, MemoryRegion *root)
4033 int i;
4035 mon(f, " Dispatch\n");
4036 mon(f, " Physical sections\n");
4038 for (i = 0; i < d->map.sections_nb; ++i) {
4039 MemoryRegionSection *s = d->map.sections + i;
4040 const char *names[] = { " [unassigned]", " [not dirty]",
4041 " [ROM]", " [watch]" };
4043 mon(f, " #%d @" TARGET_FMT_plx ".." TARGET_FMT_plx " %s%s%s%s%s",
4045 s->offset_within_address_space,
4046 s->offset_within_address_space + MR_SIZE(s->mr->size),
4047 s->mr->name ? s->mr->name : "(noname)",
4048 i < ARRAY_SIZE(names) ? names[i] : "",
4049 s->mr == root ? " [ROOT]" : "",
4050 s == d->mru_section ? " [MRU]" : "",
4051 s->mr->is_iommu ? " [iommu]" : "");
4053 if (s->mr->alias) {
4054 mon(f, " alias=%s", s->mr->alias->name ?
4055 s->mr->alias->name : "noname");
4057 mon(f, "\n");
4060 mon(f, " Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
4061 P_L2_BITS, P_L2_LEVELS, d->phys_map.ptr, d->phys_map.skip);
4062 for (i = 0; i < d->map.nodes_nb; ++i) {
4063 int j, jprev;
4064 PhysPageEntry prev;
4065 Node *n = d->map.nodes + i;
4067 mon(f, " [%d]\n", i);
4069 for (j = 0, jprev = 0, prev = *n[0]; j < ARRAY_SIZE(*n); ++j) {
4070 PhysPageEntry *pe = *n + j;
4072 if (pe->ptr == prev.ptr && pe->skip == prev.skip) {
4073 continue;
4076 mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr);
4078 jprev = j;
4079 prev = *pe;
4082 if (jprev != ARRAY_SIZE(*n)) {
4083 mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr);
4088 #endif