hw/spitz.c

   1 /*
   2  * PXA270-based Clamshell PDA platforms.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Written by Andrzej Zaborowski <balrog@zabor.org>
   6  *
   7  * This code is licensed under the GNU GPL v2.
   8  */
   9
  10 #include "hw.h"
  11 #include "pxa.h"
  12 #include "arm-misc.h"
  13 #include "sysemu.h"
  14 #include "pcmcia.h"
  15 #include "i2c.h"
  16 #include "ssi.h"
  17 #include "flash.h"
  18 #include "qemu-timer.h"
  19 #include "devices.h"
  20 #include "sharpsl.h"
  21 #include "console.h"
  22 #include "block.h"
  23 #include "audio/audio.h"
  24 #include "boards.h"
  25 #include "blockdev.h"
  26 #include "sysbus.h"
  27
  28 #undef REG_FMT
  29 #define REG_FMT                 "0x%02lx"
  30
  31 /* Spitz Flash */
  32 #define FLASH_BASE              0x0c000000
  33 #define FLASH_ECCLPLB           0x00    /* Line parity 7 - 0 bit */
  34 #define FLASH_ECCLPUB           0x04    /* Line parity 15 - 8 bit */
  35 #define FLASH_ECCCP             0x08    /* Column parity 5 - 0 bit */
  36 #define FLASH_ECCCNTR           0x0c    /* ECC byte counter */
  37 #define FLASH_ECCCLRR           0x10    /* Clear ECC */
  38 #define FLASH_FLASHIO           0x14    /* Flash I/O */
  39 #define FLASH_FLASHCTL          0x18    /* Flash Control */
  40
  41 #define FLASHCTL_CE0            (1 << 0)
  42 #define FLASHCTL_CLE            (1 << 1)
  43 #define FLASHCTL_ALE            (1 << 2)
  44 #define FLASHCTL_WP             (1 << 3)
  45 #define FLASHCTL_CE1            (1 << 4)
  46 #define FLASHCTL_RYBY           (1 << 5)
  47 #define FLASHCTL_NCE            (FLASHCTL_CE0 | FLASHCTL_CE1)
  48
  49 typedef struct {
  50     NANDFlashState *nand;
  51     uint8_t ctl;
  52     ECCState ecc;
  53 } SLNANDState;
  54
  55 static uint32_t sl_readb(void *opaque, target_phys_addr_t addr)
  56 {
  57     SLNANDState *s = (SLNANDState *) opaque;
  58     int ryby;
  59
  60     switch (addr) {
  61 #define BSHR(byte, from, to)    ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
  62     case FLASH_ECCLPLB:
  63         return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
  64                 BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
  65
  66 #define BSHL(byte, from, to)    ((s->ecc.lp[byte] << (to - from)) & (1 << to))
  67     case FLASH_ECCLPUB:
  68         return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
  69                 BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
  70
  71     case FLASH_ECCCP:
  72         return s->ecc.cp;
  73
  74     case FLASH_ECCCNTR:
  75         return s->ecc.count & 0xff;
  76
  77     case FLASH_FLASHCTL:
  78         nand_getpins(s->nand, &ryby);
  79         if (ryby)
  80             return s->ctl | FLASHCTL_RYBY;
  81         else
  82             return s->ctl;
  83
  84     case FLASH_FLASHIO:
  85         return ecc_digest(&s->ecc, nand_getio(s->nand));
  86
  87     default:
  88         zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
  89     }
  90     return 0;
  91 }
  92
  93 static uint32_t sl_readl(void *opaque, target_phys_addr_t addr)
  94 {
  95     SLNANDState *s = (SLNANDState *) opaque;
  96
  97     if (addr == FLASH_FLASHIO)
  98         return ecc_digest(&s->ecc, nand_getio(s->nand)) |
  99                 (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
 100
 101     return sl_readb(opaque, addr);
 102 }
 103
 104 static void sl_writeb(void *opaque, target_phys_addr_t addr,
 105                 uint32_t value)
 106 {
 107     SLNANDState *s = (SLNANDState *) opaque;
 108
 109     switch (addr) {
 110     case FLASH_ECCCLRR:
 111         /* Value is ignored.  */
 112         ecc_reset(&s->ecc);
 113         break;
 114
 115     case FLASH_FLASHCTL:
 116         s->ctl = value & 0xff & ~FLASHCTL_RYBY;
 117         nand_setpins(s->nand,
 118                         s->ctl & FLASHCTL_CLE,
 119                         s->ctl & FLASHCTL_ALE,
 120                         s->ctl & FLASHCTL_NCE,
 121                         s->ctl & FLASHCTL_WP,
 122                         0);
 123         break;
 124
 125     case FLASH_FLASHIO:
 126         nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
 127         break;
 128
 129     default:
 130         zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
 131     }
 132 }
 133
 134 static void sl_save(QEMUFile *f, void *opaque)
 135 {
 136     SLNANDState *s = (SLNANDState *) opaque;
 137
 138     qemu_put_8s(f, &s->ctl);
 139     ecc_put(f, &s->ecc);
 140 }
 141
 142 static int sl_load(QEMUFile *f, void *opaque, int version_id)
 143 {
 144     SLNANDState *s = (SLNANDState *) opaque;
 145
 146     qemu_get_8s(f, &s->ctl);
 147     ecc_get(f, &s->ecc);
 148
 149     return 0;
 150 }
 151
 152 enum {
 153     FLASH_128M,
 154     FLASH_1024M,
 155 };
 156
 157 static void sl_flash_register(PXA2xxState *cpu, int size)
 158 {
 159     int iomemtype;
 160     SLNANDState *s;
 161     CPUReadMemoryFunc * const sl_readfn[] = {
 162         sl_readb,
 163         sl_readb,
 164         sl_readl,
 165     };
 166     CPUWriteMemoryFunc * const sl_writefn[] = {
 167         sl_writeb,
 168         sl_writeb,
 169         sl_writeb,
 170     };
 171
 172     s = (SLNANDState *) qemu_mallocz(sizeof(SLNANDState));
 173     s->ctl = 0;
 174     if (size == FLASH_128M)
 175         s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73);
 176     else if (size == FLASH_1024M)
 177         s->nand = nand_init(NAND_MFR_SAMSUNG, 0xf1);
 178
 179     iomemtype = cpu_register_io_memory(sl_readfn,
 180                     sl_writefn, s, DEVICE_NATIVE_ENDIAN);
 181     cpu_register_physical_memory(FLASH_BASE, 0x40, iomemtype);
 182
 183     register_savevm(NULL, "sl_flash", 0, 0, sl_save, sl_load, s);
 184 }
 185
 186 /* Spitz Keyboard */
 187
 188 #define SPITZ_KEY_STROBE_NUM    11
 189 #define SPITZ_KEY_SENSE_NUM     7
 190
 191 static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
 192     12, 17, 91, 34, 36, 38, 39
 193 };
 194
 195 static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = {
 196     88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114
 197 };
 198
 199 /* Eighth additional row maps the special keys */
 200 static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
 201     { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 },
 202     {  -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 },
 203     { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25,  -1 ,  -1 ,  -1  },
 204     { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26,  -1 , 0x36,  -1  },
 205     { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34,  -1 , 0x1c, 0x2a,  -1  },
 206     { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33,  -1 , 0x48,  -1 ,  -1 , 0x38 },
 207     { 0x37, 0x3d,  -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d,  -1 ,  -1  },
 208     { 0x52, 0x43, 0x01, 0x47, 0x49,  -1 ,  -1 ,  -1 ,  -1 ,  -1 ,  -1  },
 209 };
 210
 211 #define SPITZ_GPIO_AK_INT       13      /* Remote control */
 212 #define SPITZ_GPIO_SYNC         16      /* Sync button */
 213 #define SPITZ_GPIO_ON_KEY       95      /* Power button */
 214 #define SPITZ_GPIO_SWA          97      /* Lid */
 215 #define SPITZ_GPIO_SWB          96      /* Tablet mode */
 216
 217 /* The special buttons are mapped to unused keys */
 218 static const int spitz_gpiomap[5] = {
 219     SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY,
 220     SPITZ_GPIO_SWA, SPITZ_GPIO_SWB,
 221 };
 222 static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, };
 223
 224 typedef struct {
 225     qemu_irq sense[SPITZ_KEY_SENSE_NUM];
 226     qemu_irq *strobe;
 227     qemu_irq gpiomap[5];
 228     int keymap[0x80];
 229     uint16_t keyrow[SPITZ_KEY_SENSE_NUM];
 230     uint16_t strobe_state;
 231     uint16_t sense_state;
 232
 233     uint16_t pre_map[0x100];
 234     uint16_t modifiers;
 235     uint16_t imodifiers;
 236     uint8_t fifo[16];
 237     int fifopos, fifolen;
 238     QEMUTimer *kbdtimer;
 239 } SpitzKeyboardState;
 240
 241 static void spitz_keyboard_sense_update(SpitzKeyboardState *s)
 242 {
 243     int i;
 244     uint16_t strobe, sense = 0;
 245     for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) {
 246         strobe = s->keyrow[i] & s->strobe_state;
 247         if (strobe) {
 248             sense |= 1 << i;
 249             if (!(s->sense_state & (1 << i)))
 250                 qemu_irq_raise(s->sense[i]);
 251         } else if (s->sense_state & (1 << i))
 252             qemu_irq_lower(s->sense[i]);
 253     }
 254
 255     s->sense_state = sense;
 256 }
 257
 258 static void spitz_keyboard_strobe(void *opaque, int line, int level)
 259 {
 260     SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
 261
 262     if (level)
 263         s->strobe_state |= 1 << line;
 264     else
 265         s->strobe_state &= ~(1 << line);
 266     spitz_keyboard_sense_update(s);
 267 }
 268
 269 static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode)
 270 {
 271     int spitz_keycode = s->keymap[keycode & 0x7f];
 272     if (spitz_keycode == -1)
 273         return;
 274
 275     /* Handle the additional keys */
 276     if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) {
 277         qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80) ^
 278                         spitz_gpio_invert[spitz_keycode & 0xf]);
 279         return;
 280     }
 281
 282     if (keycode & 0x80)
 283         s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf));
 284     else
 285         s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf);
 286
 287     spitz_keyboard_sense_update(s);
 288 }
 289
 290 #define SHIFT   (1 << 7)
 291 #define CTRL    (1 << 8)
 292 #define FN      (1 << 9)
 293
 294 #define QUEUE_KEY(c)    s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
 295
 296 static void spitz_keyboard_handler(SpitzKeyboardState *s, int keycode)
 297 {
 298     uint16_t code;
 299     int mapcode;
 300     switch (keycode) {
 301     case 0x2a:  /* Left Shift */
 302         s->modifiers |= 1;
 303         break;
 304     case 0xaa:
 305         s->modifiers &= ~1;
 306         break;
 307     case 0x36:  /* Right Shift */
 308         s->modifiers |= 2;
 309         break;
 310     case 0xb6:
 311         s->modifiers &= ~2;
 312         break;
 313     case 0x1d:  /* Control */
 314         s->modifiers |= 4;
 315         break;
 316     case 0x9d:
 317         s->modifiers &= ~4;
 318         break;
 319     case 0x38:  /* Alt */
 320         s->modifiers |= 8;
 321         break;
 322     case 0xb8:
 323         s->modifiers &= ~8;
 324         break;
 325     }
 326
 327     code = s->pre_map[mapcode = ((s->modifiers & 3) ?
 328             (keycode | SHIFT) :
 329             (keycode & ~SHIFT))];
 330
 331     if (code != mapcode) {
 332 #if 0
 333         if ((code & SHIFT) && !(s->modifiers & 1))
 334             QUEUE_KEY(0x2a | (keycode & 0x80));
 335         if ((code & CTRL ) && !(s->modifiers & 4))
 336             QUEUE_KEY(0x1d | (keycode & 0x80));
 337         if ((code & FN   ) && !(s->modifiers & 8))
 338             QUEUE_KEY(0x38 | (keycode & 0x80));
 339         if ((code & FN   ) && (s->modifiers & 1))
 340             QUEUE_KEY(0x2a | (~keycode & 0x80));
 341         if ((code & FN   ) && (s->modifiers & 2))
 342             QUEUE_KEY(0x36 | (~keycode & 0x80));
 343 #else
 344         if (keycode & 0x80) {
 345             if ((s->imodifiers & 1   ) && !(s->modifiers & 1))
 346                 QUEUE_KEY(0x2a | 0x80);
 347             if ((s->imodifiers & 4   ) && !(s->modifiers & 4))
 348                 QUEUE_KEY(0x1d | 0x80);
 349             if ((s->imodifiers & 8   ) && !(s->modifiers & 8))
 350                 QUEUE_KEY(0x38 | 0x80);
 351             if ((s->imodifiers & 0x10) && (s->modifiers & 1))
 352                 QUEUE_KEY(0x2a);
 353             if ((s->imodifiers & 0x20) && (s->modifiers & 2))
 354                 QUEUE_KEY(0x36);
 355             s->imodifiers = 0;
 356         } else {
 357             if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) {
 358                 QUEUE_KEY(0x2a);
 359                 s->imodifiers |= 1;
 360             }
 361             if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) {
 362                 QUEUE_KEY(0x1d);
 363                 s->imodifiers |= 4;
 364             }
 365             if ((code & FN   ) && !((s->modifiers | s->imodifiers) & 8)) {
 366                 QUEUE_KEY(0x38);
 367                 s->imodifiers |= 8;
 368             }
 369             if ((code & FN   ) && (s->modifiers & 1) &&
 370                             !(s->imodifiers & 0x10)) {
 371                 QUEUE_KEY(0x2a | 0x80);
 372                 s->imodifiers |= 0x10;
 373             }
 374             if ((code & FN   ) && (s->modifiers & 2) &&
 375                             !(s->imodifiers & 0x20)) {
 376                 QUEUE_KEY(0x36 | 0x80);
 377                 s->imodifiers |= 0x20;
 378             }
 379         }
 380 #endif
 381     }
 382
 383     QUEUE_KEY((code & 0x7f) | (keycode & 0x80));
 384 }
 385
 386 static void spitz_keyboard_tick(void *opaque)
 387 {
 388     SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
 389
 390     if (s->fifolen) {
 391         spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]);
 392         s->fifolen --;
 393         if (s->fifopos >= 16)
 394             s->fifopos = 0;
 395     }
 396
 397     qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) +
 398                    get_ticks_per_sec() / 32);
 399 }
 400
 401 static void spitz_keyboard_pre_map(SpitzKeyboardState *s)
 402 {
 403     int i;
 404     for (i = 0; i < 0x100; i ++)
 405         s->pre_map[i] = i;
 406     s->pre_map[0x02 | SHIFT     ] = 0x02 | SHIFT;       /* exclam */
 407     s->pre_map[0x28 | SHIFT     ] = 0x03 | SHIFT;       /* quotedbl */
 408     s->pre_map[0x04 | SHIFT     ] = 0x04 | SHIFT;       /* numbersign */
 409     s->pre_map[0x05 | SHIFT     ] = 0x05 | SHIFT;       /* dollar */
 410     s->pre_map[0x06 | SHIFT     ] = 0x06 | SHIFT;       /* percent */
 411     s->pre_map[0x08 | SHIFT     ] = 0x07 | SHIFT;       /* ampersand */
 412     s->pre_map[0x28             ] = 0x08 | SHIFT;       /* apostrophe */
 413     s->pre_map[0x0a | SHIFT     ] = 0x09 | SHIFT;       /* parenleft */
 414     s->pre_map[0x0b | SHIFT     ] = 0x0a | SHIFT;       /* parenright */
 415     s->pre_map[0x29 | SHIFT     ] = 0x0b | SHIFT;       /* asciitilde */
 416     s->pre_map[0x03 | SHIFT     ] = 0x0c | SHIFT;       /* at */
 417     s->pre_map[0xd3             ] = 0x0e | FN;          /* Delete */
 418     s->pre_map[0x3a             ] = 0x0f | FN;          /* Caps_Lock */
 419     s->pre_map[0x07 | SHIFT     ] = 0x11 | FN;          /* asciicircum */
 420     s->pre_map[0x0d             ] = 0x12 | FN;          /* equal */
 421     s->pre_map[0x0d | SHIFT     ] = 0x13 | FN;          /* plus */
 422     s->pre_map[0x1a             ] = 0x14 | FN;          /* bracketleft */
 423     s->pre_map[0x1b             ] = 0x15 | FN;          /* bracketright */
 424     s->pre_map[0x1a | SHIFT     ] = 0x16 | FN;          /* braceleft */
 425     s->pre_map[0x1b | SHIFT     ] = 0x17 | FN;          /* braceright */
 426     s->pre_map[0x27             ] = 0x22 | FN;          /* semicolon */
 427     s->pre_map[0x27 | SHIFT     ] = 0x23 | FN;          /* colon */
 428     s->pre_map[0x09 | SHIFT     ] = 0x24 | FN;          /* asterisk */
 429     s->pre_map[0x2b             ] = 0x25 | FN;          /* backslash */
 430     s->pre_map[0x2b | SHIFT     ] = 0x26 | FN;          /* bar */
 431     s->pre_map[0x0c | SHIFT     ] = 0x30 | FN;          /* underscore */
 432     s->pre_map[0x33 | SHIFT     ] = 0x33 | FN;          /* less */
 433     s->pre_map[0x35             ] = 0x33 | SHIFT;       /* slash */
 434     s->pre_map[0x34 | SHIFT     ] = 0x34 | FN;          /* greater */
 435     s->pre_map[0x35 | SHIFT     ] = 0x34 | SHIFT;       /* question */
 436     s->pre_map[0x49             ] = 0x48 | FN;          /* Page_Up */
 437     s->pre_map[0x51             ] = 0x50 | FN;          /* Page_Down */
 438
 439     s->modifiers = 0;
 440     s->imodifiers = 0;
 441     s->fifopos = 0;
 442     s->fifolen = 0;
 443     s->kbdtimer = qemu_new_timer(vm_clock, spitz_keyboard_tick, s);
 444     spitz_keyboard_tick(s);
 445 }
 446
 447 #undef SHIFT
 448 #undef CTRL
 449 #undef FN
 450
 451 static void spitz_keyboard_save(QEMUFile *f, void *opaque)
 452 {
 453     SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
 454     int i;
 455
 456     qemu_put_be16s(f, &s->sense_state);
 457     qemu_put_be16s(f, &s->strobe_state);
 458     for (i = 0; i < 5; i ++)
 459         qemu_put_byte(f, spitz_gpio_invert[i]);
 460 }
 461
 462 static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id)
 463 {
 464     SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
 465     int i;
 466
 467     qemu_get_be16s(f, &s->sense_state);
 468     qemu_get_be16s(f, &s->strobe_state);
 469     for (i = 0; i < 5; i ++)
 470         spitz_gpio_invert[i] = qemu_get_byte(f);
 471
 472     /* Release all pressed keys */
 473     memset(s->keyrow, 0, sizeof(s->keyrow));
 474     spitz_keyboard_sense_update(s);
 475     s->modifiers = 0;
 476     s->imodifiers = 0;
 477     s->fifopos = 0;
 478     s->fifolen = 0;
 479
 480     return 0;
 481 }
 482
 483 static void spitz_keyboard_register(PXA2xxState *cpu)
 484 {
 485     int i, j;
 486     SpitzKeyboardState *s;
 487
 488     s = (SpitzKeyboardState *)
 489             qemu_mallocz(sizeof(SpitzKeyboardState));
 490     memset(s, 0, sizeof(SpitzKeyboardState));
 491
 492     for (i = 0; i < 0x80; i ++)
 493         s->keymap[i] = -1;
 494     for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++)
 495         for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++)
 496             if (spitz_keymap[i][j] != -1)
 497                 s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
 498
 499     for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++)
 500         s->sense[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpio_key_sense[i]];
 501
 502     for (i = 0; i < 5; i ++)
 503         s->gpiomap[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpiomap[i]];
 504
 505     s->strobe = qemu_allocate_irqs(spitz_keyboard_strobe, s,
 506                     SPITZ_KEY_STROBE_NUM);
 507     for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
 508         pxa2xx_gpio_out_set(cpu->gpio, spitz_gpio_key_strobe[i], s->strobe[i]);
 509
 510     spitz_keyboard_pre_map(s);
 511     qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s);
 512
 513     register_savevm(NULL, "spitz_keyboard", 0, 0,
 514                     spitz_keyboard_save, spitz_keyboard_load, s);
 515 }
 516
 517 /* LCD backlight controller */
 518
 519 #define LCDTG_RESCTL    0x00
 520 #define LCDTG_PHACTRL   0x01
 521 #define LCDTG_DUTYCTRL  0x02
 522 #define LCDTG_POWERREG0 0x03
 523 #define LCDTG_POWERREG1 0x04
 524 #define LCDTG_GPOR3     0x05
 525 #define LCDTG_PICTRL    0x06
 526 #define LCDTG_POLCTRL   0x07
 527
 528 typedef struct {
 529     SSISlave ssidev;
 530     int bl_intensity;
 531     int bl_power;
 532 } SpitzLCDTG;
 533
 534 static void spitz_bl_update(SpitzLCDTG *s)
 535 {
 536     if (s->bl_power && s->bl_intensity)
 537         zaurus_printf("LCD Backlight now at %i/63\n", s->bl_intensity);
 538     else
 539         zaurus_printf("LCD Backlight now off\n");
 540 }
 541
 542 /* FIXME: Implement GPIO properly and remove this hack.  */
 543 static SpitzLCDTG *spitz_lcdtg;
 544
 545 static inline void spitz_bl_bit5(void *opaque, int line, int level)
 546 {
 547     SpitzLCDTG *s = spitz_lcdtg;
 548     int prev = s->bl_intensity;
 549
 550     if (level)
 551         s->bl_intensity &= ~0x20;
 552     else
 553         s->bl_intensity |= 0x20;
 554
 555     if (s->bl_power && prev != s->bl_intensity)
 556         spitz_bl_update(s);
 557 }
 558
 559 static inline void spitz_bl_power(void *opaque, int line, int level)
 560 {
 561     SpitzLCDTG *s = spitz_lcdtg;
 562     s->bl_power = !!level;
 563     spitz_bl_update(s);
 564 }
 565
 566 static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
 567 {
 568     SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
 569     int addr;
 570     addr = value >> 5;
 571     value &= 0x1f;
 572
 573     switch (addr) {
 574     case LCDTG_RESCTL:
 575         if (value)
 576             zaurus_printf("LCD in QVGA mode\n");
 577         else
 578             zaurus_printf("LCD in VGA mode\n");
 579         break;
 580
 581     case LCDTG_DUTYCTRL:
 582         s->bl_intensity &= ~0x1f;
 583         s->bl_intensity |= value;
 584         if (s->bl_power)
 585             spitz_bl_update(s);
 586         break;
 587
 588     case LCDTG_POWERREG0:
 589         /* Set common voltage to M62332FP */
 590         break;
 591     }
 592     return 0;
 593 }
 594
 595 static void spitz_lcdtg_save(QEMUFile *f, void *opaque)
 596 {
 597     SpitzLCDTG *s = (SpitzLCDTG *)opaque;
 598     qemu_put_be32(f, s->bl_intensity);
 599     qemu_put_be32(f, s->bl_power);
 600 }
 601
 602 static int spitz_lcdtg_load(QEMUFile *f, void *opaque, int version_id)
 603 {
 604     SpitzLCDTG *s = (SpitzLCDTG *)opaque;
 605     s->bl_intensity = qemu_get_be32(f);
 606     s->bl_power = qemu_get_be32(f);
 607     return 0;
 608 }
 609
 610 static int spitz_lcdtg_init(SSISlave *dev)
 611 {
 612     SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
 613
 614     spitz_lcdtg = s;
 615     s->bl_power = 0;
 616     s->bl_intensity = 0x20;
 617
 618     register_savevm(&dev->qdev, "spitz-lcdtg", -1, 1,
 619                     spitz_lcdtg_save, spitz_lcdtg_load, s);
 620     return 0;
 621 }
 622
 623 /* SSP devices */
 624
 625 #define CORGI_SSP_PORT          2
 626
 627 #define SPITZ_GPIO_LCDCON_CS    53
 628 #define SPITZ_GPIO_ADS7846_CS   14
 629 #define SPITZ_GPIO_MAX1111_CS   20
 630 #define SPITZ_GPIO_TP_INT       11
 631
 632 static DeviceState *max1111;
 633
 634 /* "Demux" the signal based on current chipselect */
 635 typedef struct {
 636     SSISlave ssidev;
 637     SSIBus *bus[3];
 638     int enable[3];
 639 } CorgiSSPState;
 640
 641 static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
 642 {
 643     CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
 644     int i;
 645
 646     for (i = 0; i < 3; i++) {
 647         if (s->enable[i]) {
 648             return ssi_transfer(s->bus[i], value);
 649         }
 650     }
 651     return 0;
 652 }
 653
 654 static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
 655 {
 656     CorgiSSPState *s = (CorgiSSPState *)opaque;
 657     assert(line >= 0 && line < 3);
 658     s->enable[line] = !level;
 659 }
 660
 661 #define MAX1111_BATT_VOLT       1
 662 #define MAX1111_BATT_TEMP       2
 663 #define MAX1111_ACIN_VOLT       3
 664
 665 #define SPITZ_BATTERY_TEMP      0xe0    /* About 2.9V */
 666 #define SPITZ_BATTERY_VOLT      0xd0    /* About 4.0V */
 667 #define SPITZ_CHARGEON_ACIN     0x80    /* About 5.0V */
 668
 669 static void spitz_adc_temp_on(void *opaque, int line, int level)
 670 {
 671     if (!max1111)
 672         return;
 673
 674     if (level)
 675         max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
 676     else
 677         max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
 678 }
 679
 680 static void spitz_ssp_save(QEMUFile *f, void *opaque)
 681 {
 682     CorgiSSPState *s = (CorgiSSPState *)opaque;
 683     int i;
 684
 685     for (i = 0; i < 3; i++) {
 686         qemu_put_be32(f, s->enable[i]);
 687     }
 688 }
 689
 690 static int spitz_ssp_load(QEMUFile *f, void *opaque, int version_id)
 691 {
 692     CorgiSSPState *s = (CorgiSSPState *)opaque;
 693     int i;
 694
 695     if (version_id != 1) {
 696         return -EINVAL;
 697     }
 698     for (i = 0; i < 3; i++) {
 699         s->enable[i] = qemu_get_be32(f);
 700     }
 701     return 0;
 702 }
 703
 704 static int corgi_ssp_init(SSISlave *dev)
 705 {
 706     CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
 707
 708     qdev_init_gpio_in(&dev->qdev, corgi_ssp_gpio_cs, 3);
 709     s->bus[0] = ssi_create_bus(&dev->qdev, "ssi0");
 710     s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1");
 711     s->bus[2] = ssi_create_bus(&dev->qdev, "ssi2");
 712
 713     register_savevm(&dev->qdev, "spitz_ssp", -1, 1,
 714                     spitz_ssp_save, spitz_ssp_load, s);
 715     return 0;
 716 }
 717
 718 static void spitz_ssp_attach(PXA2xxState *cpu)
 719 {
 720     DeviceState *mux;
 721     DeviceState *dev;
 722     void *bus;
 723
 724     mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
 725
 726     bus = qdev_get_child_bus(mux, "ssi0");
 727     ssi_create_slave(bus, "spitz-lcdtg");
 728
 729     bus = qdev_get_child_bus(mux, "ssi1");
 730     dev = ssi_create_slave(bus, "ads7846");
 731     qdev_connect_gpio_out(dev, 0,
 732                           pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_TP_INT]);
 733
 734     bus = qdev_get_child_bus(mux, "ssi2");
 735     max1111 = ssi_create_slave(bus, "max1111");
 736     max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
 737     max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
 738     max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
 739
 740     pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
 741                         qdev_get_gpio_in(mux, 0));
 742     pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
 743                         qdev_get_gpio_in(mux, 1));
 744     pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
 745                         qdev_get_gpio_in(mux, 2));
 746 }
 747
 748 /* CF Microdrive */
 749
 750 static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
 751 {
 752     PCMCIACardState *md;
 753     BlockDriverState *bs;
 754     DriveInfo *dinfo;
 755
 756     dinfo = drive_get(IF_IDE, 0, 0);
 757     if (!dinfo)
 758         return;
 759     bs = dinfo->bdrv;
 760     if (bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) {
 761         md = dscm1xxxx_init(dinfo);
 762         pxa2xx_pcmcia_attach(cpu->pcmcia[slot], md);
 763     }
 764 }
 765
 766 /* Wm8750 and Max7310 on I2C */
 767
 768 #define AKITA_MAX_ADDR  0x18
 769 #define SPITZ_WM_ADDRL  0x1b
 770 #define SPITZ_WM_ADDRH  0x1a
 771
 772 #define SPITZ_GPIO_WM   5
 773
 774 static void spitz_wm8750_addr(void *opaque, int line, int level)
 775 {
 776     i2c_slave *wm = (i2c_slave *) opaque;
 777     if (level)
 778         i2c_set_slave_address(wm, SPITZ_WM_ADDRH);
 779     else
 780         i2c_set_slave_address(wm, SPITZ_WM_ADDRL);
 781 }
 782
 783 static void spitz_i2c_setup(PXA2xxState *cpu)
 784 {
 785     /* Attach the CPU on one end of our I2C bus.  */
 786     i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
 787
 788     DeviceState *wm;
 789
 790     /* Attach a WM8750 to the bus */
 791     wm = i2c_create_slave(bus, "wm8750", 0);
 792
 793     spitz_wm8750_addr(wm, 0, 0);
 794     pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_WM,
 795                     qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]);
 796     /* .. and to the sound interface.  */
 797     cpu->i2s->opaque = wm;
 798     cpu->i2s->codec_out = wm8750_dac_dat;
 799     cpu->i2s->codec_in = wm8750_adc_dat;
 800     wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
 801 }
 802
 803 static void spitz_akita_i2c_setup(PXA2xxState *cpu)
 804 {
 805     /* Attach a Max7310 to Akita I2C bus.  */
 806     i2c_create_slave(pxa2xx_i2c_bus(cpu->i2c[0]), "max7310",
 807                      AKITA_MAX_ADDR);
 808 }
 809
 810 /* Other peripherals */
 811
 812 static void spitz_out_switch(void *opaque, int line, int level)
 813 {
 814     switch (line) {
 815     case 0:
 816         zaurus_printf("Charging %s.\n", level ? "off" : "on");
 817         break;
 818     case 1:
 819         zaurus_printf("Discharging %s.\n", level ? "on" : "off");
 820         break;
 821     case 2:
 822         zaurus_printf("Green LED %s.\n", level ? "on" : "off");
 823         break;
 824     case 3:
 825         zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
 826         break;
 827     case 4:
 828         spitz_bl_bit5(opaque, line, level);
 829         break;
 830     case 5:
 831         spitz_bl_power(opaque, line, level);
 832         break;
 833     case 6:
 834         spitz_adc_temp_on(opaque, line, level);
 835         break;
 836     }
 837 }
 838
 839 #define SPITZ_SCP_LED_GREEN             1
 840 #define SPITZ_SCP_JK_B                  2
 841 #define SPITZ_SCP_CHRG_ON               3
 842 #define SPITZ_SCP_MUTE_L                4
 843 #define SPITZ_SCP_MUTE_R                5
 844 #define SPITZ_SCP_CF_POWER              6
 845 #define SPITZ_SCP_LED_ORANGE            7
 846 #define SPITZ_SCP_JK_A                  8
 847 #define SPITZ_SCP_ADC_TEMP_ON           9
 848 #define SPITZ_SCP2_IR_ON                1
 849 #define SPITZ_SCP2_AKIN_PULLUP          2
 850 #define SPITZ_SCP2_BACKLIGHT_CONT       7
 851 #define SPITZ_SCP2_BACKLIGHT_ON         8
 852 #define SPITZ_SCP2_MIC_BIAS             9
 853
 854 static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
 855                 DeviceState *scp0, DeviceState *scp1)
 856 {
 857     qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
 858
 859     qdev_connect_gpio_out(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
 860     qdev_connect_gpio_out(scp0, SPITZ_SCP_JK_B, outsignals[1]);
 861     qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
 862     qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
 863
 864     if (scp1) {
 865         qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
 866         qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
 867     }
 868
 869     qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
 870 }
 871
 872 #define SPITZ_GPIO_HSYNC                22
 873 #define SPITZ_GPIO_SD_DETECT            9
 874 #define SPITZ_GPIO_SD_WP                81
 875 #define SPITZ_GPIO_ON_RESET             89
 876 #define SPITZ_GPIO_BAT_COVER            90
 877 #define SPITZ_GPIO_CF1_IRQ              105
 878 #define SPITZ_GPIO_CF1_CD               94
 879 #define SPITZ_GPIO_CF2_IRQ              106
 880 #define SPITZ_GPIO_CF2_CD               93
 881
 882 static int spitz_hsync;
 883
 884 static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
 885 {
 886     PXA2xxState *cpu = (PXA2xxState *) opaque;
 887     qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_HSYNC], spitz_hsync);
 888     spitz_hsync ^= 1;
 889 }
 890
 891 static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
 892 {
 893     qemu_irq lcd_hsync;
 894     /*
 895      * Bad hack: We toggle the LCD hsync GPIO on every GPIO status
 896      * read to satisfy broken guests that poll-wait for hsync.
 897      * Simulating a real hsync event would be less practical and
 898      * wouldn't guarantee that a guest ever exits the loop.
 899      */
 900     spitz_hsync = 0;
 901     lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0];
 902     pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync);
 903     pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync);
 904
 905     /* MMC/SD host */
 906     pxa2xx_mmci_handlers(cpu->mmc,
 907                     pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_WP],
 908                     pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_DETECT]);
 909
 910     /* Battery lock always closed */
 911     qemu_irq_raise(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_BAT_COVER]);
 912
 913     /* Handle reset */
 914     pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset);
 915
 916     /* PCMCIA signals: card's IRQ and Card-Detect */
 917     if (slots >= 1)
 918         pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
 919                         pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_IRQ],
 920                         pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_CD]);
 921     if (slots >= 2)
 922         pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
 923                         pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_IRQ],
 924                         pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_CD]);
 925
 926     /* Initialise the screen rotation related signals */
 927     spitz_gpio_invert[3] = 0;   /* Always open */
 928     if (graphic_rotate) {       /* Tablet mode */
 929         spitz_gpio_invert[4] = 0;
 930     } else {                    /* Portrait mode */
 931         spitz_gpio_invert[4] = 1;
 932     }
 933     qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWA],
 934                     spitz_gpio_invert[3]);
 935     qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWB],
 936                     spitz_gpio_invert[4]);
 937 }
 938
 939 /* Board init.  */
 940 enum spitz_model_e { spitz, akita, borzoi, terrier };
 941
 942 #define SPITZ_RAM       0x04000000
 943 #define SPITZ_ROM       0x00800000
 944
 945 static struct arm_boot_info spitz_binfo = {
 946     .loader_start = PXA2XX_SDRAM_BASE,
 947     .ram_size = 0x04000000,
 948 };
 949
 950 static void spitz_common_init(ram_addr_t ram_size,
 951                 const char *kernel_filename,
 952                 const char *kernel_cmdline, const char *initrd_filename,
 953                 const char *cpu_model, enum spitz_model_e model, int arm_id)
 954 {
 955     PXA2xxState *cpu;
 956     DeviceState *scp0, *scp1 = NULL;
 957
 958     if (!cpu_model)
 959         cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
 960
 961     /* Setup CPU & memory */
 962     cpu = pxa270_init(spitz_binfo.ram_size, cpu_model);
 963
 964     sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
 965
 966     cpu_register_physical_memory(0, SPITZ_ROM,
 967                     qemu_ram_alloc(NULL, "spitz.rom", SPITZ_ROM) | IO_MEM_ROM);
 968
 969     /* Setup peripherals */
 970     spitz_keyboard_register(cpu);
 971
 972     spitz_ssp_attach(cpu);
 973
 974     scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
 975     if (model != akita) {
 976         scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
 977     }
 978
 979     spitz_scoop_gpio_setup(cpu, scp0, scp1);
 980
 981     spitz_gpio_setup(cpu, (model == akita) ? 1 : 2);
 982
 983     spitz_i2c_setup(cpu);
 984
 985     if (model == akita)
 986         spitz_akita_i2c_setup(cpu);
 987
 988     if (model == terrier)
 989         /* A 6.0 GB microdrive is permanently sitting in CF slot 1.  */
 990         spitz_microdrive_attach(cpu, 1);
 991     else if (model != akita)
 992         /* A 4.0 GB microdrive is permanently sitting in CF slot 0.  */
 993         spitz_microdrive_attach(cpu, 0);
 994
 995     spitz_binfo.kernel_filename = kernel_filename;
 996     spitz_binfo.kernel_cmdline = kernel_cmdline;
 997     spitz_binfo.initrd_filename = initrd_filename;
 998     spitz_binfo.board_id = arm_id;
 999     arm_load_kernel(cpu->env, &spitz_binfo);
1000     sl_bootparam_write(SL_PXA_PARAM_BASE);
1001 }
1002
1003 static void spitz_init(ram_addr_t ram_size,
1004                 const char *boot_device,
1005                 const char *kernel_filename, const char *kernel_cmdline,
1006                 const char *initrd_filename, const char *cpu_model)
1007 {
1008     spitz_common_init(ram_size, kernel_filename,
1009                 kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
1010 }
1011
1012 static void borzoi_init(ram_addr_t ram_size,
1013                 const char *boot_device,
1014                 const char *kernel_filename, const char *kernel_cmdline,
1015                 const char *initrd_filename, const char *cpu_model)
1016 {
1017     spitz_common_init(ram_size, kernel_filename,
1018                 kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
1019 }
1020
1021 static void akita_init(ram_addr_t ram_size,
1022                 const char *boot_device,
1023                 const char *kernel_filename, const char *kernel_cmdline,
1024                 const char *initrd_filename, const char *cpu_model)
1025 {
1026     spitz_common_init(ram_size, kernel_filename,
1027                 kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
1028 }
1029
1030 static void terrier_init(ram_addr_t ram_size,
1031                 const char *boot_device,
1032                 const char *kernel_filename, const char *kernel_cmdline,
1033                 const char *initrd_filename, const char *cpu_model)
1034 {
1035     spitz_common_init(ram_size, kernel_filename,
1036                 kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
1037 }
1038
1039 static QEMUMachine akitapda_machine = {
1040     .name = "akita",
1041     .desc = "Akita PDA (PXA270)",
1042     .init = akita_init,
1043 };
1044
1045 static QEMUMachine spitzpda_machine = {
1046     .name = "spitz",
1047     .desc = "Spitz PDA (PXA270)",
1048     .init = spitz_init,
1049 };
1050
1051 static QEMUMachine borzoipda_machine = {
1052     .name = "borzoi",
1053     .desc = "Borzoi PDA (PXA270)",
1054     .init = borzoi_init,
1055 };
1056
1057 static QEMUMachine terrierpda_machine = {
1058     .name = "terrier",
1059     .desc = "Terrier PDA (PXA270)",
1060     .init = terrier_init,
1061 };
1062
1063 static void spitz_machine_init(void)
1064 {
1065     qemu_register_machine(&akitapda_machine);
1066     qemu_register_machine(&spitzpda_machine);
1067     qemu_register_machine(&borzoipda_machine);
1068     qemu_register_machine(&terrierpda_machine);
1069 }
1070
1071 machine_init(spitz_machine_init);
1072
1073 static SSISlaveInfo corgi_ssp_info = {
1074     .qdev.name = "corgi-ssp",
1075     .qdev.size = sizeof(CorgiSSPState),
1076     .init = corgi_ssp_init,
1077     .transfer = corgi_ssp_transfer
1078 };
1079
1080 static SSISlaveInfo spitz_lcdtg_info = {
1081     .qdev.name = "spitz-lcdtg",
1082     .qdev.size = sizeof(SpitzLCDTG),
1083     .init = spitz_lcdtg_init,
1084     .transfer = spitz_lcdtg_transfer
1085 };
1086
1087 static void spitz_register_devices(void)
1088 {
1089     ssi_register_slave(&corgi_ssp_info);
1090     ssi_register_slave(&spitz_lcdtg_info);
1091 }
1092
1093 device_init(spitz_register_devices)