target-s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * Contributions after 2012-10-29 are licensed under the terms of the
  17  * GNU GPL, version 2 or (at your option) any later version.
  18  *
  19  * You should have received a copy of the GNU (Lesser) General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22 #ifndef CPU_S390X_H
  23 #define CPU_S390X_H
  24
  25 #include "config.h"
  26 #include "qemu-common.h"
  27
  28 #define TARGET_LONG_BITS 64
  29
  30 #define ELF_MACHINE     EM_S390
  31
  32 #define CPUArchState struct CPUS390XState
  33
  34 #include "exec/cpu-defs.h"
  35 #define TARGET_PAGE_BITS 12
  36
  37 #define TARGET_PHYS_ADDR_SPACE_BITS 64
  38 #define TARGET_VIRT_ADDR_SPACE_BITS 64
  39
  40 #include "exec/cpu-all.h"
  41
  42 #include "fpu/softfloat.h"
  43
  44 #define NB_MMU_MODES 3
  45
  46 #define MMU_MODE0_SUFFIX _primary
  47 #define MMU_MODE1_SUFFIX _secondary
  48 #define MMU_MODE2_SUFFIX _home
  49
  50 #define MMU_USER_IDX 1
  51
  52 #define MAX_EXT_QUEUE 16
  53
  54 typedef struct PSW {
  55     uint64_t mask;
  56     uint64_t addr;
  57 } PSW;
  58
  59 typedef struct ExtQueue {
  60     uint32_t code;
  61     uint32_t param;
  62     uint32_t param64;
  63 } ExtQueue;
  64
  65 typedef struct CPUS390XState {
  66     uint64_t regs[16];     /* GP registers */
  67     CPU_DoubleU fregs[16]; /* FP registers */
  68     uint32_t aregs[16];    /* access registers */
  69
  70     uint32_t fpc;          /* floating-point control register */
  71     uint32_t cc_op;
  72
  73     float_status fpu_status; /* passed to softfloat lib */
  74
  75     /* The low part of a 128-bit return, or remainder of a divide.  */
  76     uint64_t retxl;
  77
  78     PSW psw;
  79
  80     uint64_t cc_src;
  81     uint64_t cc_dst;
  82     uint64_t cc_vr;
  83
  84     uint64_t __excp_addr;
  85     uint64_t psa;
  86
  87     uint32_t int_pgm_code;
  88     uint32_t int_pgm_ilen;
  89
  90     uint32_t int_svc_code;
  91     uint32_t int_svc_ilen;
  92
  93     uint64_t cregs[16]; /* control registers */
  94
  95     ExtQueue ext_queue[MAX_EXT_QUEUE];
  96     int pending_int;
  97
  98     int ext_index;
  99
 100     CPU_COMMON
 101
 102     /* reset does memset(0) up to here */
 103
 104     int cpu_num;
 105     uint8_t *storage_keys;
 106
 107     uint64_t tod_offset;
 108     uint64_t tod_basetime;
 109     QEMUTimer *tod_timer;
 110
 111     QEMUTimer *cpu_timer;
 112 } CPUS390XState;
 113
 114 #include "cpu-qom.h"
 115
 116 #if defined(CONFIG_USER_ONLY)
 117 static inline void cpu_clone_regs(CPUS390XState *env, target_ulong newsp)
 118 {
 119     if (newsp) {
 120         env->regs[15] = newsp;
 121     }
 122     env->regs[2] = 0;
 123 }
 124 #endif
 125
 126 /* Interrupt Codes */
 127 /* Program Interrupts */
 128 #define PGM_OPERATION                   0x0001
 129 #define PGM_PRIVILEGED                  0x0002
 130 #define PGM_EXECUTE                     0x0003
 131 #define PGM_PROTECTION                  0x0004
 132 #define PGM_ADDRESSING                  0x0005
 133 #define PGM_SPECIFICATION               0x0006
 134 #define PGM_DATA                        0x0007
 135 #define PGM_FIXPT_OVERFLOW              0x0008
 136 #define PGM_FIXPT_DIVIDE                0x0009
 137 #define PGM_DEC_OVERFLOW                0x000a
 138 #define PGM_DEC_DIVIDE                  0x000b
 139 #define PGM_HFP_EXP_OVERFLOW            0x000c
 140 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 141 #define PGM_HFP_SIGNIFICANCE            0x000e
 142 #define PGM_HFP_DIVIDE                  0x000f
 143 #define PGM_SEGMENT_TRANS               0x0010
 144 #define PGM_PAGE_TRANS                  0x0011
 145 #define PGM_TRANS_SPEC                  0x0012
 146 #define PGM_SPECIAL_OP                  0x0013
 147 #define PGM_OPERAND                     0x0015
 148 #define PGM_TRACE_TABLE                 0x0016
 149 #define PGM_SPACE_SWITCH                0x001c
 150 #define PGM_HFP_SQRT                    0x001d
 151 #define PGM_PC_TRANS_SPEC               0x001f
 152 #define PGM_AFX_TRANS                   0x0020
 153 #define PGM_ASX_TRANS                   0x0021
 154 #define PGM_LX_TRANS                    0x0022
 155 #define PGM_EX_TRANS                    0x0023
 156 #define PGM_PRIM_AUTH                   0x0024
 157 #define PGM_SEC_AUTH                    0x0025
 158 #define PGM_ALET_SPEC                   0x0028
 159 #define PGM_ALEN_SPEC                   0x0029
 160 #define PGM_ALE_SEQ                     0x002a
 161 #define PGM_ASTE_VALID                  0x002b
 162 #define PGM_ASTE_SEQ                    0x002c
 163 #define PGM_EXT_AUTH                    0x002d
 164 #define PGM_STACK_FULL                  0x0030
 165 #define PGM_STACK_EMPTY                 0x0031
 166 #define PGM_STACK_SPEC                  0x0032
 167 #define PGM_STACK_TYPE                  0x0033
 168 #define PGM_STACK_OP                    0x0034
 169 #define PGM_ASCE_TYPE                   0x0038
 170 #define PGM_REG_FIRST_TRANS             0x0039
 171 #define PGM_REG_SEC_TRANS               0x003a
 172 #define PGM_REG_THIRD_TRANS             0x003b
 173 #define PGM_MONITOR                     0x0040
 174 #define PGM_PER                         0x0080
 175 #define PGM_CRYPTO                      0x0119
 176
 177 /* External Interrupts */
 178 #define EXT_INTERRUPT_KEY               0x0040
 179 #define EXT_CLOCK_COMP                  0x1004
 180 #define EXT_CPU_TIMER                   0x1005
 181 #define EXT_MALFUNCTION                 0x1200
 182 #define EXT_EMERGENCY                   0x1201
 183 #define EXT_EXTERNAL_CALL               0x1202
 184 #define EXT_ETR                         0x1406
 185 #define EXT_SERVICE                     0x2401
 186 #define EXT_VIRTIO                      0x2603
 187
 188 /* PSW defines */
 189 #undef PSW_MASK_PER
 190 #undef PSW_MASK_DAT
 191 #undef PSW_MASK_IO
 192 #undef PSW_MASK_EXT
 193 #undef PSW_MASK_KEY
 194 #undef PSW_SHIFT_KEY
 195 #undef PSW_MASK_MCHECK
 196 #undef PSW_MASK_WAIT
 197 #undef PSW_MASK_PSTATE
 198 #undef PSW_MASK_ASC
 199 #undef PSW_MASK_CC
 200 #undef PSW_MASK_PM
 201 #undef PSW_MASK_64
 202
 203 #define PSW_MASK_PER            0x4000000000000000ULL
 204 #define PSW_MASK_DAT            0x0400000000000000ULL
 205 #define PSW_MASK_IO             0x0200000000000000ULL
 206 #define PSW_MASK_EXT            0x0100000000000000ULL
 207 #define PSW_MASK_KEY            0x00F0000000000000ULL
 208 #define PSW_SHIFT_KEY           56
 209 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 210 #define PSW_MASK_WAIT           0x0002000000000000ULL
 211 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 212 #define PSW_MASK_ASC            0x0000C00000000000ULL
 213 #define PSW_MASK_CC             0x0000300000000000ULL
 214 #define PSW_MASK_PM             0x00000F0000000000ULL
 215 #define PSW_MASK_64             0x0000000100000000ULL
 216 #define PSW_MASK_32             0x0000000080000000ULL
 217
 218 #undef PSW_ASC_PRIMARY
 219 #undef PSW_ASC_ACCREG
 220 #undef PSW_ASC_SECONDARY
 221 #undef PSW_ASC_HOME
 222
 223 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 224 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 225 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 226 #define PSW_ASC_HOME            0x0000C00000000000ULL
 227
 228 /* tb flags */
 229
 230 #define FLAG_MASK_PER           (PSW_MASK_PER    >> 32)
 231 #define FLAG_MASK_DAT           (PSW_MASK_DAT    >> 32)
 232 #define FLAG_MASK_IO            (PSW_MASK_IO     >> 32)
 233 #define FLAG_MASK_EXT           (PSW_MASK_EXT    >> 32)
 234 #define FLAG_MASK_KEY           (PSW_MASK_KEY    >> 32)
 235 #define FLAG_MASK_MCHECK        (PSW_MASK_MCHECK >> 32)
 236 #define FLAG_MASK_WAIT          (PSW_MASK_WAIT   >> 32)
 237 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> 32)
 238 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> 32)
 239 #define FLAG_MASK_CC            (PSW_MASK_CC     >> 32)
 240 #define FLAG_MASK_PM            (PSW_MASK_PM     >> 32)
 241 #define FLAG_MASK_64            (PSW_MASK_64     >> 32)
 242 #define FLAG_MASK_32            0x00001000
 243
 244 static inline int cpu_mmu_index (CPUS390XState *env)
 245 {
 246     if (env->psw.mask & PSW_MASK_PSTATE) {
 247         return 1;
 248     }
 249
 250     return 0;
 251 }
 252
 253 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 254                                         target_ulong *cs_base, int *flags)
 255 {
 256     *pc = env->psw.addr;
 257     *cs_base = 0;
 258     *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
 259              ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
 260 }
 261
 262 /* While the PoO talks about ILC (a number between 1-3) what is actually
 263    stored in LowCore is shifted left one bit (an even between 2-6).  As
 264    this is the actual length of the insn and therefore more useful, that
 265    is what we want to pass around and manipulate.  To make sure that we
 266    have applied this distinction universally, rename the "ILC" to "ILEN".  */
 267 static inline int get_ilen(uint8_t opc)
 268 {
 269     switch (opc >> 6) {
 270     case 0:
 271         return 2;
 272     case 1:
 273     case 2:
 274         return 4;
 275     default:
 276         return 6;
 277     }
 278 }
 279
 280 #ifndef CONFIG_USER_ONLY
 281 /* In several cases of runtime exceptions, we havn't recorded the true
 282    instruction length.  Use these codes when raising exceptions in order
 283    to re-compute the length by examining the insn in memory.  */
 284 #define ILEN_LATER       0x20
 285 #define ILEN_LATER_INC   0x21
 286 #endif
 287
 288 S390CPU *cpu_s390x_init(const char *cpu_model);
 289 void s390x_translate_init(void);
 290 int cpu_s390x_exec(CPUS390XState *s);
 291 void cpu_s390x_close(CPUS390XState *s);
 292 void do_interrupt (CPUS390XState *env);
 293
 294 /* you can call this signal handler from your SIGBUS and SIGSEGV
 295    signal handlers to inform the virtual CPU of exceptions. non zero
 296    is returned if the signal was handled by the virtual CPU.  */
 297 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
 298                            void *puc);
 299 int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
 300                                 int mmu_idx);
 301 #define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault
 302
 303
 304 #ifndef CONFIG_USER_ONLY
 305 void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
 306                                    int is_write);
 307 void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
 308                                     int is_write);
 309 void s390x_tod_timer(void *opaque);
 310 void s390x_cpu_timer(void *opaque);
 311
 312 int s390_virtio_hypercall(CPUS390XState *env);
 313
 314 #ifdef CONFIG_KVM
 315 void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code);
 316 void kvm_s390_virtio_irq(S390CPU *cpu, int config_change, uint64_t token);
 317 void kvm_s390_interrupt_internal(S390CPU *cpu, int type, uint32_t parm,
 318                                  uint64_t parm64, int vm);
 319 #else
 320 static inline void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code)
 321 {
 322 }
 323
 324 static inline void kvm_s390_virtio_irq(S390CPU *cpu, int config_change,
 325                                        uint64_t token)
 326 {
 327 }
 328
 329 static inline void kvm_s390_interrupt_internal(S390CPU *cpu, int type,
 330                                                uint32_t parm, uint64_t parm64,
 331                                                int vm)
 332 {
 333 }
 334 #endif
 335 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 336 void s390_add_running_cpu(CPUS390XState *env);
 337 unsigned s390_del_running_cpu(CPUS390XState *env);
 338
 339 /* service interrupts are floating therefore we must not pass an cpustate */
 340 void s390_sclp_extint(uint32_t parm);
 341
 342 /* from s390-virtio-bus */
 343 extern const hwaddr virtio_size;
 344
 345 #else
 346 static inline void s390_add_running_cpu(CPUS390XState *env)
 347 {
 348 }
 349
 350 static inline unsigned s390_del_running_cpu(CPUS390XState *env)
 351 {
 352     return 0;
 353 }
 354 #endif
 355 void cpu_lock(void);
 356 void cpu_unlock(void);
 357
 358 static inline void cpu_set_tls(CPUS390XState *env, target_ulong newtls)
 359 {
 360     env->aregs[0] = newtls >> 32;
 361     env->aregs[1] = newtls & 0xffffffffULL;
 362 }
 363
 364 #define cpu_init(model) (&cpu_s390x_init(model)->env)
 365 #define cpu_exec cpu_s390x_exec
 366 #define cpu_gen_code cpu_s390x_gen_code
 367 #define cpu_signal_handler cpu_s390x_signal_handler
 368
 369 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 370 #define cpu_list s390_cpu_list
 371
 372 #include "exec/exec-all.h"
 373
 374 #define EXCP_EXT 1 /* external interrupt */
 375 #define EXCP_SVC 2 /* supervisor call (syscall) */
 376 #define EXCP_PGM 3 /* program interruption */
 377
 378 #define INTERRUPT_EXT        (1 << 0)
 379 #define INTERRUPT_TOD        (1 << 1)
 380 #define INTERRUPT_CPUTIMER   (1 << 2)
 381
 382 /* Program Status Word.  */
 383 #define S390_PSWM_REGNUM 0
 384 #define S390_PSWA_REGNUM 1
 385 /* General Purpose Registers.  */
 386 #define S390_R0_REGNUM 2
 387 #define S390_R1_REGNUM 3
 388 #define S390_R2_REGNUM 4
 389 #define S390_R3_REGNUM 5
 390 #define S390_R4_REGNUM 6
 391 #define S390_R5_REGNUM 7
 392 #define S390_R6_REGNUM 8
 393 #define S390_R7_REGNUM 9
 394 #define S390_R8_REGNUM 10
 395 #define S390_R9_REGNUM 11
 396 #define S390_R10_REGNUM 12
 397 #define S390_R11_REGNUM 13
 398 #define S390_R12_REGNUM 14
 399 #define S390_R13_REGNUM 15
 400 #define S390_R14_REGNUM 16
 401 #define S390_R15_REGNUM 17
 402 /* Access Registers.  */
 403 #define S390_A0_REGNUM 18
 404 #define S390_A1_REGNUM 19
 405 #define S390_A2_REGNUM 20
 406 #define S390_A3_REGNUM 21
 407 #define S390_A4_REGNUM 22
 408 #define S390_A5_REGNUM 23
 409 #define S390_A6_REGNUM 24
 410 #define S390_A7_REGNUM 25
 411 #define S390_A8_REGNUM 26
 412 #define S390_A9_REGNUM 27
 413 #define S390_A10_REGNUM 28
 414 #define S390_A11_REGNUM 29
 415 #define S390_A12_REGNUM 30
 416 #define S390_A13_REGNUM 31
 417 #define S390_A14_REGNUM 32
 418 #define S390_A15_REGNUM 33
 419 /* Floating Point Control Word.  */
 420 #define S390_FPC_REGNUM 34
 421 /* Floating Point Registers.  */
 422 #define S390_F0_REGNUM 35
 423 #define S390_F1_REGNUM 36
 424 #define S390_F2_REGNUM 37
 425 #define S390_F3_REGNUM 38
 426 #define S390_F4_REGNUM 39
 427 #define S390_F5_REGNUM 40
 428 #define S390_F6_REGNUM 41
 429 #define S390_F7_REGNUM 42
 430 #define S390_F8_REGNUM 43
 431 #define S390_F9_REGNUM 44
 432 #define S390_F10_REGNUM 45
 433 #define S390_F11_REGNUM 46
 434 #define S390_F12_REGNUM 47
 435 #define S390_F13_REGNUM 48
 436 #define S390_F14_REGNUM 49
 437 #define S390_F15_REGNUM 50
 438 /* Total.  */
 439 #define S390_NUM_REGS 51
 440
 441 /* CC optimization */
 442
 443 enum cc_op {
 444     CC_OP_CONST0 = 0,           /* CC is 0 */
 445     CC_OP_CONST1,               /* CC is 1 */
 446     CC_OP_CONST2,               /* CC is 2 */
 447     CC_OP_CONST3,               /* CC is 3 */
 448
 449     CC_OP_DYNAMIC,              /* CC calculation defined by env->cc_op */
 450     CC_OP_STATIC,               /* CC value is env->cc_op */
 451
 452     CC_OP_NZ,                   /* env->cc_dst != 0 */
 453     CC_OP_LTGT_32,              /* signed less/greater than (32bit) */
 454     CC_OP_LTGT_64,              /* signed less/greater than (64bit) */
 455     CC_OP_LTUGTU_32,            /* unsigned less/greater than (32bit) */
 456     CC_OP_LTUGTU_64,            /* unsigned less/greater than (64bit) */
 457     CC_OP_LTGT0_32,             /* signed less/greater than 0 (32bit) */
 458     CC_OP_LTGT0_64,             /* signed less/greater than 0 (64bit) */
 459
 460     CC_OP_ADD_64,               /* overflow on add (64bit) */
 461     CC_OP_ADDU_64,              /* overflow on unsigned add (64bit) */
 462     CC_OP_ADDC_64,              /* overflow on unsigned add-carry (64bit) */
 463     CC_OP_SUB_64,               /* overflow on subtraction (64bit) */
 464     CC_OP_SUBU_64,              /* overflow on unsigned subtraction (64bit) */
 465     CC_OP_SUBB_64,              /* overflow on unsigned sub-borrow (64bit) */
 466     CC_OP_ABS_64,               /* sign eval on abs (64bit) */
 467     CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
 468
 469     CC_OP_ADD_32,               /* overflow on add (32bit) */
 470     CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
 471     CC_OP_ADDC_32,              /* overflow on unsigned add-carry (32bit) */
 472     CC_OP_SUB_32,               /* overflow on subtraction (32bit) */
 473     CC_OP_SUBU_32,              /* overflow on unsigned subtraction (32bit) */
 474     CC_OP_SUBB_32,              /* overflow on unsigned sub-borrow (32bit) */
 475     CC_OP_ABS_32,               /* sign eval on abs (64bit) */
 476     CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
 477
 478     CC_OP_COMP_32,              /* complement */
 479     CC_OP_COMP_64,              /* complement */
 480
 481     CC_OP_TM_32,                /* test under mask (32bit) */
 482     CC_OP_TM_64,                /* test under mask (64bit) */
 483
 484     CC_OP_NZ_F32,               /* FP dst != 0 (32bit) */
 485     CC_OP_NZ_F64,               /* FP dst != 0 (64bit) */
 486     CC_OP_NZ_F128,              /* FP dst != 0 (128bit) */
 487
 488     CC_OP_ICM,                  /* insert characters under mask */
 489     CC_OP_SLA_32,               /* Calculate shift left signed (32bit) */
 490     CC_OP_SLA_64,               /* Calculate shift left signed (64bit) */
 491     CC_OP_FLOGR,                /* find leftmost one */
 492     CC_OP_MAX
 493 };
 494
 495 static const char *cc_names[] = {
 496     [CC_OP_CONST0]    = "CC_OP_CONST0",
 497     [CC_OP_CONST1]    = "CC_OP_CONST1",
 498     [CC_OP_CONST2]    = "CC_OP_CONST2",
 499     [CC_OP_CONST3]    = "CC_OP_CONST3",
 500     [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 501     [CC_OP_STATIC]    = "CC_OP_STATIC",
 502     [CC_OP_NZ]        = "CC_OP_NZ",
 503     [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 504     [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 505     [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
 506     [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
 507     [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 508     [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 509     [CC_OP_ADD_64]    = "CC_OP_ADD_64",
 510     [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
 511     [CC_OP_ADDC_64]   = "CC_OP_ADDC_64",
 512     [CC_OP_SUB_64]    = "CC_OP_SUB_64",
 513     [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 514     [CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 515     [CC_OP_ABS_64]    = "CC_OP_ABS_64",
 516     [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 517     [CC_OP_ADD_32]    = "CC_OP_ADD_32",
 518     [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
 519     [CC_OP_ADDC_32]   = "CC_OP_ADDC_32",
 520     [CC_OP_SUB_32]    = "CC_OP_SUB_32",
 521     [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 522     [CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
 523     [CC_OP_ABS_32]    = "CC_OP_ABS_32",
 524     [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 525     [CC_OP_COMP_32]   = "CC_OP_COMP_32",
 526     [CC_OP_COMP_64]   = "CC_OP_COMP_64",
 527     [CC_OP_TM_32]     = "CC_OP_TM_32",
 528     [CC_OP_TM_64]     = "CC_OP_TM_64",
 529     [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
 530     [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
 531     [CC_OP_NZ_F128]   = "CC_OP_NZ_F128",
 532     [CC_OP_ICM]       = "CC_OP_ICM",
 533     [CC_OP_SLA_32]    = "CC_OP_SLA_32",
 534     [CC_OP_SLA_64]    = "CC_OP_SLA_64",
 535     [CC_OP_FLOGR]     = "CC_OP_FLOGR",
 536 };
 537
 538 static inline const char *cc_name(int cc_op)
 539 {
 540     return cc_names[cc_op];
 541 }
 542
 543 typedef struct LowCore
 544 {
 545     /* prefix area: defined by architecture */
 546     uint32_t        ccw1[2];                  /* 0x000 */
 547     uint32_t        ccw2[4];                  /* 0x008 */
 548     uint8_t         pad1[0x80-0x18];          /* 0x018 */
 549     uint32_t        ext_params;               /* 0x080 */
 550     uint16_t        cpu_addr;                 /* 0x084 */
 551     uint16_t        ext_int_code;             /* 0x086 */
 552     uint16_t        svc_ilen;                 /* 0x088 */
 553     uint16_t        svc_code;                 /* 0x08a */
 554     uint16_t        pgm_ilen;                 /* 0x08c */
 555     uint16_t        pgm_code;                 /* 0x08e */
 556     uint32_t        data_exc_code;            /* 0x090 */
 557     uint16_t        mon_class_num;            /* 0x094 */
 558     uint16_t        per_perc_atmid;           /* 0x096 */
 559     uint64_t        per_address;              /* 0x098 */
 560     uint8_t         exc_access_id;            /* 0x0a0 */
 561     uint8_t         per_access_id;            /* 0x0a1 */
 562     uint8_t         op_access_id;             /* 0x0a2 */
 563     uint8_t         ar_access_id;             /* 0x0a3 */
 564     uint8_t         pad2[0xA8-0xA4];          /* 0x0a4 */
 565     uint64_t        trans_exc_code;           /* 0x0a8 */
 566     uint64_t        monitor_code;             /* 0x0b0 */
 567     uint16_t        subchannel_id;            /* 0x0b8 */
 568     uint16_t        subchannel_nr;            /* 0x0ba */
 569     uint32_t        io_int_parm;              /* 0x0bc */
 570     uint32_t        io_int_word;              /* 0x0c0 */
 571     uint8_t         pad3[0xc8-0xc4];          /* 0x0c4 */
 572     uint32_t        stfl_fac_list;            /* 0x0c8 */
 573     uint8_t         pad4[0xe8-0xcc];          /* 0x0cc */
 574     uint32_t        mcck_interruption_code[2]; /* 0x0e8 */
 575     uint8_t         pad5[0xf4-0xf0];          /* 0x0f0 */
 576     uint32_t        external_damage_code;     /* 0x0f4 */
 577     uint64_t        failing_storage_address;  /* 0x0f8 */
 578     uint8_t         pad6[0x120-0x100];        /* 0x100 */
 579     PSW             restart_old_psw;          /* 0x120 */
 580     PSW             external_old_psw;         /* 0x130 */
 581     PSW             svc_old_psw;              /* 0x140 */
 582     PSW             program_old_psw;          /* 0x150 */
 583     PSW             mcck_old_psw;             /* 0x160 */
 584     PSW             io_old_psw;               /* 0x170 */
 585     uint8_t         pad7[0x1a0-0x180];        /* 0x180 */
 586     PSW             restart_psw;              /* 0x1a0 */
 587     PSW             external_new_psw;         /* 0x1b0 */
 588     PSW             svc_new_psw;              /* 0x1c0 */
 589     PSW             program_new_psw;          /* 0x1d0 */
 590     PSW             mcck_new_psw;             /* 0x1e0 */
 591     PSW             io_new_psw;               /* 0x1f0 */
 592     PSW             return_psw;               /* 0x200 */
 593     uint8_t         irb[64];                  /* 0x210 */
 594     uint64_t        sync_enter_timer;         /* 0x250 */
 595     uint64_t        async_enter_timer;        /* 0x258 */
 596     uint64_t        exit_timer;               /* 0x260 */
 597     uint64_t        last_update_timer;        /* 0x268 */
 598     uint64_t        user_timer;               /* 0x270 */
 599     uint64_t        system_timer;             /* 0x278 */
 600     uint64_t        last_update_clock;        /* 0x280 */
 601     uint64_t        steal_clock;              /* 0x288 */
 602     PSW             return_mcck_psw;          /* 0x290 */
 603     uint8_t         pad8[0xc00-0x2a0];        /* 0x2a0 */
 604     /* System info area */
 605     uint64_t        save_area[16];            /* 0xc00 */
 606     uint8_t         pad9[0xd40-0xc80];        /* 0xc80 */
 607     uint64_t        kernel_stack;             /* 0xd40 */
 608     uint64_t        thread_info;              /* 0xd48 */
 609     uint64_t        async_stack;              /* 0xd50 */
 610     uint64_t        kernel_asce;              /* 0xd58 */
 611     uint64_t        user_asce;                /* 0xd60 */
 612     uint64_t        panic_stack;              /* 0xd68 */
 613     uint64_t        user_exec_asce;           /* 0xd70 */
 614     uint8_t         pad10[0xdc0-0xd78];       /* 0xd78 */
 615
 616     /* SMP info area: defined by DJB */
 617     uint64_t        clock_comparator;         /* 0xdc0 */
 618     uint64_t        ext_call_fast;            /* 0xdc8 */
 619     uint64_t        percpu_offset;            /* 0xdd0 */
 620     uint64_t        current_task;             /* 0xdd8 */
 621     uint32_t        softirq_pending;          /* 0xde0 */
 622     uint32_t        pad_0x0de4;               /* 0xde4 */
 623     uint64_t        int_clock;                /* 0xde8 */
 624     uint8_t         pad12[0xe00-0xdf0];       /* 0xdf0 */
 625
 626     /* 0xe00 is used as indicator for dump tools */
 627     /* whether the kernel died with panic() or not */
 628     uint32_t        panic_magic;              /* 0xe00 */
 629
 630     uint8_t         pad13[0x11b8-0xe04];      /* 0xe04 */
 631
 632     /* 64 bit extparam used for pfault, diag 250 etc  */
 633     uint64_t        ext_params2;               /* 0x11B8 */
 634
 635     uint8_t         pad14[0x1200-0x11C0];      /* 0x11C0 */
 636
 637     /* System info area */
 638
 639     uint64_t        floating_pt_save_area[16]; /* 0x1200 */
 640     uint64_t        gpregs_save_area[16];      /* 0x1280 */
 641     uint32_t        st_status_fixed_logout[4]; /* 0x1300 */
 642     uint8_t         pad15[0x1318-0x1310];      /* 0x1310 */
 643     uint32_t        prefixreg_save_area;       /* 0x1318 */
 644     uint32_t        fpt_creg_save_area;        /* 0x131c */
 645     uint8_t         pad16[0x1324-0x1320];      /* 0x1320 */
 646     uint32_t        tod_progreg_save_area;     /* 0x1324 */
 647     uint32_t        cpu_timer_save_area[2];    /* 0x1328 */
 648     uint32_t        clock_comp_save_area[2];   /* 0x1330 */
 649     uint8_t         pad17[0x1340-0x1338];      /* 0x1338 */
 650     uint32_t        access_regs_save_area[16]; /* 0x1340 */
 651     uint64_t        cregs_save_area[16];       /* 0x1380 */
 652
 653     /* align to the top of the prefix area */
 654
 655     uint8_t         pad18[0x2000-0x1400];      /* 0x1400 */
 656 } QEMU_PACKED LowCore;
 657
 658 /* STSI */
 659 #define STSI_LEVEL_MASK         0x00000000f0000000ULL
 660 #define STSI_LEVEL_CURRENT      0x0000000000000000ULL
 661 #define STSI_LEVEL_1            0x0000000010000000ULL
 662 #define STSI_LEVEL_2            0x0000000020000000ULL
 663 #define STSI_LEVEL_3            0x0000000030000000ULL
 664 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 665 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 666 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 667 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 668
 669 /* Basic Machine Configuration */
 670 struct sysib_111 {
 671     uint32_t res1[8];
 672     uint8_t  manuf[16];
 673     uint8_t  type[4];
 674     uint8_t  res2[12];
 675     uint8_t  model[16];
 676     uint8_t  sequence[16];
 677     uint8_t  plant[4];
 678     uint8_t  res3[156];
 679 };
 680
 681 /* Basic Machine CPU */
 682 struct sysib_121 {
 683     uint32_t res1[80];
 684     uint8_t  sequence[16];
 685     uint8_t  plant[4];
 686     uint8_t  res2[2];
 687     uint16_t cpu_addr;
 688     uint8_t  res3[152];
 689 };
 690
 691 /* Basic Machine CPUs */
 692 struct sysib_122 {
 693     uint8_t res1[32];
 694     uint32_t capability;
 695     uint16_t total_cpus;
 696     uint16_t active_cpus;
 697     uint16_t standby_cpus;
 698     uint16_t reserved_cpus;
 699     uint16_t adjustments[2026];
 700 };
 701
 702 /* LPAR CPU */
 703 struct sysib_221 {
 704     uint32_t res1[80];
 705     uint8_t  sequence[16];
 706     uint8_t  plant[4];
 707     uint16_t cpu_id;
 708     uint16_t cpu_addr;
 709     uint8_t  res3[152];
 710 };
 711
 712 /* LPAR CPUs */
 713 struct sysib_222 {
 714     uint32_t res1[32];
 715     uint16_t lpar_num;
 716     uint8_t  res2;
 717     uint8_t  lcpuc;
 718     uint16_t total_cpus;
 719     uint16_t conf_cpus;
 720     uint16_t standby_cpus;
 721     uint16_t reserved_cpus;
 722     uint8_t  name[8];
 723     uint32_t caf;
 724     uint8_t  res3[16];
 725     uint16_t dedicated_cpus;
 726     uint16_t shared_cpus;
 727     uint8_t  res4[180];
 728 };
 729
 730 /* VM CPUs */
 731 struct sysib_322 {
 732     uint8_t  res1[31];
 733     uint8_t  count;
 734     struct {
 735         uint8_t  res2[4];
 736         uint16_t total_cpus;
 737         uint16_t conf_cpus;
 738         uint16_t standby_cpus;
 739         uint16_t reserved_cpus;
 740         uint8_t  name[8];
 741         uint32_t caf;
 742         uint8_t  cpi[16];
 743         uint8_t  res3[24];
 744     } vm[8];
 745     uint8_t res4[3552];
 746 };
 747
 748 /* MMU defines */
 749 #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
 750 #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
 751 #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
 752 #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
 753 #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
 754 #define _ASCE_REAL_SPACE        0x20      /* real space control               */
 755 #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
 756 #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
 757 #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
 758 #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
 759 #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
 760 #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
 761
 762 #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
 763 #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
 764 #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
 765 #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
 766 #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
 767 #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
 768 #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
 769
 770 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
 771 #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
 772 #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
 773
 774 #define _PAGE_RO        0x200            /* HW read-only bit  */
 775 #define _PAGE_INVALID   0x400            /* HW invalid bit    */
 776
 777 #define SK_C                    (0x1 << 1)
 778 #define SK_R                    (0x1 << 2)
 779 #define SK_F                    (0x1 << 3)
 780 #define SK_ACC_MASK             (0xf << 4)
 781
 782 #define SIGP_SENSE             0x01
 783 #define SIGP_EXTERNAL_CALL     0x02
 784 #define SIGP_EMERGENCY         0x03
 785 #define SIGP_START             0x04
 786 #define SIGP_STOP              0x05
 787 #define SIGP_RESTART           0x06
 788 #define SIGP_STOP_STORE_STATUS 0x09
 789 #define SIGP_INITIAL_CPU_RESET 0x0b
 790 #define SIGP_CPU_RESET         0x0c
 791 #define SIGP_SET_PREFIX        0x0d
 792 #define SIGP_STORE_STATUS_ADDR 0x0e
 793 #define SIGP_SET_ARCH          0x12
 794
 795 /* cpu status bits */
 796 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
 797 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
 798 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
 799 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
 800 #define SIGP_STAT_STOPPED           0x00000040UL
 801 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
 802 #define SIGP_STAT_CHECK_STOP        0x00000010UL
 803 #define SIGP_STAT_INOPERATIVE       0x00000004UL
 804 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
 805 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
 806
 807 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
 808 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 809                   target_ulong *raddr, int *flags);
 810 int sclp_service_call(uint32_t sccb, uint64_t code);
 811 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
 812                  uint64_t vr);
 813
 814 #define TARGET_HAS_ICE 1
 815
 816 /* The value of the TOD clock for 1.1.1970. */
 817 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
 818
 819 /* Converts ns to s390's clock format */
 820 static inline uint64_t time2tod(uint64_t ns) {
 821     return (ns << 9) / 125;
 822 }
 823
 824 static inline void cpu_inject_ext(CPUS390XState *env, uint32_t code, uint32_t param,
 825                                   uint64_t param64)
 826 {
 827     if (env->ext_index == MAX_EXT_QUEUE - 1) {
 828         /* ugh - can't queue anymore. Let's drop. */
 829         return;
 830     }
 831
 832     env->ext_index++;
 833     assert(env->ext_index < MAX_EXT_QUEUE);
 834
 835     env->ext_queue[env->ext_index].code = code;
 836     env->ext_queue[env->ext_index].param = param;
 837     env->ext_queue[env->ext_index].param64 = param64;
 838
 839     env->pending_int |= INTERRUPT_EXT;
 840     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 841 }
 842
 843 static inline bool cpu_has_work(CPUState *cpu)
 844 {
 845     CPUS390XState *env = &S390_CPU(cpu)->env;
 846
 847     return (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 848         (env->psw.mask & PSW_MASK_EXT);
 849 }
 850
 851 static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* tb)
 852 {
 853     env->psw.addr = tb->pc;
 854 }
 855
 856 /* fpu_helper.c */
 857 uint32_t set_cc_nz_f32(float32 v);
 858 uint32_t set_cc_nz_f64(float64 v);
 859 uint32_t set_cc_nz_f128(float128 v);
 860
 861 /* misc_helper.c */
 862 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
 863 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
 864                                      uintptr_t retaddr);
 865
 866 #endif