hw/riscv/sifive_plic.c

   1 /*
   2  * SiFive PLIC (Platform Level Interrupt Controller)
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * This provides a parameterizable interrupt controller based on SiFive's PLIC.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/log.h"
  23 #include "qemu/module.h"
  24 #include "qemu/error-report.h"
  25 #include "hw/sysbus.h"
  26 #include "hw/pci/msi.h"
  27 #include "hw/boards.h"
  28 #include "target/riscv/cpu.h"
  29 #include "sysemu/sysemu.h"
  30 #include "hw/riscv/sifive_plic.h"
  31
  32 #define RISCV_DEBUG_PLIC 0
  33
  34 static PLICMode char_to_mode(char c)
  35 {
  36     switch (c) {
  37     case 'U': return PLICMode_U;
  38     case 'S': return PLICMode_S;
  39     case 'H': return PLICMode_H;
  40     case 'M': return PLICMode_M;
  41     default:
  42         error_report("plic: invalid mode '%c'", c);
  43         exit(1);
  44     }
  45 }
  46
  47 static char mode_to_char(PLICMode m)
  48 {
  49     switch (m) {
  50     case PLICMode_U: return 'U';
  51     case PLICMode_S: return 'S';
  52     case PLICMode_H: return 'H';
  53     case PLICMode_M: return 'M';
  54     default: return '?';
  55     }
  56 }
  57
  58 static void sifive_plic_print_state(SiFivePLICState *plic)
  59 {
  60     int i;
  61     int addrid;
  62
  63     /* pending */
  64     qemu_log("pending       : ");
  65     for (i = plic->bitfield_words - 1; i >= 0; i--) {
  66         qemu_log("%08x", plic->pending[i]);
  67     }
  68     qemu_log("\n");
  69
  70     /* pending */
  71     qemu_log("claimed       : ");
  72     for (i = plic->bitfield_words - 1; i >= 0; i--) {
  73         qemu_log("%08x", plic->claimed[i]);
  74     }
  75     qemu_log("\n");
  76
  77     for (addrid = 0; addrid < plic->num_addrs; addrid++) {
  78         qemu_log("hart%d-%c enable: ",
  79             plic->addr_config[addrid].hartid,
  80             mode_to_char(plic->addr_config[addrid].mode));
  81         for (i = plic->bitfield_words - 1; i >= 0; i--) {
  82             qemu_log("%08x", plic->enable[addrid * plic->bitfield_words + i]);
  83         }
  84         qemu_log("\n");
  85     }
  86 }
  87
  88 static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t value)
  89 {
  90     uint32_t old, new, cmp = atomic_read(a);
  91
  92     do {
  93         old = cmp;
  94         new = (old & ~mask) | (value & mask);
  95         cmp = atomic_cmpxchg(a, old, new);
  96     } while (old != cmp);
  97
  98     return old;
  99 }
 100
 101 static void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool level)
 102 {
 103     atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -!!level);
 104 }
 105
 106 static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level)
 107 {
 108     atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level);
 109 }
 110
 111 static int sifive_plic_irqs_pending(SiFivePLICState *plic, uint32_t addrid)
 112 {
 113     int i, j;
 114     for (i = 0; i < plic->bitfield_words; i++) {
 115         uint32_t pending_enabled_not_claimed =
 116             (plic->pending[i] & ~plic->claimed[i]) &
 117             plic->enable[addrid * plic->bitfield_words + i];
 118         if (!pending_enabled_not_claimed) {
 119             continue;
 120         }
 121         for (j = 0; j < 32; j++) {
 122             int irq = (i << 5) + j;
 123             uint32_t prio = plic->source_priority[irq];
 124             int enabled = pending_enabled_not_claimed & (1 << j);
 125             if (enabled && prio > plic->target_priority[addrid]) {
 126                 return 1;
 127             }
 128         }
 129     }
 130     return 0;
 131 }
 132
 133 static void sifive_plic_update(SiFivePLICState *plic)
 134 {
 135     int addrid;
 136
 137     /* raise irq on harts where this irq is enabled */
 138     for (addrid = 0; addrid < plic->num_addrs; addrid++) {
 139         uint32_t hartid = plic->addr_config[addrid].hartid;
 140         PLICMode mode = plic->addr_config[addrid].mode;
 141         CPUState *cpu = qemu_get_cpu(hartid);
 142         CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
 143         if (!env) {
 144             continue;
 145         }
 146         int level = sifive_plic_irqs_pending(plic, addrid);
 147         switch (mode) {
 148         case PLICMode_M:
 149             riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
 150             break;
 151         case PLICMode_S:
 152             riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
 153             break;
 154         default:
 155             break;
 156         }
 157     }
 158
 159     if (RISCV_DEBUG_PLIC) {
 160         sifive_plic_print_state(plic);
 161     }
 162 }
 163
 164 void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq)
 165 {
 166     sifive_plic_set_pending(plic, irq, true);
 167     sifive_plic_update(plic);
 168 }
 169
 170 void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq)
 171 {
 172     sifive_plic_set_pending(plic, irq, false);
 173     sifive_plic_update(plic);
 174 }
 175
 176 static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
 177 {
 178     int i, j;
 179     for (i = 0; i < plic->bitfield_words; i++) {
 180         uint32_t pending_enabled_not_claimed =
 181             (plic->pending[i] & ~plic->claimed[i]) &
 182             plic->enable[addrid * plic->bitfield_words + i];
 183         if (!pending_enabled_not_claimed) {
 184             continue;
 185         }
 186         for (j = 0; j < 32; j++) {
 187             int irq = (i << 5) + j;
 188             uint32_t prio = plic->source_priority[irq];
 189             int enabled = pending_enabled_not_claimed & (1 << j);
 190             if (enabled && prio > plic->target_priority[addrid]) {
 191                 sifive_plic_set_pending(plic, irq, false);
 192                 sifive_plic_set_claimed(plic, irq, true);
 193                 return irq;
 194             }
 195         }
 196     }
 197     return 0;
 198 }
 199
 200 static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
 201 {
 202     SiFivePLICState *plic = opaque;
 203
 204     /* writes must be 4 byte words */
 205     if ((addr & 0x3) != 0) {
 206         goto err;
 207     }
 208
 209     if (addr >= plic->priority_base && /* 4 bytes per source */
 210         addr < plic->priority_base + (plic->num_sources << 2))
 211     {
 212         uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
 213         if (RISCV_DEBUG_PLIC) {
 214             qemu_log("plic: read priority: irq=%d priority=%d\n",
 215                 irq, plic->source_priority[irq]);
 216         }
 217         return plic->source_priority[irq];
 218     } else if (addr >= plic->pending_base && /* 1 bit per source */
 219                addr < plic->pending_base + (plic->num_sources >> 3))
 220     {
 221         uint32_t word = (addr - plic->pending_base) >> 2;
 222         if (RISCV_DEBUG_PLIC) {
 223             qemu_log("plic: read pending: word=%d value=%d\n",
 224                 word, plic->pending[word]);
 225         }
 226         return plic->pending[word];
 227     } else if (addr >= plic->enable_base && /* 1 bit per source */
 228              addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
 229     {
 230         uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
 231         uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
 232         if (wordid < plic->bitfield_words) {
 233             if (RISCV_DEBUG_PLIC) {
 234                 qemu_log("plic: read enable: hart%d-%c word=%d value=%x\n",
 235                     plic->addr_config[addrid].hartid,
 236                     mode_to_char(plic->addr_config[addrid].mode), wordid,
 237                     plic->enable[addrid * plic->bitfield_words + wordid]);
 238             }
 239             return plic->enable[addrid * plic->bitfield_words + wordid];
 240         }
 241     } else if (addr >= plic->context_base && /* 1 bit per source */
 242              addr < plic->context_base + plic->num_addrs * plic->context_stride)
 243     {
 244         uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
 245         uint32_t contextid = (addr & (plic->context_stride - 1));
 246         if (contextid == 0) {
 247             if (RISCV_DEBUG_PLIC) {
 248                 qemu_log("plic: read priority: hart%d-%c priority=%x\n",
 249                     plic->addr_config[addrid].hartid,
 250                     mode_to_char(plic->addr_config[addrid].mode),
 251                     plic->target_priority[addrid]);
 252             }
 253             return plic->target_priority[addrid];
 254         } else if (contextid == 4) {
 255             uint32_t value = sifive_plic_claim(plic, addrid);
 256             if (RISCV_DEBUG_PLIC) {
 257                 qemu_log("plic: read claim: hart%d-%c irq=%x\n",
 258                     plic->addr_config[addrid].hartid,
 259                     mode_to_char(plic->addr_config[addrid].mode),
 260                     value);
 261                 sifive_plic_print_state(plic);
 262             }
 263             return value;
 264         }
 265     }
 266
 267 err:
 268     qemu_log_mask(LOG_GUEST_ERROR,
 269                   "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
 270                   __func__, addr);
 271     return 0;
 272 }
 273
 274 static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
 275         unsigned size)
 276 {
 277     SiFivePLICState *plic = opaque;
 278
 279     /* writes must be 4 byte words */
 280     if ((addr & 0x3) != 0) {
 281         goto err;
 282     }
 283
 284     if (addr >= plic->priority_base && /* 4 bytes per source */
 285         addr < plic->priority_base + (plic->num_sources << 2))
 286     {
 287         uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
 288         plic->source_priority[irq] = value & 7;
 289         if (RISCV_DEBUG_PLIC) {
 290             qemu_log("plic: write priority: irq=%d priority=%d\n",
 291                 irq, plic->source_priority[irq]);
 292         }
 293         return;
 294     } else if (addr >= plic->pending_base && /* 1 bit per source */
 295                addr < plic->pending_base + (plic->num_sources >> 3))
 296     {
 297         qemu_log_mask(LOG_GUEST_ERROR,
 298                       "%s: invalid pending write: 0x%" HWADDR_PRIx "",
 299                       __func__, addr);
 300         return;
 301     } else if (addr >= plic->enable_base && /* 1 bit per source */
 302         addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
 303     {
 304         uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
 305         uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
 306         if (wordid < plic->bitfield_words) {
 307             plic->enable[addrid * plic->bitfield_words + wordid] = value;
 308             if (RISCV_DEBUG_PLIC) {
 309                 qemu_log("plic: write enable: hart%d-%c word=%d value=%x\n",
 310                     plic->addr_config[addrid].hartid,
 311                     mode_to_char(plic->addr_config[addrid].mode), wordid,
 312                     plic->enable[addrid * plic->bitfield_words + wordid]);
 313             }
 314             return;
 315         }
 316     } else if (addr >= plic->context_base && /* 4 bytes per reg */
 317         addr < plic->context_base + plic->num_addrs * plic->context_stride)
 318     {
 319         uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
 320         uint32_t contextid = (addr & (plic->context_stride - 1));
 321         if (contextid == 0) {
 322             if (RISCV_DEBUG_PLIC) {
 323                 qemu_log("plic: write priority: hart%d-%c priority=%x\n",
 324                     plic->addr_config[addrid].hartid,
 325                     mode_to_char(plic->addr_config[addrid].mode),
 326                     plic->target_priority[addrid]);
 327             }
 328             if (value <= plic->num_priorities) {
 329                 plic->target_priority[addrid] = value;
 330                 sifive_plic_update(plic);
 331             }
 332             return;
 333         } else if (contextid == 4) {
 334             if (RISCV_DEBUG_PLIC) {
 335                 qemu_log("plic: write claim: hart%d-%c irq=%x\n",
 336                     plic->addr_config[addrid].hartid,
 337                     mode_to_char(plic->addr_config[addrid].mode),
 338                     (uint32_t)value);
 339             }
 340             if (value < plic->num_sources) {
 341                 sifive_plic_set_claimed(plic, value, false);
 342                 sifive_plic_update(plic);
 343             }
 344             return;
 345         }
 346     }
 347
 348 err:
 349     qemu_log_mask(LOG_GUEST_ERROR,
 350                   "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
 351                   __func__, addr);
 352 }
 353
 354 static const MemoryRegionOps sifive_plic_ops = {
 355     .read = sifive_plic_read,
 356     .write = sifive_plic_write,
 357     .endianness = DEVICE_LITTLE_ENDIAN,
 358     .valid = {
 359         .min_access_size = 4,
 360         .max_access_size = 4
 361     }
 362 };
 363
 364 static Property sifive_plic_properties[] = {
 365     DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
 366     DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
 367     DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
 368     DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
 369     DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
 370     DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
 371     DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
 372     DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
 373     DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
 374     DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
 375     DEFINE_PROP_END_OF_LIST(),
 376 };
 377
 378 /*
 379  * parse PLIC hart/mode address offset config
 380  *
 381  * "M"              1 hart with M mode
 382  * "MS,MS"          2 harts, 0-1 with M and S mode
 383  * "M,MS,MS,MS,MS"  5 harts, 0 with M mode, 1-5 with M and S mode
 384  */
 385 static void parse_hart_config(SiFivePLICState *plic)
 386 {
 387     int addrid, hartid, modes;
 388     const char *p;
 389     char c;
 390
 391     /* count and validate hart/mode combinations */
 392     addrid = 0, hartid = 0, modes = 0;
 393     p = plic->hart_config;
 394     while ((c = *p++)) {
 395         if (c == ',') {
 396             addrid += ctpop8(modes);
 397             modes = 0;
 398             hartid++;
 399         } else {
 400             int m = 1 << char_to_mode(c);
 401             if (modes == (modes | m)) {
 402                 error_report("plic: duplicate mode '%c' in config: %s",
 403                              c, plic->hart_config);
 404                 exit(1);
 405             }
 406             modes |= m;
 407         }
 408     }
 409     if (modes) {
 410         addrid += ctpop8(modes);
 411     }
 412     hartid++;
 413
 414     /* store hart/mode combinations */
 415     plic->num_addrs = addrid;
 416     plic->addr_config = g_new(PLICAddr, plic->num_addrs);
 417     addrid = 0, hartid = 0;
 418     p = plic->hart_config;
 419     while ((c = *p++)) {
 420         if (c == ',') {
 421             hartid++;
 422         } else {
 423             plic->addr_config[addrid].addrid = addrid;
 424             plic->addr_config[addrid].hartid = hartid;
 425             plic->addr_config[addrid].mode = char_to_mode(c);
 426             addrid++;
 427         }
 428     }
 429 }
 430
 431 static void sifive_plic_irq_request(void *opaque, int irq, int level)
 432 {
 433     SiFivePLICState *plic = opaque;
 434     if (RISCV_DEBUG_PLIC) {
 435         qemu_log("sifive_plic_irq_request: irq=%d level=%d\n", irq, level);
 436     }
 437     sifive_plic_set_pending(plic, irq, level > 0);
 438     sifive_plic_update(plic);
 439 }
 440
 441 static void sifive_plic_realize(DeviceState *dev, Error **errp)
 442 {
 443     MachineState *ms = MACHINE(qdev_get_machine());
 444     unsigned int smp_cpus = ms->smp.cpus;
 445     SiFivePLICState *plic = SIFIVE_PLIC(dev);
 446     int i;
 447
 448     memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,
 449                           TYPE_SIFIVE_PLIC, plic->aperture_size);
 450     parse_hart_config(plic);
 451     plic->bitfield_words = (plic->num_sources + 31) >> 5;
 452     plic->source_priority = g_new0(uint32_t, plic->num_sources);
 453     plic->target_priority = g_new(uint32_t, plic->num_addrs);
 454     plic->pending = g_new0(uint32_t, plic->bitfield_words);
 455     plic->claimed = g_new0(uint32_t, plic->bitfield_words);
 456     plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
 457     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
 458     qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
 459
 460     /* We can't allow the supervisor to control SEIP as this would allow the
 461      * supervisor to clear a pending external interrupt which will result in
 462      * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
 463      * hardware controlled when a PLIC is attached.
 464      */
 465     for (i = 0; i < smp_cpus; i++) {
 466         RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
 467         if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
 468             error_report("SEIP already claimed");
 469             exit(1);
 470         }
 471     }
 472
 473     msi_nonbroken = true;
 474 }
 475
 476 static void sifive_plic_class_init(ObjectClass *klass, void *data)
 477 {
 478     DeviceClass *dc = DEVICE_CLASS(klass);
 479
 480     dc->props = sifive_plic_properties;
 481     dc->realize = sifive_plic_realize;
 482 }
 483
 484 static const TypeInfo sifive_plic_info = {
 485     .name          = TYPE_SIFIVE_PLIC,
 486     .parent        = TYPE_SYS_BUS_DEVICE,
 487     .instance_size = sizeof(SiFivePLICState),
 488     .class_init    = sifive_plic_class_init,
 489 };
 490
 491 static void sifive_plic_register_types(void)
 492 {
 493     type_register_static(&sifive_plic_info);
 494 }
 495
 496 type_init(sifive_plic_register_types)
 497
 498 /*
 499  * Create PLIC device.
 500  */
 501 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
 502     uint32_t num_sources, uint32_t num_priorities,
 503     uint32_t priority_base, uint32_t pending_base,
 504     uint32_t enable_base, uint32_t enable_stride,
 505     uint32_t context_base, uint32_t context_stride,
 506     uint32_t aperture_size)
 507 {
 508     DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_PLIC);
 509     assert(enable_stride == (enable_stride & -enable_stride));
 510     assert(context_stride == (context_stride & -context_stride));
 511     qdev_prop_set_string(dev, "hart-config", hart_config);
 512     qdev_prop_set_uint32(dev, "num-sources", num_sources);
 513     qdev_prop_set_uint32(dev, "num-priorities", num_priorities);
 514     qdev_prop_set_uint32(dev, "priority-base", priority_base);
 515     qdev_prop_set_uint32(dev, "pending-base", pending_base);
 516     qdev_prop_set_uint32(dev, "enable-base", enable_base);
 517     qdev_prop_set_uint32(dev, "enable-stride", enable_stride);
 518     qdev_prop_set_uint32(dev, "context-base", context_base);
 519     qdev_prop_set_uint32(dev, "context-stride", context_stride);
 520     qdev_prop_set_uint32(dev, "aperture-size", aperture_size);
 521     qdev_init_nofail(dev);
 522     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
 523     return dev;
 524 }