hw/mips/mips_jazz.c

   1 /*
   2  * QEMU MIPS Jazz support
   3  *
   4  * Copyright (c) 2007-2008 Hervé Poussineau
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu-common.h"
  27 #include "hw/hw.h"
  28 #include "hw/mips/mips.h"
  29 #include "hw/mips/cpudevs.h"
  30 #include "hw/i386/pc.h"
  31 #include "hw/dma/i8257.h"
  32 #include "hw/char/serial.h"
  33 #include "hw/char/parallel.h"
  34 #include "hw/isa/isa.h"
  35 #include "hw/block/fdc.h"
  36 #include "sysemu/sysemu.h"
  37 #include "sysemu/arch_init.h"
  38 #include "hw/boards.h"
  39 #include "net/net.h"
  40 #include "hw/scsi/esp.h"
  41 #include "hw/mips/bios.h"
  42 #include "hw/loader.h"
  43 #include "hw/timer/mc146818rtc.h"
  44 #include "hw/timer/i8254.h"
  45 #include "hw/display/vga.h"
  46 #include "hw/audio/pcspk.h"
  47 #include "hw/input/i8042.h"
  48 #include "hw/sysbus.h"
  49 #include "exec/address-spaces.h"
  50 #include "sysemu/qtest.h"
  51 #include "qapi/error.h"
  52 #include "qemu/error-report.h"
  53 #include "qemu/help_option.h"
  54
  55 enum jazz_model_e
  56 {
  57     JAZZ_MAGNUM,
  58     JAZZ_PICA61,
  59 };
  60
  61 static void main_cpu_reset(void *opaque)
  62 {
  63     MIPSCPU *cpu = opaque;
  64
  65     cpu_reset(CPU(cpu));
  66 }
  67
  68 static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
  69 {
  70     uint8_t val;
  71     address_space_read(&address_space_memory, 0x90000071,
  72                        MEMTXATTRS_UNSPECIFIED, &val, 1);
  73     return val;
  74 }
  75
  76 static void rtc_write(void *opaque, hwaddr addr,
  77                       uint64_t val, unsigned size)
  78 {
  79     uint8_t buf = val & 0xff;
  80     address_space_write(&address_space_memory, 0x90000071,
  81                         MEMTXATTRS_UNSPECIFIED, &buf, 1);
  82 }
  83
  84 static const MemoryRegionOps rtc_ops = {
  85     .read = rtc_read,
  86     .write = rtc_write,
  87     .endianness = DEVICE_NATIVE_ENDIAN,
  88 };
  89
  90 static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
  91                                unsigned size)
  92 {
  93     /* Nothing to do. That is only to ensure that
  94      * the current DMA acknowledge cycle is completed. */
  95     return 0xff;
  96 }
  97
  98 static void dma_dummy_write(void *opaque, hwaddr addr,
  99                             uint64_t val, unsigned size)
 100 {
 101     /* Nothing to do. That is only to ensure that
 102      * the current DMA acknowledge cycle is completed. */
 103 }
 104
 105 static const MemoryRegionOps dma_dummy_ops = {
 106     .read = dma_dummy_read,
 107     .write = dma_dummy_write,
 108     .endianness = DEVICE_NATIVE_ENDIAN,
 109 };
 110
 111 #define MAGNUM_BIOS_SIZE_MAX 0x7e000
 112 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
 113
 114 static CPUUnassignedAccess real_do_unassigned_access;
 115 static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr,
 116                                            bool is_write, bool is_exec,
 117                                            int opaque, unsigned size)
 118 {
 119     if (!is_exec) {
 120         /* ignore invalid access (ie do not raise exception) */
 121         return;
 122     }
 123     (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size);
 124 }
 125
 126 static void mips_jazz_init(MachineState *machine,
 127                            enum jazz_model_e jazz_model)
 128 {
 129     MemoryRegion *address_space = get_system_memory();
 130     char *filename;
 131     int bios_size, n;
 132     MIPSCPU *cpu;
 133     CPUClass *cc;
 134     CPUMIPSState *env;
 135     qemu_irq *i8259;
 136     rc4030_dma *dmas;
 137     IOMMUMemoryRegion *rc4030_dma_mr;
 138     MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
 139     MemoryRegion *isa_io = g_new(MemoryRegion, 1);
 140     MemoryRegion *rtc = g_new(MemoryRegion, 1);
 141     MemoryRegion *i8042 = g_new(MemoryRegion, 1);
 142     MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
 143     NICInfo *nd;
 144     DeviceState *dev, *rc4030;
 145     SysBusDevice *sysbus;
 146     ISABus *isa_bus;
 147     ISADevice *pit;
 148     DriveInfo *fds[MAX_FD];
 149     MemoryRegion *ram = g_new(MemoryRegion, 1);
 150     MemoryRegion *bios = g_new(MemoryRegion, 1);
 151     MemoryRegion *bios2 = g_new(MemoryRegion, 1);
 152     SysBusESPState *sysbus_esp;
 153     ESPState *esp;
 154
 155     /* init CPUs */
 156     cpu = MIPS_CPU(cpu_create(machine->cpu_type));
 157     env = &cpu->env;
 158     qemu_register_reset(main_cpu_reset, cpu);
 159
 160     /* Chipset returns 0 in invalid reads and do not raise data exceptions.
 161      * However, we can't simply add a global memory region to catch
 162      * everything, as memory core directly call unassigned_mem_read/write
 163      * on some invalid accesses, which call do_unassigned_access on the
 164      * CPU, which raise an exception.
 165      * Handle that case by hijacking the do_unassigned_access method on
 166      * the CPU, and do not raise exceptions for data access. */
 167     cc = CPU_GET_CLASS(cpu);
 168     real_do_unassigned_access = cc->do_unassigned_access;
 169     cc->do_unassigned_access = mips_jazz_do_unassigned_access;
 170
 171     /* allocate RAM */
 172     memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram",
 173                                          machine->ram_size);
 174     memory_region_add_subregion(address_space, 0, ram);
 175
 176     memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
 177                            &error_fatal);
 178     memory_region_set_readonly(bios, true);
 179     memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
 180                              0, MAGNUM_BIOS_SIZE);
 181     memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
 182     memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
 183
 184     /* load the BIOS image. */
 185     if (bios_name == NULL)
 186         bios_name = BIOS_FILENAME;
 187     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 188     if (filename) {
 189         bios_size = load_image_targphys(filename, 0xfff00000LL,
 190                                         MAGNUM_BIOS_SIZE);
 191         g_free(filename);
 192     } else {
 193         bios_size = -1;
 194     }
 195     if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
 196         error_report("Could not load MIPS bios '%s'", bios_name);
 197         exit(1);
 198     }
 199
 200     /* Init CPU internal devices */
 201     cpu_mips_irq_init_cpu(cpu);
 202     cpu_mips_clock_init(cpu);
 203
 204     /* Chipset */
 205     rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
 206     sysbus = SYS_BUS_DEVICE(rc4030);
 207     sysbus_connect_irq(sysbus, 0, env->irq[6]);
 208     sysbus_connect_irq(sysbus, 1, env->irq[3]);
 209     memory_region_add_subregion(address_space, 0x80000000,
 210                                 sysbus_mmio_get_region(sysbus, 0));
 211     memory_region_add_subregion(address_space, 0xf0000000,
 212                                 sysbus_mmio_get_region(sysbus, 1));
 213     memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
 214     memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
 215
 216     /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
 217     memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
 218     memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
 219     memory_region_add_subregion(address_space, 0x90000000, isa_io);
 220     memory_region_add_subregion(address_space, 0x91000000, isa_mem);
 221     isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
 222
 223     /* ISA devices */
 224     i8259 = i8259_init(isa_bus, env->irq[4]);
 225     isa_bus_irqs(isa_bus, i8259);
 226     i8257_dma_init(isa_bus, 0);
 227     pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
 228     pcspk_init(isa_bus, pit);
 229
 230     /* Video card */
 231     switch (jazz_model) {
 232     case JAZZ_MAGNUM:
 233         dev = qdev_create(NULL, "sysbus-g364");
 234         qdev_init_nofail(dev);
 235         sysbus = SYS_BUS_DEVICE(dev);
 236         sysbus_mmio_map(sysbus, 0, 0x60080000);
 237         sysbus_mmio_map(sysbus, 1, 0x40000000);
 238         sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
 239         {
 240             /* Simple ROM, so user doesn't have to provide one */
 241             MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
 242             memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000,
 243                                    &error_fatal);
 244             memory_region_set_readonly(rom_mr, true);
 245             uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
 246             memory_region_add_subregion(address_space, 0x60000000, rom_mr);
 247             rom[0] = 0x10; /* Mips G364 */
 248         }
 249         break;
 250     case JAZZ_PICA61:
 251         isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
 252         break;
 253     default:
 254         break;
 255     }
 256
 257     /* Network controller */
 258     for (n = 0; n < nb_nics; n++) {
 259         nd = &nd_table[n];
 260         if (!nd->model)
 261             nd->model = g_strdup("dp83932");
 262         if (strcmp(nd->model, "dp83932") == 0) {
 263             qemu_check_nic_model(nd, "dp83932");
 264
 265             dev = qdev_create(NULL, "dp8393x");
 266             qdev_set_nic_properties(dev, nd);
 267             qdev_prop_set_uint8(dev, "it_shift", 2);
 268             qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr);
 269             qdev_init_nofail(dev);
 270             sysbus = SYS_BUS_DEVICE(dev);
 271             sysbus_mmio_map(sysbus, 0, 0x80001000);
 272             sysbus_mmio_map(sysbus, 1, 0x8000b000);
 273             sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
 274             break;
 275         } else if (is_help_option(nd->model)) {
 276             error_report("Supported NICs: dp83932");
 277             exit(1);
 278         } else {
 279             error_report("Unsupported NIC: %s", nd->model);
 280             exit(1);
 281         }
 282     }
 283
 284     /* SCSI adapter */
 285     dev = qdev_create(NULL, TYPE_ESP);
 286     sysbus_esp = ESP_STATE(dev);
 287     esp = &sysbus_esp->esp;
 288     esp->dma_memory_read = rc4030_dma_read;
 289     esp->dma_memory_write = rc4030_dma_write;
 290     esp->dma_opaque = dmas[0];
 291     sysbus_esp->it_shift = 0;
 292     /* XXX for now until rc4030 has been changed to use DMA enable signal */
 293     esp->dma_enabled = 1;
 294     qdev_init_nofail(dev);
 295
 296     sysbus = SYS_BUS_DEVICE(dev);
 297     sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 5));
 298     sysbus_mmio_map(sysbus, 0, 0x80002000);
 299
 300     scsi_bus_legacy_handle_cmdline(&esp->bus);
 301
 302     /* Floppy */
 303     for (n = 0; n < MAX_FD; n++) {
 304         fds[n] = drive_get(IF_FLOPPY, 0, n);
 305     }
 306     /* FIXME: we should enable DMA with a custom IsaDma device */
 307     fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);
 308
 309     /* Real time clock */
 310     mc146818_rtc_init(isa_bus, 1980, NULL);
 311     memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
 312     memory_region_add_subregion(address_space, 0x80004000, rtc);
 313
 314     /* Keyboard (i8042) */
 315     i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
 316                   i8042, 0x1000, 0x1);
 317     memory_region_add_subregion(address_space, 0x80005000, i8042);
 318
 319     /* Serial ports */
 320     if (serial_hd(0)) {
 321         serial_mm_init(address_space, 0x80006000, 0,
 322                        qdev_get_gpio_in(rc4030, 8), 8000000/16,
 323                        serial_hd(0), DEVICE_NATIVE_ENDIAN);
 324     }
 325     if (serial_hd(1)) {
 326         serial_mm_init(address_space, 0x80007000, 0,
 327                        qdev_get_gpio_in(rc4030, 9), 8000000/16,
 328                        serial_hd(1), DEVICE_NATIVE_ENDIAN);
 329     }
 330
 331     /* Parallel port */
 332     if (parallel_hds[0])
 333         parallel_mm_init(address_space, 0x80008000, 0,
 334                          qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
 335
 336     /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
 337
 338     /* NVRAM */
 339     dev = qdev_create(NULL, "ds1225y");
 340     qdev_init_nofail(dev);
 341     sysbus = SYS_BUS_DEVICE(dev);
 342     sysbus_mmio_map(sysbus, 0, 0x80009000);
 343
 344     /* LED indicator */
 345     sysbus_create_simple("jazz-led", 0x8000f000, NULL);
 346 }
 347
 348 static
 349 void mips_magnum_init(MachineState *machine)
 350 {
 351     mips_jazz_init(machine, JAZZ_MAGNUM);
 352 }
 353
 354 static
 355 void mips_pica61_init(MachineState *machine)
 356 {
 357     mips_jazz_init(machine, JAZZ_PICA61);
 358 }
 359
 360 static void mips_magnum_class_init(ObjectClass *oc, void *data)
 361 {
 362     MachineClass *mc = MACHINE_CLASS(oc);
 363
 364     mc->desc = "MIPS Magnum";
 365     mc->init = mips_magnum_init;
 366     mc->block_default_type = IF_SCSI;
 367     mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
 368 }
 369
 370 static const TypeInfo mips_magnum_type = {
 371     .name = MACHINE_TYPE_NAME("magnum"),
 372     .parent = TYPE_MACHINE,
 373     .class_init = mips_magnum_class_init,
 374 };
 375
 376 static void mips_pica61_class_init(ObjectClass *oc, void *data)
 377 {
 378     MachineClass *mc = MACHINE_CLASS(oc);
 379
 380     mc->desc = "Acer Pica 61";
 381     mc->init = mips_pica61_init;
 382     mc->block_default_type = IF_SCSI;
 383     mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
 384 }
 385
 386 static const TypeInfo mips_pica61_type = {
 387     .name = MACHINE_TYPE_NAME("pica61"),
 388     .parent = TYPE_MACHINE,
 389     .class_init = mips_pica61_class_init,
 390 };
 391
 392 static void mips_jazz_machine_init(void)
 393 {
 394     type_register_static(&mips_magnum_type);
 395     type_register_static(&mips_pica61_type);
 396 }
 397
 398 type_init(mips_jazz_machine_init)