target/riscv: Remove the hardcoded RVXLEN macro
[qemu/ar7.git] / tcg / i386 / tcg-target-con-set.h
blob78774d1005f4feef77454c81156a7851cc78939d
1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Define i386 target-specific constraint sets.
4 * Copyright (c) 2021 Linaro
5 */
7 /*
8 * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
9 * Each operand should be a sequence of constraint letters as defined by
10 * tcg-target-con-str.h; the constraint combination is inclusive or.
12 * C_N1_Im(...) defines a constraint set with 1 output and <m> inputs,
13 * except that the output must use a new register.
15 C_O0_I1(r)
16 C_O0_I2(L, L)
17 C_O0_I2(qi, r)
18 C_O0_I2(re, r)
19 C_O0_I2(ri, r)
20 C_O0_I2(r, re)
21 C_O0_I2(s, L)
22 C_O0_I2(x, r)
23 C_O0_I3(L, L, L)
24 C_O0_I3(s, L, L)
25 C_O0_I4(L, L, L, L)
26 C_O0_I4(r, r, ri, ri)
27 C_O1_I1(r, 0)
28 C_O1_I1(r, L)
29 C_O1_I1(r, q)
30 C_O1_I1(r, r)
31 C_O1_I1(x, r)
32 C_O1_I1(x, x)
33 C_O1_I2(Q, 0, Q)
34 C_O1_I2(q, r, re)
35 C_O1_I2(r, 0, ci)
36 C_O1_I2(r, 0, r)
37 C_O1_I2(r, 0, re)
38 C_O1_I2(r, 0, reZ)
39 C_O1_I2(r, 0, ri)
40 C_O1_I2(r, 0, rI)
41 C_O1_I2(r, L, L)
42 C_O1_I2(r, r, re)
43 C_O1_I2(r, r, ri)
44 C_O1_I2(r, r, rI)
45 C_O1_I2(x, x, x)
46 C_N1_I2(r, r, r)
47 C_N1_I2(r, r, rW)
48 C_O1_I3(x, x, x, x)
49 C_O1_I4(r, r, re, r, 0)
50 C_O1_I4(r, r, r, ri, ri)
51 C_O2_I1(r, r, L)
52 C_O2_I2(a, d, a, r)
53 C_O2_I2(r, r, L, L)
54 C_O2_I3(a, d, 0, 1, r)
55 C_O2_I4(r, r, 0, 1, re, re)