hw/arm/vexpress.c

   1 /*
   2  * ARM Versatile Express emulation.
   3  *
   4  * Copyright (c) 2010 - 2011 B Labs Ltd.
   5  * Copyright (c) 2011 Linaro Limited
   6  * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License version 2 as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  Contributions after 2012-01-13 are licensed under the terms of the
  21  *  GNU GPL, version 2 or (at your option) any later version.
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "hw/sysbus.h"
  26 #include "hw/arm/arm.h"
  27 #include "hw/arm/primecell.h"
  28 #include "hw/devices.h"
  29 #include "net/net.h"
  30 #include "sysemu/sysemu.h"
  31 #include "hw/boards.h"
  32 #include "hw/loader.h"
  33 #include "exec/address-spaces.h"
  34 #include "sysemu/block-backend.h"
  35 #include "hw/block/flash.h"
  36 #include "sysemu/device_tree.h"
  37 #include "qemu/error-report.h"
  38 #include <libfdt.h>
  39
  40 #define VEXPRESS_BOARD_ID 0x8e0
  41 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
  42 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
  43
  44 /* Number of virtio transports to create (0..8; limited by
  45  * number of available IRQ lines).
  46  */
  47 #define NUM_VIRTIO_TRANSPORTS 4
  48
  49 /* Address maps for peripherals:
  50  * the Versatile Express motherboard has two possible maps,
  51  * the "legacy" one (used for A9) and the "Cortex-A Series"
  52  * map (used for newer cores).
  53  * Individual daughterboards can also have different maps for
  54  * their peripherals.
  55  */
  56
  57 enum {
  58     VE_SYSREGS,
  59     VE_SP810,
  60     VE_SERIALPCI,
  61     VE_PL041,
  62     VE_MMCI,
  63     VE_KMI0,
  64     VE_KMI1,
  65     VE_UART0,
  66     VE_UART1,
  67     VE_UART2,
  68     VE_UART3,
  69     VE_WDT,
  70     VE_TIMER01,
  71     VE_TIMER23,
  72     VE_SERIALDVI,
  73     VE_RTC,
  74     VE_COMPACTFLASH,
  75     VE_CLCD,
  76     VE_NORFLASH0,
  77     VE_NORFLASH1,
  78     VE_NORFLASHALIAS,
  79     VE_SRAM,
  80     VE_VIDEORAM,
  81     VE_ETHERNET,
  82     VE_USB,
  83     VE_DAPROM,
  84     VE_VIRTIO,
  85 };
  86
  87 static hwaddr motherboard_legacy_map[] = {
  88     [VE_NORFLASHALIAS] = 0,
  89     /* CS7: 0x10000000 .. 0x10020000 */
  90     [VE_SYSREGS] = 0x10000000,
  91     [VE_SP810] = 0x10001000,
  92     [VE_SERIALPCI] = 0x10002000,
  93     [VE_PL041] = 0x10004000,
  94     [VE_MMCI] = 0x10005000,
  95     [VE_KMI0] = 0x10006000,
  96     [VE_KMI1] = 0x10007000,
  97     [VE_UART0] = 0x10009000,
  98     [VE_UART1] = 0x1000a000,
  99     [VE_UART2] = 0x1000b000,
 100     [VE_UART3] = 0x1000c000,
 101     [VE_WDT] = 0x1000f000,
 102     [VE_TIMER01] = 0x10011000,
 103     [VE_TIMER23] = 0x10012000,
 104     [VE_VIRTIO] = 0x10013000,
 105     [VE_SERIALDVI] = 0x10016000,
 106     [VE_RTC] = 0x10017000,
 107     [VE_COMPACTFLASH] = 0x1001a000,
 108     [VE_CLCD] = 0x1001f000,
 109     /* CS0: 0x40000000 .. 0x44000000 */
 110     [VE_NORFLASH0] = 0x40000000,
 111     /* CS1: 0x44000000 .. 0x48000000 */
 112     [VE_NORFLASH1] = 0x44000000,
 113     /* CS2: 0x48000000 .. 0x4a000000 */
 114     [VE_SRAM] = 0x48000000,
 115     /* CS3: 0x4c000000 .. 0x50000000 */
 116     [VE_VIDEORAM] = 0x4c000000,
 117     [VE_ETHERNET] = 0x4e000000,
 118     [VE_USB] = 0x4f000000,
 119 };
 120
 121 static hwaddr motherboard_aseries_map[] = {
 122     [VE_NORFLASHALIAS] = 0,
 123     /* CS0: 0x08000000 .. 0x0c000000 */
 124     [VE_NORFLASH0] = 0x08000000,
 125     /* CS4: 0x0c000000 .. 0x10000000 */
 126     [VE_NORFLASH1] = 0x0c000000,
 127     /* CS5: 0x10000000 .. 0x14000000 */
 128     /* CS1: 0x14000000 .. 0x18000000 */
 129     [VE_SRAM] = 0x14000000,
 130     /* CS2: 0x18000000 .. 0x1c000000 */
 131     [VE_VIDEORAM] = 0x18000000,
 132     [VE_ETHERNET] = 0x1a000000,
 133     [VE_USB] = 0x1b000000,
 134     /* CS3: 0x1c000000 .. 0x20000000 */
 135     [VE_DAPROM] = 0x1c000000,
 136     [VE_SYSREGS] = 0x1c010000,
 137     [VE_SP810] = 0x1c020000,
 138     [VE_SERIALPCI] = 0x1c030000,
 139     [VE_PL041] = 0x1c040000,
 140     [VE_MMCI] = 0x1c050000,
 141     [VE_KMI0] = 0x1c060000,
 142     [VE_KMI1] = 0x1c070000,
 143     [VE_UART0] = 0x1c090000,
 144     [VE_UART1] = 0x1c0a0000,
 145     [VE_UART2] = 0x1c0b0000,
 146     [VE_UART3] = 0x1c0c0000,
 147     [VE_WDT] = 0x1c0f0000,
 148     [VE_TIMER01] = 0x1c110000,
 149     [VE_TIMER23] = 0x1c120000,
 150     [VE_VIRTIO] = 0x1c130000,
 151     [VE_SERIALDVI] = 0x1c160000,
 152     [VE_RTC] = 0x1c170000,
 153     [VE_COMPACTFLASH] = 0x1c1a0000,
 154     [VE_CLCD] = 0x1c1f0000,
 155 };
 156
 157 /* Structure defining the peculiarities of a specific daughterboard */
 158
 159 typedef struct VEDBoardInfo VEDBoardInfo;
 160
 161 typedef struct {
 162     MachineClass parent;
 163     VEDBoardInfo *daughterboard;
 164 } VexpressMachineClass;
 165
 166 typedef struct {
 167     MachineState parent;
 168     bool secure;
 169 } VexpressMachineState;
 170
 171 #define TYPE_VEXPRESS_MACHINE   "vexpress"
 172 #define TYPE_VEXPRESS_A9_MACHINE   MACHINE_TYPE_NAME("vexpress-a9")
 173 #define TYPE_VEXPRESS_A15_MACHINE   MACHINE_TYPE_NAME("vexpress-a15")
 174 #define VEXPRESS_MACHINE(obj) \
 175     OBJECT_CHECK(VexpressMachineState, (obj), TYPE_VEXPRESS_MACHINE)
 176 #define VEXPRESS_MACHINE_GET_CLASS(obj) \
 177     OBJECT_GET_CLASS(VexpressMachineClass, obj, TYPE_VEXPRESS_MACHINE)
 178 #define VEXPRESS_MACHINE_CLASS(klass) \
 179     OBJECT_CLASS_CHECK(VexpressMachineClass, klass, TYPE_VEXPRESS_MACHINE)
 180
 181 typedef void DBoardInitFn(const VexpressMachineState *machine,
 182                           ram_addr_t ram_size,
 183                           const char *cpu_model,
 184                           qemu_irq *pic);
 185
 186 struct VEDBoardInfo {
 187     struct arm_boot_info bootinfo;
 188     const hwaddr *motherboard_map;
 189     hwaddr loader_start;
 190     const hwaddr gic_cpu_if_addr;
 191     uint32_t proc_id;
 192     uint32_t num_voltage_sensors;
 193     const uint32_t *voltages;
 194     uint32_t num_clocks;
 195     const uint32_t *clocks;
 196     DBoardInitFn *init;
 197 };
 198
 199 static void init_cpus(const char *cpu_model, const char *privdev,
 200                       hwaddr periphbase, qemu_irq *pic, bool secure)
 201 {
 202     ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
 203     DeviceState *dev;
 204     SysBusDevice *busdev;
 205     int n;
 206
 207     if (!cpu_oc) {
 208         fprintf(stderr, "Unable to find CPU definition\n");
 209         exit(1);
 210     }
 211
 212     /* Create the actual CPUs */
 213     for (n = 0; n < smp_cpus; n++) {
 214         Object *cpuobj = object_new(object_class_get_name(cpu_oc));
 215
 216         if (!secure) {
 217             object_property_set_bool(cpuobj, false, "has_el3", NULL);
 218         }
 219
 220         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
 221             object_property_set_int(cpuobj, periphbase,
 222                                     "reset-cbar", &error_abort);
 223         }
 224         object_property_set_bool(cpuobj, true, "realized", &error_fatal);
 225     }
 226
 227     /* Create the private peripheral devices (including the GIC);
 228      * this must happen after the CPUs are created because a15mpcore_priv
 229      * wires itself up to the CPU's generic_timer gpio out lines.
 230      */
 231     dev = qdev_create(NULL, privdev);
 232     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 233     qdev_init_nofail(dev);
 234     busdev = SYS_BUS_DEVICE(dev);
 235     sysbus_mmio_map(busdev, 0, periphbase);
 236
 237     /* Interrupts [42:0] are from the motherboard;
 238      * [47:43] are reserved; [63:48] are daughterboard
 239      * peripherals. Note that some documentation numbers
 240      * external interrupts starting from 32 (because there
 241      * are internal interrupts 0..31).
 242      */
 243     for (n = 0; n < 64; n++) {
 244         pic[n] = qdev_get_gpio_in(dev, n);
 245     }
 246
 247     /* Connect the CPUs to the GIC */
 248     for (n = 0; n < smp_cpus; n++) {
 249         DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
 250
 251         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 252         sysbus_connect_irq(busdev, n + smp_cpus,
 253                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
 254     }
 255 }
 256
 257 static void a9_daughterboard_init(const VexpressMachineState *vms,
 258                                   ram_addr_t ram_size,
 259                                   const char *cpu_model,
 260                                   qemu_irq *pic)
 261 {
 262     MemoryRegion *sysmem = get_system_memory();
 263     MemoryRegion *ram = g_new(MemoryRegion, 1);
 264     MemoryRegion *lowram = g_new(MemoryRegion, 1);
 265     ram_addr_t low_ram_size;
 266
 267     if (!cpu_model) {
 268         cpu_model = "cortex-a9";
 269     }
 270
 271     if (ram_size > 0x40000000) {
 272         /* 1GB is the maximum the address space permits */
 273         fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n");
 274         exit(1);
 275     }
 276
 277     memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem",
 278                                          ram_size);
 279     low_ram_size = ram_size;
 280     if (low_ram_size > 0x4000000) {
 281         low_ram_size = 0x4000000;
 282     }
 283     /* RAM is from 0x60000000 upwards. The bottom 64MB of the
 284      * address space should in theory be remappable to various
 285      * things including ROM or RAM; we always map the RAM there.
 286      */
 287     memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size);
 288     memory_region_add_subregion(sysmem, 0x0, lowram);
 289     memory_region_add_subregion(sysmem, 0x60000000, ram);
 290
 291     /* 0x1e000000 A9MPCore (SCU) private memory region */
 292     init_cpus(cpu_model, "a9mpcore_priv", 0x1e000000, pic, vms->secure);
 293
 294     /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
 295
 296     /* 0x10020000 PL111 CLCD (daughterboard) */
 297     sysbus_create_simple("pl111", 0x10020000, pic[44]);
 298
 299     /* 0x10060000 AXI RAM */
 300     /* 0x100e0000 PL341 Dynamic Memory Controller */
 301     /* 0x100e1000 PL354 Static Memory Controller */
 302     /* 0x100e2000 System Configuration Controller */
 303
 304     sysbus_create_simple("sp804", 0x100e4000, pic[48]);
 305     /* 0x100e5000 SP805 Watchdog module */
 306     /* 0x100e6000 BP147 TrustZone Protection Controller */
 307     /* 0x100e9000 PL301 'Fast' AXI matrix */
 308     /* 0x100ea000 PL301 'Slow' AXI matrix */
 309     /* 0x100ec000 TrustZone Address Space Controller */
 310     /* 0x10200000 CoreSight debug APB */
 311     /* 0x1e00a000 PL310 L2 Cache Controller */
 312     sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
 313 }
 314
 315 /* Voltage values for SYS_CFG_VOLT daughterboard registers;
 316  * values are in microvolts.
 317  */
 318 static const uint32_t a9_voltages[] = {
 319     1000000, /* VD10 : 1.0V : SoC internal logic voltage */
 320     1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */
 321     1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */
 322     1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */
 323     900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */
 324     3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */
 325 };
 326
 327 /* Reset values for daughterboard oscillators (in Hz) */
 328 static const uint32_t a9_clocks[] = {
 329     45000000, /* AMBA AXI ACLK: 45MHz */
 330     23750000, /* daughterboard CLCD clock: 23.75MHz */
 331     66670000, /* Test chip reference clock: 66.67MHz */
 332 };
 333
 334 static VEDBoardInfo a9_daughterboard = {
 335     .motherboard_map = motherboard_legacy_map,
 336     .loader_start = 0x60000000,
 337     .gic_cpu_if_addr = 0x1e000100,
 338     .proc_id = 0x0c000191,
 339     .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
 340     .voltages = a9_voltages,
 341     .num_clocks = ARRAY_SIZE(a9_clocks),
 342     .clocks = a9_clocks,
 343     .init = a9_daughterboard_init,
 344 };
 345
 346 static void a15_daughterboard_init(const VexpressMachineState *vms,
 347                                    ram_addr_t ram_size,
 348                                    const char *cpu_model,
 349                                    qemu_irq *pic)
 350 {
 351     MemoryRegion *sysmem = get_system_memory();
 352     MemoryRegion *ram = g_new(MemoryRegion, 1);
 353     MemoryRegion *sram = g_new(MemoryRegion, 1);
 354
 355     if (!cpu_model) {
 356         cpu_model = "cortex-a15";
 357     }
 358
 359     {
 360         /* We have to use a separate 64 bit variable here to avoid the gcc
 361          * "comparison is always false due to limited range of data type"
 362          * warning if we are on a host where ram_addr_t is 32 bits.
 363          */
 364         uint64_t rsz = ram_size;
 365         if (rsz > (30ULL * 1024 * 1024 * 1024)) {
 366             fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n");
 367             exit(1);
 368         }
 369     }
 370
 371     memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem",
 372                                          ram_size);
 373     /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
 374     memory_region_add_subregion(sysmem, 0x80000000, ram);
 375
 376     /* 0x2c000000 A15MPCore private memory region (GIC) */
 377     init_cpus(cpu_model, "a15mpcore_priv", 0x2c000000, pic, vms->secure);
 378
 379     /* A15 daughterboard peripherals: */
 380
 381     /* 0x20000000: CoreSight interfaces: not modelled */
 382     /* 0x2a000000: PL301 AXI interconnect: not modelled */
 383     /* 0x2a420000: SCC: not modelled */
 384     /* 0x2a430000: system counter: not modelled */
 385     /* 0x2b000000: HDLCD controller: not modelled */
 386     /* 0x2b060000: SP805 watchdog: not modelled */
 387     /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
 388     /* 0x2e000000: system SRAM */
 389     memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000,
 390                            &error_fatal);
 391     vmstate_register_ram_global(sram);
 392     memory_region_add_subregion(sysmem, 0x2e000000, sram);
 393
 394     /* 0x7ffb0000: DMA330 DMA controller: not modelled */
 395     /* 0x7ffd0000: PL354 static memory controller: not modelled */
 396 }
 397
 398 static const uint32_t a15_voltages[] = {
 399     900000, /* Vcore: 0.9V : CPU core voltage */
 400 };
 401
 402 static const uint32_t a15_clocks[] = {
 403     60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */
 404     0, /* OSCCLK1: reserved */
 405     0, /* OSCCLK2: reserved */
 406     0, /* OSCCLK3: reserved */
 407     40000000, /* OSCCLK4: 40MHz : external AXI master clock */
 408     23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
 409     50000000, /* OSCCLK6: 50MHz : static memory controller clock */
 410     60000000, /* OSCCLK7: 60MHz : SYSCLK reference */
 411     40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
 412 };
 413
 414 static VEDBoardInfo a15_daughterboard = {
 415     .motherboard_map = motherboard_aseries_map,
 416     .loader_start = 0x80000000,
 417     .gic_cpu_if_addr = 0x2c002000,
 418     .proc_id = 0x14000237,
 419     .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
 420     .voltages = a15_voltages,
 421     .num_clocks = ARRAY_SIZE(a15_clocks),
 422     .clocks = a15_clocks,
 423     .init = a15_daughterboard_init,
 424 };
 425
 426 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells,
 427                                 hwaddr addr, hwaddr size, uint32_t intc,
 428                                 int irq)
 429 {
 430     /* Add a virtio_mmio node to the device tree blob:
 431      *   virtio_mmio@ADDRESS {
 432      *       compatible = "virtio,mmio";
 433      *       reg = <ADDRESS, SIZE>;
 434      *       interrupt-parent = <&intc>;
 435      *       interrupts = <0, irq, 1>;
 436      *   }
 437      * (Note that the format of the interrupts property is dependent on the
 438      * interrupt controller that interrupt-parent points to; these are for
 439      * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.)
 440      */
 441     int rc;
 442     char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr);
 443
 444     rc = qemu_fdt_add_subnode(fdt, nodename);
 445     rc |= qemu_fdt_setprop_string(fdt, nodename,
 446                                   "compatible", "virtio,mmio");
 447     rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
 448                                        acells, addr, scells, size);
 449     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);
 450     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);
 451     g_free(nodename);
 452     if (rc) {
 453         return -1;
 454     }
 455     return 0;
 456 }
 457
 458 static uint32_t find_int_controller(void *fdt)
 459 {
 460     /* Find the FDT node corresponding to the interrupt controller
 461      * for virtio-mmio devices. We do this by scanning the fdt for
 462      * a node with the right compatibility, since we know there is
 463      * only one GIC on a vexpress board.
 464      * We return the phandle of the node, or 0 if none was found.
 465      */
 466     const char *compat = "arm,cortex-a9-gic";
 467     int offset;
 468
 469     offset = fdt_node_offset_by_compatible(fdt, -1, compat);
 470     if (offset >= 0) {
 471         return fdt_get_phandle(fdt, offset);
 472     }
 473     return 0;
 474 }
 475
 476 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt)
 477 {
 478     uint32_t acells, scells, intc;
 479     const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info;
 480
 481     acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
 482                                    NULL, &error_fatal);
 483     scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
 484                                    NULL, &error_fatal);
 485     intc = find_int_controller(fdt);
 486     if (!intc) {
 487         /* Not fatal, we just won't provide virtio. This will
 488          * happen with older device tree blobs.
 489          */
 490         fprintf(stderr, "QEMU: warning: couldn't find interrupt controller in "
 491                 "dtb; will not include virtio-mmio devices in the dtb.\n");
 492     } else {
 493         int i;
 494         const hwaddr *map = daughterboard->motherboard_map;
 495
 496         /* We iterate backwards here because adding nodes
 497          * to the dtb puts them in last-first.
 498          */
 499         for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
 500             add_virtio_mmio_node(fdt, acells, scells,
 501                                  map[VE_VIRTIO] + 0x200 * i,
 502                                  0x200, intc, 40 + i);
 503         }
 504     }
 505 }
 506
 507
 508 /* Open code a private version of pflash registration since we
 509  * need to set non-default device width for VExpress platform.
 510  */
 511 static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name,
 512                                           DriveInfo *di)
 513 {
 514     DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
 515
 516     if (di) {
 517         qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di),
 518                             &error_abort);
 519     }
 520
 521     qdev_prop_set_uint32(dev, "num-blocks",
 522                          VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE);
 523     qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE);
 524     qdev_prop_set_uint8(dev, "width", 4);
 525     qdev_prop_set_uint8(dev, "device-width", 2);
 526     qdev_prop_set_bit(dev, "big-endian", false);
 527     qdev_prop_set_uint16(dev, "id0", 0x89);
 528     qdev_prop_set_uint16(dev, "id1", 0x18);
 529     qdev_prop_set_uint16(dev, "id2", 0x00);
 530     qdev_prop_set_uint16(dev, "id3", 0x00);
 531     qdev_prop_set_string(dev, "name", name);
 532     qdev_init_nofail(dev);
 533
 534     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 535     return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
 536 }
 537
 538 static void vexpress_common_init(MachineState *machine)
 539 {
 540     VexpressMachineState *vms = VEXPRESS_MACHINE(machine);
 541     VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine);
 542     VEDBoardInfo *daughterboard = vmc->daughterboard;
 543     DeviceState *dev, *sysctl, *pl041;
 544     qemu_irq pic[64];
 545     uint32_t sys_id;
 546     DriveInfo *dinfo;
 547     pflash_t *pflash0;
 548     ram_addr_t vram_size, sram_size;
 549     MemoryRegion *sysmem = get_system_memory();
 550     MemoryRegion *vram = g_new(MemoryRegion, 1);
 551     MemoryRegion *sram = g_new(MemoryRegion, 1);
 552     MemoryRegion *flashalias = g_new(MemoryRegion, 1);
 553     MemoryRegion *flash0mem;
 554     const hwaddr *map = daughterboard->motherboard_map;
 555     int i;
 556
 557     daughterboard->init(vms, machine->ram_size, machine->cpu_model, pic);
 558
 559     /*
 560      * If a bios file was provided, attempt to map it into memory
 561      */
 562     if (bios_name) {
 563         char *fn;
 564         int image_size;
 565
 566         if (drive_get(IF_PFLASH, 0, 0)) {
 567             error_report("The contents of the first flash device may be "
 568                          "specified with -bios or with -drive if=pflash... "
 569                          "but you cannot use both options at once");
 570             exit(1);
 571         }
 572         fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 573         if (!fn) {
 574             error_report("Could not find ROM image '%s'", bios_name);
 575             exit(1);
 576         }
 577         image_size = load_image_targphys(fn, map[VE_NORFLASH0],
 578                                          VEXPRESS_FLASH_SIZE);
 579         g_free(fn);
 580         if (image_size < 0) {
 581             error_report("Could not load ROM image '%s'", bios_name);
 582             exit(1);
 583         }
 584     }
 585
 586     /* Motherboard peripherals: the wiring is the same but the
 587      * addresses vary between the legacy and A-Series memory maps.
 588      */
 589
 590     sys_id = 0x1190f500;
 591
 592     sysctl = qdev_create(NULL, "realview_sysctl");
 593     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 594     qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
 595     qdev_prop_set_uint32(sysctl, "len-db-voltage",
 596                          daughterboard->num_voltage_sensors);
 597     for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
 598         char *propname = g_strdup_printf("db-voltage[%d]", i);
 599         qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
 600         g_free(propname);
 601     }
 602     qdev_prop_set_uint32(sysctl, "len-db-clock",
 603                          daughterboard->num_clocks);
 604     for (i = 0; i < daughterboard->num_clocks; i++) {
 605         char *propname = g_strdup_printf("db-clock[%d]", i);
 606         qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
 607         g_free(propname);
 608     }
 609     qdev_init_nofail(sysctl);
 610     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
 611
 612     /* VE_SP810: not modelled */
 613     /* VE_SERIALPCI: not modelled */
 614
 615     pl041 = qdev_create(NULL, "pl041");
 616     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 617     qdev_init_nofail(pl041);
 618     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
 619     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
 620
 621     dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
 622     /* Wire up MMC card detect and read-only signals */
 623     qdev_connect_gpio_out(dev, 0,
 624                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
 625     qdev_connect_gpio_out(dev, 1,
 626                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
 627
 628     sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
 629     sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
 630
 631     sysbus_create_simple("pl011", map[VE_UART0], pic[5]);
 632     sysbus_create_simple("pl011", map[VE_UART1], pic[6]);
 633     sysbus_create_simple("pl011", map[VE_UART2], pic[7]);
 634     sysbus_create_simple("pl011", map[VE_UART3], pic[8]);
 635
 636     sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
 637     sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
 638
 639     /* VE_SERIALDVI: not modelled */
 640
 641     sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
 642
 643     /* VE_COMPACTFLASH: not modelled */
 644
 645     sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
 646
 647     dinfo = drive_get_next(IF_PFLASH);
 648     pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
 649                                        dinfo);
 650     if (!pflash0) {
 651         fprintf(stderr, "vexpress: error registering flash 0.\n");
 652         exit(1);
 653     }
 654
 655     if (map[VE_NORFLASHALIAS] != -1) {
 656         /* Map flash 0 as an alias into low memory */
 657         flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
 658         memory_region_init_alias(flashalias, NULL, "vexpress.flashalias",
 659                                  flash0mem, 0, VEXPRESS_FLASH_SIZE);
 660         memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias);
 661     }
 662
 663     dinfo = drive_get_next(IF_PFLASH);
 664     if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
 665                                   dinfo)) {
 666         fprintf(stderr, "vexpress: error registering flash 1.\n");
 667         exit(1);
 668     }
 669
 670     sram_size = 0x2000000;
 671     memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size,
 672                            &error_fatal);
 673     vmstate_register_ram_global(sram);
 674     memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
 675
 676     vram_size = 0x800000;
 677     memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size,
 678                            &error_fatal);
 679     vmstate_register_ram_global(vram);
 680     memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
 681
 682     /* 0x4e000000 LAN9118 Ethernet */
 683     if (nd_table[0].used) {
 684         lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
 685     }
 686
 687     /* VE_USB: not modelled */
 688
 689     /* VE_DAPROM: not modelled */
 690
 691     /* Create mmio transports, so the user can create virtio backends
 692      * (which will be automatically plugged in to the transports). If
 693      * no backend is created the transport will just sit harmlessly idle.
 694      */
 695     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
 696         sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,
 697                              pic[40 + i]);
 698     }
 699
 700     daughterboard->bootinfo.ram_size = machine->ram_size;
 701     daughterboard->bootinfo.kernel_filename = machine->kernel_filename;
 702     daughterboard->bootinfo.kernel_cmdline = machine->kernel_cmdline;
 703     daughterboard->bootinfo.initrd_filename = machine->initrd_filename;
 704     daughterboard->bootinfo.nb_cpus = smp_cpus;
 705     daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
 706     daughterboard->bootinfo.loader_start = daughterboard->loader_start;
 707     daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
 708     daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
 709     daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
 710     daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
 711     /* Indicate that when booting Linux we should be in secure state */
 712     daughterboard->bootinfo.secure_boot = true;
 713     arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo);
 714 }
 715
 716 static bool vexpress_get_secure(Object *obj, Error **errp)
 717 {
 718     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 719
 720     return vms->secure;
 721 }
 722
 723 static void vexpress_set_secure(Object *obj, bool value, Error **errp)
 724 {
 725     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 726
 727     vms->secure = value;
 728 }
 729
 730 static void vexpress_instance_init(Object *obj)
 731 {
 732     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 733
 734     /* EL3 is enabled by default on vexpress */
 735     vms->secure = true;
 736     object_property_add_bool(obj, "secure", vexpress_get_secure,
 737                              vexpress_set_secure, NULL);
 738     object_property_set_description(obj, "secure",
 739                                     "Set on/off to enable/disable the ARM "
 740                                     "Security Extensions (TrustZone)",
 741                                     NULL);
 742 }
 743
 744 static void vexpress_class_init(ObjectClass *oc, void *data)
 745 {
 746     MachineClass *mc = MACHINE_CLASS(oc);
 747
 748     mc->desc = "ARM Versatile Express";
 749     mc->init = vexpress_common_init;
 750     mc->block_default_type = IF_SCSI;
 751     mc->max_cpus = 4;
 752 }
 753
 754 static void vexpress_a9_class_init(ObjectClass *oc, void *data)
 755 {
 756     MachineClass *mc = MACHINE_CLASS(oc);
 757     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
 758
 759     mc->desc = "ARM Versatile Express for Cortex-A9";
 760
 761     vmc->daughterboard = &a9_daughterboard;
 762 }
 763
 764 static void vexpress_a15_class_init(ObjectClass *oc, void *data)
 765 {
 766     MachineClass *mc = MACHINE_CLASS(oc);
 767     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
 768
 769     mc->desc = "ARM Versatile Express for Cortex-A15";
 770
 771     vmc->daughterboard = &a15_daughterboard;
 772 }
 773
 774 static const TypeInfo vexpress_info = {
 775     .name = TYPE_VEXPRESS_MACHINE,
 776     .parent = TYPE_MACHINE,
 777     .abstract = true,
 778     .instance_size = sizeof(VexpressMachineState),
 779     .instance_init = vexpress_instance_init,
 780     .class_size = sizeof(VexpressMachineClass),
 781     .class_init = vexpress_class_init,
 782 };
 783
 784 static const TypeInfo vexpress_a9_info = {
 785     .name = TYPE_VEXPRESS_A9_MACHINE,
 786     .parent = TYPE_VEXPRESS_MACHINE,
 787     .class_init = vexpress_a9_class_init,
 788 };
 789
 790 static const TypeInfo vexpress_a15_info = {
 791     .name = TYPE_VEXPRESS_A15_MACHINE,
 792     .parent = TYPE_VEXPRESS_MACHINE,
 793     .class_init = vexpress_a15_class_init,
 794 };
 795
 796 static void vexpress_machine_init(void)
 797 {
 798     type_register_static(&vexpress_info);
 799     type_register_static(&vexpress_a9_info);
 800     type_register_static(&vexpress_a15_info);
 801 }
 802
 803 machine_init(vexpress_machine_init);