4 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
27 #include "sysemu/reset.h"
28 #include "sysemu/runstate.h"
29 #include "qemu/module.h"
30 #include "qemu/timer.h"
32 #include "hw/ptimer.h"
33 #include "qom/object.h"
37 #define RW_TMR0_DIV 0x00
38 #define R_TMR0_DATA 0x04
39 #define RW_TMR0_CTRL 0x08
40 #define RW_TMR1_DIV 0x10
41 #define R_TMR1_DATA 0x14
42 #define RW_TMR1_CTRL 0x18
44 #define RW_WD_CTRL 0x40
45 #define R_WD_STAT 0x44
46 #define RW_INTR_MASK 0x48
47 #define RW_ACK_INTR 0x4c
49 #define R_MASKED_INTR 0x54
51 #define TYPE_ETRAX_FS_TIMER "etraxfs-timer"
52 typedef struct ETRAXTimerState ETRAXTimerState
;
53 DECLARE_INSTANCE_CHECKER(ETRAXTimerState
, ETRAX_TIMER
,
56 struct ETRAXTimerState
{
57 SysBusDevice parent_obj
;
63 ptimer_state
*ptimer_t0
;
64 ptimer_state
*ptimer_t1
;
65 ptimer_state
*ptimer_wd
;
69 /* Control registers. */
72 uint32_t rw_tmr0_ctrl
;
76 uint32_t rw_tmr1_ctrl
;
80 uint32_t rw_intr_mask
;
83 uint32_t r_masked_intr
;
87 timer_read(void *opaque
, hwaddr addr
, unsigned int size
)
89 ETRAXTimerState
*t
= opaque
;
94 r
= ptimer_get_count(t
->ptimer_t0
);
97 r
= ptimer_get_count(t
->ptimer_t1
);
100 r
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / 10;
106 r
= t
->r_intr
& t
->rw_intr_mask
;
109 D(printf ("%s %x\n", __func__
, addr
));
115 static void update_ctrl(ETRAXTimerState
*t
, int tnum
)
119 unsigned int freq_hz
;
126 ctrl
= t
->rw_tmr0_ctrl
;
127 div
= t
->rw_tmr0_div
;
128 timer
= t
->ptimer_t0
;
130 ctrl
= t
->rw_tmr1_ctrl
;
131 div
= t
->rw_tmr1_div
;
132 timer
= t
->ptimer_t1
;
144 D(printf ("extern or disabled timer clock?\n"));
146 case 4: freq_hz
= 29493000; break;
147 case 5: freq_hz
= 32000000; break;
148 case 6: freq_hz
= 32768000; break;
149 case 7: freq_hz
= 100000000; break;
155 D(printf ("freq_hz=%d div=%d\n", freq_hz
, div
));
156 ptimer_transaction_begin(timer
);
157 ptimer_set_freq(timer
, freq_hz
);
158 ptimer_set_limit(timer
, div
, 0);
164 ptimer_set_limit(timer
, div
, 1);
172 ptimer_run(timer
, 0);
178 ptimer_transaction_commit(timer
);
181 static void timer_update_irq(ETRAXTimerState
*t
)
183 t
->r_intr
&= ~(t
->rw_ack_intr
);
184 t
->r_masked_intr
= t
->r_intr
& t
->rw_intr_mask
;
186 D(printf("%s: masked_intr=%x\n", __func__
, t
->r_masked_intr
));
187 qemu_set_irq(t
->irq
, !!t
->r_masked_intr
);
190 static void timer0_hit(void *opaque
)
192 ETRAXTimerState
*t
= opaque
;
197 static void timer1_hit(void *opaque
)
199 ETRAXTimerState
*t
= opaque
;
204 static void watchdog_hit(void *opaque
)
206 ETRAXTimerState
*t
= opaque
;
207 if (t
->wd_hits
== 0) {
208 /* real hw gives a single tick before reseting but we are
209 a bit friendlier to compensate for our slower execution. */
210 ptimer_set_count(t
->ptimer_wd
, 10);
211 ptimer_run(t
->ptimer_wd
, 1);
212 qemu_irq_raise(t
->nmi
);
215 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
220 static inline void timer_watchdog_update(ETRAXTimerState
*t
, uint32_t value
)
222 unsigned int wd_en
= t
->rw_wd_ctrl
& (1 << 8);
223 unsigned int wd_key
= t
->rw_wd_ctrl
>> 9;
224 unsigned int wd_cnt
= t
->rw_wd_ctrl
& 511;
225 unsigned int new_key
= value
>> 9 & ((1 << 7) - 1);
226 unsigned int new_cmd
= (value
>> 8) & 1;
228 /* If the watchdog is enabled, they written key must match the
229 complement of the previous. */
230 wd_key
= ~wd_key
& ((1 << 7) - 1);
232 if (wd_en
&& wd_key
!= new_key
)
235 D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
236 wd_en
, new_key
, wd_key
, new_cmd
, wd_cnt
));
239 qemu_irq_lower(t
->nmi
);
243 ptimer_transaction_begin(t
->ptimer_wd
);
244 ptimer_set_freq(t
->ptimer_wd
, 760);
247 ptimer_set_count(t
->ptimer_wd
, wd_cnt
);
249 ptimer_run(t
->ptimer_wd
, 1);
251 ptimer_stop(t
->ptimer_wd
);
253 t
->rw_wd_ctrl
= value
;
254 ptimer_transaction_commit(t
->ptimer_wd
);
258 timer_write(void *opaque
, hwaddr addr
,
259 uint64_t val64
, unsigned int size
)
261 ETRAXTimerState
*t
= opaque
;
262 uint32_t value
= val64
;
267 t
->rw_tmr0_div
= value
;
270 D(printf ("RW_TMR0_CTRL=%x\n", value
));
271 t
->rw_tmr0_ctrl
= value
;
275 t
->rw_tmr1_div
= value
;
278 D(printf ("RW_TMR1_CTRL=%x\n", value
));
279 t
->rw_tmr1_ctrl
= value
;
283 D(printf ("RW_INTR_MASK=%x\n", value
));
284 t
->rw_intr_mask
= value
;
288 timer_watchdog_update(t
, value
);
291 t
->rw_ack_intr
= value
;
296 printf ("%s " TARGET_FMT_plx
" %x\n",
297 __func__
, addr
, value
);
302 static const MemoryRegionOps timer_ops
= {
304 .write
= timer_write
,
305 .endianness
= DEVICE_LITTLE_ENDIAN
,
307 .min_access_size
= 4,
312 static void etraxfs_timer_reset_enter(Object
*obj
, ResetType type
)
314 ETRAXTimerState
*t
= ETRAX_TIMER(obj
);
316 ptimer_transaction_begin(t
->ptimer_t0
);
317 ptimer_stop(t
->ptimer_t0
);
318 ptimer_transaction_commit(t
->ptimer_t0
);
319 ptimer_transaction_begin(t
->ptimer_t1
);
320 ptimer_stop(t
->ptimer_t1
);
321 ptimer_transaction_commit(t
->ptimer_t1
);
322 ptimer_transaction_begin(t
->ptimer_wd
);
323 ptimer_stop(t
->ptimer_wd
);
324 ptimer_transaction_commit(t
->ptimer_wd
);
330 static void etraxfs_timer_reset_hold(Object
*obj
)
332 ETRAXTimerState
*t
= ETRAX_TIMER(obj
);
334 qemu_irq_lower(t
->irq
);
337 static void etraxfs_timer_realize(DeviceState
*dev
, Error
**errp
)
339 ETRAXTimerState
*t
= ETRAX_TIMER(dev
);
340 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
342 t
->ptimer_t0
= ptimer_init(timer0_hit
, t
, PTIMER_POLICY_DEFAULT
);
343 t
->ptimer_t1
= ptimer_init(timer1_hit
, t
, PTIMER_POLICY_DEFAULT
);
344 t
->ptimer_wd
= ptimer_init(watchdog_hit
, t
, PTIMER_POLICY_DEFAULT
);
346 sysbus_init_irq(sbd
, &t
->irq
);
347 sysbus_init_irq(sbd
, &t
->nmi
);
349 memory_region_init_io(&t
->mmio
, OBJECT(t
), &timer_ops
, t
,
350 "etraxfs-timer", 0x5c);
351 sysbus_init_mmio(sbd
, &t
->mmio
);
354 static void etraxfs_timer_class_init(ObjectClass
*klass
, void *data
)
356 DeviceClass
*dc
= DEVICE_CLASS(klass
);
357 ResettableClass
*rc
= RESETTABLE_CLASS(klass
);
359 dc
->realize
= etraxfs_timer_realize
;
360 rc
->phases
.enter
= etraxfs_timer_reset_enter
;
361 rc
->phases
.hold
= etraxfs_timer_reset_hold
;
364 static const TypeInfo etraxfs_timer_info
= {
365 .name
= TYPE_ETRAX_FS_TIMER
,
366 .parent
= TYPE_SYS_BUS_DEVICE
,
367 .instance_size
= sizeof(ETRAXTimerState
),
368 .class_init
= etraxfs_timer_class_init
,
371 static void etraxfs_timer_register_types(void)
373 type_register_static(&etraxfs_timer_info
);
376 type_init(etraxfs_timer_register_types
)