hw/rtc/m48t59-isa.c

   1 /*
   2  * QEMU M48T59 and M48T08 NVRAM emulation (ISA bus interface)
   3  *
   4  * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
   5  * Copyright (c) 2013 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/isa/isa.h"
  28 #include "hw/qdev-properties.h"
  29 #include "hw/rtc/m48t59.h"
  30 #include "m48t59-internal.h"
  31 #include "qapi/error.h"
  32 #include "qemu/module.h"
  33 #include "qom/object.h"
  34
  35 #define TYPE_M48TXX_ISA "isa-m48txx"
  36 typedef struct M48txxISADeviceClass M48txxISADeviceClass;
  37 typedef struct M48txxISAState M48txxISAState;
  38 DECLARE_OBJ_CHECKERS(M48txxISAState, M48txxISADeviceClass,
  39                      M48TXX_ISA, TYPE_M48TXX_ISA)
  40
  41 struct M48txxISAState {
  42     ISADevice parent_obj;
  43     M48t59State state;
  44     uint32_t io_base;
  45     MemoryRegion io;
  46 };
  47
  48 struct M48txxISADeviceClass {
  49     ISADeviceClass parent_class;
  50     M48txxInfo info;
  51 };
  52
  53 static M48txxInfo m48txx_isa_info[] = {
  54     {
  55         .bus_name = "isa-m48t59",
  56         .model = 59,
  57         .size = 0x2000,
  58     }
  59 };
  60
  61 static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr)
  62 {
  63     M48txxISAState *d = M48TXX_ISA(obj);
  64     return m48t59_read(&d->state, addr);
  65 }
  66
  67 static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val)
  68 {
  69     M48txxISAState *d = M48TXX_ISA(obj);
  70     m48t59_write(&d->state, addr, val);
  71 }
  72
  73 static void m48txx_isa_toggle_lock(Nvram *obj, int lock)
  74 {
  75     M48txxISAState *d = M48TXX_ISA(obj);
  76     m48t59_toggle_lock(&d->state, lock);
  77 }
  78
  79 static Property m48t59_isa_properties[] = {
  80     DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0),
  81     DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74),
  82     DEFINE_PROP_END_OF_LIST(),
  83 };
  84
  85 static void m48t59_reset_isa(DeviceState *d)
  86 {
  87     M48txxISAState *isa = M48TXX_ISA(d);
  88     M48t59State *NVRAM = &isa->state;
  89
  90     m48t59_reset_common(NVRAM);
  91 }
  92
  93 static void m48t59_isa_realize(DeviceState *dev, Error **errp)
  94 {
  95     M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev);
  96     ISADevice *isadev = ISA_DEVICE(dev);
  97     M48txxISAState *d = M48TXX_ISA(dev);
  98     M48t59State *s = &d->state;
  99
 100     s->model = u->info.model;
 101     s->size = u->info.size;
 102     isa_init_irq(isadev, &s->IRQ, 8);
 103     m48t59_realize_common(s, errp);
 104     memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4);
 105     if (d->io_base != 0) {
 106         isa_register_ioport(isadev, &d->io, d->io_base);
 107     }
 108 }
 109
 110 static void m48txx_isa_class_init(ObjectClass *klass, void *data)
 111 {
 112     DeviceClass *dc = DEVICE_CLASS(klass);
 113     NvramClass *nc = NVRAM_CLASS(klass);
 114
 115     dc->realize = m48t59_isa_realize;
 116     dc->reset = m48t59_reset_isa;
 117     device_class_set_props(dc, m48t59_isa_properties);
 118     nc->read = m48txx_isa_read;
 119     nc->write = m48txx_isa_write;
 120     nc->toggle_lock = m48txx_isa_toggle_lock;
 121 }
 122
 123 static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data)
 124 {
 125     M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass);
 126     M48txxInfo *info = data;
 127
 128     u->info = *info;
 129 }
 130
 131 static const TypeInfo m48txx_isa_type_info = {
 132     .name = TYPE_M48TXX_ISA,
 133     .parent = TYPE_ISA_DEVICE,
 134     .instance_size = sizeof(M48txxISAState),
 135     .abstract = true,
 136     .class_init = m48txx_isa_class_init,
 137     .interfaces = (InterfaceInfo[]) {
 138         { TYPE_NVRAM },
 139         { }
 140     }
 141 };
 142
 143 static void m48t59_isa_register_types(void)
 144 {
 145     TypeInfo isa_type_info = {
 146         .parent = TYPE_M48TXX_ISA,
 147         .class_size = sizeof(M48txxISADeviceClass),
 148         .class_init = m48txx_isa_concrete_class_init,
 149     };
 150     int i;
 151
 152     type_register_static(&m48txx_isa_type_info);
 153
 154     for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) {
 155         isa_type_info.name = m48txx_isa_info[i].bus_name;
 156         isa_type_info.class_data = &m48txx_isa_info[i];
 157         type_register(&isa_type_info);
 158     }
 159 }
 160
 161 type_init(m48t59_isa_register_types)