| blob | 2f4e463bb62c6f3c7706b394d0d523349037192d |
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
21 #include "disas/dis-asm.h"
22 #include "exec/gdbstub.h"
23 #include "kvm_ppc.h"
24 #include "sysemu/arch_init.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/tcg.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "qemu/qemu-print.h"
34 #include "qapi/error.h"
35 #include "qapi/qmp/qnull.h"
36 #include "qapi/visitor.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/ppc/ppc.h"
39 #include "mmu-book3s-v3.h"
40 #include "qemu/cutils.h"
41 #include "disas/capstone.h"
42 #include "fpu/softfloat.h"
43 #include "qapi/qapi-commands-machine-target.h"
45 /* #define PPC_DEBUG_SPR */
46 /* #define USE_APPLE_GDB */
48 static inline void vscr_init(CPUPPCState *env, uint32_t val)
49 {
50 /* Altivec always uses round-to-nearest */
51 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
52 helper_mtvscr(env, val);
53 }
55 /**
56 * _spr_register
57 *
58 * Register an SPR with all the callbacks required for tcg,
59 * and the ID number for KVM.
60 *
61 * The reason for the conditional compilation is that the tcg functions
62 * may be compiled out, and the system kvm header may not be available
63 * for supplying the ID numbers. This is ugly, but the best we can do.
64 */
66 #ifdef CONFIG_TCG
67 # define USR_ARG(X) X,
68 # ifdef CONFIG_USER_ONLY
69 # define SYS_ARG(X)
70 # else
71 # define SYS_ARG(X) X,
72 # endif
73 #else
74 # define USR_ARG(X)
75 # define SYS_ARG(X)
76 #endif
77 #ifdef CONFIG_KVM
78 # define KVM_ARG(X) X,
79 #else
80 # define KVM_ARG(X)
81 #endif
83 typedef void spr_callback(DisasContext *, int, int);
85 static void _spr_register(CPUPPCState *env, int num, const char *name,
86 USR_ARG(spr_callback *uea_read)
87 USR_ARG(spr_callback *uea_write)
88 SYS_ARG(spr_callback *oea_read)
89 SYS_ARG(spr_callback *oea_write)
90 SYS_ARG(spr_callback *hea_read)
91 SYS_ARG(spr_callback *hea_write)
92 KVM_ARG(uint64_t one_reg_id)
93 target_ulong initial_value)
94 {
95 ppc_spr_t *spr = &env->spr_cb[num];
97 /* No SPR should be registered twice. */
98 assert(spr->name == NULL);
99 assert(name != NULL);
101 spr->name = name;
102 spr->default_value = initial_value;
103 env->spr[num] = initial_value;
105 #ifdef CONFIG_TCG
106 spr->uea_read = uea_read;
107 spr->uea_write = uea_write;
108 # ifndef CONFIG_USER_ONLY
109 spr->oea_read = oea_read;
110 spr->oea_write = oea_write;
111 spr->hea_read = hea_read;
112 spr->hea_write = hea_write;
113 # endif
114 #endif
115 #ifdef CONFIG_KVM
116 spr->one_reg_id = one_reg_id;
117 #endif
118 }
120 /* spr_register_kvm_hv passes all required arguments. */
121 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
122 oea_read, oea_write, hea_read, hea_write, \
123 one_reg_id, initial_value) \
124 _spr_register(env, num, name, \
125 USR_ARG(uea_read) USR_ARG(uea_write) \
126 SYS_ARG(oea_read) SYS_ARG(oea_write) \
127 SYS_ARG(hea_read) SYS_ARG(hea_write) \
128 KVM_ARG(one_reg_id) initial_value)
130 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */
131 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
132 oea_read, oea_write, one_reg_id, ival) \
133 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
134 oea_write, oea_read, oea_write, one_reg_id, ival)
136 /* spr_register_hv and spr_register are similar, except there is no kvm id. */
137 #define spr_register_hv(env, num, name, uea_read, uea_write, \
138 oea_read, oea_write, hea_read, hea_write, ival) \
139 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
140 oea_write, hea_read, hea_write, 0, ival)
142 #define spr_register(env, num, name, uea_read, uea_write, \
143 oea_read, oea_write, ival) \
144 spr_register_kvm(env, num, name, uea_read, uea_write, \
145 oea_read, oea_write, 0, ival)
147 /* Generic PowerPC SPRs */
148 static void register_generic_sprs(CPUPPCState *env)
149 {
150 /* Integer processing */
151 spr_register(env, SPR_XER, "XER",
152 &spr_read_xer, &spr_write_xer,
153 &spr_read_xer, &spr_write_xer,
154 0x00000000);
155 /* Branch control */
156 spr_register(env, SPR_LR, "LR",
157 &spr_read_lr, &spr_write_lr,
158 &spr_read_lr, &spr_write_lr,
159 0x00000000);
160 spr_register(env, SPR_CTR, "CTR",
161 &spr_read_ctr, &spr_write_ctr,
162 &spr_read_ctr, &spr_write_ctr,
163 0x00000000);
164 /* Interrupt processing */
165 spr_register(env, SPR_SRR0, "SRR0",
166 SPR_NOACCESS, SPR_NOACCESS,
167 &spr_read_generic, &spr_write_generic,
168 0x00000000);
169 spr_register(env, SPR_SRR1, "SRR1",
170 SPR_NOACCESS, SPR_NOACCESS,
171 &spr_read_generic, &spr_write_generic,
172 0x00000000);
173 /* Processor control */
174 spr_register(env, SPR_SPRG0, "SPRG0",
175 SPR_NOACCESS, SPR_NOACCESS,
176 &spr_read_generic, &spr_write_generic,
177 0x00000000);
178 spr_register(env, SPR_SPRG1, "SPRG1",
179 SPR_NOACCESS, SPR_NOACCESS,
180 &spr_read_generic, &spr_write_generic,
181 0x00000000);
182 spr_register(env, SPR_SPRG2, "SPRG2",
183 SPR_NOACCESS, SPR_NOACCESS,
184 &spr_read_generic, &spr_write_generic,
185 0x00000000);
186 spr_register(env, SPR_SPRG3, "SPRG3",
187 SPR_NOACCESS, SPR_NOACCESS,
188 &spr_read_generic, &spr_write_generic,
189 0x00000000);
190 }
192 /* SPR common to all non-embedded PowerPC, including 601 */
193 static void register_ne_601_sprs(CPUPPCState *env)
194 {
195 /* Exception processing */
196 spr_register_kvm(env, SPR_DSISR, "DSISR",
197 SPR_NOACCESS, SPR_NOACCESS,
198 &spr_read_generic, &spr_write_generic,
199 KVM_REG_PPC_DSISR, 0x00000000);
200 spr_register_kvm(env, SPR_DAR, "DAR",
201 SPR_NOACCESS, SPR_NOACCESS,
202 &spr_read_generic, &spr_write_generic,
203 KVM_REG_PPC_DAR, 0x00000000);
204 /* Timer */
205 spr_register(env, SPR_DECR, "DECR",
206 SPR_NOACCESS, SPR_NOACCESS,
207 &spr_read_decr, &spr_write_decr,
208 0x00000000);
209 }
211 /* Storage Description Register 1 */
212 static void register_sdr1_sprs(CPUPPCState *env)
213 {
214 #ifndef CONFIG_USER_ONLY
215 if (env->has_hv_mode) {
216 /*
217 * SDR1 is a hypervisor resource on CPUs which have a
218 * hypervisor mode
219 */
220 spr_register_hv(env, SPR_SDR1, "SDR1",
221 SPR_NOACCESS, SPR_NOACCESS,
222 SPR_NOACCESS, SPR_NOACCESS,
223 &spr_read_generic, &spr_write_sdr1,
224 0x00000000);
225 } else {
226 spr_register(env, SPR_SDR1, "SDR1",
227 SPR_NOACCESS, SPR_NOACCESS,
228 &spr_read_generic, &spr_write_sdr1,
229 0x00000000);
230 }
231 #endif
232 }
234 /* BATs 0-3 */
235 static void register_low_BATs(CPUPPCState *env)
236 {
237 #if !defined(CONFIG_USER_ONLY)
238 spr_register(env, SPR_IBAT0U, "IBAT0U",
239 SPR_NOACCESS, SPR_NOACCESS,
240 &spr_read_ibat, &spr_write_ibatu,
241 0x00000000);
242 spr_register(env, SPR_IBAT0L, "IBAT0L",
243 SPR_NOACCESS, SPR_NOACCESS,
244 &spr_read_ibat, &spr_write_ibatl,
245 0x00000000);
246 spr_register(env, SPR_IBAT1U, "IBAT1U",
247 SPR_NOACCESS, SPR_NOACCESS,
248 &spr_read_ibat, &spr_write_ibatu,
249 0x00000000);
250 spr_register(env, SPR_IBAT1L, "IBAT1L",
251 SPR_NOACCESS, SPR_NOACCESS,
252 &spr_read_ibat, &spr_write_ibatl,
253 0x00000000);
254 spr_register(env, SPR_IBAT2U, "IBAT2U",
255 SPR_NOACCESS, SPR_NOACCESS,
256 &spr_read_ibat, &spr_write_ibatu,
257 0x00000000);
258 spr_register(env, SPR_IBAT2L, "IBAT2L",
259 SPR_NOACCESS, SPR_NOACCESS,
260 &spr_read_ibat, &spr_write_ibatl,
261 0x00000000);
262 spr_register(env, SPR_IBAT3U, "IBAT3U",
263 SPR_NOACCESS, SPR_NOACCESS,
264 &spr_read_ibat, &spr_write_ibatu,
265 0x00000000);
266 spr_register(env, SPR_IBAT3L, "IBAT3L",
267 SPR_NOACCESS, SPR_NOACCESS,
268 &spr_read_ibat, &spr_write_ibatl,
269 0x00000000);
270 spr_register(env, SPR_DBAT0U, "DBAT0U",
271 SPR_NOACCESS, SPR_NOACCESS,
272 &spr_read_dbat, &spr_write_dbatu,
273 0x00000000);
274 spr_register(env, SPR_DBAT0L, "DBAT0L",
275 SPR_NOACCESS, SPR_NOACCESS,
276 &spr_read_dbat, &spr_write_dbatl,
277 0x00000000);
278 spr_register(env, SPR_DBAT1U, "DBAT1U",
279 SPR_NOACCESS, SPR_NOACCESS,
280 &spr_read_dbat, &spr_write_dbatu,
281 0x00000000);
282 spr_register(env, SPR_DBAT1L, "DBAT1L",
283 SPR_NOACCESS, SPR_NOACCESS,
284 &spr_read_dbat, &spr_write_dbatl,
285 0x00000000);
286 spr_register(env, SPR_DBAT2U, "DBAT2U",
287 SPR_NOACCESS, SPR_NOACCESS,
288 &spr_read_dbat, &spr_write_dbatu,
289 0x00000000);
290 spr_register(env, SPR_DBAT2L, "DBAT2L",
291 SPR_NOACCESS, SPR_NOACCESS,
292 &spr_read_dbat, &spr_write_dbatl,
293 0x00000000);
294 spr_register(env, SPR_DBAT3U, "DBAT3U",
295 SPR_NOACCESS, SPR_NOACCESS,
296 &spr_read_dbat, &spr_write_dbatu,
297 0x00000000);
298 spr_register(env, SPR_DBAT3L, "DBAT3L",
299 SPR_NOACCESS, SPR_NOACCESS,
300 &spr_read_dbat, &spr_write_dbatl,
301 0x00000000);
302 env->nb_BATs += 4;
303 #endif
304 }
306 /* BATs 4-7 */
307 static void register_high_BATs(CPUPPCState *env)
308 {
309 #if !defined(CONFIG_USER_ONLY)
310 spr_register(env, SPR_IBAT4U, "IBAT4U",
311 SPR_NOACCESS, SPR_NOACCESS,
312 &spr_read_ibat_h, &spr_write_ibatu_h,
313 0x00000000);
314 spr_register(env, SPR_IBAT4L, "IBAT4L",
315 SPR_NOACCESS, SPR_NOACCESS,
316 &spr_read_ibat_h, &spr_write_ibatl_h,
317 0x00000000);
318 spr_register(env, SPR_IBAT5U, "IBAT5U",
319 SPR_NOACCESS, SPR_NOACCESS,
320 &spr_read_ibat_h, &spr_write_ibatu_h,
321 0x00000000);
322 spr_register(env, SPR_IBAT5L, "IBAT5L",
323 SPR_NOACCESS, SPR_NOACCESS,
324 &spr_read_ibat_h, &spr_write_ibatl_h,
325 0x00000000);
326 spr_register(env, SPR_IBAT6U, "IBAT6U",
327 SPR_NOACCESS, SPR_NOACCESS,
328 &spr_read_ibat_h, &spr_write_ibatu_h,
329 0x00000000);
330 spr_register(env, SPR_IBAT6L, "IBAT6L",
331 SPR_NOACCESS, SPR_NOACCESS,
332 &spr_read_ibat_h, &spr_write_ibatl_h,
333 0x00000000);
334 spr_register(env, SPR_IBAT7U, "IBAT7U",
335 SPR_NOACCESS, SPR_NOACCESS,
336 &spr_read_ibat_h, &spr_write_ibatu_h,
337 0x00000000);
338 spr_register(env, SPR_IBAT7L, "IBAT7L",
339 SPR_NOACCESS, SPR_NOACCESS,
340 &spr_read_ibat_h, &spr_write_ibatl_h,
341 0x00000000);
342 spr_register(env, SPR_DBAT4U, "DBAT4U",
343 SPR_NOACCESS, SPR_NOACCESS,
344 &spr_read_dbat_h, &spr_write_dbatu_h,
345 0x00000000);
346 spr_register(env, SPR_DBAT4L, "DBAT4L",
347 SPR_NOACCESS, SPR_NOACCESS,
348 &spr_read_dbat_h, &spr_write_dbatl_h,
349 0x00000000);
350 spr_register(env, SPR_DBAT5U, "DBAT5U",
351 SPR_NOACCESS, SPR_NOACCESS,
352 &spr_read_dbat_h, &spr_write_dbatu_h,
353 0x00000000);
354 spr_register(env, SPR_DBAT5L, "DBAT5L",
355 SPR_NOACCESS, SPR_NOACCESS,
356 &spr_read_dbat_h, &spr_write_dbatl_h,
357 0x00000000);
358 spr_register(env, SPR_DBAT6U, "DBAT6U",
359 SPR_NOACCESS, SPR_NOACCESS,
360 &spr_read_dbat_h, &spr_write_dbatu_h,
361 0x00000000);
362 spr_register(env, SPR_DBAT6L, "DBAT6L",
363 SPR_NOACCESS, SPR_NOACCESS,
364 &spr_read_dbat_h, &spr_write_dbatl_h,
365 0x00000000);
366 spr_register(env, SPR_DBAT7U, "DBAT7U",
367 SPR_NOACCESS, SPR_NOACCESS,
368 &spr_read_dbat_h, &spr_write_dbatu_h,
369 0x00000000);
370 spr_register(env, SPR_DBAT7L, "DBAT7L",
371 SPR_NOACCESS, SPR_NOACCESS,
372 &spr_read_dbat_h, &spr_write_dbatl_h,
373 0x00000000);
374 env->nb_BATs += 4;
375 #endif
376 }
378 /* Generic PowerPC time base */
379 static void register_tbl(CPUPPCState *env)
380 {
381 spr_register(env, SPR_VTBL, "TBL",
382 &spr_read_tbl, SPR_NOACCESS,
383 &spr_read_tbl, SPR_NOACCESS,
384 0x00000000);
385 spr_register(env, SPR_TBL, "TBL",
386 &spr_read_tbl, SPR_NOACCESS,
387 &spr_read_tbl, &spr_write_tbl,
388 0x00000000);
389 spr_register(env, SPR_VTBU, "TBU",
390 &spr_read_tbu, SPR_NOACCESS,
391 &spr_read_tbu, SPR_NOACCESS,
392 0x00000000);
393 spr_register(env, SPR_TBU, "TBU",
394 &spr_read_tbu, SPR_NOACCESS,
395 &spr_read_tbu, &spr_write_tbu,
396 0x00000000);
397 }
399 /* Softare table search registers */
400 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
401 {
402 #if !defined(CONFIG_USER_ONLY)
403 env->nb_tlb = nb_tlbs;
404 env->nb_ways = nb_ways;
405 env->id_tlbs = 1;
406 env->tlb_type = TLB_6XX;
407 spr_register(env, SPR_DMISS, "DMISS",
408 SPR_NOACCESS, SPR_NOACCESS,
409 &spr_read_generic, SPR_NOACCESS,
410 0x00000000);
411 spr_register(env, SPR_DCMP, "DCMP",
412 SPR_NOACCESS, SPR_NOACCESS,
413 &spr_read_generic, SPR_NOACCESS,
414 0x00000000);
415 spr_register(env, SPR_HASH1, "HASH1",
416 SPR_NOACCESS, SPR_NOACCESS,
417 &spr_read_generic, SPR_NOACCESS,
418 0x00000000);
419 spr_register(env, SPR_HASH2, "HASH2",
420 SPR_NOACCESS, SPR_NOACCESS,
421 &spr_read_generic, SPR_NOACCESS,
422 0x00000000);
423 spr_register(env, SPR_IMISS, "IMISS",
424 SPR_NOACCESS, SPR_NOACCESS,
425 &spr_read_generic, SPR_NOACCESS,
426 0x00000000);
427 spr_register(env, SPR_ICMP, "ICMP",
428 SPR_NOACCESS, SPR_NOACCESS,
429 &spr_read_generic, SPR_NOACCESS,
430 0x00000000);
431 spr_register(env, SPR_RPA, "RPA",
432 SPR_NOACCESS, SPR_NOACCESS,
433 &spr_read_generic, &spr_write_generic,
434 0x00000000);
435 #endif
436 }
438 /* SPR common to MPC755 and G2 */
439 static void register_G2_755_sprs(CPUPPCState *env)
440 {
441 /* SGPRs */
442 spr_register(env, SPR_SPRG4, "SPRG4",
443 SPR_NOACCESS, SPR_NOACCESS,
444 &spr_read_generic, &spr_write_generic,
445 0x00000000);
446 spr_register(env, SPR_SPRG5, "SPRG5",
447 SPR_NOACCESS, SPR_NOACCESS,
448 &spr_read_generic, &spr_write_generic,
449 0x00000000);
450 spr_register(env, SPR_SPRG6, "SPRG6",
451 SPR_NOACCESS, SPR_NOACCESS,
452 &spr_read_generic, &spr_write_generic,
453 0x00000000);
454 spr_register(env, SPR_SPRG7, "SPRG7",
455 SPR_NOACCESS, SPR_NOACCESS,
456 &spr_read_generic, &spr_write_generic,
457 0x00000000);
458 }
460 /* SPR common to all 7xx PowerPC implementations */
461 static void register_7xx_sprs(CPUPPCState *env)
462 {
463 /* Breakpoints */
464 /* XXX : not implemented */
465 spr_register_kvm(env, SPR_DABR, "DABR",
466 SPR_NOACCESS, SPR_NOACCESS,
467 &spr_read_generic, &spr_write_generic,
468 KVM_REG_PPC_DABR, 0x00000000);
469 /* XXX : not implemented */
470 spr_register(env, SPR_IABR, "IABR",
471 SPR_NOACCESS, SPR_NOACCESS,
472 &spr_read_generic, &spr_write_generic,
473 0x00000000);
474 /* Cache management */
475 /* XXX : not implemented */
476 spr_register(env, SPR_ICTC, "ICTC",
477 SPR_NOACCESS, SPR_NOACCESS,
478 &spr_read_generic, &spr_write_generic,
479 0x00000000);
480 /* Performance monitors */
481 /* XXX : not implemented */
482 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
483 SPR_NOACCESS, SPR_NOACCESS,
484 &spr_read_generic, &spr_write_generic,
485 0x00000000);
486 /* XXX : not implemented */
487 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
488 SPR_NOACCESS, SPR_NOACCESS,
489 &spr_read_generic, &spr_write_generic,
490 0x00000000);
491 /* XXX : not implemented */
492 spr_register(env, SPR_7XX_PMC1, "PMC1",
493 SPR_NOACCESS, SPR_NOACCESS,
494 &spr_read_generic, &spr_write_generic,
495 0x00000000);
496 /* XXX : not implemented */
497 spr_register(env, SPR_7XX_PMC2, "PMC2",
498 SPR_NOACCESS, SPR_NOACCESS,
499 &spr_read_generic, &spr_write_generic,
500 0x00000000);
501 /* XXX : not implemented */
502 spr_register(env, SPR_7XX_PMC3, "PMC3",
503 SPR_NOACCESS, SPR_NOACCESS,
504 &spr_read_generic, &spr_write_generic,
505 0x00000000);
506 /* XXX : not implemented */
507 spr_register(env, SPR_7XX_PMC4, "PMC4",
508 SPR_NOACCESS, SPR_NOACCESS,
509 &spr_read_generic, &spr_write_generic,
510 0x00000000);
511 /* XXX : not implemented */
512 spr_register(env, SPR_7XX_SIAR, "SIAR",
513 SPR_NOACCESS, SPR_NOACCESS,
514 &spr_read_generic, SPR_NOACCESS,
515 0x00000000);
516 /* XXX : not implemented */
517 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
518 &spr_read_ureg, SPR_NOACCESS,
519 &spr_read_ureg, SPR_NOACCESS,
520 0x00000000);
521 /* XXX : not implemented */
522 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
523 &spr_read_ureg, SPR_NOACCESS,
524 &spr_read_ureg, SPR_NOACCESS,
525 0x00000000);
526 /* XXX : not implemented */
527 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
528 &spr_read_ureg, SPR_NOACCESS,
529 &spr_read_ureg, SPR_NOACCESS,
530 0x00000000);
531 /* XXX : not implemented */
532 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
533 &spr_read_ureg, SPR_NOACCESS,
534 &spr_read_ureg, SPR_NOACCESS,
535 0x00000000);
536 /* XXX : not implemented */
537 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
538 &spr_read_ureg, SPR_NOACCESS,
539 &spr_read_ureg, SPR_NOACCESS,
540 0x00000000);
541 /* XXX : not implemented */
542 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
543 &spr_read_ureg, SPR_NOACCESS,
544 &spr_read_ureg, SPR_NOACCESS,
545 0x00000000);
546 /* XXX : not implemented */
547 spr_register(env, SPR_7XX_USIAR, "USIAR",
548 &spr_read_ureg, SPR_NOACCESS,
549 &spr_read_ureg, SPR_NOACCESS,
550 0x00000000);
551 /* External access control */
552 /* XXX : not implemented */
553 spr_register(env, SPR_EAR, "EAR",
554 SPR_NOACCESS, SPR_NOACCESS,
555 &spr_read_generic, &spr_write_generic,
556 0x00000000);
557 }
559 #ifdef TARGET_PPC64
560 static void register_amr_sprs(CPUPPCState *env)
561 {
562 #ifndef CONFIG_USER_ONLY
563 /*
564 * Virtual Page Class Key protection
565 *
566 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
567 * userspace accessible, 29 is privileged. So we only need to set
568 * the kvm ONE_REG id on one of them, we use 29
569 */
570 spr_register(env, SPR_UAMR, "UAMR",
571 &spr_read_generic, &spr_write_amr,
572 &spr_read_generic, &spr_write_amr,
573 0);
574 spr_register_kvm_hv(env, SPR_AMR, "AMR",
575 SPR_NOACCESS, SPR_NOACCESS,
576 &spr_read_generic, &spr_write_amr,
577 &spr_read_generic, &spr_write_generic,
578 KVM_REG_PPC_AMR, 0);
579 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
580 SPR_NOACCESS, SPR_NOACCESS,
581 &spr_read_generic, &spr_write_uamor,
582 &spr_read_generic, &spr_write_generic,
583 KVM_REG_PPC_UAMOR, 0);
584 spr_register_hv(env, SPR_AMOR, "AMOR",
585 SPR_NOACCESS, SPR_NOACCESS,
586 SPR_NOACCESS, SPR_NOACCESS,
587 &spr_read_generic, &spr_write_generic,
588 0);
589 #endif /* !CONFIG_USER_ONLY */
590 }
592 static void register_iamr_sprs(CPUPPCState *env)
593 {
594 #ifndef CONFIG_USER_ONLY
595 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
596 SPR_NOACCESS, SPR_NOACCESS,
597 &spr_read_generic, &spr_write_iamr,
598 &spr_read_generic, &spr_write_generic,
599 KVM_REG_PPC_IAMR, 0);
600 #endif /* !CONFIG_USER_ONLY */
601 }
602 #endif /* TARGET_PPC64 */
604 static void register_thrm_sprs(CPUPPCState *env)
605 {
606 /* Thermal management */
607 /* XXX : not implemented */
608 spr_register(env, SPR_THRM1, "THRM1",
609 SPR_NOACCESS, SPR_NOACCESS,
610 &spr_read_thrm, &spr_write_generic,
611 0x00000000);
612 /* XXX : not implemented */
613 spr_register(env, SPR_THRM2, "THRM2",
614 SPR_NOACCESS, SPR_NOACCESS,
615 &spr_read_thrm, &spr_write_generic,
616 0x00000000);
617 /* XXX : not implemented */
618 spr_register(env, SPR_THRM3, "THRM3",
619 SPR_NOACCESS, SPR_NOACCESS,
620 &spr_read_thrm, &spr_write_generic,
621 0x00000000);
622 }
624 /* SPR specific to PowerPC 604 implementation */
625 static void register_604_sprs(CPUPPCState *env)
626 {
627 /* Processor identification */
628 spr_register(env, SPR_PIR, "PIR",
629 SPR_NOACCESS, SPR_NOACCESS,
630 &spr_read_generic, &spr_write_pir,
631 0x00000000);
632 /* Breakpoints */
633 /* XXX : not implemented */
634 spr_register(env, SPR_IABR, "IABR",
635 SPR_NOACCESS, SPR_NOACCESS,
636 &spr_read_generic, &spr_write_generic,
637 0x00000000);
638 /* XXX : not implemented */
639 spr_register_kvm(env, SPR_DABR, "DABR",
640 SPR_NOACCESS, SPR_NOACCESS,
641 &spr_read_generic, &spr_write_generic,
642 KVM_REG_PPC_DABR, 0x00000000);
643 /* Performance counters */
644 /* XXX : not implemented */
645 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
646 SPR_NOACCESS, SPR_NOACCESS,
647 &spr_read_generic, &spr_write_generic,
648 0x00000000);
649 /* XXX : not implemented */
650 spr_register(env, SPR_7XX_PMC1, "PMC1",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_generic, &spr_write_generic,
653 0x00000000);
654 /* XXX : not implemented */
655 spr_register(env, SPR_7XX_PMC2, "PMC2",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 /* XXX : not implemented */
660 spr_register(env, SPR_7XX_SIAR, "SIAR",
661 SPR_NOACCESS, SPR_NOACCESS,
662 &spr_read_generic, SPR_NOACCESS,
663 0x00000000);
664 /* XXX : not implemented */
665 spr_register(env, SPR_SDA, "SDA",
666 SPR_NOACCESS, SPR_NOACCESS,
667 &spr_read_generic, SPR_NOACCESS,
668 0x00000000);
669 /* External access control */
670 /* XXX : not implemented */
671 spr_register(env, SPR_EAR, "EAR",
672 SPR_NOACCESS, SPR_NOACCESS,
673 &spr_read_generic, &spr_write_generic,
674 0x00000000);
675 }
677 /* SPR specific to PowerPC 603 implementation */
678 static void register_603_sprs(CPUPPCState *env)
679 {
680 /* External access control */
681 /* XXX : not implemented */
682 spr_register(env, SPR_EAR, "EAR",
683 SPR_NOACCESS, SPR_NOACCESS,
684 &spr_read_generic, &spr_write_generic,
685 0x00000000);
686 /* Breakpoints */
687 /* XXX : not implemented */
688 spr_register(env, SPR_IABR, "IABR",
689 SPR_NOACCESS, SPR_NOACCESS,
690 &spr_read_generic, &spr_write_generic,
691 0x00000000);
693 }
695 /* SPR specific to PowerPC G2 implementation */
696 static void register_G2_sprs(CPUPPCState *env)
697 {
698 /* Memory base address */
699 /* MBAR */
700 /* XXX : not implemented */
701 spr_register(env, SPR_MBAR, "MBAR",
702 SPR_NOACCESS, SPR_NOACCESS,
703 &spr_read_generic, &spr_write_generic,
704 0x00000000);
705 /* Exception processing */
706 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
707 SPR_NOACCESS, SPR_NOACCESS,
708 &spr_read_generic, &spr_write_generic,
709 0x00000000);
710 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_generic, &spr_write_generic,
713 0x00000000);
714 /* Breakpoints */
715 /* XXX : not implemented */
716 spr_register(env, SPR_DABR, "DABR",
717 SPR_NOACCESS, SPR_NOACCESS,
718 &spr_read_generic, &spr_write_generic,
719 0x00000000);
720 /* XXX : not implemented */
721 spr_register(env, SPR_DABR2, "DABR2",
722 SPR_NOACCESS, SPR_NOACCESS,
723 &spr_read_generic, &spr_write_generic,
724 0x00000000);
725 /* XXX : not implemented */
726 spr_register(env, SPR_IABR, "IABR",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_generic, &spr_write_generic,
729 0x00000000);
730 /* XXX : not implemented */
731 spr_register(env, SPR_IABR2, "IABR2",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_generic, &spr_write_generic,
734 0x00000000);
735 /* XXX : not implemented */
736 spr_register(env, SPR_IBCR, "IBCR",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_generic, &spr_write_generic,
739 0x00000000);
740 /* XXX : not implemented */
741 spr_register(env, SPR_DBCR, "DBCR",
742 SPR_NOACCESS, SPR_NOACCESS,
743 &spr_read_generic, &spr_write_generic,
744 0x00000000);
745 }
747 /* SPR specific to PowerPC 602 implementation */
748 static void register_602_sprs(CPUPPCState *env)
749 {
750 /* ESA registers */
751 /* XXX : not implemented */
752 spr_register(env, SPR_SER, "SER",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_generic, &spr_write_generic,
755 0x00000000);
756 /* XXX : not implemented */
757 spr_register(env, SPR_SEBR, "SEBR",
758 SPR_NOACCESS, SPR_NOACCESS,
759 &spr_read_generic, &spr_write_generic,
760 0x00000000);
761 /* XXX : not implemented */
762 spr_register(env, SPR_ESASRR, "ESASRR",
763 SPR_NOACCESS, SPR_NOACCESS,
764 &spr_read_generic, &spr_write_generic,
765 0x00000000);
766 /* Floating point status */
767 /* XXX : not implemented */
768 spr_register(env, SPR_SP, "SP",
769 SPR_NOACCESS, SPR_NOACCESS,
770 &spr_read_generic, &spr_write_generic,
771 0x00000000);
772 /* XXX : not implemented */
773 spr_register(env, SPR_LT, "LT",
774 SPR_NOACCESS, SPR_NOACCESS,
775 &spr_read_generic, &spr_write_generic,
776 0x00000000);
777 /* Watchdog timer */
778 /* XXX : not implemented */
779 spr_register(env, SPR_TCR, "TCR",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_generic, &spr_write_generic,
782 0x00000000);
783 /* Interrupt base */
784 spr_register(env, SPR_IBR, "IBR",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_generic, &spr_write_generic,
787 0x00000000);
788 /* XXX : not implemented */
789 spr_register(env, SPR_IABR, "IABR",
790 SPR_NOACCESS, SPR_NOACCESS,
791 &spr_read_generic, &spr_write_generic,
792 0x00000000);
793 }
795 /* SPR specific to PowerPC 601 implementation */
796 static void register_601_sprs(CPUPPCState *env)
797 {
798 /* Multiplication/division register */
799 /* MQ */
800 spr_register(env, SPR_MQ, "MQ",
801 &spr_read_generic, &spr_write_generic,
802 &spr_read_generic, &spr_write_generic,
803 0x00000000);
804 /* RTC registers */
805 spr_register(env, SPR_601_RTCU, "RTCU",
806 SPR_NOACCESS, SPR_NOACCESS,
807 SPR_NOACCESS, &spr_write_601_rtcu,
808 0x00000000);
809 spr_register(env, SPR_601_VRTCU, "RTCU",
810 &spr_read_601_rtcu, SPR_NOACCESS,
811 &spr_read_601_rtcu, SPR_NOACCESS,
812 0x00000000);
813 spr_register(env, SPR_601_RTCL, "RTCL",
814 SPR_NOACCESS, SPR_NOACCESS,
815 SPR_NOACCESS, &spr_write_601_rtcl,
816 0x00000000);
817 spr_register(env, SPR_601_VRTCL, "RTCL",
818 &spr_read_601_rtcl, SPR_NOACCESS,
819 &spr_read_601_rtcl, SPR_NOACCESS,
820 0x00000000);
821 /* Timer */
822 #if 0 /* ? */
823 spr_register(env, SPR_601_UDECR, "UDECR",
824 &spr_read_decr, SPR_NOACCESS,
825 &spr_read_decr, SPR_NOACCESS,
826 0x00000000);
827 #endif
828 /* External access control */
829 /* XXX : not implemented */
830 spr_register(env, SPR_EAR, "EAR",
831 SPR_NOACCESS, SPR_NOACCESS,
832 &spr_read_generic, &spr_write_generic,
833 0x00000000);
834 /* Memory management */
835 #if !defined(CONFIG_USER_ONLY)
836 spr_register(env, SPR_IBAT0U, "IBAT0U",
837 SPR_NOACCESS, SPR_NOACCESS,
838 &spr_read_601_ubat, &spr_write_601_ubatu,
839 0x00000000);
840 spr_register(env, SPR_IBAT0L, "IBAT0L",
841 SPR_NOACCESS, SPR_NOACCESS,
842 &spr_read_601_ubat, &spr_write_601_ubatl,
843 0x00000000);
844 spr_register(env, SPR_IBAT1U, "IBAT1U",
845 SPR_NOACCESS, SPR_NOACCESS,
846 &spr_read_601_ubat, &spr_write_601_ubatu,
847 0x00000000);
848 spr_register(env, SPR_IBAT1L, "IBAT1L",
849 SPR_NOACCESS, SPR_NOACCESS,
850 &spr_read_601_ubat, &spr_write_601_ubatl,
851 0x00000000);
852 spr_register(env, SPR_IBAT2U, "IBAT2U",
853 SPR_NOACCESS, SPR_NOACCESS,
854 &spr_read_601_ubat, &spr_write_601_ubatu,
855 0x00000000);
856 spr_register(env, SPR_IBAT2L, "IBAT2L",
857 SPR_NOACCESS, SPR_NOACCESS,
858 &spr_read_601_ubat, &spr_write_601_ubatl,
859 0x00000000);
860 spr_register(env, SPR_IBAT3U, "IBAT3U",
861 SPR_NOACCESS, SPR_NOACCESS,
862 &spr_read_601_ubat, &spr_write_601_ubatu,
863 0x00000000);
864 spr_register(env, SPR_IBAT3L, "IBAT3L",
865 SPR_NOACCESS, SPR_NOACCESS,
866 &spr_read_601_ubat, &spr_write_601_ubatl,
867 0x00000000);
868 env->nb_BATs = 4;
869 #endif
870 }
872 static void register_74xx_sprs(CPUPPCState *env)
873 {
874 /* Processor identification */
875 spr_register(env, SPR_PIR, "PIR",
876 SPR_NOACCESS, SPR_NOACCESS,
877 &spr_read_generic, &spr_write_pir,
878 0x00000000);
879 /* XXX : not implemented */
880 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
881 SPR_NOACCESS, SPR_NOACCESS,
882 &spr_read_generic, &spr_write_generic,
883 0x00000000);
884 /* XXX : not implemented */
885 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
886 &spr_read_ureg, SPR_NOACCESS,
887 &spr_read_ureg, SPR_NOACCESS,
888 0x00000000);
889 /* XXX: not implemented */
890 spr_register(env, SPR_BAMR, "BAMR",
891 SPR_NOACCESS, SPR_NOACCESS,
892 &spr_read_generic, &spr_write_generic,
893 0x00000000);
894 /* XXX : not implemented */
895 spr_register(env, SPR_MSSCR0, "MSSCR0",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, &spr_write_generic,
898 0x00000000);
899 /* Hardware implementation registers */
900 /* XXX : not implemented */
901 spr_register(env, SPR_HID0, "HID0",
902 SPR_NOACCESS, SPR_NOACCESS,
903 &spr_read_generic, &spr_write_generic,
904 0x00000000);
905 /* XXX : not implemented */
906 spr_register(env, SPR_HID1, "HID1",
907 SPR_NOACCESS, SPR_NOACCESS,
908 &spr_read_generic, &spr_write_generic,
909 0x00000000);
910 /* Altivec */
911 spr_register(env, SPR_VRSAVE, "VRSAVE",
912 &spr_read_generic, &spr_write_generic,
913 &spr_read_generic, &spr_write_generic,
914 0x00000000);
915 /* XXX : not implemented */
916 spr_register(env, SPR_L2CR, "L2CR",
917 SPR_NOACCESS, SPR_NOACCESS,
918 &spr_read_generic, spr_access_nop,
919 0x00000000);
920 }
922 static void register_l3_ctrl(CPUPPCState *env)
923 {
924 /* L3CR */
925 /* XXX : not implemented */
926 spr_register(env, SPR_L3CR, "L3CR",
927 SPR_NOACCESS, SPR_NOACCESS,
928 &spr_read_generic, &spr_write_generic,
929 0x00000000);
930 /* L3ITCR0 */
931 /* XXX : not implemented */
932 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
933 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_generic, &spr_write_generic,
935 0x00000000);
936 /* L3PM */
937 /* XXX : not implemented */
938 spr_register(env, SPR_L3PM, "L3PM",
939 SPR_NOACCESS, SPR_NOACCESS,
940 &spr_read_generic, &spr_write_generic,
941 0x00000000);
942 }
944 static void register_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
945 {
946 #if !defined(CONFIG_USER_ONLY)
947 env->nb_tlb = nb_tlbs;
948 env->nb_ways = nb_ways;
949 env->id_tlbs = 1;
950 env->tlb_type = TLB_6XX;
951 /* XXX : not implemented */
952 spr_register(env, SPR_PTEHI, "PTEHI",
953 SPR_NOACCESS, SPR_NOACCESS,
954 &spr_read_generic, &spr_write_generic,
955 0x00000000);
956 /* XXX : not implemented */
957 spr_register(env, SPR_PTELO, "PTELO",
958 SPR_NOACCESS, SPR_NOACCESS,
959 &spr_read_generic, &spr_write_generic,
960 0x00000000);
961 /* XXX : not implemented */
962 spr_register(env, SPR_TLBMISS, "TLBMISS",
963 SPR_NOACCESS, SPR_NOACCESS,
964 &spr_read_generic, &spr_write_generic,
965 0x00000000);
966 #endif
967 }
969 static void register_usprg3_sprs(CPUPPCState *env)
970 {
971 spr_register(env, SPR_USPRG3, "USPRG3",
972 &spr_read_ureg, SPR_NOACCESS,
973 &spr_read_ureg, SPR_NOACCESS,
974 0x00000000);
975 }
977 static void register_usprgh_sprs(CPUPPCState *env)
978 {
979 spr_register(env, SPR_USPRG4, "USPRG4",
980 &spr_read_ureg, SPR_NOACCESS,
981 &spr_read_ureg, SPR_NOACCESS,
982 0x00000000);
983 spr_register(env, SPR_USPRG5, "USPRG5",
984 &spr_read_ureg, SPR_NOACCESS,
985 &spr_read_ureg, SPR_NOACCESS,
986 0x00000000);
987 spr_register(env, SPR_USPRG6, "USPRG6",
988 &spr_read_ureg, SPR_NOACCESS,
989 &spr_read_ureg, SPR_NOACCESS,
990 0x00000000);
991 spr_register(env, SPR_USPRG7, "USPRG7",
992 &spr_read_ureg, SPR_NOACCESS,
993 &spr_read_ureg, SPR_NOACCESS,
994 0x00000000);
995 }
997 /* PowerPC BookE SPR */
998 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
999 {
1000 const char *ivor_names[64] = {
1001 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1002 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1003 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1004 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1005 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1006 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1007 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1008 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1009 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1010 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1011 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1012 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1013 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1014 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1015 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1016 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1017 };
1018 #define SPR_BOOKE_IVORxx (-1)
1019 int ivor_sprn[64] = {
1020 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1021 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1022 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1023 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1024 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1025 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1026 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1027 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1028 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1029 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1030 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1031 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1032 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1033 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1034 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1035 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1036 };
1037 int i;
1039 /* Interrupt processing */
1040 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1041 SPR_NOACCESS, SPR_NOACCESS,
1042 &spr_read_generic, &spr_write_generic,
1043 0x00000000);
1044 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1045 SPR_NOACCESS, SPR_NOACCESS,
1046 &spr_read_generic, &spr_write_generic,
1047 0x00000000);
1048 /* Debug */
1049 /* XXX : not implemented */
1050 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1051 SPR_NOACCESS, SPR_NOACCESS,
1052 &spr_read_generic, &spr_write_generic,
1053 0x00000000);
1054 /* XXX : not implemented */
1055 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1056 SPR_NOACCESS, SPR_NOACCESS,
1057 &spr_read_generic, &spr_write_generic,
1058 0x00000000);
1059 /* XXX : not implemented */
1060 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1061 SPR_NOACCESS, SPR_NOACCESS,
1062 &spr_read_generic, &spr_write_generic,
1063 0x00000000);
1064 /* XXX : not implemented */
1065 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1066 SPR_NOACCESS, SPR_NOACCESS,
1067 &spr_read_generic, &spr_write_generic,
1068 0x00000000);
1069 /* XXX : not implemented */
1070 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1071 SPR_NOACCESS, SPR_NOACCESS,
1072 &spr_read_generic, &spr_write_40x_dbcr0,
1073 0x00000000);
1074 /* XXX : not implemented */
1075 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1076 SPR_NOACCESS, SPR_NOACCESS,
1077 &spr_read_generic, &spr_write_generic,
1078 0x00000000);
1079 /* XXX : not implemented */
1080 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1081 SPR_NOACCESS, SPR_NOACCESS,
1082 &spr_read_generic, &spr_write_generic,
1083 0x00000000);
1084 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1085 SPR_NOACCESS, SPR_NOACCESS,
1086 &spr_read_generic, &spr_write_generic,
1087 0x00000000);
1088 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1089 SPR_NOACCESS, SPR_NOACCESS,
1090 &spr_read_generic, &spr_write_generic,
1091 0x00000000);
1092 /* XXX : not implemented */
1093 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1094 SPR_NOACCESS, SPR_NOACCESS,
1095 &spr_read_generic, &spr_write_clear,
1096 0x00000000);
1097 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1098 SPR_NOACCESS, SPR_NOACCESS,
1099 &spr_read_generic, &spr_write_generic,
1100 0x00000000);
1101 spr_register(env, SPR_BOOKE_ESR, "ESR",
1102 SPR_NOACCESS, SPR_NOACCESS,
1103 &spr_read_generic, &spr_write_generic,
1104 0x00000000);
1105 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1106 SPR_NOACCESS, SPR_NOACCESS,
1107 &spr_read_generic, &spr_write_excp_prefix,
1108 0x00000000);
1109 /* Exception vectors */
1110 for (i = 0; i < 64; i++) {
1111 if (ivor_mask & (1ULL << i)) {
1112 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1113 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1114 exit(1);
1115 }
1116 spr_register(env, ivor_sprn[i], ivor_names[i],
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 &spr_read_generic, &spr_write_excp_vector,
1119 0x00000000);
1120 }
1121 }
1122 spr_register(env, SPR_BOOKE_PID, "PID",
1123 SPR_NOACCESS, SPR_NOACCESS,
1124 &spr_read_generic, &spr_write_booke_pid,
1125 0x00000000);
1126 spr_register(env, SPR_BOOKE_TCR, "TCR",
1127 SPR_NOACCESS, SPR_NOACCESS,
1128 &spr_read_generic, &spr_write_booke_tcr,
1129 0x00000000);
1130 spr_register(env, SPR_BOOKE_TSR, "TSR",
1131 SPR_NOACCESS, SPR_NOACCESS,
1132 &spr_read_generic, &spr_write_booke_tsr,
1133 0x00000000);
1134 /* Timer */
1135 spr_register(env, SPR_DECR, "DECR",
1136 SPR_NOACCESS, SPR_NOACCESS,
1137 &spr_read_decr, &spr_write_decr,
1138 0x00000000);
1139 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1140 SPR_NOACCESS, SPR_NOACCESS,
1141 SPR_NOACCESS, &spr_write_generic,
1142 0x00000000);
1143 /* SPRGs */
1144 spr_register(env, SPR_USPRG0, "USPRG0",
1145 &spr_read_generic, &spr_write_generic,
1146 &spr_read_generic, &spr_write_generic,
1147 0x00000000);
1148 spr_register(env, SPR_SPRG4, "SPRG4",
1149 SPR_NOACCESS, SPR_NOACCESS,
1150 &spr_read_generic, &spr_write_generic,
1151 0x00000000);
1152 spr_register(env, SPR_SPRG5, "SPRG5",
1153 SPR_NOACCESS, SPR_NOACCESS,
1154 &spr_read_generic, &spr_write_generic,
1155 0x00000000);
1156 spr_register(env, SPR_SPRG6, "SPRG6",
1157 SPR_NOACCESS, SPR_NOACCESS,
1158 &spr_read_generic, &spr_write_generic,
1159 0x00000000);
1160 spr_register(env, SPR_SPRG7, "SPRG7",
1161 SPR_NOACCESS, SPR_NOACCESS,
1162 &spr_read_generic, &spr_write_generic,
1163 0x00000000);
1164 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
1165 SPR_NOACCESS, SPR_NOACCESS,
1166 &spr_read_generic, &spr_write_generic,
1167 0x00000000);
1168 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
1169 SPR_NOACCESS, SPR_NOACCESS,
1170 &spr_read_generic, &spr_write_generic,
1171 0x00000000);
1172 }
1174 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
1175 uint32_t maxsize, uint32_t flags,
1176 uint32_t nentries)
1177 {
1178 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1179 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1180 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1181 flags | nentries;
1182 }
1184 /* BookE 2.06 storage control registers */
1185 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
1186 uint32_t *tlbncfg, uint32_t mmucfg)
1187 {
1188 #if !defined(CONFIG_USER_ONLY)
1189 const char *mas_names[8] = {
1190 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1191 };
1192 int mas_sprn[8] = {
1193 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1194 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1195 };
1196 int i;
1198 /* TLB assist registers */
1199 /* XXX : not implemented */
1200 for (i = 0; i < 8; i++) {
1201 void (*uea_write)(DisasContext *ctx, int sprn, int gprn) =
1202 &spr_write_generic32;
1203 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1204 uea_write = &spr_write_generic;
1205 }
1206 if (mas_mask & (1 << i)) {
1207 spr_register(env, mas_sprn[i], mas_names[i],
1208 SPR_NOACCESS, SPR_NOACCESS,
1209 &spr_read_generic, uea_write,
1210 0x00000000);
1211 }
1212 }
1213 if (env->nb_pids > 1) {
1214 /* XXX : not implemented */
1215 spr_register(env, SPR_BOOKE_PID1, "PID1",
1216 SPR_NOACCESS, SPR_NOACCESS,
1217 &spr_read_generic, &spr_write_booke_pid,
1218 0x00000000);
1219 }
1220 if (env->nb_pids > 2) {
1221 /* XXX : not implemented */
1222 spr_register(env, SPR_BOOKE_PID2, "PID2",
1223 SPR_NOACCESS, SPR_NOACCESS,
1224 &spr_read_generic, &spr_write_booke_pid,
1225 0x00000000);
1226 }
1228 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
1229 SPR_NOACCESS, SPR_NOACCESS,
1230 &spr_read_generic, &spr_write_eplc,
1231 0x00000000);
1232 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_generic, &spr_write_epsc,
1235 0x00000000);
1237 /* XXX : not implemented */
1238 spr_register(env, SPR_MMUCFG, "MMUCFG",
1239 SPR_NOACCESS, SPR_NOACCESS,
1240 &spr_read_generic, SPR_NOACCESS,
1241 mmucfg);
1242 switch (env->nb_ways) {
1243 case 4:
1244 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1245 SPR_NOACCESS, SPR_NOACCESS,
1246 &spr_read_generic, SPR_NOACCESS,
1247 tlbncfg[3]);
1248 /* Fallthru */
1249 case 3:
1250 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1251 SPR_NOACCESS, SPR_NOACCESS,
1252 &spr_read_generic, SPR_NOACCESS,
1253 tlbncfg[2]);
1254 /* Fallthru */
1255 case 2:
1256 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1257 SPR_NOACCESS, SPR_NOACCESS,
1258 &spr_read_generic, SPR_NOACCESS,
1259 tlbncfg[1]);
1260 /* Fallthru */
1261 case 1:
1262 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1263 SPR_NOACCESS, SPR_NOACCESS,
1264 &spr_read_generic, SPR_NOACCESS,
1265 tlbncfg[0]);
1266 /* Fallthru */
1267 case 0:
1268 default:
1269 break;
1270 }
1271 #endif
1273 register_usprgh_sprs(env);
1274 }
1276 /* SPR specific to PowerPC 440 implementation */
1277 static void register_440_sprs(CPUPPCState *env)
1278 {
1279 /* Cache control */
1280 /* XXX : not implemented */
1281 spr_register(env, SPR_440_DNV0, "DNV0",
1282 SPR_NOACCESS, SPR_NOACCESS,
1283 &spr_read_generic, &spr_write_generic,
1284 0x00000000);
1285 /* XXX : not implemented */
1286 spr_register(env, SPR_440_DNV1, "DNV1",
1287 SPR_NOACCESS, SPR_NOACCESS,
1288 &spr_read_generic, &spr_write_generic,
1289 0x00000000);
1290 /* XXX : not implemented */
1291 spr_register(env, SPR_440_DNV2, "DNV2",
1292 SPR_NOACCESS, SPR_NOACCESS,
1293 &spr_read_generic, &spr_write_generic,
1294 0x00000000);
1295 /* XXX : not implemented */
1296 spr_register(env, SPR_440_DNV3, "DNV3",
1297 SPR_NOACCESS, SPR_NOACCESS,
1298 &spr_read_generic, &spr_write_generic,
1299 0x00000000);
1300 /* XXX : not implemented */
1301 spr_register(env, SPR_440_DTV0, "DTV0",
1302 SPR_NOACCESS, SPR_NOACCESS,
1303 &spr_read_generic, &spr_write_generic,
1304 0x00000000);
1305 /* XXX : not implemented */
1306 spr_register(env, SPR_440_DTV1, "DTV1",
1307 SPR_NOACCESS, SPR_NOACCESS,
1308 &spr_read_generic, &spr_write_generic,
1309 0x00000000);
1310 /* XXX : not implemented */
1311 spr_register(env, SPR_440_DTV2, "DTV2",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_generic, &spr_write_generic,
1314 0x00000000);
1315 /* XXX : not implemented */
1316 spr_register(env, SPR_440_DTV3, "DTV3",
1317 SPR_NOACCESS, SPR_NOACCESS,
1318 &spr_read_generic, &spr_write_generic,
1319 0x00000000);
1320 /* XXX : not implemented */
1321 spr_register(env, SPR_440_DVLIM, "DVLIM",
1322 SPR_NOACCESS, SPR_NOACCESS,
1323 &spr_read_generic, &spr_write_generic,
1324 0x00000000);
1325 /* XXX : not implemented */
1326 spr_register(env, SPR_440_INV0, "INV0",
1327 SPR_NOACCESS, SPR_NOACCESS,
1328 &spr_read_generic, &spr_write_generic,
1329 0x00000000);
1330 /* XXX : not implemented */
1331 spr_register(env, SPR_440_INV1, "INV1",
1332 SPR_NOACCESS, SPR_NOACCESS,
1333 &spr_read_generic, &spr_write_generic,
1334 0x00000000);
1335 /* XXX : not implemented */
1336 spr_register(env, SPR_440_INV2, "INV2",
1337 SPR_NOACCESS, SPR_NOACCESS,
1338 &spr_read_generic, &spr_write_generic,
1339 0x00000000);
1340 /* XXX : not implemented */
1341 spr_register(env, SPR_440_INV3, "INV3",
1342 SPR_NOACCESS, SPR_NOACCESS,
1343 &spr_read_generic, &spr_write_generic,
1344 0x00000000);
1345 /* XXX : not implemented */
1346 spr_register(env, SPR_440_ITV0, "ITV0",
1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_generic,
1349 0x00000000);
1350 /* XXX : not implemented */
1351 spr_register(env, SPR_440_ITV1, "ITV1",
1352 SPR_NOACCESS, SPR_NOACCESS,
1353 &spr_read_generic, &spr_write_generic,
1354 0x00000000);
1355 /* XXX : not implemented */
1356 spr_register(env, SPR_440_ITV2, "ITV2",
1357 SPR_NOACCESS, SPR_NOACCESS,
1358 &spr_read_generic, &spr_write_generic,
1359 0x00000000);
1360 /* XXX : not implemented */
1361 spr_register(env, SPR_440_ITV3, "ITV3",
1362 SPR_NOACCESS, SPR_NOACCESS,
1363 &spr_read_generic, &spr_write_generic,
1364 0x00000000);
1365 /* XXX : not implemented */
1366 spr_register(env, SPR_440_IVLIM, "IVLIM",
1367 SPR_NOACCESS, SPR_NOACCESS,
1368 &spr_read_generic, &spr_write_generic,
1369 0x00000000);
1370 /* Cache debug */
1371 /* XXX : not implemented */
1372 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1373 SPR_NOACCESS, SPR_NOACCESS,
1374 &spr_read_generic, SPR_NOACCESS,
1375 0x00000000);
1376 /* XXX : not implemented */
1377 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1378 SPR_NOACCESS, SPR_NOACCESS,
1379 &spr_read_generic, SPR_NOACCESS,
1380 0x00000000);
1381 /* XXX : not implemented */
1382 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1383 SPR_NOACCESS, SPR_NOACCESS,
1384 &spr_read_generic, SPR_NOACCESS,
1385 0x00000000);
1386 /* XXX : not implemented */
1387 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1388 SPR_NOACCESS, SPR_NOACCESS,
1389 &spr_read_generic, SPR_NOACCESS,
1390 0x00000000);
1391 /* XXX : not implemented */
1392 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1393 SPR_NOACCESS, SPR_NOACCESS,
1394 &spr_read_generic, SPR_NOACCESS,
1395 0x00000000);
1396 /* XXX : not implemented */
1397 spr_register(env, SPR_440_DBDR, "DBDR",
1398 SPR_NOACCESS, SPR_NOACCESS,
1399 &spr_read_generic, &spr_write_generic,
1400 0x00000000);
1401 /* Processor control */
1402 spr_register(env, SPR_4xx_CCR0, "CCR0",
1403 SPR_NOACCESS, SPR_NOACCESS,
1404 &spr_read_generic, &spr_write_generic,
1405 0x00000000);
1406 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1407 SPR_NOACCESS, SPR_NOACCESS,
1408 &spr_read_generic, SPR_NOACCESS,
1409 0x00000000);
1410 /* Storage control */
1411 spr_register(env, SPR_440_MMUCR, "MMUCR",
1412 SPR_NOACCESS, SPR_NOACCESS,
1413 &spr_read_generic, &spr_write_generic,
1414 0x00000000);
1415 }
1417 /* SPR shared between PowerPC 40x implementations */
1418 static void register_40x_sprs(CPUPPCState *env)
1419 {
1420 /* Cache */
1421 /* not emulated, as QEMU do not emulate caches */
1422 spr_register(env, SPR_40x_DCCR, "DCCR",
1423 SPR_NOACCESS, SPR_NOACCESS,
1424 &spr_read_generic, &spr_write_generic,
1425 0x00000000);
1426 /* not emulated, as QEMU do not emulate caches */
1427 spr_register(env, SPR_40x_ICCR, "ICCR",
1428 SPR_NOACCESS, SPR_NOACCESS,
1429 &spr_read_generic, &spr_write_generic,
1430 0x00000000);
1431 /* not emulated, as QEMU do not emulate caches */
1432 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1433 SPR_NOACCESS, SPR_NOACCESS,
1434 &spr_read_generic, SPR_NOACCESS,
1435 0x00000000);
1436 /* Exception */
1437 spr_register(env, SPR_40x_DEAR, "DEAR",
1438 SPR_NOACCESS, SPR_NOACCESS,
1439 &spr_read_generic, &spr_write_generic,
1440 0x00000000);
1441 spr_register(env, SPR_40x_ESR, "ESR",
1442 SPR_NOACCESS, SPR_NOACCESS,
1443 &spr_read_generic, &spr_write_generic,
1444 0x00000000);
1445 spr_register(env, SPR_40x_EVPR, "EVPR",
1446 SPR_NOACCESS, SPR_NOACCESS,
1447 &spr_read_generic, &spr_write_excp_prefix,
1448 0x00000000);
1449 spr_register(env, SPR_40x_SRR2, "SRR2",
1450 &spr_read_generic, &spr_write_generic,
1451 &spr_read_generic, &spr_write_generic,
1452 0x00000000);
1453 spr_register(env, SPR_40x_SRR3, "SRR3",
1454 &spr_read_generic, &spr_write_generic,
1455 &spr_read_generic, &spr_write_generic,
1456 0x00000000);
1457 /* Timers */
1458 spr_register(env, SPR_40x_PIT, "PIT",
1459 SPR_NOACCESS, SPR_NOACCESS,
1460 &spr_read_40x_pit, &spr_write_40x_pit,
1461 0x00000000);
1462 spr_register(env, SPR_40x_TCR, "TCR",
1463 SPR_NOACCESS, SPR_NOACCESS,
1464 &spr_read_generic, &spr_write_booke_tcr,
1465 0x00000000);
1466 spr_register(env, SPR_40x_TSR, "TSR",
1467 SPR_NOACCESS, SPR_NOACCESS,
1468 &spr_read_generic, &spr_write_booke_tsr,
1469 0x00000000);
1470 }
1472 /* SPR specific to PowerPC 405 implementation */
1473 static void register_405_sprs(CPUPPCState *env)
1474 {
1475 /* MMU */
1476 spr_register(env, SPR_40x_PID, "PID",
1477 SPR_NOACCESS, SPR_NOACCESS,
1478 &spr_read_generic, &spr_write_generic,
1479 0x00000000);
1480 spr_register(env, SPR_4xx_CCR0, "CCR0",
1481 SPR_NOACCESS, SPR_NOACCESS,
1482 &spr_read_generic, &spr_write_generic,
1483 0x00700000);
1484 /* Debug interface */
1485 /* XXX : not implemented */
1486 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1487 SPR_NOACCESS, SPR_NOACCESS,
1488 &spr_read_generic, &spr_write_40x_dbcr0,
1489 0x00000000);
1490 /* XXX : not implemented */
1491 spr_register(env, SPR_405_DBCR1, "DBCR1",
1492 SPR_NOACCESS, SPR_NOACCESS,
1493 &spr_read_generic, &spr_write_generic,
1494 0x00000000);
1495 /* XXX : not implemented */
1496 spr_register(env, SPR_40x_DBSR, "DBSR",
1497 SPR_NOACCESS, SPR_NOACCESS,
1498 &spr_read_generic, &spr_write_clear,
1499 /* Last reset was system reset */
1500 0x00000300);
1501 /* XXX : not implemented */
1502 spr_register(env, SPR_40x_DAC1, "DAC1",
1503 SPR_NOACCESS, SPR_NOACCESS,
1504 &spr_read_generic, &spr_write_generic,
1505 0x00000000);
1506 spr_register(env, SPR_40x_DAC2, "DAC2",
1507 SPR_NOACCESS, SPR_NOACCESS,
1508 &spr_read_generic, &spr_write_generic,
1509 0x00000000);
1510 /* XXX : not implemented */
1511 spr_register(env, SPR_405_DVC1, "DVC1",
1512 SPR_NOACCESS, SPR_NOACCESS,
1513 &spr_read_generic, &spr_write_generic,
1514 0x00000000);
1515 /* XXX : not implemented */
1516 spr_register(env, SPR_405_DVC2, "DVC2",
1517 SPR_NOACCESS, SPR_NOACCESS,
1518 &spr_read_generic, &spr_write_generic,
1519 0x00000000);
1520 /* XXX : not implemented */
1521 spr_register(env, SPR_40x_IAC1, "IAC1",
1522 SPR_NOACCESS, SPR_NOACCESS,
1523 &spr_read_generic, &spr_write_generic,
1524 0x00000000);
1525 spr_register(env, SPR_40x_IAC2, "IAC2",
1526 SPR_NOACCESS, SPR_NOACCESS,
1527 &spr_read_generic, &spr_write_generic,
1528 0x00000000);
1529 /* XXX : not implemented */
1530 spr_register(env, SPR_405_IAC3, "IAC3",
1531 SPR_NOACCESS, SPR_NOACCESS,
1532 &spr_read_generic, &spr_write_generic,
1533 0x00000000);
1534 /* XXX : not implemented */
1535 spr_register(env, SPR_405_IAC4, "IAC4",
1536 SPR_NOACCESS, SPR_NOACCESS,
1537 &spr_read_generic, &spr_write_generic,
1538 0x00000000);
1539 /* Storage control */
1540 /* XXX: TODO: not implemented */
1541 spr_register(env, SPR_405_SLER, "SLER",
1542 SPR_NOACCESS, SPR_NOACCESS,
1543 &spr_read_generic, &spr_write_40x_sler,
1544 0x00000000);
1545 spr_register(env, SPR_40x_ZPR, "ZPR",
1546 SPR_NOACCESS, SPR_NOACCESS,
1547 &spr_read_generic, &spr_write_generic,
1548 0x00000000);
1549 /* XXX : not implemented */
1550 spr_register(env, SPR_405_SU0R, "SU0R",
1551 SPR_NOACCESS, SPR_NOACCESS,
1552 &spr_read_generic, &spr_write_generic,
1553 0x00000000);
1554 /* SPRG */
1555 spr_register(env, SPR_USPRG0, "USPRG0",
1556 &spr_read_ureg, SPR_NOACCESS,
1557 &spr_read_ureg, SPR_NOACCESS,
1558 0x00000000);
1559 spr_register(env, SPR_SPRG4, "SPRG4",
1560 SPR_NOACCESS, SPR_NOACCESS,
1561 &spr_read_generic, &spr_write_generic,
1562 0x00000000);
1563 spr_register(env, SPR_SPRG5, "SPRG5",
1564 SPR_NOACCESS, SPR_NOACCESS,
1565 spr_read_generic, &spr_write_generic,
1566 0x00000000);
1567 spr_register(env, SPR_SPRG6, "SPRG6",
1568 SPR_NOACCESS, SPR_NOACCESS,
1569 spr_read_generic, &spr_write_generic,
1570 0x00000000);
1571 spr_register(env, SPR_SPRG7, "SPRG7",
1572 SPR_NOACCESS, SPR_NOACCESS,
1573 spr_read_generic, &spr_write_generic,
1574 0x00000000);
1575 register_usprgh_sprs(env);
1576 }
1578 /* SPR shared between PowerPC 401 & 403 implementations */
1579 static void register_401_403_sprs(CPUPPCState *env)
1580 {
1581 /* Time base */
1582 spr_register(env, SPR_403_VTBL, "TBL",
1583 &spr_read_tbl, SPR_NOACCESS,
1584 &spr_read_tbl, SPR_NOACCESS,
1585 0x00000000);
1586 spr_register(env, SPR_403_TBL, "TBL",
1587 SPR_NOACCESS, SPR_NOACCESS,
1588 SPR_NOACCESS, &spr_write_tbl,
1589 0x00000000);
1590 spr_register(env, SPR_403_VTBU, "TBU",
1591 &spr_read_tbu, SPR_NOACCESS,
1592 &spr_read_tbu, SPR_NOACCESS,
1593 0x00000000);
1594 spr_register(env, SPR_403_TBU, "TBU",
1595 SPR_NOACCESS, SPR_NOACCESS,
1596 SPR_NOACCESS, &spr_write_tbu,
1597 0x00000000);
1598 /* Debug */
1599 /* not emulated, as QEMU do not emulate caches */
1600 spr_register(env, SPR_403_CDBCR, "CDBCR",
1601 SPR_NOACCESS, SPR_NOACCESS,
1602 &spr_read_generic, &spr_write_generic,
1603 0x00000000);
1604 }
1606 /* SPR specific to PowerPC 401 implementation */
1607 static void register_401_sprs(CPUPPCState *env)
1608 {
1609 /* Debug interface */
1610 /* XXX : not implemented */
1611 spr_register(env, SPR_40x_DBCR0, "DBCR",
1612 SPR_NOACCESS, SPR_NOACCESS,
1613 &spr_read_generic, &spr_write_40x_dbcr0,
1614 0x00000000);
1615 /* XXX : not implemented */
1616 spr_register(env, SPR_40x_DBSR, "DBSR",
1617 SPR_NOACCESS, SPR_NOACCESS,
1618 &spr_read_generic, &spr_write_clear,
1619 /* Last reset was system reset */
1620 0x00000300);
1621 /* XXX : not implemented */
1622 spr_register(env, SPR_40x_DAC1, "DAC",
1623 SPR_NOACCESS, SPR_NOACCESS,
1624 &spr_read_generic, &spr_write_generic,
1625 0x00000000);
1626 /* XXX : not implemented */
1627 spr_register(env, SPR_40x_IAC1, "IAC",
1628 SPR_NOACCESS, SPR_NOACCESS,
1629 &spr_read_generic, &spr_write_generic,
1630 0x00000000);
1631 /* Storage control */
1632 /* XXX: TODO: not implemented */
1633 spr_register(env, SPR_405_SLER, "SLER",
1634 SPR_NOACCESS, SPR_NOACCESS,
1635 &spr_read_generic, &spr_write_40x_sler,
1636 0x00000000);
1637 /* not emulated, as QEMU never does speculative access */
1638 spr_register(env, SPR_40x_SGR, "SGR",
1639 SPR_NOACCESS, SPR_NOACCESS,
1640 &spr_read_generic, &spr_write_generic,
1641 0xFFFFFFFF);
1642 /* not emulated, as QEMU do not emulate caches */
1643 spr_register(env, SPR_40x_DCWR, "DCWR",
1644 SPR_NOACCESS, SPR_NOACCESS,
1645 &spr_read_generic, &spr_write_generic,
1646 0x00000000);
1647 }
1649 static void register_401x2_sprs(CPUPPCState *env)
1650 {
1651 register_401_sprs(env);
1652 spr_register(env, SPR_40x_PID, "PID",
1653 SPR_NOACCESS, SPR_NOACCESS,
1654 &spr_read_generic, &spr_write_generic,
1655 0x00000000);
1656 spr_register(env, SPR_40x_ZPR, "ZPR",
1657 SPR_NOACCESS, SPR_NOACCESS,
1658 &spr_read_generic, &spr_write_generic,
1659 0x00000000);
1660 }
1662 /* SPR specific to PowerPC 403 implementation */
1663 static void register_403_sprs(CPUPPCState *env)
1664 {
1665 /* Debug interface */
1666 /* XXX : not implemented */
1667 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1668 SPR_NOACCESS, SPR_NOACCESS,
1669 &spr_read_generic, &spr_write_40x_dbcr0,
1670 0x00000000);
1671 /* XXX : not implemented */
1672 spr_register(env, SPR_40x_DBSR, "DBSR",
1673 SPR_NOACCESS, SPR_NOACCESS,
1674 &spr_read_generic, &spr_write_clear,
1675 /* Last reset was system reset */
1676 0x00000300);
1677 /* XXX : not implemented */
1678 spr_register(env, SPR_40x_DAC1, "DAC1",
1679 SPR_NOACCESS, SPR_NOACCESS,
1680 &spr_read_generic, &spr_write_generic,
1681 0x00000000);
1682 /* XXX : not implemented */
1683 spr_register(env, SPR_40x_DAC2, "DAC2",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_generic,
1686 0x00000000);
1687 /* XXX : not implemented */
1688 spr_register(env, SPR_40x_IAC1, "IAC1",
1689 SPR_NOACCESS, SPR_NOACCESS,
1690 &spr_read_generic, &spr_write_generic,
1691 0x00000000);
1692 /* XXX : not implemented */
1693 spr_register(env, SPR_40x_IAC2, "IAC2",
1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, &spr_write_generic,
1696 0x00000000);
1697 }
1699 static void register_403_real_sprs(CPUPPCState *env)
1700 {
1701 spr_register(env, SPR_403_PBL1, "PBL1",
1702 SPR_NOACCESS, SPR_NOACCESS,
1703 &spr_read_403_pbr, &spr_write_403_pbr,
1704 0x00000000);
1705 spr_register(env, SPR_403_PBU1, "PBU1",
1706 SPR_NOACCESS, SPR_NOACCESS,
1707 &spr_read_403_pbr, &spr_write_403_pbr,
1708 0x00000000);
1709 spr_register(env, SPR_403_PBL2, "PBL2",
1710 SPR_NOACCESS, SPR_NOACCESS,
1711 &spr_read_403_pbr, &spr_write_403_pbr,
1712 0x00000000);
1713 spr_register(env, SPR_403_PBU2, "PBU2",
1714 SPR_NOACCESS, SPR_NOACCESS,
1715 &spr_read_403_pbr, &spr_write_403_pbr,
1716 0x00000000);
1717 }
1719 static void register_403_mmu_sprs(CPUPPCState *env)
1720 {
1721 /* MMU */
1722 spr_register(env, SPR_40x_PID, "PID",
1723 SPR_NOACCESS, SPR_NOACCESS,
1724 &spr_read_generic, &spr_write_generic,
1725 0x00000000);
1726 spr_register(env, SPR_40x_ZPR, "ZPR",
1727 SPR_NOACCESS, SPR_NOACCESS,
1728 &spr_read_generic, &spr_write_generic,
1729 0x00000000);
1730 }
1732 /* SPR specific to PowerPC compression coprocessor extension */
1733 static void register_compress_sprs(CPUPPCState *env)
1734 {
1735 /* XXX : not implemented */
1736 spr_register(env, SPR_401_SKR, "SKR",
1737 SPR_NOACCESS, SPR_NOACCESS,
1738 &spr_read_generic, &spr_write_generic,
1739 0x00000000);
1740 }
1742 static void register_5xx_8xx_sprs(CPUPPCState *env)
1743 {
1744 /* Exception processing */
1745 spr_register_kvm(env, SPR_DSISR, "DSISR",
1746 SPR_NOACCESS, SPR_NOACCESS,
1747 &spr_read_generic, &spr_write_generic,
1748 KVM_REG_PPC_DSISR, 0x00000000);
1749 spr_register_kvm(env, SPR_DAR, "DAR",
1750 SPR_NOACCESS, SPR_NOACCESS,
1751 &spr_read_generic, &spr_write_generic,
1752 KVM_REG_PPC_DAR, 0x00000000);
1753 /* Timer */
1754 spr_register(env, SPR_DECR, "DECR",
1755 SPR_NOACCESS, SPR_NOACCESS,
1756 &spr_read_decr, &spr_write_decr,
1757 0x00000000);
1758 /* XXX : not implemented */
1759 spr_register(env, SPR_MPC_EIE, "EIE",
1760 SPR_NOACCESS, SPR_NOACCESS,
1761 &spr_read_generic, &spr_write_generic,
1762 0x00000000);
1763 /* XXX : not implemented */
1764 spr_register(env, SPR_MPC_EID, "EID",
1765 SPR_NOACCESS, SPR_NOACCESS,
1766 &spr_read_generic, &spr_write_generic,
1767 0x00000000);
1768 /* XXX : not implemented */
1769 spr_register(env, SPR_MPC_NRI, "NRI",
1770 SPR_NOACCESS, SPR_NOACCESS,
1771 &spr_read_generic, &spr_write_generic,
1772 0x00000000);
1773 /* XXX : not implemented */
1774 spr_register(env, SPR_MPC_CMPA, "CMPA",
1775 SPR_NOACCESS, SPR_NOACCESS,
1776 &spr_read_generic, &spr_write_generic,
1777 0x00000000);
1778 /* XXX : not implemented */
1779 spr_register(env, SPR_MPC_CMPB, "CMPB",
1780 SPR_NOACCESS, SPR_NOACCESS,
1781 &spr_read_generic, &spr_write_generic,
1782 0x00000000);
1783 /* XXX : not implemented */
1784 spr_register(env, SPR_MPC_CMPC, "CMPC",
1785 SPR_NOACCESS, SPR_NOACCESS,
1786 &spr_read_generic, &spr_write_generic,
1787 0x00000000);
1788 /* XXX : not implemented */
1789 spr_register(env, SPR_MPC_CMPD, "CMPD",
1790 SPR_NOACCESS, SPR_NOACCESS,
1791 &spr_read_generic, &spr_write_generic,
1792 0x00000000);
1793 /* XXX : not implemented */
1794 spr_register(env, SPR_MPC_ECR, "ECR",
1795 SPR_NOACCESS, SPR_NOACCESS,
1796 &spr_read_generic, &spr_write_generic,
1797 0x00000000);
1798 /* XXX : not implemented */
1799 spr_register(env, SPR_MPC_DER, "DER",
1800 SPR_NOACCESS, SPR_NOACCESS,
1801 &spr_read_generic, &spr_write_generic,
1802 0x00000000);
1803 /* XXX : not implemented */
1804 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1805 SPR_NOACCESS, SPR_NOACCESS,
1806 &spr_read_generic, &spr_write_generic,
1807 0x00000000);
1808 /* XXX : not implemented */
1809 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_generic, &spr_write_generic,
1812 0x00000000);
1813 /* XXX : not implemented */
1814 spr_register(env, SPR_MPC_CMPE, "CMPE",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_generic,
1817 0x00000000);
1818 /* XXX : not implemented */
1819 spr_register(env, SPR_MPC_CMPF, "CMPF",
1820 SPR_NOACCESS, SPR_NOACCESS,
1821 &spr_read_generic, &spr_write_generic,
1822 0x00000000);
1823 /* XXX : not implemented */
1824 spr_register(env, SPR_MPC_CMPG, "CMPG",
1825 SPR_NOACCESS, SPR_NOACCESS,
1826 &spr_read_generic, &spr_write_generic,
1827 0x00000000);
1828 /* XXX : not implemented */
1829 spr_register(env, SPR_MPC_CMPH, "CMPH",
1830 SPR_NOACCESS, SPR_NOACCESS,
1831 &spr_read_generic, &spr_write_generic,
1832 0x00000000);
1833 /* XXX : not implemented */
1834 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1835 SPR_NOACCESS, SPR_NOACCESS,
1836 &spr_read_generic, &spr_write_generic,
1837 0x00000000);
1838 /* XXX : not implemented */
1839 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1840 SPR_NOACCESS, SPR_NOACCESS,
1841 &spr_read_generic, &spr_write_generic,
1842 0x00000000);
1843 /* XXX : not implemented */
1844 spr_register(env, SPR_MPC_BAR, "BAR",
1845 SPR_NOACCESS, SPR_NOACCESS,
1846 &spr_read_generic, &spr_write_generic,
1847 0x00000000);
1848 /* XXX : not implemented */
1849 spr_register(env, SPR_MPC_DPDR, "DPDR",
1850 SPR_NOACCESS, SPR_NOACCESS,
1851 &spr_read_generic, &spr_write_generic,
1852 0x00000000);
1853 /* XXX : not implemented */
1854 spr_register(env, SPR_MPC_IMMR, "IMMR",
1855 SPR_NOACCESS, SPR_NOACCESS,
1856 &spr_read_generic, &spr_write_generic,
1857 0x00000000);
1858 }
1860 static void register_5xx_sprs(CPUPPCState *env)
1861 {
1862 /* XXX : not implemented */
1863 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1864 SPR_NOACCESS, SPR_NOACCESS,
1865 &spr_read_generic, &spr_write_generic,
1866 0x00000000);
1867 /* XXX : not implemented */
1868 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1869 SPR_NOACCESS, SPR_NOACCESS,
1870 &spr_read_generic, &spr_write_generic,
1871 0x00000000);
1872 /* XXX : not implemented */
1873 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1874 SPR_NOACCESS, SPR_NOACCESS,
1875 &spr_read_generic, &spr_write_generic,
1876 0x00000000);
1877 /* XXX : not implemented */
1878 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, &spr_write_generic,
1881 0x00000000);
1882 /* XXX : not implemented */
1883 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_generic, &spr_write_generic,
1886 0x00000000);
1887 /* XXX : not implemented */
1888 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1889 SPR_NOACCESS, SPR_NOACCESS,
1890 &spr_read_generic, &spr_write_generic,
1891 0x00000000);
1892 /* XXX : not implemented */
1893 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1894 SPR_NOACCESS, SPR_NOACCESS,
1895 &spr_read_generic, &spr_write_generic,
1896 0x00000000);
1897 /* XXX : not implemented */
1898 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_generic,
1901 0x00000000);
1902 /* XXX : not implemented */
1903 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1904 SPR_NOACCESS, SPR_NOACCESS,
1905 &spr_read_generic, &spr_write_generic,
1906 0x00000000);
1907 /* XXX : not implemented */
1908 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, &spr_write_generic,
1911 0x00000000);
1912 /* XXX : not implemented */
1913 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1914 SPR_NOACCESS, SPR_NOACCESS,
1915 &spr_read_generic, &spr_write_generic,
1916 0x00000000);
1917 /* XXX : not implemented */
1918 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1919 SPR_NOACCESS, SPR_NOACCESS,
1920 &spr_read_generic, &spr_write_generic,
1921 0x00000000);
1922 /* XXX : not implemented */
1923 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1924 SPR_NOACCESS, SPR_NOACCESS,
1925 &spr_read_generic, &spr_write_generic,
1926 0x00000000);
1927 /* XXX : not implemented */
1928 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1929 SPR_NOACCESS, SPR_NOACCESS,
1930 &spr_read_generic, &spr_write_generic,
1931 0x00000000);
1932 /* XXX : not implemented */
1933 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1934 SPR_NOACCESS, SPR_NOACCESS,
1935 &spr_read_generic, &spr_write_generic,
1936 0x00000000);
1937 /* XXX : not implemented */
1938 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1939 SPR_NOACCESS, SPR_NOACCESS,
1940 &spr_read_generic, &spr_write_generic,
1941 0x00000000);
1942 /* XXX : not implemented */
1943 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1944 SPR_NOACCESS, SPR_NOACCESS,
1945 &spr_read_generic, &spr_write_generic,
1946 0x00000000);
1947 /* XXX : not implemented */
1948 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1949 SPR_NOACCESS, SPR_NOACCESS,
1950 &spr_read_generic, &spr_write_generic,
1951 0x00000000);
1952 /* XXX : not implemented */
1953 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1954 SPR_NOACCESS, SPR_NOACCESS,
1955 &spr_read_generic, &spr_write_generic,
1956 0x00000000);
1957 /* XXX : not implemented */
1958 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1959 SPR_NOACCESS, SPR_NOACCESS,
1960 &spr_read_generic, &spr_write_generic,
1961 0x00000000);
1962 /* XXX : not implemented */
1963 spr_register(env, SPR_RCPU_FPECR, "FPECR",
1964 SPR_NOACCESS, SPR_NOACCESS,
1965 &spr_read_generic, &spr_write_generic,
1966 0x00000000);
1967 }
1969 static void register_8xx_sprs(CPUPPCState *env)
1970 {
1971 /* XXX : not implemented */
1972 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1973 SPR_NOACCESS, SPR_NOACCESS,
1974 &spr_read_generic, &spr_write_generic,
1975 0x00000000);
1976 /* XXX : not implemented */
1977 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1978 SPR_NOACCESS, SPR_NOACCESS,
1979 &spr_read_generic, &spr_write_generic,
1980 0x00000000);
1981 /* XXX : not implemented */
1982 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1983 SPR_NOACCESS, SPR_NOACCESS,
1984 &spr_read_generic, &spr_write_generic,
1985 0x00000000);
1986 /* XXX : not implemented */
1987 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1988 SPR_NOACCESS, SPR_NOACCESS,
1989 &spr_read_generic, &spr_write_generic,
1990 0x00000000);
1991 /* XXX : not implemented */
1992 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
1993 SPR_NOACCESS, SPR_NOACCESS,
1994 &spr_read_generic, &spr_write_generic,
1995 0x00000000);
1996 /* XXX : not implemented */
1997 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
1998 SPR_NOACCESS, SPR_NOACCESS,
1999 &spr_read_generic, &spr_write_generic,
2000 0x00000000);
2001 /* XXX : not implemented */
2002 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2003 SPR_NOACCESS, SPR_NOACCESS,
2004 &spr_read_generic, &spr_write_generic,
2005 0x00000000);
2006 /* XXX : not implemented */
2007 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2008 SPR_NOACCESS, SPR_NOACCESS,
2009 &spr_read_generic, &spr_write_generic,
2010 0x00000000);
2011 /* XXX : not implemented */
2012 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2013 SPR_NOACCESS, SPR_NOACCESS,
2014 &spr_read_generic, &spr_write_generic,
2015 0x00000000);
2016 /* XXX : not implemented */
2017 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2018 SPR_NOACCESS, SPR_NOACCESS,
2019 &spr_read_generic, &spr_write_generic,
2020 0x00000000);
2021 /* XXX : not implemented */
2022 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2023 SPR_NOACCESS, SPR_NOACCESS,
2024 &spr_read_generic, &spr_write_generic,
2025 0x00000000);
2026 /* XXX : not implemented */
2027 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2028 SPR_NOACCESS, SPR_NOACCESS,
2029 &spr_read_generic, &spr_write_generic,
2030 0x00000000);
2031 /* XXX : not implemented */
2032 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2033 SPR_NOACCESS, SPR_NOACCESS,
2034 &spr_read_generic, &spr_write_generic,
2035 0x00000000);
2036 /* XXX : not implemented */
2037 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2038 SPR_NOACCESS, SPR_NOACCESS,
2039 &spr_read_generic, &spr_write_generic,
2040 0x00000000);
2041 /* XXX : not implemented */
2042 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2043 SPR_NOACCESS, SPR_NOACCESS,
2044 &spr_read_generic, &spr_write_generic,
2045 0x00000000);
2046 /* XXX : not implemented */
2047 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2048 SPR_NOACCESS, SPR_NOACCESS,
2049 &spr_read_generic, &spr_write_generic,
2050 0x00000000);
2051 /* XXX : not implemented */
2052 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2053 SPR_NOACCESS, SPR_NOACCESS,
2054 &spr_read_generic, &spr_write_generic,
2055 0x00000000);
2056 /* XXX : not implemented */
2057 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2058 SPR_NOACCESS, SPR_NOACCESS,
2059 &spr_read_generic, &spr_write_generic,
2060 0x00000000);
2061 /* XXX : not implemented */
2062 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2063 SPR_NOACCESS, SPR_NOACCESS,
2064 &spr_read_generic, &spr_write_generic,
2065 0x00000000);
2066 /* XXX : not implemented */
2067 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2068 SPR_NOACCESS, SPR_NOACCESS,
2069 &spr_read_generic, &spr_write_generic,
2070 0x00000000);
2071 /* XXX : not implemented */
2072 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2073 SPR_NOACCESS, SPR_NOACCESS,
2074 &spr_read_generic, &spr_write_generic,
2075 0x00000000);
2076 /* XXX : not implemented */
2077 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2078 SPR_NOACCESS, SPR_NOACCESS,
2079 &spr_read_generic, &spr_write_generic,
2080 0x00000000);
2081 /* XXX : not implemented */
2082 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2083 SPR_NOACCESS, SPR_NOACCESS,
2084 &spr_read_generic, &spr_write_generic,
2085 0x00000000);
2086 /* XXX : not implemented */
2087 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2088 SPR_NOACCESS, SPR_NOACCESS,
2089 &spr_read_generic, &spr_write_generic,
2090 0x00000000);
2091 /* XXX : not implemented */
2092 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2093 SPR_NOACCESS, SPR_NOACCESS,
2094 &spr_read_generic, &spr_write_generic,
2095 0x00000000);
2096 }
2098 /*
2099 * AMR => SPR 29 (Power 2.04)
2100 * CTRL => SPR 136 (Power 2.04)
2101 * CTRL => SPR 152 (Power 2.04)
2102 * SCOMC => SPR 276 (64 bits ?)
2103 * SCOMD => SPR 277 (64 bits ?)
2104 * TBU40 => SPR 286 (Power 2.04 hypv)
2105 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2106 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2107 * HDSISR => SPR 306 (Power 2.04 hypv)
2108 * HDAR => SPR 307 (Power 2.04 hypv)
2109 * PURR => SPR 309 (Power 2.04 hypv)
2110 * HDEC => SPR 310 (Power 2.04 hypv)
2111 * HIOR => SPR 311 (hypv)
2112 * RMOR => SPR 312 (970)
2113 * HRMOR => SPR 313 (Power 2.04 hypv)
2114 * HSRR0 => SPR 314 (Power 2.04 hypv)
2115 * HSRR1 => SPR 315 (Power 2.04 hypv)
2116 * LPIDR => SPR 317 (970)
2117 * EPR => SPR 702 (Power 2.04 emb)
2118 * perf => 768-783 (Power 2.04)
2119 * perf => 784-799 (Power 2.04)
2120 * PPR => SPR 896 (Power 2.04)
2121 * DABRX => 1015 (Power 2.04 hypv)
2122 * FPECR => SPR 1022 (?)
2123 * ... and more (thermal management, performance counters, ...)
2124 */
2126 /*****************************************************************************/
2127 /* Exception vectors models */
2128 static void init_excp_4xx_real(CPUPPCState *env)
2129 {
2130 #if !defined(CONFIG_USER_ONLY)
2131 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2132 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2133 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2134 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2135 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2136 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2137 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2138 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2139 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2140 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2141 env->ivor_mask = 0x0000FFF0UL;
2142 env->ivpr_mask = 0xFFFF0000UL;
2143 /* Hardware reset vector */
2144 env->hreset_vector = 0xFFFFFFFCUL;
2145 #endif
2146 }
2148 static void init_excp_4xx_softmmu(CPUPPCState *env)
2149 {
2150 #if !defined(CONFIG_USER_ONLY)
2151 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2152 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2153 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2154 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2155 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2156 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2157 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2158 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2159 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2160 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2161 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2162 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2163 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2164 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2165 env->ivor_mask = 0x0000FFF0UL;
2166 env->ivpr_mask = 0xFFFF0000UL;
2167 /* Hardware reset vector */
2168 env->hreset_vector = 0xFFFFFFFCUL;
2169 #endif
2170 }
2172 static void init_excp_MPC5xx(CPUPPCState *env)
2173 {
2174 #if !defined(CONFIG_USER_ONLY)
2175 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2176 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2177 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2178 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2179 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2180 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2181 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2182 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2183 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2184 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2185 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2186 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2187 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2188 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2189 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2190 env->ivor_mask = 0x0000FFF0UL;
2191 env->ivpr_mask = 0xFFFF0000UL;
2192 /* Hardware reset vector */
2193 env->hreset_vector = 0x00000100UL;
2194 #endif
2195 }
2197 static void init_excp_MPC8xx(CPUPPCState *env)
2198 {
2199 #if !defined(CONFIG_USER_ONLY)
2200 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2201 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2202 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2203 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2204 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2205 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2206 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2207 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2208 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2209 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2210 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2211 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2212 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2213 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2214 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2215 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2216 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2217 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2218 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2219 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2220 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2221 env->ivor_mask = 0x0000FFF0UL;
2222 env->ivpr_mask = 0xFFFF0000UL;
2223 /* Hardware reset vector */
2224 env->hreset_vector = 0x00000100UL;
2225 #endif
2226 }
2228 static void init_excp_G2(CPUPPCState *env)
2229 {
2230 #if !defined(CONFIG_USER_ONLY)
2231 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2232 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2233 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2234 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2235 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2236 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2237 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2238 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2239 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2240 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2241 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2242 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2243 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2244 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2245 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2246 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2247 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2248 /* Hardware reset vector */
2249 env->hreset_vector = 0x00000100UL;
2250 #endif
2251 }
2253 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2254 {
2255 #if !defined(CONFIG_USER_ONLY)
2256 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2257 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2258 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2259 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2260 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2261 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2262 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2263 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2264 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2265 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2266 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2267 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2268 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2269 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2270 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2271 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2272 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2273 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2274 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2275 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2276 env->ivor_mask = 0x0000FFF7UL;
2277 env->ivpr_mask = ivpr_mask;
2278 /* Hardware reset vector */
2279 env->hreset_vector = 0xFFFFFFFCUL;
2280 #endif
2281 }
2283 static void init_excp_BookE(CPUPPCState *env)
2284 {
2285 #if !defined(CONFIG_USER_ONLY)
2286 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2287 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2288 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2289 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2290 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2291 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2292 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2293 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2294 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2295 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2296 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2297 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2298 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2299 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2300 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2301 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2302 env->ivor_mask = 0x0000FFF0UL;
2303 env->ivpr_mask = 0xFFFF0000UL;
2304 /* Hardware reset vector */
2305 env->hreset_vector = 0xFFFFFFFCUL;
2306 #endif
2307 }
2309 static void init_excp_601(CPUPPCState *env)
2310 {
2311 #if !defined(CONFIG_USER_ONLY)
2312 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2313 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2314 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2315 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2316 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2317 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2318 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2319 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2320 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2321 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2322 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2323 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2324 /* Hardware reset vector */
2325 env->hreset_vector = 0x00000100UL;
2326 #endif
2327 }
2329 static void init_excp_602(CPUPPCState *env)
2330 {
2331 #if !defined(CONFIG_USER_ONLY)
2332 /* XXX: exception prefix has a special behavior on 602 */
2333 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2334 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2335 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2336 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2337 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2338 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2339 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2340 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2341 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2342 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2343 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2344 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2345 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2346 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2347 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2348 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2349 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2350 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2351 /* Hardware reset vector */
2352 env->hreset_vector = 0x00000100UL;
2353 #endif
2354 }
2356 static void init_excp_603(CPUPPCState *env)
2357 {
2358 #if !defined(CONFIG_USER_ONLY)
2359 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2360 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2361 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2362 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2363 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2364 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2365 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2366 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2367 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2368 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2369 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2370 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2371 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2372 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2373 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2374 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2375 /* Hardware reset vector */
2376 env->hreset_vector = 0x00000100UL;
2377 #endif
2378 }
2380 static void init_excp_604(CPUPPCState *env)
2381 {
2382 #if !defined(CONFIG_USER_ONLY)
2383 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2384 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2385 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2386 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2387 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2388 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2389 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2390 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2391 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2392 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2393 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2394 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2395 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2396 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2397 /* Hardware reset vector */
2398 env->hreset_vector = 0x00000100UL;
2399 #endif
2400 }
2402 static void init_excp_7x0(CPUPPCState *env)
2403 {
2404 #if !defined(CONFIG_USER_ONLY)
2405 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2406 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2407 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2408 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2409 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2410 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2411 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2412 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2413 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2414 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2415 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2416 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2417 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2418 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2419 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2420 /* Hardware reset vector */
2421 env->hreset_vector = 0x00000100UL;
2422 #endif
2423 }
2425 static void init_excp_750cl(CPUPPCState *env)
2426 {
2427 #if !defined(CONFIG_USER_ONLY)
2428 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2429 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2430 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2431 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2432 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2433 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2434 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2435 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2436 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2437 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2438 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2439 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2440 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2441 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2442 /* Hardware reset vector */
2443 env->hreset_vector = 0x00000100UL;
2444 #endif
2445 }
2447 static void init_excp_750cx(CPUPPCState *env)
2448 {
2449 #if !defined(CONFIG_USER_ONLY)
2450 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2451 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2452 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2453 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2454 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2455 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2456 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2457 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2458 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2459 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2460 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2461 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2462 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2463 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2464 /* Hardware reset vector */
2465 env->hreset_vector = 0x00000100UL;
2466 #endif
2467 }
2469 /* XXX: Check if this is correct */
2470 static void init_excp_7x5(CPUPPCState *env)
2471 {
2472 #if !defined(CONFIG_USER_ONLY)
2473 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2474 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2475 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2476 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2477 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2478 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2479 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2480 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2481 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2482 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2483 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2484 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2485 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2486 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2487 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2488 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2489 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2490 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2491 /* Hardware reset vector */
2492 env->hreset_vector = 0x00000100UL;
2493 #endif
2494 }
2496 static void init_excp_7400(CPUPPCState *env)
2497 {
2498 #if !defined(CONFIG_USER_ONLY)
2499 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2500 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2501 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2502 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2503 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2504 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2505 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2506 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2507 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2508 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2509 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2510 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2511 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2512 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2513 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2514 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2515 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2516 /* Hardware reset vector */
2517 env->hreset_vector = 0x00000100UL;
2518 #endif
2519 }
2521 static void init_excp_7450(CPUPPCState *env)
2522 {
2523 #if !defined(CONFIG_USER_ONLY)
2524 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2525 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2526 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2527 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2528 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2529 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2530 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2531 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2532 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2533 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2534 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2535 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2536 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2537 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2538 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2539 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2540 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2541 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2542 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2543 /* Hardware reset vector */
2544 env->hreset_vector = 0x00000100UL;
2545 #endif
2546 }
2548 #if defined(TARGET_PPC64)
2549 static void init_excp_970(CPUPPCState *env)
2550 {
2551 #if !defined(CONFIG_USER_ONLY)
2552 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2553 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2554 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2555 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2556 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2557 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2558 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2559 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2560 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2561 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2562 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2563 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2564 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2565 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2566 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2567 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2568 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2569 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2570 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2571 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2572 /* Hardware reset vector */
2573 env->hreset_vector = 0x0000000000000100ULL;
2574 #endif
2575 }
2577 static void init_excp_POWER7(CPUPPCState *env)
2578 {
2579 #if !defined(CONFIG_USER_ONLY)
2580 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2581 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2582 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2583 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2584 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2585 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2586 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2587 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2588 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2589 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2590 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2591 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2592 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2593 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2594 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
2595 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
2596 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
2597 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
2598 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2599 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2600 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
2601 /* Hardware reset vector */
2602 env->hreset_vector = 0x0000000000000100ULL;
2603 #endif
2604 }
2606 static void init_excp_POWER8(CPUPPCState *env)
2607 {
2608 init_excp_POWER7(env);
2610 #if !defined(CONFIG_USER_ONLY)
2611 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
2612 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
2613 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
2614 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
2615 #endif
2616 }
2618 static void init_excp_POWER9(CPUPPCState *env)
2619 {
2620 init_excp_POWER8(env);
2622 #if !defined(CONFIG_USER_ONLY)
2623 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
2624 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
2625 #endif
2626 }
2628 static void init_excp_POWER10(CPUPPCState *env)
2629 {
2630 init_excp_POWER9(env);
2631 }
2633 #endif
2635 /*****************************************************************************/
2636 /* Power management enable checks */
2637 static int check_pow_none(CPUPPCState *env)
2638 {
2639 return 0;
2640 }
2642 static int check_pow_nocheck(CPUPPCState *env)
2643 {
2644 return 1;
2645 }
2647 static int check_pow_hid0(CPUPPCState *env)
2648 {
2649 if (env->spr[SPR_HID0] & 0x00E00000) {
2650 return 1;
2651 }
2653 return 0;
2654 }
2656 static int check_pow_hid0_74xx(CPUPPCState *env)
2657 {
2658 if (env->spr[SPR_HID0] & 0x00600000) {
2659 return 1;
2660 }
2662 return 0;
2663 }
2665 static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
2666 {
2667 return true;
2668 }
2670 #ifdef TARGET_PPC64
2671 static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
2672 {
2673 return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
2674 }
2675 #endif
2677 /*****************************************************************************/
2678 /* PowerPC implementations definitions */
2680 #define POWERPC_FAMILY(_name) \
2681 static void \
2682 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
2683 \
2684 static const TypeInfo \
2685 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
2686 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
2687 .parent = TYPE_POWERPC_CPU, \
2688 .abstract = true, \
2689 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
2690 }; \
2691 \
2692 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
2693 { \
2694 type_register_static( \
2695 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
2696 } \
2697 \
2698 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
2699 \
2700 static void glue(glue(ppc_, _name), _cpu_family_class_init)
2702 static void init_proc_401(CPUPPCState *env)
2703 {
2704 register_40x_sprs(env);
2705 register_401_403_sprs(env);
2706 register_401_sprs(env);
2707 init_excp_4xx_real(env);
2708 env->dcache_line_size = 32;
2709 env->icache_line_size = 32;
2710 /* Allocate hardware IRQ controller */
2711 ppc40x_irq_init(env_archcpu(env));
2713 SET_FIT_PERIOD(12, 16, 20, 24);
2714 SET_WDT_PERIOD(16, 20, 24, 28);
2715 }
2717 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
2718 {
2719 DeviceClass *dc = DEVICE_CLASS(oc);
2720 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2722 dc->desc = "PowerPC 401";
2723 pcc->init_proc = init_proc_401;
2724 pcc->check_pow = check_pow_nocheck;
2725 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2726 PPC_WRTEE | PPC_DCR |
2727 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2728 PPC_CACHE_DCBZ |
2729 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2730 PPC_4xx_COMMON | PPC_40x_EXCP;
2731 pcc->msr_mask = (1ull << MSR_KEY) |
2732 (1ull << MSR_POW) |
2733 (1ull << MSR_CE) |
2734 (1ull << MSR_ILE) |
2735 (1ull << MSR_EE) |
2736 (1ull << MSR_PR) |
2737 (1ull << MSR_ME) |
2738 (1ull << MSR_DE) |
2739 (1ull << MSR_LE);
2740 pcc->mmu_model = POWERPC_MMU_REAL;
2741 pcc->excp_model = POWERPC_EXCP_40x;
2742 pcc->bus_model = PPC_FLAGS_INPUT_401;
2743 pcc->bfd_mach = bfd_mach_ppc_403;
2744 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
2745 POWERPC_FLAG_BUS_CLK;
2746 }
2748 static void init_proc_401x2(CPUPPCState *env)
2749 {
2750 register_40x_sprs(env);
2751 register_401_403_sprs(env);
2752 register_401x2_sprs(env);
2753 register_compress_sprs(env);
2754 /* Memory management */
2755 #if !defined(CONFIG_USER_ONLY)
2756 env->nb_tlb = 64;
2757 env->nb_ways = 1;
2758 env->id_tlbs = 0;
2759 env->tlb_type = TLB_EMB;
2760 #endif
2761 init_excp_4xx_softmmu(env);
2762 env->dcache_line_size = 32;
2763 env->icache_line_size = 32;
2764 /* Allocate hardware IRQ controller */
2765 ppc40x_irq_init(env_archcpu(env));
2767 SET_FIT_PERIOD(12, 16, 20, 24);
2768 SET_WDT_PERIOD(16, 20, 24, 28);
2769 }
2771 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
2772 {
2773 DeviceClass *dc = DEVICE_CLASS(oc);
2774 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2776 dc->desc = "PowerPC 401x2";
2777 pcc->init_proc = init_proc_401x2;
2778 pcc->check_pow = check_pow_nocheck;
2779 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2780 PPC_DCR | PPC_WRTEE |
2781 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2782 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2783 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2784 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2785 PPC_4xx_COMMON | PPC_40x_EXCP;
2786 pcc->msr_mask = (1ull << 20) |
2787 (1ull << MSR_KEY) |
2788 (1ull << MSR_POW) |
2789 (1ull << MSR_CE) |
2790 (1ull << MSR_ILE) |
2791 (1ull << MSR_EE) |
2792 (1ull << MSR_PR) |
2793 (1ull << MSR_ME) |
2794 (1ull << MSR_DE) |
2795 (1ull << MSR_IR) |
2796 (1ull << MSR_DR) |
2797 (1ull << MSR_LE);
2798 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
2799 pcc->excp_model = POWERPC_EXCP_40x;
2800 pcc->bus_model = PPC_FLAGS_INPUT_401;
2801 pcc->bfd_mach = bfd_mach_ppc_403;
2802 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
2803 POWERPC_FLAG_BUS_CLK;
2804 }
2806 static void init_proc_401x3(CPUPPCState *env)
2807 {
2808 register_40x_sprs(env);
2809 register_401_403_sprs(env);
2810 register_401_sprs(env);
2811 register_401x2_sprs(env);
2812 register_compress_sprs(env);
2813 init_excp_4xx_softmmu(env);
2814 env->dcache_line_size = 32;
2815 env->icache_line_size = 32;
2816 /* Allocate hardware IRQ controller */
2817 ppc40x_irq_init(env_archcpu(env));
2819 SET_FIT_PERIOD(12, 16, 20, 24);
2820 SET_WDT_PERIOD(16, 20, 24, 28);
2821 }
2823 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
2824 {
2825 DeviceClass *dc = DEVICE_CLASS(oc);
2826 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2828 dc->desc = "PowerPC 401x3";
2829 pcc->init_proc = init_proc_401x3;
2830 pcc->check_pow = check_pow_nocheck;
2831 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2832 PPC_DCR | PPC_WRTEE |
2833 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2834 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2835 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2836 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2837 PPC_4xx_COMMON | PPC_40x_EXCP;
2838 pcc->msr_mask = (1ull << 20) |
2839 (1ull << MSR_KEY) |
2840 (1ull << MSR_POW) |
2841 (1ull << MSR_CE) |
2842 (1ull << MSR_ILE) |
2843 (1ull << MSR_EE) |
2844 (1ull << MSR_PR) |
2845 (1ull << MSR_ME) |
2846 (1ull << MSR_DWE) |
2847 (1ull << MSR_DE) |
2848 (1ull << MSR_IR) |
2849 (1ull << MSR_DR) |
2850 (1ull << MSR_LE);
2851 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
2852 pcc->excp_model = POWERPC_EXCP_40x;
2853 pcc->bus_model = PPC_FLAGS_INPUT_401;
2854 pcc->bfd_mach = bfd_mach_ppc_403;
2855 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
2856 POWERPC_FLAG_BUS_CLK;
2857 }
2859 static void init_proc_IOP480(CPUPPCState *env)
2860 {
2861 register_40x_sprs(env);
2862 register_401_403_sprs(env);
2863 register_401x2_sprs(env);
2864 register_compress_sprs(env);
2865 /* Memory management */
2866 #if !defined(CONFIG_USER_ONLY)
2867 env->nb_tlb = 64;
2868 env->nb_ways = 1;
2869 env->id_tlbs = 0;
2870 env->tlb_type = TLB_EMB;
2871 #endif
2872 init_excp_4xx_softmmu(env);
2873 env->dcache_line_size = 32;
2874 env->icache_line_size = 32;
2875 /* Allocate hardware IRQ controller */
2876 ppc40x_irq_init(env_archcpu(env));
2878 SET_FIT_PERIOD(8, 12, 16, 20);
2879 SET_WDT_PERIOD(16, 20, 24, 28);
2880 }
2882 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
2883 {
2884 DeviceClass *dc = DEVICE_CLASS(oc);
2885 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2887 dc->desc = "IOP480";
2888 pcc->init_proc = init_proc_IOP480;
2889 pcc->check_pow = check_pow_nocheck;
2890 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2891 PPC_DCR | PPC_WRTEE |
2892 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2893 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2894 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2895 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2896 PPC_4xx_COMMON | PPC_40x_EXCP;
2897 pcc->msr_mask = (1ull << 20) |
2898 (1ull << MSR_KEY) |
2899 (1ull << MSR_POW) |
2900 (1ull << MSR_CE) |
2901 (1ull << MSR_ILE) |
2902 (1ull << MSR_EE) |
2903 (1ull << MSR_PR) |
2904 (1ull << MSR_ME) |
2905 (1ull << MSR_DE) |
2906 (1ull << MSR_IR) |
2907 (1ull << MSR_DR) |
2908 (1ull << MSR_LE);
2909 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
2910 pcc->excp_model = POWERPC_EXCP_40x;
2911 pcc->bus_model = PPC_FLAGS_INPUT_401;
2912 pcc->bfd_mach = bfd_mach_ppc_403;
2913 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
2914 POWERPC_FLAG_BUS_CLK;
2915 }
2917 static void init_proc_403(CPUPPCState *env)
2918 {
2919 register_40x_sprs(env);
2920 register_401_403_sprs(env);
2921 register_403_sprs(env);
2922 register_403_real_sprs(env);
2923 init_excp_4xx_real(env);
2924 env->dcache_line_size = 32;
2925 env->icache_line_size = 32;
2926 /* Allocate hardware IRQ controller */
2927 ppc40x_irq_init(env_archcpu(env));
2929 SET_FIT_PERIOD(8, 12, 16, 20);
2930 SET_WDT_PERIOD(16, 20, 24, 28);
2931 }
2933 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
2934 {
2935 DeviceClass *dc = DEVICE_CLASS(oc);
2936 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2938 dc->desc = "PowerPC 403";
2939 pcc->init_proc = init_proc_403;
2940 pcc->check_pow = check_pow_nocheck;
2941 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2942 PPC_DCR | PPC_WRTEE |
2943 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2944 PPC_CACHE_DCBZ |
2945 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2946 PPC_4xx_COMMON | PPC_40x_EXCP;
2947 pcc->msr_mask = (1ull << MSR_POW) |
2948 (1ull << MSR_CE) |
2949 (1ull << MSR_ILE) |
2950 (1ull << MSR_EE) |
2951 (1ull << MSR_PR) |
2952 (1ull << MSR_ME) |
2953 (1ull << MSR_PE) |
2954 (1ull << MSR_PX) |
2955 (1ull << MSR_LE);
2956 pcc->mmu_model = POWERPC_MMU_REAL;
2957 pcc->excp_model = POWERPC_EXCP_40x;
2958 pcc->bus_model = PPC_FLAGS_INPUT_401;
2959 pcc->bfd_mach = bfd_mach_ppc_403;
2960 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
2961 POWERPC_FLAG_BUS_CLK;
2962 }
2964 static void init_proc_403GCX(CPUPPCState *env)
2965 {
2966 register_40x_sprs(env);
2967 register_401_403_sprs(env);
2968 register_403_sprs(env);
2969 register_403_real_sprs(env);
2970 register_403_mmu_sprs(env);
2971 /* Bus access control */
2972 /* not emulated, as QEMU never does speculative access */
2973 spr_register(env, SPR_40x_SGR, "SGR",
2974 SPR_NOACCESS, SPR_NOACCESS,
2975 &spr_read_generic, &spr_write_generic,
2976 0xFFFFFFFF);
2977 /* not emulated, as QEMU do not emulate caches */
2978 spr_register(env, SPR_40x_DCWR, "DCWR",
2979 SPR_NOACCESS, SPR_NOACCESS,
2980 &spr_read_generic, &spr_write_generic,
2981 0x00000000);
2982 /* Memory management */
2983 #if !defined(CONFIG_USER_ONLY)
2984 env->nb_tlb = 64;
2985 env->nb_ways = 1;
2986 env->id_tlbs = 0;
2987 env->tlb_type = TLB_EMB;
2988 #endif
2989 init_excp_4xx_softmmu(env);
2990 env->dcache_line_size = 32;
2991 env->icache_line_size = 32;
2992 /* Allocate hardware IRQ controller */
2993 ppc40x_irq_init(env_archcpu(env));
2995 SET_FIT_PERIOD(8, 12, 16, 20);
2996 SET_WDT_PERIOD(16, 20, 24, 28);
2997 }
2999 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3000 {
3001 DeviceClass *dc = DEVICE_CLASS(oc);
3002 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3004 dc->desc = "PowerPC 403 GCX";
3005 pcc->init_proc = init_proc_403GCX;
3006 pcc->check_pow = check_pow_nocheck;
3007 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3008 PPC_DCR | PPC_WRTEE |
3009 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3010 PPC_CACHE_DCBZ |
3011 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3012 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3013 PPC_4xx_COMMON | PPC_40x_EXCP;
3014 pcc->msr_mask = (1ull << MSR_POW) |
3015 (1ull << MSR_CE) |
3016 (1ull << MSR_ILE) |
3017 (1ull << MSR_EE) |
3018 (1ull << MSR_PR) |
3019 (1ull << MSR_ME) |
3020 (1ull << MSR_PE) |
3021 (1ull << MSR_PX) |
3022 (1ull << MSR_LE);
3023 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3024 pcc->excp_model = POWERPC_EXCP_40x;
3025 pcc->bus_model = PPC_FLAGS_INPUT_401;
3026 pcc->bfd_mach = bfd_mach_ppc_403;
3027 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3028 POWERPC_FLAG_BUS_CLK;
3029 }
3031 static void init_proc_405(CPUPPCState *env)
3032 {
3033 /* Time base */
3034 register_tbl(env);
3035 register_40x_sprs(env);
3036 register_405_sprs(env);
3037 /* Bus access control */
3038 /* not emulated, as QEMU never does speculative access */
3039 spr_register(env, SPR_40x_SGR, "SGR",
3040 SPR_NOACCESS, SPR_NOACCESS,
3041 &spr_read_generic, &spr_write_generic,
3042 0xFFFFFFFF);
3043 /* not emulated, as QEMU do not emulate caches */
3044 spr_register(env, SPR_40x_DCWR, "DCWR",
3045 SPR_NOACCESS, SPR_NOACCESS,
3046 &spr_read_generic, &spr_write_generic,
3047 0x00000000);
3048 /* Memory management */
3049 #if !defined(CONFIG_USER_ONLY)
3050 env->nb_tlb = 64;
3051 env->nb_ways = 1;
3052 env->id_tlbs = 0;
3053 env->tlb_type = TLB_EMB;
3054 #endif
3055 init_excp_4xx_softmmu(env);
3056 env->dcache_line_size = 32;
3057 env->icache_line_size = 32;
3058 /* Allocate hardware IRQ controller */
3059 ppc40x_irq_init(env_archcpu(env));
3061 SET_FIT_PERIOD(8, 12, 16, 20);
3062 SET_WDT_PERIOD(16, 20, 24, 28);
3063 }
3065 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3066 {
3067 DeviceClass *dc = DEVICE_CLASS(oc);
3068 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3070 dc->desc = "PowerPC 405";
3071 pcc->init_proc = init_proc_405;
3072 pcc->check_pow = check_pow_nocheck;
3073 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3074 PPC_DCR | PPC_WRTEE |
3075 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3076 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3077 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3078 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3079 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3080 pcc->msr_mask = (1ull << MSR_POW) |
3081 (1ull << MSR_CE) |
3082 (1ull << MSR_EE) |
3083 (1ull << MSR_PR) |
3084 (1ull << MSR_FP) |
3085 (1ull << MSR_DWE) |
3086 (1ull << MSR_DE) |
3087 (1ull << MSR_IR) |
3088 (1ull << MSR_DR);
3089 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3090 pcc->excp_model = POWERPC_EXCP_40x;
3091 pcc->bus_model = PPC_FLAGS_INPUT_405;
3092 pcc->bfd_mach = bfd_mach_ppc_403;
3093 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3094 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3095 }
3097 static void init_proc_440EP(CPUPPCState *env)
3098 {
3099 /* Time base */
3100 register_tbl(env);
3101 register_BookE_sprs(env, 0x000000000000FFFFULL);
3102 register_440_sprs(env);
3103 register_usprgh_sprs(env);
3104 /* Processor identification */
3105 spr_register(env, SPR_BOOKE_PIR, "PIR",
3106 SPR_NOACCESS, SPR_NOACCESS,
3107 &spr_read_generic, &spr_write_pir,
3108 0x00000000);
3109 /* XXX : not implemented */
3110 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3111 SPR_NOACCESS, SPR_NOACCESS,
3112 &spr_read_generic, &spr_write_generic,
3113 0x00000000);
3114 /* XXX : not implemented */
3115 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3116 SPR_NOACCESS, SPR_NOACCESS,
3117 &spr_read_generic, &spr_write_generic,
3118 0x00000000);
3119 /* XXX : not implemented */
3120 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3121 SPR_NOACCESS, SPR_NOACCESS,
3122 &spr_read_generic, &spr_write_generic,
3123 0x00000000);
3124 /* XXX : not implemented */
3125 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3126 SPR_NOACCESS, SPR_NOACCESS,
3127 &spr_read_generic, &spr_write_generic,
3128 0x00000000);
3129 /* XXX : not implemented */
3130 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3131 SPR_NOACCESS, SPR_NOACCESS,
3132 &spr_read_generic, &spr_write_generic,
3133 0x00000000);
3134 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3135 SPR_NOACCESS, SPR_NOACCESS,
3136 &spr_read_generic, &spr_write_generic,
3137 0x00000000);
3138 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3139 SPR_NOACCESS, SPR_NOACCESS,
3140 &spr_read_generic, &spr_write_generic,
3141 0x00000000);
3142 /* XXX : not implemented */
3143 spr_register(env, SPR_440_CCR1, "CCR1",
3144 SPR_NOACCESS, SPR_NOACCESS,
3145 &spr_read_generic, &spr_write_generic,
3146 0x00000000);
3147 /* Memory management */
3148 #if !defined(CONFIG_USER_ONLY)
3149 env->nb_tlb = 64;
3150 env->nb_ways = 1;
3151 env->id_tlbs = 0;
3152 env->tlb_type = TLB_EMB;
3153 #endif
3154 init_excp_BookE(env);
3155 env->dcache_line_size = 32;
3156 env->icache_line_size = 32;
3157 ppc40x_irq_init(env_archcpu(env));
3159 SET_FIT_PERIOD(12, 16, 20, 24);
3160 SET_WDT_PERIOD(20, 24, 28, 32);
3161 }
3163 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3164 {
3165 DeviceClass *dc = DEVICE_CLASS(oc);
3166 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3168 dc->desc = "PowerPC 440 EP";
3169 pcc->init_proc = init_proc_440EP;
3170 pcc->check_pow = check_pow_nocheck;
3171 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3172 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3173 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3174 PPC_FLOAT_STFIWX |
3175 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3176 PPC_CACHE | PPC_CACHE_ICBI |
3177 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3178 PPC_MEM_TLBSYNC | PPC_MFTB |
3179 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3180 PPC_440_SPEC;
3181 pcc->msr_mask = (1ull << MSR_POW) |
3182 (1ull << MSR_CE) |
3183 (1ull << MSR_EE) |
3184 (1ull << MSR_PR) |
3185 (1ull << MSR_FP) |
3186 (1ull << MSR_ME) |
3187 (1ull << MSR_FE0) |
3188 (1ull << MSR_DWE) |
3189 (1ull << MSR_DE) |
3190 (1ull << MSR_FE1) |
3191 (1ull << MSR_IR) |
3192 (1ull << MSR_DR);
3193 pcc->mmu_model = POWERPC_MMU_BOOKE;
3194 pcc->excp_model = POWERPC_EXCP_BOOKE;
3195 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3196 pcc->bfd_mach = bfd_mach_ppc_403;
3197 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3198 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3199 }
3201 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
3202 {
3203 DeviceClass *dc = DEVICE_CLASS(oc);
3204 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3206 dc->desc = "PowerPC 460 EX";
3207 pcc->init_proc = init_proc_440EP;
3208 pcc->check_pow = check_pow_nocheck;
3209 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3210 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3211 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3212 PPC_FLOAT_STFIWX |
3213 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
3214 PPC_CACHE | PPC_CACHE_ICBI |
3215 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3216 PPC_MEM_TLBSYNC | PPC_MFTB |
3217 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3218 PPC_440_SPEC;
3219 pcc->msr_mask = (1ull << MSR_POW) |
3220 (1ull << MSR_CE) |
3221 (1ull << MSR_EE) |
3222 (1ull << MSR_PR) |
3223 (1ull << MSR_FP) |
3224 (1ull << MSR_ME) |
3225 (1ull << MSR_FE0) |
3226 (1ull << MSR_DWE) |
3227 (1ull << MSR_DE) |
3228 (1ull << MSR_FE1) |
3229 (1ull << MSR_IR) |
3230 (1ull << MSR_DR);
3231 pcc->mmu_model = POWERPC_MMU_BOOKE;
3232 pcc->excp_model = POWERPC_EXCP_BOOKE;
3233 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3234 pcc->bfd_mach = bfd_mach_ppc_403;
3235 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3236 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3237 }
3239 static void init_proc_440GP(CPUPPCState *env)
3240 {
3241 /* Time base */
3242 register_tbl(env);
3243 register_BookE_sprs(env, 0x000000000000FFFFULL);
3244 register_440_sprs(env);
3245 register_usprgh_sprs(env);
3246 /* Processor identification */
3247 spr_register(env, SPR_BOOKE_PIR, "PIR",
3248 SPR_NOACCESS, SPR_NOACCESS,
3249 &spr_read_generic, &spr_write_pir,
3250 0x00000000);
3251 /* XXX : not implemented */
3252 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3253 SPR_NOACCESS, SPR_NOACCESS,
3254 &spr_read_generic, &spr_write_generic,
3255 0x00000000);
3256 /* XXX : not implemented */
3257 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3258 SPR_NOACCESS, SPR_NOACCESS,
3259 &spr_read_generic, &spr_write_generic,
3260 0x00000000);
3261 /* XXX : not implemented */
3262 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3263 SPR_NOACCESS, SPR_NOACCESS,
3264 &spr_read_generic, &spr_write_generic,
3265 0x00000000);
3266 /* XXX : not implemented */
3267 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3268 SPR_NOACCESS, SPR_NOACCESS,
3269 &spr_read_generic, &spr_write_generic,
3270 0x00000000);
3271 /* Memory management */
3272 #if !defined(CONFIG_USER_ONLY)
3273 env->nb_tlb = 64;
3274 env->nb_ways = 1;
3275 env->id_tlbs = 0;
3276 env->tlb_type = TLB_EMB;
3277 #endif
3278 init_excp_BookE(env);
3279 env->dcache_line_size = 32;
3280 env->icache_line_size = 32;
3281 /* XXX: TODO: allocate internal IRQ controller */
3283 SET_FIT_PERIOD(12, 16, 20, 24);
3284 SET_WDT_PERIOD(20, 24, 28, 32);
3285 }
3287 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3288 {
3289 DeviceClass *dc = DEVICE_CLASS(oc);
3290 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3292 dc->desc = "PowerPC 440 GP";
3293 pcc->init_proc = init_proc_440GP;
3294 pcc->check_pow = check_pow_nocheck;
3295 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3296 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3297 PPC_CACHE | PPC_CACHE_ICBI |
3298 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3299 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3300 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3301 PPC_440_SPEC;
3302 pcc->msr_mask = (1ull << MSR_POW) |
3303 (1ull << MSR_CE) |
3304 (1ull << MSR_EE) |
3305 (1ull << MSR_PR) |
3306 (1ull << MSR_FP) |
3307 (1ull << MSR_ME) |
3308 (1ull << MSR_FE0) |
3309 (1ull << MSR_DWE) |
3310 (1ull << MSR_DE) |
3311 (1ull << MSR_FE1) |
3312 (1ull << MSR_IR) |
3313 (1ull << MSR_DR);
3314 pcc->mmu_model = POWERPC_MMU_BOOKE;
3315 pcc->excp_model = POWERPC_EXCP_BOOKE;
3316 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3317 pcc->bfd_mach = bfd_mach_ppc_403;
3318 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3319 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3320 }
3322 static void init_proc_440x4(CPUPPCState *env)
3323 {
3324 /* Time base */
3325 register_tbl(env);
3326 register_BookE_sprs(env, 0x000000000000FFFFULL);
3327 register_440_sprs(env);
3328 register_usprgh_sprs(env);
3329 /* Processor identification */
3330 spr_register(env, SPR_BOOKE_PIR, "PIR",
3331 SPR_NOACCESS, SPR_NOACCESS,
3332 &spr_read_generic, &spr_write_pir,
3333 0x00000000);
3334 /* XXX : not implemented */
3335 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3336 SPR_NOACCESS, SPR_NOACCESS,
3337 &spr_read_generic, &spr_write_generic,
3338 0x00000000);
3339 /* XXX : not implemented */
3340 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3341 SPR_NOACCESS, SPR_NOACCESS,
3342 &spr_read_generic, &spr_write_generic,
3343 0x00000000);
3344 /* XXX : not implemented */
3345 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3346 SPR_NOACCESS, SPR_NOACCESS,
3347 &spr_read_generic, &spr_write_generic,
3348 0x00000000);
3349 /* XXX : not implemented */
3350 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3351 SPR_NOACCESS, SPR_NOACCESS,
3352 &spr_read_generic, &spr_write_generic,
3353 0x00000000);
3354 /* Memory management */
3355 #if !defined(CONFIG_USER_ONLY)
3356 env->nb_tlb = 64;
3357 env->nb_ways = 1;
3358 env->id_tlbs = 0;
3359 env->tlb_type = TLB_EMB;
3360 #endif
3361 init_excp_BookE(env);
3362 env->dcache_line_size = 32;
3363 env->icache_line_size = 32;
3364 /* XXX: TODO: allocate internal IRQ controller */
3366 SET_FIT_PERIOD(12, 16, 20, 24);
3367 SET_WDT_PERIOD(20, 24, 28, 32);
3368 }
3370 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3371 {
3372 DeviceClass *dc = DEVICE_CLASS(oc);
3373 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3375 dc->desc = "PowerPC 440x4";
3376 pcc->init_proc = init_proc_440x4;
3377 pcc->check_pow = check_pow_nocheck;
3378 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3379 PPC_DCR | PPC_WRTEE |
3380 PPC_CACHE | PPC_CACHE_ICBI |
3381 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3382 PPC_MEM_TLBSYNC | PPC_MFTB |
3383 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3384 PPC_440_SPEC;
3385 pcc->msr_mask = (1ull << MSR_POW) |
3386 (1ull << MSR_CE) |
3387 (1ull << MSR_EE) |
3388 (1ull << MSR_PR) |
3389 (1ull << MSR_FP) |
3390 (1ull << MSR_ME) |
3391 (1ull << MSR_FE0) |
3392 (1ull << MSR_DWE) |
3393 (1ull << MSR_DE) |
3394 (1ull << MSR_FE1) |
3395 (1ull << MSR_IR) |
3396 (1ull << MSR_DR);
3397 pcc->mmu_model = POWERPC_MMU_BOOKE;
3398 pcc->excp_model = POWERPC_EXCP_BOOKE;
3399 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3400 pcc->bfd_mach = bfd_mach_ppc_403;
3401 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3402 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3403 }
3405 static void init_proc_440x5(CPUPPCState *env)
3406 {
3407 /* Time base */
3408 register_tbl(env);
3409 register_BookE_sprs(env, 0x000000000000FFFFULL);
3410 register_440_sprs(env);
3411 register_usprgh_sprs(env);
3412 /* Processor identification */
3413 spr_register(env, SPR_BOOKE_PIR, "PIR",
3414 SPR_NOACCESS, SPR_NOACCESS,
3415 &spr_read_generic, &spr_write_pir,
3416 0x00000000);
3417 /* XXX : not implemented */
3418 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3419 SPR_NOACCESS, SPR_NOACCESS,
3420 &spr_read_generic, &spr_write_generic,
3421 0x00000000);
3422 /* XXX : not implemented */
3423 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3424 SPR_NOACCESS, SPR_NOACCESS,
3425 &spr_read_generic, &spr_write_generic,
3426 0x00000000);
3427 /* XXX : not implemented */
3428 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3429 SPR_NOACCESS, SPR_NOACCESS,
3430 &spr_read_generic, &spr_write_generic,
3431 0x00000000);
3432 /* XXX : not implemented */
3433 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3434 SPR_NOACCESS, SPR_NOACCESS,
3435 &spr_read_generic, &spr_write_generic,
3436 0x00000000);
3437 /* XXX : not implemented */
3438 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3439 SPR_NOACCESS, SPR_NOACCESS,
3440 &spr_read_generic, &spr_write_generic,
3441 0x00000000);
3442 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3443 SPR_NOACCESS, SPR_NOACCESS,
3444 &spr_read_generic, &spr_write_generic,
3445 0x00000000);
3446 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3447 SPR_NOACCESS, SPR_NOACCESS,
3448 &spr_read_generic, &spr_write_generic,
3449 0x00000000);
3450 /* XXX : not implemented */
3451 spr_register(env, SPR_440_CCR1, "CCR1",
3452 SPR_NOACCESS, SPR_NOACCESS,
3453 &spr_read_generic, &spr_write_generic,
3454 0x00000000);
3455 /* Memory management */
3456 #if !defined(CONFIG_USER_ONLY)
3457 env->nb_tlb = 64;
3458 env->nb_ways = 1;
3459 env->id_tlbs = 0;
3460 env->tlb_type = TLB_EMB;
3461 #endif
3462 init_excp_BookE(env);
3463 env->dcache_line_size = 32;
3464 env->icache_line_size = 32;
3465 ppc40x_irq_init(env_archcpu(env));
3467 SET_FIT_PERIOD(12, 16, 20, 24);
3468 SET_WDT_PERIOD(20, 24, 28, 32);
3469 }
3471 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3472 {
3473 DeviceClass *dc = DEVICE_CLASS(oc);
3474 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3476 dc->desc = "PowerPC 440x5";
3477 pcc->init_proc = init_proc_440x5;
3478 pcc->check_pow = check_pow_nocheck;
3479 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3480 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3481 PPC_CACHE | PPC_CACHE_ICBI |
3482 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3483 PPC_MEM_TLBSYNC | PPC_MFTB |
3484 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3485 PPC_440_SPEC;
3486 pcc->msr_mask = (1ull << MSR_POW) |
3487 (1ull << MSR_CE) |
3488 (1ull << MSR_EE) |
3489 (1ull << MSR_PR) |
3490 (1ull << MSR_FP) |
3491 (1ull << MSR_ME) |
3492 (1ull << MSR_FE0) |
3493 (1ull << MSR_DWE) |
3494 (1ull << MSR_DE) |
3495 (1ull << MSR_FE1) |
3496 (1ull << MSR_IR) |
3497 (1ull << MSR_DR);
3498 pcc->mmu_model = POWERPC_MMU_BOOKE;
3499 pcc->excp_model = POWERPC_EXCP_BOOKE;
3500 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3501 pcc->bfd_mach = bfd_mach_ppc_403;
3502 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3503 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3504 }
3506 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
3507 {
3508 DeviceClass *dc = DEVICE_CLASS(oc);
3509 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3511 dc->desc = "PowerPC 440x5 with double precision FPU";
3512 pcc->init_proc = init_proc_440x5;
3513 pcc->check_pow = check_pow_nocheck;
3514 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3515 PPC_FLOAT | PPC_FLOAT_FSQRT |
3516 PPC_FLOAT_STFIWX |
3517 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3518 PPC_CACHE | PPC_CACHE_ICBI |
3519 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3520 PPC_MEM_TLBSYNC | PPC_MFTB |
3521 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3522 PPC_440_SPEC;
3523 pcc->insns_flags2 = PPC2_FP_CVT_S64;
3524 pcc->msr_mask = (1ull << MSR_POW) |
3525 (1ull << MSR_CE) |
3526 (1ull << MSR_EE) |
3527 (1ull << MSR_PR) |
3528 (1ull << MSR_FP) |
3529 (1ull << MSR_ME) |
3530 (1ull << MSR_FE0) |
3531 (1ull << MSR_DWE) |
3532 (1ull << MSR_DE) |
3533 (1ull << MSR_FE1) |
3534 (1ull << MSR_IR) |
3535 (1ull << MSR_DR);
3536 pcc->mmu_model = POWERPC_MMU_BOOKE;
3537 pcc->excp_model = POWERPC_EXCP_BOOKE;
3538 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3539 pcc->bfd_mach = bfd_mach_ppc_403;
3540 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3541 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3542 }
3544 static void init_proc_MPC5xx(CPUPPCState *env)
3545 {
3546 /* Time base */
3547 register_tbl(env);
3548 register_5xx_8xx_sprs(env);
3549 register_5xx_sprs(env);
3550 init_excp_MPC5xx(env);
3551 env->dcache_line_size = 32;
3552 env->icache_line_size = 32;
3553 /* XXX: TODO: allocate internal IRQ controller */
3554 }
3556 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
3557 {
3558 DeviceClass *dc = DEVICE_CLASS(oc);
3559 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3561 dc->desc = "Freescale 5xx cores (aka RCPU)";
3562 pcc->init_proc = init_proc_MPC5xx;
3563 pcc->check_pow = check_pow_none;
3564 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3565 PPC_MEM_EIEIO | PPC_MEM_SYNC |
3566 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
3567 PPC_MFTB;
3568 pcc->msr_mask = (1ull << MSR_ILE) |
3569 (1ull << MSR_EE) |
3570 (1ull << MSR_PR) |
3571 (1ull << MSR_FP) |
3572 (1ull << MSR_ME) |
3573 (1ull << MSR_FE0) |
3574 (1ull << MSR_SE) |
3575 (1ull << MSR_DE) |
3576 (1ull << MSR_FE1) |
3577 (1ull << MSR_EP) |
3578 (1ull << MSR_RI) |
3579 (1ull << MSR_LE);
3580 pcc->mmu_model = POWERPC_MMU_REAL;
3581 pcc->excp_model = POWERPC_EXCP_603;
3582 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
3583 pcc->bfd_mach = bfd_mach_ppc_505;
3584 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3585 POWERPC_FLAG_BUS_CLK;
3586 }
3588 static void init_proc_MPC8xx(CPUPPCState *env)
3589 {
3590 /* Time base */
3591 register_tbl(env);
3592 register_5xx_8xx_sprs(env);
3593 register_8xx_sprs(env);
3594 init_excp_MPC8xx(env);
3595 env->dcache_line_size = 32;
3596 env->icache_line_size = 32;
3597 /* XXX: TODO: allocate internal IRQ controller */
3598 }
3600 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
3601 {
3602 DeviceClass *dc = DEVICE_CLASS(oc);
3603 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3605 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
3606 pcc->init_proc = init_proc_MPC8xx;
3607 pcc->check_pow = check_pow_none;
3608 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3609 PPC_MEM_EIEIO | PPC_MEM_SYNC |
3610 PPC_CACHE_ICBI | PPC_MFTB;
3611 pcc->msr_mask = (1ull << MSR_ILE) |
3612 (1ull << MSR_EE) |
3613 (1ull << MSR_PR) |
3614 (1ull << MSR_FP) |
3615 (1ull << MSR_ME) |
3616 (1ull << MSR_SE) |
3617 (1ull << MSR_DE) |
3618 (1ull << MSR_EP) |
3619 (1ull << MSR_IR) |
3620 (1ull << MSR_DR) |
3621 (1ull << MSR_RI) |
3622 (1ull << MSR_LE);
3623 pcc->mmu_model = POWERPC_MMU_MPC8xx;
3624 pcc->excp_model = POWERPC_EXCP_603;
3625 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
3626 pcc->bfd_mach = bfd_mach_ppc_860;
3627 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3628 POWERPC_FLAG_BUS_CLK;
3629 }
3631 /* Freescale 82xx cores (aka PowerQUICC-II) */
3633 static void init_proc_G2(CPUPPCState *env)
3634 {
3635 register_ne_601_sprs(env);
3636 register_sdr1_sprs(env);
3637 register_G2_755_sprs(env);
3638 register_G2_sprs(env);
3639 /* Time base */
3640 register_tbl(env);
3641 /* External access control */
3642 /* XXX : not implemented */
3643 spr_register(env, SPR_EAR, "EAR",
3644 SPR_NOACCESS, SPR_NOACCESS,
3645 &spr_read_generic, &spr_write_generic,
3646 0x00000000);
3647 /* Hardware implementation register */
3648 /* XXX : not implemented */
3649 spr_register(env, SPR_HID0, "HID0",
3650 SPR_NOACCESS, SPR_NOACCESS,
3651 &spr_read_generic, &spr_write_generic,
3652 0x00000000);
3653 /* XXX : not implemented */
3654 spr_register(env, SPR_HID1, "HID1",
3655 SPR_NOACCESS, SPR_NOACCESS,
3656 &spr_read_generic, &spr_write_generic,
3657 0x00000000);
3658 /* XXX : not implemented */
3659 spr_register(env, SPR_HID2, "HID2",
3660 SPR_NOACCESS, SPR_NOACCESS,
3661 &spr_read_generic, &spr_write_generic,
3662 0x00000000);
3663 /* Memory management */
3664 register_low_BATs(env);
3665 register_high_BATs(env);
3666 register_6xx_7xx_soft_tlb(env, 64, 2);
3667 init_excp_G2(env);
3668 env->dcache_line_size = 32;
3669 env->icache_line_size = 32;
3670 /* Allocate hardware IRQ controller */
3671 ppc6xx_irq_init(env_archcpu(env));
3672 }
3674 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
3675 {
3676 DeviceClass *dc = DEVICE_CLASS(oc);
3677 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3679 dc->desc = "PowerPC G2";
3680 pcc->init_proc = init_proc_G2;
3681 pcc->check_pow = check_pow_hid0;
3682 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3683 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3684 PPC_FLOAT_STFIWX |
3685 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3686 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3687 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3688 PPC_SEGMENT | PPC_EXTERN;
3689 pcc->msr_mask = (1ull << MSR_POW) |
3690 (1ull << MSR_TGPR) |
3691 (1ull << MSR_EE) |
3692 (1ull << MSR_PR) |
3693 (1ull << MSR_FP) |
3694 (1ull << MSR_ME) |
3695 (1ull << MSR_FE0) |
3696 (1ull << MSR_SE) |
3697 (1ull << MSR_DE) |
3698 (1ull << MSR_FE1) |
3699 (1ull << MSR_AL) |
3700 (1ull << MSR_EP) |
3701 (1ull << MSR_IR) |
3702 (1ull << MSR_DR) |
3703 (1ull << MSR_RI);
3704 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3705 pcc->excp_model = POWERPC_EXCP_G2;
3706 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3707 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3708 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3709 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3710 }
3712 static void init_proc_G2LE(CPUPPCState *env)
3713 {
3714 register_ne_601_sprs(env);
3715 register_sdr1_sprs(env);
3716 register_G2_755_sprs(env);
3717 register_G2_sprs(env);
3718 /* Time base */
3719 register_tbl(env);
3720 /* External access control */
3721 /* XXX : not implemented */
3722 spr_register(env, SPR_EAR, "EAR",
3723 SPR_NOACCESS, SPR_NOACCESS,
3724 &spr_read_generic, &spr_write_generic,
3725 0x00000000);
3726 /* Hardware implementation register */
3727 /* XXX : not implemented */
3728 spr_register(env, SPR_HID0, "HID0",
3729 SPR_NOACCESS, SPR_NOACCESS,
3730 &spr_read_generic, &spr_write_generic,
3731 0x00000000);
3732 /* XXX : not implemented */
3733 spr_register(env, SPR_HID1, "HID1",
3734 SPR_NOACCESS, SPR_NOACCESS,
3735 &spr_read_generic, &spr_write_generic,
3736 0x00000000);
3737 /* XXX : not implemented */
3738 spr_register(env, SPR_HID2, "HID2",
3739 SPR_NOACCESS, SPR_NOACCESS,
3740 &spr_read_generic, &spr_write_generic,
3741 0x00000000);
3743 /* Memory management */
3744 register_low_BATs(env);
3745 register_high_BATs(env);
3746 register_6xx_7xx_soft_tlb(env, 64, 2);
3747 init_excp_G2(env);
3748 env->dcache_line_size = 32;
3749 env->icache_line_size = 32;
3750 /* Allocate hardware IRQ controller */
3751 ppc6xx_irq_init(env_archcpu(env));
3752 }
3754 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
3755 {
3756 DeviceClass *dc = DEVICE_CLASS(oc);
3757 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3759 dc->desc = "PowerPC G2LE";
3760 pcc->init_proc = init_proc_G2LE;
3761 pcc->check_pow = check_pow_hid0;
3762 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3763 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3764 PPC_FLOAT_STFIWX |
3765 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3766 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3767 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3768 PPC_SEGMENT | PPC_EXTERN;
3769 pcc->msr_mask = (1ull << MSR_POW) |
3770 (1ull << MSR_TGPR) |
3771 (1ull << MSR_ILE) |
3772 (1ull << MSR_EE) |
3773 (1ull << MSR_PR) |
3774 (1ull << MSR_FP) |
3775 (1ull << MSR_ME) |
3776 (1ull << MSR_FE0) |
3777 (1ull << MSR_SE) |
3778 (1ull << MSR_DE) |
3779 (1ull << MSR_FE1) |
3780 (1ull << MSR_AL) |
3781 (1ull << MSR_EP) |
3782 (1ull << MSR_IR) |
3783 (1ull << MSR_DR) |
3784 (1ull << MSR_RI) |
3785 (1ull << MSR_LE);
3786 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3787 pcc->excp_model = POWERPC_EXCP_G2;
3788 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3789 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3790 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3791 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3792 }
3794 static void init_proc_e200(CPUPPCState *env)
3795 {
3796 /* Time base */
3797 register_tbl(env);
3798 register_BookE_sprs(env, 0x000000070000FFFFULL);
3799 /* XXX : not implemented */
3800 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
3801 &spr_read_spefscr, &spr_write_spefscr,
3802 &spr_read_spefscr, &spr_write_spefscr,
3803 0x00000000);
3804 /* Memory management */
3805 register_BookE206_sprs(env, 0x0000005D, NULL, 0);
3806 /* XXX : not implemented */
3807 spr_register(env, SPR_HID0, "HID0",
3808 SPR_NOACCESS, SPR_NOACCESS,
3809 &spr_read_generic, &spr_write_generic,
3810 0x00000000);
3811 /* XXX : not implemented */
3812 spr_register(env, SPR_HID1, "HID1",
3813 SPR_NOACCESS, SPR_NOACCESS,
3814 &spr_read_generic, &spr_write_generic,
3815 0x00000000);
3816 /* XXX : not implemented */
3817 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
3818 SPR_NOACCESS, SPR_NOACCESS,
3819 &spr_read_generic, &spr_write_generic,
3820 0x00000000);
3821 /* XXX : not implemented */
3822 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3823 SPR_NOACCESS, SPR_NOACCESS,
3824 &spr_read_generic, &spr_write_generic,
3825 0x00000000);
3826 /* XXX : not implemented */
3827 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
3828 SPR_NOACCESS, SPR_NOACCESS,
3829 &spr_read_generic, &spr_write_generic,
3830 0x00000000);
3831 /* XXX : not implemented */
3832 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
3833 SPR_NOACCESS, SPR_NOACCESS,
3834 &spr_read_generic, &spr_write_generic,
3835 0x00000000);
3836 /* XXX : not implemented */
3837 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
3838 SPR_NOACCESS, SPR_NOACCESS,
3839 &spr_read_generic, &spr_write_generic,
3840 0x00000000);
3841 /* XXX : not implemented */
3842 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3843 &spr_read_generic, SPR_NOACCESS,
3844 &spr_read_generic, SPR_NOACCESS,
3845 0x00000000);
3846 /* XXX : not implemented */
3847 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
3848 SPR_NOACCESS, SPR_NOACCESS,
3849 &spr_read_generic, &spr_write_generic,
3850 0x00000000);
3851 /* XXX : not implemented */
3852 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
3853 SPR_NOACCESS, SPR_NOACCESS,
3854 &spr_read_generic, &spr_write_generic,
3855 0x00000000);
3856 /* XXX : not implemented */
3857 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
3858 SPR_NOACCESS, SPR_NOACCESS,
3859 &spr_read_generic, &spr_write_generic,
3860 0x00000000);
3861 /* XXX : not implemented */
3862 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
3863 SPR_NOACCESS, SPR_NOACCESS,
3864 &spr_read_generic, &spr_write_generic,
3865 0x00000000);
3866 /* XXX : not implemented */
3867 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3868 SPR_NOACCESS, SPR_NOACCESS,
3869 &spr_read_generic, &spr_write_generic,
3870 0x00000000);
3871 /* XXX : not implemented */
3872 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3873 SPR_NOACCESS, SPR_NOACCESS,
3874 &spr_read_generic, &spr_write_generic,
3875 0x00000000);
3876 /* XXX : not implemented */
3877 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
3878 SPR_NOACCESS, SPR_NOACCESS,
3879 &spr_read_generic, &spr_write_generic,
3880 0x00000000); /* TOFIX */
3881 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
3882 SPR_NOACCESS, SPR_NOACCESS,
3883 &spr_read_generic, &spr_write_generic,
3884 0x00000000);
3885 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
3886 SPR_NOACCESS, SPR_NOACCESS,
3887 &spr_read_generic, &spr_write_generic,
3888 0x00000000);
3889 #if !defined(CONFIG_USER_ONLY)
3890 env->nb_tlb = 64;
3891 env->nb_ways = 1;
3892 env->id_tlbs = 0;
3893 env->tlb_type = TLB_EMB;
3894 #endif
3895 init_excp_e200(env, 0xFFFF0000UL);
3896 env->dcache_line_size = 32;
3897 env->icache_line_size = 32;
3898 /* XXX: TODO: allocate internal IRQ controller */
3899 }
3901 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
3902 {
3903 DeviceClass *dc = DEVICE_CLASS(oc);
3904 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3906 dc->desc = "e200 core";
3907 pcc->init_proc = init_proc_e200;
3908 pcc->check_pow = check_pow_hid0;
3909 /*
3910 * XXX: unimplemented instructions:
3911 * dcblc
3912 * dcbtlst
3913 * dcbtstls
3914 * icblc
3915 * icbtls
3916 * tlbivax
3917 * all SPE multiply-accumulate instructions
3918 */
3919 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3920 PPC_SPE | PPC_SPE_SINGLE |
3921 PPC_WRTEE | PPC_RFDI |
3922 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3923 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3924 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
3925 PPC_BOOKE;
3926 pcc->msr_mask = (1ull << MSR_UCLE) |
3927 (1ull << MSR_SPE) |
3928 (1ull << MSR_POW) |
3929 (1ull << MSR_CE) |
3930 (1ull << MSR_EE) |
3931 (1ull << MSR_PR) |
3932 (1ull << MSR_FP) |
3933 (1ull << MSR_ME) |
3934 (1ull << MSR_FE0) |
3935 (1ull << MSR_DWE) |
3936 (1ull << MSR_DE) |
3937 (1ull << MSR_FE1) |
3938 (1ull << MSR_IR) |
3939 (1ull << MSR_DR);
3940 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3941 pcc->excp_model = POWERPC_EXCP_BOOKE;
3942 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3943 pcc->bfd_mach = bfd_mach_ppc_860;
3944 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3945 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3946 POWERPC_FLAG_BUS_CLK;
3947 }
3949 static void init_proc_e300(CPUPPCState *env)
3950 {
3951 register_ne_601_sprs(env);
3952 register_sdr1_sprs(env);
3953 register_603_sprs(env);
3954 /* Time base */
3955 register_tbl(env);
3956 /* hardware implementation registers */
3957 /* XXX : not implemented */
3958 spr_register(env, SPR_HID0, "HID0",
3959 SPR_NOACCESS, SPR_NOACCESS,
3960 &spr_read_generic, &spr_write_generic,
3961 0x00000000);
3962 /* XXX : not implemented */
3963 spr_register(env, SPR_HID1, "HID1",
3964 SPR_NOACCESS, SPR_NOACCESS,
3965 &spr_read_generic, &spr_write_generic,
3966 0x00000000);
3967 /* XXX : not implemented */
3968 spr_register(env, SPR_HID2, "HID2",
3969 SPR_NOACCESS, SPR_NOACCESS,
3970 &spr_read_generic, &spr_write_generic,
3971 0x00000000);
3972 /* Breakpoints */
3973 /* XXX : not implemented */
3974 spr_register(env, SPR_DABR, "DABR",
3975 SPR_NOACCESS, SPR_NOACCESS,
3976 &spr_read_generic, &spr_write_generic,
3977 0x00000000);
3978 /* XXX : not implemented */
3979 spr_register(env, SPR_DABR2, "DABR2",
3980 SPR_NOACCESS, SPR_NOACCESS,
3981 &spr_read_generic, &spr_write_generic,
3982 0x00000000);
3983 /* XXX : not implemented */
3984 spr_register(env, SPR_IABR2, "IABR2",
3985 SPR_NOACCESS, SPR_NOACCESS,
3986 &spr_read_generic, &spr_write_generic,
3987 0x00000000);
3988 /* XXX : not implemented */
3989 spr_register(env, SPR_IBCR, "IBCR",
3990 SPR_NOACCESS, SPR_NOACCESS,
3991 &spr_read_generic, &spr_write_generic,
3992 0x00000000);
3993 /* XXX : not implemented */
3994 spr_register(env, SPR_DBCR, "DBCR",
3995 SPR_NOACCESS, SPR_NOACCESS,
3996 &spr_read_generic, &spr_write_generic,
3997 0x00000000);
3998 /* Memory management */
3999 register_low_BATs(env);
4000 register_high_BATs(env);
4001 register_6xx_7xx_soft_tlb(env, 64, 2);
4002 init_excp_603(env);
4003 env->dcache_line_size = 32;
4004 env->icache_line_size = 32;
4005 /* Allocate hardware IRQ controller */
4006 ppc6xx_irq_init(env_archcpu(env));
4007 }
4009 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4010 {
4011 DeviceClass *dc = DEVICE_CLASS(oc);
4012 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4014 dc->desc = "e300 core";
4015 pcc->init_proc = init_proc_e300;
4016 pcc->check_pow = check_pow_hid0;
4017 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4018 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4019 PPC_FLOAT_STFIWX |
4020 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4021 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4022 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4023 PPC_SEGMENT | PPC_EXTERN;
4024 pcc->msr_mask = (1ull << MSR_POW) |
4025 (1ull << MSR_TGPR) |
4026 (1ull << MSR_ILE) |
4027 (1ull << MSR_EE) |
4028 (1ull << MSR_PR) |
4029 (1ull << MSR_FP) |
4030 (1ull << MSR_ME) |
4031 (1ull << MSR_FE0) |
4032 (1ull << MSR_SE) |
4033 (1ull << MSR_DE) |
4034 (1ull << MSR_FE1) |
4035 (1ull << MSR_AL) |
4036 (1ull << MSR_EP) |
4037 (1ull << MSR_IR) |
4038 (1ull << MSR_DR) |
4039 (1ull << MSR_RI) |
4040 (1ull << MSR_LE);
4041 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4042 pcc->excp_model = POWERPC_EXCP_603;
4043 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4044 pcc->bfd_mach = bfd_mach_ppc_603;
4045 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4046 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4047 }
4049 enum fsl_e500_version {
4050 fsl_e500v1,
4051 fsl_e500v2,
4052 fsl_e500mc,
4053 fsl_e5500,
4054 fsl_e6500,
4055 };
4057 static void init_proc_e500(CPUPPCState *env, int version)
4058 {
4059 uint32_t tlbncfg[2];
4060 uint64_t ivor_mask;
4061 uint64_t ivpr_mask = 0xFFFF0000ULL;
4062 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4063 | 0x0020; /* 32 kb */
4064 uint32_t l1cfg1 = 0x3800 /* 8 ways */
4065 | 0x0020; /* 32 kb */
4066 uint32_t mmucfg = 0;
4067 #if !defined(CONFIG_USER_ONLY)
4068 int i;
4069 #endif
4071 /* Time base */
4072 register_tbl(env);
4073 /*
4074 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4075 * complain when accessing them.
4076 * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
4077 */
4078 switch (version) {
4079 case fsl_e500v1:
4080 case fsl_e500v2:
4081 default:
4082 ivor_mask = 0x0000000F0000FFFFULL;
4083 break;
4084 case fsl_e500mc:
4085 case fsl_e5500:
4086 ivor_mask = 0x000003FE0000FFFFULL;
4087 break;
4088 case fsl_e6500:
4089 ivor_mask = 0x000003FF0000FFFFULL;
4090 break;
4091 }
4092 register_BookE_sprs(env, ivor_mask);
4093 register_usprg3_sprs(env);
4094 /* Processor identification */
4095 spr_register(env, SPR_BOOKE_PIR, "PIR",
4096 SPR_NOACCESS, SPR_NOACCESS,
4097 &spr_read_generic, &spr_write_pir,
4098 0x00000000);
4099 /* XXX : not implemented */
4100 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4101 &spr_read_spefscr, &spr_write_spefscr,
4102 &spr_read_spefscr, &spr_write_spefscr,
4103 0x00000000);
4104 #if !defined(CONFIG_USER_ONLY)
4105 /* Memory management */
4106 env->nb_pids = 3;
4107 env->nb_ways = 2;
4108 env->id_tlbs = 0;
4109 switch (version) {
4110 case fsl_e500v1:
4111 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
4112 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4113 break;
4114 case fsl_e500v2:
4115 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
4116 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4117 break;
4118 case fsl_e500mc:
4119 case fsl_e5500:
4120 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
4121 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4122 break;
4123 case fsl_e6500:
4124 mmucfg = 0x6510B45;
4125 env->nb_pids = 1;
4126 tlbncfg[0] = 0x08052400;
4127 tlbncfg[1] = 0x40028040;
4128 break;
4129 default:
4130 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
4131 env->spr[SPR_PVR]);
4132 }
4133 #endif
4134 /* Cache sizes */
4135 switch (version) {
4136 case fsl_e500v1:
4137 case fsl_e500v2:
4138 env->dcache_line_size = 32;
4139 env->icache_line_size = 32;
4140 break;
4141 case fsl_e500mc:
4142 case fsl_e5500:
4143 env->dcache_line_size = 64;
4144 env->icache_line_size = 64;
4145 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4146 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4147 break;
4148 case fsl_e6500:
4149 env->dcache_line_size = 32;
4150 env->icache_line_size = 32;
4151 l1cfg0 |= 0x0F83820;
4152 l1cfg1 |= 0x0B83820;
4153 break;
4154 default:
4155 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
4156 env->spr[SPR_PVR]);
4157 }
4158 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
4159 /* XXX : not implemented */
4160 spr_register(env, SPR_HID0, "HID0",
4161 SPR_NOACCESS, SPR_NOACCESS,
4162 &spr_read_generic, &spr_write_generic,
4163 0x00000000);
4164 /* XXX : not implemented */
4165 spr_register(env, SPR_HID1, "HID1",
4166 SPR_NOACCESS, SPR_NOACCESS,
4167 &spr_read_generic, &spr_write_generic,
4168 0x00000000);
4169 /* XXX : not implemented */
4170 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4171 SPR_NOACCESS, SPR_NOACCESS,
4172 &spr_read_generic, &spr_write_generic,
4173 0x00000000);
4174 /* XXX : not implemented */
4175 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4176 SPR_NOACCESS, SPR_NOACCESS,
4177 &spr_read_generic, &spr_write_generic,
4178 0x00000000);
4179 /* XXX : not implemented */
4180 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4181 SPR_NOACCESS, SPR_NOACCESS,
4182 &spr_read_generic, &spr_write_generic,
4183 0x00000000);
4184 /* XXX : not implemented */
4185 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4186 SPR_NOACCESS, SPR_NOACCESS,
4187 &spr_read_generic, &spr_write_generic,
4188 0x00000000);
4189 /* XXX : not implemented */
4190 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4191 SPR_NOACCESS, SPR_NOACCESS,
4192 &spr_read_generic, &spr_write_generic,
4193 0x00000000);
4194 /* XXX : not implemented */
4195 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4196 SPR_NOACCESS, SPR_NOACCESS,
4197 &spr_read_generic, &spr_write_generic,
4198 0x00000000);
4199 /* XXX : not implemented */
4200 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4201 &spr_read_generic, SPR_NOACCESS,
4202 &spr_read_generic, SPR_NOACCESS,
4203 l1cfg0);
4204 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
4205 &spr_read_generic, SPR_NOACCESS,
4206 &spr_read_generic, SPR_NOACCESS,
4207 l1cfg1);
4208 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4209 SPR_NOACCESS, SPR_NOACCESS,
4210 &spr_read_generic, &spr_write_e500_l1csr0,
4211 0x00000000);
4212 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4213 SPR_NOACCESS, SPR_NOACCESS,
4214 &spr_read_generic, &spr_write_e500_l1csr1,
4215 0x00000000);
4216 if (version != fsl_e500v1 && version != fsl_e500v2) {
4217 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
4218 SPR_NOACCESS, SPR_NOACCESS,
4219 &spr_read_generic, &spr_write_e500_l2csr0,
4220 0x00000000);
4221 }
4222 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4223 SPR_NOACCESS, SPR_NOACCESS,
4224 &spr_read_generic, &spr_write_generic,
4225 0x00000000);
4226 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4227 SPR_NOACCESS, SPR_NOACCESS,
4228 &spr_read_generic, &spr_write_generic,
4229 0x00000000);
4230 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4231 SPR_NOACCESS, SPR_NOACCESS,
4232 &spr_read_generic, &spr_write_booke206_mmucsr0,
4233 0x00000000);
4234 spr_register(env, SPR_BOOKE_EPR, "EPR",
4235 SPR_NOACCESS, SPR_NOACCESS,
4236 &spr_read_generic, SPR_NOACCESS,
4237 0x00000000);
4238 /* XXX better abstract into Emb.xxx features */
4239 if ((version == fsl_e5500) || (version == fsl_e6500)) {
4240 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4241 SPR_NOACCESS, SPR_NOACCESS,
4242 &spr_read_generic, &spr_write_generic,
4243 0x00000000);
4244 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4245 SPR_NOACCESS, SPR_NOACCESS,
4246 &spr_read_mas73, &spr_write_mas73,
4247 0x00000000);
4248 ivpr_mask = (target_ulong)~0xFFFFULL;
4249 }
4251 if (version == fsl_e6500) {
4252 /* Thread identification */
4253 spr_register(env, SPR_TIR, "TIR",
4254 SPR_NOACCESS, SPR_NOACCESS,
4255 &spr_read_generic, SPR_NOACCESS,
4256 0x00000000);
4257 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
4258 SPR_NOACCESS, SPR_NOACCESS,
4259 &spr_read_generic, SPR_NOACCESS,
4260 0x00000004);
4261 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
4262 SPR_NOACCESS, SPR_NOACCESS,
4263 &spr_read_generic, SPR_NOACCESS,
4264 0x7FFFFFFC);
4265 }
4267 #if !defined(CONFIG_USER_ONLY)
4268 env->nb_tlb = 0;
4269 env->tlb_type = TLB_MAS;
4270 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4271 env->nb_tlb += booke206_tlb_size(env, i);
4272 }
4273 #endif
4275 init_excp_e200(env, ivpr_mask);
4276 /* Allocate hardware IRQ controller */
4277 ppce500_irq_init(env_archcpu(env));
4278 }
4280 static void init_proc_e500v1(CPUPPCState *env)
4281 {
4282 init_proc_e500(env, fsl_e500v1);
4283 }
4285 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4286 {
4287 DeviceClass *dc = DEVICE_CLASS(oc);
4288 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4290 dc->desc = "e500v1 core";
4291 pcc->init_proc = init_proc_e500v1;
4292 pcc->check_pow = check_pow_hid0;
4293 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4294 PPC_SPE | PPC_SPE_SINGLE |
4295 PPC_WRTEE | PPC_RFDI |
4296 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4297 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4298 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4299 pcc->insns_flags2 = PPC2_BOOKE206;
4300 pcc->msr_mask = (1ull << MSR_UCLE) |
4301 (1ull << MSR_SPE) |
4302 (1ull << MSR_POW) |
4303 (1ull << MSR_CE) |
4304 (1ull << MSR_EE) |
4305 (1ull << MSR_PR) |
4306 (1ull << MSR_FP) |
4307 (1ull << MSR_ME) |
4308 (1ull << MSR_FE0) |
4309 (1ull << MSR_DWE) |
4310 (1ull << MSR_DE) |
4311 (1ull << MSR_FE1) |
4312 (1ull << MSR_IR) |
4313 (1ull << MSR_DR);
4314 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4315 pcc->excp_model = POWERPC_EXCP_BOOKE;
4316 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4317 pcc->bfd_mach = bfd_mach_ppc_860;
4318 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4319 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4320 POWERPC_FLAG_BUS_CLK;
4321 }
4323 static void init_proc_e500v2(CPUPPCState *env)
4324 {
4325 init_proc_e500(env, fsl_e500v2);
4326 }
4328 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4329 {
4330 DeviceClass *dc = DEVICE_CLASS(oc);
4331 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4333 dc->desc = "e500v2 core";
4334 pcc->init_proc = init_proc_e500v2;
4335 pcc->check_pow = check_pow_hid0;
4336 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4337 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4338 PPC_WRTEE | PPC_RFDI |
4339 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4340 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4341 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4342 pcc->insns_flags2 = PPC2_BOOKE206;
4343 pcc->msr_mask = (1ull << MSR_UCLE) |
4344 (1ull << MSR_SPE) |
4345 (1ull << MSR_POW) |
4346 (1ull << MSR_CE) |
4347 (1ull << MSR_EE) |
4348 (1ull << MSR_PR) |
4349 (1ull << MSR_FP) |
4350 (1ull << MSR_ME) |
4351 (1ull << MSR_FE0) |
4352 (1ull << MSR_DWE) |
4353 (1ull << MSR_DE) |
4354 (1ull << MSR_FE1) |
4355 (1ull << MSR_IR) |
4356 (1ull << MSR_DR);
4357 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4358 pcc->excp_model = POWERPC_EXCP_BOOKE;
4359 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4360 pcc->bfd_mach = bfd_mach_ppc_860;
4361 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4362 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4363 POWERPC_FLAG_BUS_CLK;
4364 }
4366 static void init_proc_e500mc(CPUPPCState *env)
4367 {
4368 init_proc_e500(env, fsl_e500mc);
4369 }
4371 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4372 {
4373 DeviceClass *dc = DEVICE_CLASS(oc);
4374 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4376 dc->desc = "e500mc core";
4377 pcc->init_proc = init_proc_e500mc;
4378 pcc->check_pow = check_pow_none;
4379 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
4380 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4381 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4382 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4383 PPC_FLOAT | PPC_FLOAT_FRES |
4384 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4385 PPC_FLOAT_STFIWX | PPC_WAIT |
4386 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4387 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4388 pcc->msr_mask = (1ull << MSR_GS) |
4389 (1ull << MSR_UCLE) |
4390 (1ull << MSR_CE) |
4391 (1ull << MSR_EE) |
4392 (1ull << MSR_PR) |
4393 (1ull << MSR_FP) |
4394 (1ull << MSR_ME) |
4395 (1ull << MSR_FE0) |
4396 (1ull << MSR_DE) |
4397 (1ull << MSR_FE1) |
4398 (1ull << MSR_IR) |
4399 (1ull << MSR_DR) |
4400 (1ull << MSR_PX) |
4401 (1ull << MSR_RI);
4402 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4403 pcc->excp_model = POWERPC_EXCP_BOOKE;
4404 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4405 /* FIXME: figure out the correct flag for e500mc */
4406 pcc->bfd_mach = bfd_mach_ppc_e500;
4407 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4408 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4409 }
4411 #ifdef TARGET_PPC64
4412 static void init_proc_e5500(CPUPPCState *env)
4413 {
4414 init_proc_e500(env, fsl_e5500);
4415 }
4417 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4418 {
4419 DeviceClass *dc = DEVICE_CLASS(oc);
4420 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4422 dc->desc = "e5500 core";
4423 pcc->init_proc = init_proc_e5500;
4424 pcc->check_pow = check_pow_none;
4425 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
4426 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4427 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4428 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4429 PPC_FLOAT | PPC_FLOAT_FRES |
4430 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4431 PPC_FLOAT_STFIWX | PPC_WAIT |
4432 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4433 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
4434 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
4435 PPC2_FP_CVT_S64;
4436 pcc->msr_mask = (1ull << MSR_CM) |
4437 (1ull << MSR_GS) |
4438 (1ull << MSR_UCLE) |
4439 (1ull << MSR_CE) |
4440 (1ull << MSR_EE) |
4441 (1ull << MSR_PR) |
4442 (1ull << MSR_FP) |
4443 (1ull << MSR_ME) |
4444 (1ull << MSR_FE0) |
4445 (1ull << MSR_DE) |
4446 (1ull << MSR_FE1) |
4447 (1ull << MSR_IR) |
4448 (1ull << MSR_DR) |
4449 (1ull << MSR_PX) |
4450 (1ull << MSR_RI);
4451 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4452 pcc->excp_model = POWERPC_EXCP_BOOKE;
4453 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4454 /* FIXME: figure out the correct flag for e5500 */
4455 pcc->bfd_mach = bfd_mach_ppc_e500;
4456 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4457 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4458 }
4460 static void init_proc_e6500(CPUPPCState *env)
4461 {
4462 init_proc_e500(env, fsl_e6500);
4463 }
4465 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
4466 {
4467 DeviceClass *dc = DEVICE_CLASS(oc);
4468 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4470 dc->desc = "e6500 core";
4471 pcc->init_proc = init_proc_e6500;
4472 pcc->check_pow = check_pow_none;
4473 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
4474 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4475 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4476 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4477 PPC_FLOAT | PPC_FLOAT_FRES |
4478 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4479 PPC_FLOAT_STFIWX | PPC_WAIT |
4480 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4481 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
4482 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
4483 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
4484 pcc->msr_mask = (1ull << MSR_CM) |
4485 (1ull << MSR_GS) |
4486 (1ull << MSR_UCLE) |
4487 (1ull << MSR_CE) |
4488 (1ull << MSR_EE) |
4489 (1ull << MSR_PR) |
4490 (1ull << MSR_FP) |
4491 (1ull << MSR_ME) |
4492 (1ull << MSR_FE0) |
4493 (1ull << MSR_DE) |
4494 (1ull << MSR_FE1) |
4495 (1ull << MSR_IS) |
4496 (1ull << MSR_DS) |
4497 (1ull << MSR_PX) |
4498 (1ull << MSR_RI) |
4499 (1ull << MSR_VR);
4500 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4501 pcc->excp_model = POWERPC_EXCP_BOOKE;
4502 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4503 pcc->bfd_mach = bfd_mach_ppc_e500;
4504 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4505 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
4506 }
4508 #endif
4510 /* Non-embedded PowerPC */
4512 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4514 static void init_proc_601(CPUPPCState *env)
4515 {
4516 register_ne_601_sprs(env);
4517 register_sdr1_sprs(env);
4518 register_601_sprs(env);
4519 /* Hardware implementation registers */
4520 /* XXX : not implemented */
4521 spr_register(env, SPR_HID0, "HID0",
4522 SPR_NOACCESS, SPR_NOACCESS,
4523 &spr_read_generic, &spr_write_hid0_601,
4524 0x80010080);
4525 /* XXX : not implemented */
4526 spr_register(env, SPR_HID1, "HID1",
4527 SPR_NOACCESS, SPR_NOACCESS,
4528 &spr_read_generic, &spr_write_generic,
4529 0x00000000);
4530 /* XXX : not implemented */
4531 spr_register(env, SPR_601_HID2, "HID2",
4532 SPR_NOACCESS, SPR_NOACCESS,
4533 &spr_read_generic, &spr_write_generic,
4534 0x00000000);
4535 /* XXX : not implemented */
4536 spr_register(env, SPR_601_HID5, "HID5",
4537 SPR_NOACCESS, SPR_NOACCESS,
4538 &spr_read_generic, &spr_write_generic,
4539 0x00000000);
4540 /* Memory management */
4541 init_excp_601(env);
4542 /*
4543 * XXX: beware that dcache line size is 64
4544 * but dcbz uses 32 bytes "sectors"
4545 * XXX: this breaks clcs instruction !
4546 */
4547 env->dcache_line_size = 32;
4548 env->icache_line_size = 64;
4549 /* Allocate hardware IRQ controller */
4550 ppc6xx_irq_init(env_archcpu(env));
4551 }
4553 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
4554 {
4555 DeviceClass *dc = DEVICE_CLASS(oc);
4556 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4558 dc->desc = "PowerPC 601";
4559 pcc->init_proc = init_proc_601;
4560 pcc->check_pow = check_pow_none;
4561 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4562 PPC_FLOAT |
4563 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4564 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4565 PPC_SEGMENT | PPC_EXTERN;
4566 pcc->msr_mask = (1ull << MSR_EE) |
4567 (1ull << MSR_PR) |
4568 (1ull << MSR_FP) |
4569 (1ull << MSR_ME) |
4570 (1ull << MSR_FE0) |
4571 (1ull << MSR_SE) |
4572 (1ull << MSR_FE1) |
4573 (1ull << MSR_EP) |
4574 (1ull << MSR_IR) |
4575 (1ull << MSR_DR);
4576 pcc->mmu_model = POWERPC_MMU_601;
4577 #if defined(CONFIG_SOFTMMU)
4578 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
4579 #endif
4580 pcc->excp_model = POWERPC_EXCP_601;
4581 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4582 pcc->bfd_mach = bfd_mach_ppc_601;
4583 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE;
4584 }
4586 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4588 static void init_proc_601v(CPUPPCState *env)
4589 {
4590 init_proc_601(env);
4591 /* XXX : not implemented */
4592 spr_register(env, SPR_601_HID15, "HID15",
4593 SPR_NOACCESS, SPR_NOACCESS,
4594 &spr_read_generic, &spr_write_generic,
4595 0x00000000);
4596 }
4598 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
4599 {
4600 DeviceClass *dc = DEVICE_CLASS(oc);
4601 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4603 dc->desc = "PowerPC 601v";
4604 pcc->init_proc = init_proc_601v;
4605 pcc->check_pow = check_pow_none;
4606 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4607 PPC_FLOAT |
4608 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4609 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4610 PPC_SEGMENT | PPC_EXTERN;
4611 pcc->msr_mask = (1ull << MSR_EE) |
4612 (1ull << MSR_PR) |
4613 (1ull << MSR_FP) |
4614 (1ull << MSR_ME) |
4615 (1ull << MSR_FE0) |
4616 (1ull << MSR_SE) |
4617 (1ull << MSR_FE1) |
4618 (1ull << MSR_EP) |
4619 (1ull << MSR_IR) |
4620 (1ull << MSR_DR);
4621 pcc->mmu_model = POWERPC_MMU_601;
4622 #if defined(CONFIG_SOFTMMU)
4623 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
4624 #endif
4625 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4626 pcc->bfd_mach = bfd_mach_ppc_601;
4627 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE;
4628 }
4630 static void init_proc_602(CPUPPCState *env)
4631 {
4632 register_ne_601_sprs(env);
4633 register_sdr1_sprs(env);
4634 register_602_sprs(env);
4635 /* Time base */
4636 register_tbl(env);
4637 /* hardware implementation registers */
4638 /* XXX : not implemented */
4639 spr_register(env, SPR_HID0, "HID0",
4640 SPR_NOACCESS, SPR_NOACCESS,
4641 &spr_read_generic, &spr_write_generic,
4642 0x00000000);
4643 /* XXX : not implemented */
4644 spr_register(env, SPR_HID1, "HID1",
4645 SPR_NOACCESS, SPR_NOACCESS,
4646 &spr_read_generic, &spr_write_generic,
4647 0x00000000);
4648 /* Memory management */
4649 register_low_BATs(env);
4650 register_6xx_7xx_soft_tlb(env, 64, 2);
4651 init_excp_602(env);
4652 env->dcache_line_size = 32;
4653 env->icache_line_size = 32;
4654 /* Allocate hardware IRQ controller */
4655 ppc6xx_irq_init(env_archcpu(env));
4656 }
4658 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
4659 {
4660 DeviceClass *dc = DEVICE_CLASS(oc);
4661 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4663 dc->desc = "PowerPC 602";
4664 pcc->init_proc = init_proc_602;
4665 pcc->check_pow = check_pow_hid0;
4666 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4667 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4668 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4669 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4670 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4671 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
4672 PPC_SEGMENT | PPC_602_SPEC;
4673 pcc->msr_mask = (1ull << MSR_VSX) |
4674 (1ull << MSR_SA) |
4675 (1ull << MSR_POW) |
4676 (1ull << MSR_TGPR) |
4677 (1ull << MSR_ILE) |
4678 (1ull << MSR_EE) |
4679 (1ull << MSR_PR) |
4680 (1ull << MSR_FP) |
4681 (1ull << MSR_ME) |
4682 (1ull << MSR_FE0) |
4683 (1ull << MSR_SE) |
4684 (1ull << MSR_DE) |
4685 (1ull << MSR_FE1) |
4686 (1ull << MSR_EP) |
4687 (1ull << MSR_IR) |
4688 (1ull << MSR_DR) |
4689 (1ull << MSR_RI) |
4690 (1ull << MSR_LE);
4691 /* XXX: 602 MMU is quite specific. Should add a special case */
4692 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4693 pcc->excp_model = POWERPC_EXCP_602;
4694 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4695 pcc->bfd_mach = bfd_mach_ppc_602;
4696 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4697 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4698 }
4700 static void init_proc_603(CPUPPCState *env)
4701 {
4702 register_ne_601_sprs(env);
4703 register_sdr1_sprs(env);
4704 register_603_sprs(env);
4705 /* Time base */
4706 register_tbl(env);
4707 /* hardware implementation registers */
4708 /* XXX : not implemented */
4709 spr_register(env, SPR_HID0, "HID0",
4710 SPR_NOACCESS, SPR_NOACCESS,
4711 &spr_read_generic, &spr_write_generic,
4712 0x00000000);
4713 /* XXX : not implemented */
4714 spr_register(env, SPR_HID1, "HID1",
4715 SPR_NOACCESS, SPR_NOACCESS,
4716 &spr_read_generic, &spr_write_generic,
4717 0x00000000);
4718 /* Memory management */
4719 register_low_BATs(env);
4720 register_6xx_7xx_soft_tlb(env, 64, 2);
4721 init_excp_603(env);
4722 env->dcache_line_size = 32;
4723 env->icache_line_size = 32;
4724 /* Allocate hardware IRQ controller */
4725 ppc6xx_irq_init(env_archcpu(env));
4726 }
4728 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
4729 {
4730 DeviceClass *dc = DEVICE_CLASS(oc);
4731 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4733 dc->desc = "PowerPC 603";
4734 pcc->init_proc = init_proc_603;
4735 pcc->check_pow = check_pow_hid0;
4736 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4737 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4738 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4739 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4740 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4741 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4742 PPC_SEGMENT | PPC_EXTERN;
4743 pcc->msr_mask = (1ull << MSR_POW) |
4744 (1ull << MSR_TGPR) |
4745 (1ull << MSR_ILE) |
4746 (1ull << MSR_EE) |
4747 (1ull << MSR_PR) |
4748 (1ull << MSR_FP) |
4749 (1ull << MSR_ME) |
4750 (1ull << MSR_FE0) |
4751 (1ull << MSR_SE) |
4752 (1ull << MSR_DE) |
4753 (1ull << MSR_FE1) |
4754 (1ull << MSR_EP) |
4755 (1ull << MSR_IR) |
4756 (1ull << MSR_DR) |
4757 (1ull << MSR_RI) |
4758 (1ull << MSR_LE);
4759 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4760 pcc->excp_model = POWERPC_EXCP_603;
4761 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4762 pcc->bfd_mach = bfd_mach_ppc_603;
4763 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4764 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4765 }
4767 static void init_proc_603E(CPUPPCState *env)
4768 {
4769 register_ne_601_sprs(env);
4770 register_sdr1_sprs(env);
4771 register_603_sprs(env);
4772 /* Time base */
4773 register_tbl(env);
4774 /* hardware implementation registers */
4775 /* XXX : not implemented */
4776 spr_register(env, SPR_HID0, "HID0",
4777 SPR_NOACCESS, SPR_NOACCESS,
4778 &spr_read_generic, &spr_write_generic,
4779 0x00000000);
4780 /* XXX : not implemented */
4781 spr_register(env, SPR_HID1, "HID1",
4782 SPR_NOACCESS, SPR_NOACCESS,
4783 &spr_read_generic, &spr_write_generic,
4784 0x00000000);
4785 /* Memory management */
4786 register_low_BATs(env);
4787 register_6xx_7xx_soft_tlb(env, 64, 2);
4788 init_excp_603(env);
4789 env->dcache_line_size = 32;
4790 env->icache_line_size = 32;
4791 /* Allocate hardware IRQ controller */
4792 ppc6xx_irq_init(env_archcpu(env));
4793 }
4795 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
4796 {
4797 DeviceClass *dc = DEVICE_CLASS(oc);
4798 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4800 dc->desc = "PowerPC 603e";
4801 pcc->init_proc = init_proc_603E;
4802 pcc->check_pow = check_pow_hid0;
4803 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4804 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4805 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4806 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4807 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4808 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4809 PPC_SEGMENT | PPC_EXTERN;
4810 pcc->msr_mask = (1ull << MSR_POW) |
4811 (1ull << MSR_TGPR) |
4812 (1ull << MSR_ILE) |
4813 (1ull << MSR_EE) |
4814 (1ull << MSR_PR) |
4815 (1ull << MSR_FP) |
4816 (1ull << MSR_ME) |
4817 (1ull << MSR_FE0) |
4818 (1ull << MSR_SE) |
4819 (1ull << MSR_DE) |
4820 (1ull << MSR_FE1) |
4821 (1ull << MSR_EP) |
4822 (1ull << MSR_IR) |
4823 (1ull << MSR_DR) |
4824 (1ull << MSR_RI) |
4825 (1ull << MSR_LE);
4826 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4827 pcc->excp_model = POWERPC_EXCP_603E;
4828 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4829 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4830 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4831 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4832 }
4834 static void init_proc_604(CPUPPCState *env)
4835 {
4836 register_ne_601_sprs(env);
4837 register_sdr1_sprs(env);
4838 register_604_sprs(env);
4839 /* Time base */
4840 register_tbl(env);
4841 /* Hardware implementation registers */
4842 /* XXX : not implemented */
4843 spr_register(env, SPR_HID0, "HID0",
4844 SPR_NOACCESS, SPR_NOACCESS,
4845 &spr_read_generic, &spr_write_generic,
4846 0x00000000);
4847 /* Memory management */
4848 register_low_BATs(env);
4849 init_excp_604(env);
4850 env->dcache_line_size = 32;
4851 env->icache_line_size = 32;
4852 /* Allocate hardware IRQ controller */
4853 ppc6xx_irq_init(env_archcpu(env));
4854 }
4856 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
4857 {
4858 DeviceClass *dc = DEVICE_CLASS(oc);
4859 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4861 dc->desc = "PowerPC 604";
4862 pcc->init_proc = init_proc_604;
4863 pcc->check_pow = check_pow_nocheck;
4864 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4865 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4866 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4867 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4868 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4869 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4870 PPC_SEGMENT | PPC_EXTERN;
4871 pcc->msr_mask = (1ull << MSR_POW) |
4872 (1ull << MSR_ILE) |
4873 (1ull << MSR_EE) |
4874 (1ull << MSR_PR) |
4875 (1ull << MSR_FP) |
4876 (1ull << MSR_ME) |
4877 (1ull << MSR_FE0) |
4878 (1ull << MSR_SE) |
4879 (1ull << MSR_DE) |
4880 (1ull << MSR_FE1) |
4881 (1ull << MSR_EP) |
4882 (1ull << MSR_IR) |
4883 (1ull << MSR_DR) |
4884 (1ull << MSR_PMM) |
4885 (1ull << MSR_RI) |
4886 (1ull << MSR_LE);
4887 pcc->mmu_model = POWERPC_MMU_32B;
4888 #if defined(CONFIG_SOFTMMU)
4889 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
4890 #endif
4891 pcc->excp_model = POWERPC_EXCP_604;
4892 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4893 pcc->bfd_mach = bfd_mach_ppc_604;
4894 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4895 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4896 }
4898 static void init_proc_604E(CPUPPCState *env)
4899 {
4900 register_ne_601_sprs(env);
4901 register_sdr1_sprs(env);
4902 register_604_sprs(env);
4903 /* XXX : not implemented */
4904 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
4905 SPR_NOACCESS, SPR_NOACCESS,
4906 &spr_read_generic, &spr_write_generic,
4907 0x00000000);
4908 /* XXX : not implemented */
4909 spr_register(env, SPR_7XX_PMC3, "PMC3",
4910 SPR_NOACCESS, SPR_NOACCESS,
4911 &spr_read_generic, &spr_write_generic,
4912 0x00000000);
4913 /* XXX : not implemented */
4914 spr_register(env, SPR_7XX_PMC4, "PMC4",
4915 SPR_NOACCESS, SPR_NOACCESS,
4916 &spr_read_generic, &spr_write_generic,
4917 0x00000000);
4918 /* Time base */
4919 register_tbl(env);
4920 /* Hardware implementation registers */
4921 /* XXX : not implemented */
4922 spr_register(env, SPR_HID0, "HID0",
4923 SPR_NOACCESS, SPR_NOACCESS,
4924 &spr_read_generic, &spr_write_generic,
4925 0x00000000);
4926 /* XXX : not implemented */
4927 spr_register(env, SPR_HID1, "HID1",
4928 SPR_NOACCESS, SPR_NOACCESS,
4929 &spr_read_generic, &spr_write_generic,
4930 0x00000000);
4931 /* Memory management */
4932 register_low_BATs(env);
4933 init_excp_604(env);
4934 env->dcache_line_size = 32;
4935 env->icache_line_size = 32;
4936 /* Allocate hardware IRQ controller */
4937 ppc6xx_irq_init(env_archcpu(env));
4938 }
4940 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
4941 {
4942 DeviceClass *dc = DEVICE_CLASS(oc);
4943 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4945 dc->desc = "PowerPC 604E";
4946 pcc->init_proc = init_proc_604E;
4947 pcc->check_pow = check_pow_nocheck;
4948 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4949 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4950 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4951 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4952 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4953 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4954 PPC_SEGMENT | PPC_EXTERN;
4955 pcc->msr_mask = (1ull << MSR_POW) |
4956 (1ull << MSR_ILE) |
4957 (1ull << MSR_EE) |
4958 (1ull << MSR_PR) |
4959 (1ull << MSR_FP) |
4960 (1ull << MSR_ME) |
4961 (1ull << MSR_FE0) |
4962 (1ull << MSR_SE) |
4963 (1ull << MSR_DE) |
4964 (1ull << MSR_FE1) |
4965 (1ull << MSR_EP) |
4966 (1ull << MSR_IR) |
4967 (1ull << MSR_DR) |
4968 (1ull << MSR_PMM) |
4969 (1ull << MSR_RI) |
4970 (1ull << MSR_LE);
4971 pcc->mmu_model = POWERPC_MMU_32B;
4972 #if defined(CONFIG_SOFTMMU)
4973 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
4974 #endif
4975 pcc->excp_model = POWERPC_EXCP_604;
4976 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4977 pcc->bfd_mach = bfd_mach_ppc_604;
4978 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4979 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4980 }
4982 static void init_proc_740(CPUPPCState *env)
4983 {
4984 register_ne_601_sprs(env);
4985 register_sdr1_sprs(env);
4986 register_7xx_sprs(env);
4987 /* Time base */
4988 register_tbl(env);
4989 /* Thermal management */
4990 register_thrm_sprs(env);
4991 /* Hardware implementation registers */
4992 /* XXX : not implemented */
4993 spr_register(env, SPR_HID0, "HID0",
4994 SPR_NOACCESS, SPR_NOACCESS,
4995 &spr_read_generic, &spr_write_generic,
4996 0x00000000);
4997 /* XXX : not implemented */
4998 spr_register(env, SPR_HID1, "HID1",
4999 SPR_NOACCESS, SPR_NOACCESS,
5000 &spr_read_generic, &spr_write_generic,
5001 0x00000000);
5002 /* Memory management */
5003 register_low_BATs(env);
5004 init_excp_7x0(env);
5005 env->dcache_line_size = 32;
5006 env->icache_line_size = 32;
5007 /* Allocate hardware IRQ controller */
5008 ppc6xx_irq_init(env_archcpu(env));
5009 }
5011 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5012 {
5013 DeviceClass *dc = DEVICE_CLASS(oc);
5014 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5016 dc->desc = "PowerPC 740";
5017 pcc->init_proc = init_proc_740;
5018 pcc->check_pow = check_pow_hid0;
5019 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5020 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5021 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5022 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5023 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5024 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5025 PPC_SEGMENT | PPC_EXTERN;
5026 pcc->msr_mask = (1ull << MSR_POW) |
5027 (1ull << MSR_ILE) |
5028 (1ull << MSR_EE) |
5029 (1ull << MSR_PR) |
5030 (1ull << MSR_FP) |
5031 (1ull << MSR_ME) |
5032 (1ull << MSR_FE0) |
5033 (1ull << MSR_SE) |
5034 (1ull << MSR_DE) |
5035 (1ull << MSR_FE1) |
5036 (1ull << MSR_EP) |
5037 (1ull << MSR_IR) |
5038 (1ull << MSR_DR) |
5039 (1ull << MSR_PMM) |
5040 (1ull << MSR_RI) |
5041 (1ull << MSR_LE);
5042 pcc->mmu_model = POWERPC_MMU_32B;
5043 #if defined(CONFIG_SOFTMMU)
5044 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5045 #endif
5046 pcc->excp_model = POWERPC_EXCP_7x0;
5047 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5048 pcc->bfd_mach = bfd_mach_ppc_750;
5049 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5050 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5051 }
5053 static void init_proc_750(CPUPPCState *env)
5054 {
5055 register_ne_601_sprs(env);
5056 register_sdr1_sprs(env);
5057 register_7xx_sprs(env);
5058 /* XXX : not implemented */
5059 spr_register(env, SPR_L2CR, "L2CR",
5060 SPR_NOACCESS, SPR_NOACCESS,
5061 &spr_read_generic, spr_access_nop,
5062 0x00000000);
5063 /* Time base */
5064 register_tbl(env);
5065 /* Thermal management */
5066 register_thrm_sprs(env);
5067 /* Hardware implementation registers */
5068 /* XXX : not implemented */
5069 spr_register(env, SPR_HID0, "HID0",
5070 SPR_NOACCESS, SPR_NOACCESS,
5071 &spr_read_generic, &spr_write_generic,
5072 0x00000000);
5073 /* XXX : not implemented */
5074 spr_register(env, SPR_HID1, "HID1",
5075 SPR_NOACCESS, SPR_NOACCESS,
5076 &spr_read_generic, &spr_write_generic,
5077 0x00000000);
5078 /* Memory management */
5079 register_low_BATs(env);
5080 /*
5081 * XXX: high BATs are also present but are known to be bugged on
5082 * die version 1.x
5083 */
5084 init_excp_7x0(env);
5085 env->dcache_line_size = 32;
5086 env->icache_line_size = 32;
5087 /* Allocate hardware IRQ controller */
5088 ppc6xx_irq_init(env_archcpu(env));
5089 }
5091 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5092 {
5093 DeviceClass *dc = DEVICE_CLASS(oc);
5094 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5096 dc->desc = "PowerPC 750";
5097 pcc->init_proc = init_proc_750;
5098 pcc->check_pow = check_pow_hid0;
5099 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5100 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5101 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5102 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5103 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5104 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5105 PPC_SEGMENT | PPC_EXTERN;
5106 pcc->msr_mask = (1ull << MSR_POW) |
5107 (1ull << MSR_ILE) |
5108 (1ull << MSR_EE) |
5109 (1ull << MSR_PR) |
5110 (1ull << MSR_FP) |
5111 (1ull << MSR_ME) |
5112 (1ull << MSR_FE0) |
5113 (1ull << MSR_SE) |
5114 (1ull << MSR_DE) |
5115 (1ull << MSR_FE1) |
5116 (1ull << MSR_EP) |
5117 (1ull << MSR_IR) |
5118 (1ull << MSR_DR) |
5119 (1ull << MSR_PMM) |
5120 (1ull << MSR_RI) |
5121 (1ull << MSR_LE);
5122 pcc->mmu_model = POWERPC_MMU_32B;
5123 #if defined(CONFIG_SOFTMMU)
5124 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5125 #endif
5126 pcc->excp_model = POWERPC_EXCP_7x0;
5127 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5128 pcc->bfd_mach = bfd_mach_ppc_750;
5129 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5130 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5131 }
5133 static void init_proc_750cl(CPUPPCState *env)
5134 {
5135 register_ne_601_sprs(env);
5136 register_sdr1_sprs(env);
5137 register_7xx_sprs(env);
5138 /* XXX : not implemented */
5139 spr_register(env, SPR_L2CR, "L2CR",
5140 SPR_NOACCESS, SPR_NOACCESS,
5141 &spr_read_generic, spr_access_nop,
5142 0x00000000);
5143 /* Time base */
5144 register_tbl(env);
5145 /* Thermal management */
5146 /* Those registers are fake on 750CL */
5147 spr_register(env, SPR_THRM1, "THRM1",
5148 SPR_NOACCESS, SPR_NOACCESS,
5149 &spr_read_generic, &spr_write_generic,
5150 0x00000000);
5151 spr_register(env, SPR_THRM2, "THRM2",
5152 SPR_NOACCESS, SPR_NOACCESS,
5153 &spr_read_generic, &spr_write_generic,
5154 0x00000000);
5155 spr_register(env, SPR_THRM3, "THRM3",
5156 SPR_NOACCESS, SPR_NOACCESS,
5157 &spr_read_generic, &spr_write_generic,
5158 0x00000000);
5159 /* XXX: not implemented */
5160 spr_register(env, SPR_750_TDCL, "TDCL",
5161 SPR_NOACCESS, SPR_NOACCESS,
5162 &spr_read_generic, &spr_write_generic,
5163 0x00000000);
5164 spr_register(env, SPR_750_TDCH, "TDCH",
5165 SPR_NOACCESS, SPR_NOACCESS,
5166 &spr_read_generic, &spr_write_generic,
5167 0x00000000);
5168 /* DMA */
5169 /* XXX : not implemented */
5170 spr_register(env, SPR_750_WPAR, "WPAR",
5171 SPR_NOACCESS, SPR_NOACCESS,
5172 &spr_read_generic, &spr_write_generic,
5173 0x00000000);
5174 spr_register(env, SPR_750_DMAL, "DMAL",
5175 SPR_NOACCESS, SPR_NOACCESS,
5176 &spr_read_generic, &spr_write_generic,
5177 0x00000000);
5178 spr_register(env, SPR_750_DMAU, "DMAU",
5179 SPR_NOACCESS, SPR_NOACCESS,
5180 &spr_read_generic, &spr_write_generic,
5181 0x00000000);
5182 /* Hardware implementation registers */
5183 /* XXX : not implemented */
5184 spr_register(env, SPR_HID0, "HID0",
5185 SPR_NOACCESS, SPR_NOACCESS,
5186 &spr_read_generic, &spr_write_generic,
5187 0x00000000);
5188 /* XXX : not implemented */
5189 spr_register(env, SPR_HID1, "HID1",
5190 SPR_NOACCESS, SPR_NOACCESS,
5191 &spr_read_generic, &spr_write_generic,
5192 0x00000000);
5193 /* XXX : not implemented */
5194 spr_register(env, SPR_750CL_HID2, "HID2",
5195 SPR_NOACCESS, SPR_NOACCESS,
5196 &spr_read_generic, &spr_write_generic,
5197 0x00000000);
5198 /* XXX : not implemented */
5199 spr_register(env, SPR_750CL_HID4, "HID4",
5200 SPR_NOACCESS, SPR_NOACCESS,
5201 &spr_read_generic, &spr_write_generic,
5202 0x00000000);
5203 /* Quantization registers */
5204 /* XXX : not implemented */
5205 spr_register(env, SPR_750_GQR0, "GQR0",
5206 SPR_NOACCESS, SPR_NOACCESS,
5207 &spr_read_generic, &spr_write_generic,
5208 0x00000000);
5209 /* XXX : not implemented */
5210 spr_register(env, SPR_750_GQR1, "GQR1",
5211 SPR_NOACCESS, SPR_NOACCESS,
5212 &spr_read_generic, &spr_write_generic,
5213 0x00000000);
5214 /* XXX : not implemented */
5215 spr_register(env, SPR_750_GQR2, "GQR2",
5216 SPR_NOACCESS, SPR_NOACCESS,
5217 &spr_read_generic, &spr_write_generic,
5218 0x00000000);
5219 /* XXX : not implemented */
5220 spr_register(env, SPR_750_GQR3, "GQR3",
5221 SPR_NOACCESS, SPR_NOACCESS,
5222 &spr_read_generic, &spr_write_generic,
5223 0x00000000);
5224 /* XXX : not implemented */
5225 spr_register(env, SPR_750_GQR4, "GQR4",
5226 SPR_NOACCESS, SPR_NOACCESS,
5227 &spr_read_generic, &spr_write_generic,
5228 0x00000000);
5229 /* XXX : not implemented */
5230 spr_register(env, SPR_750_GQR5, "GQR5",
5231 SPR_NOACCESS, SPR_NOACCESS,
5232 &spr_read_generic, &spr_write_generic,
5233 0x00000000);
5234 /* XXX : not implemented */
5235 spr_register(env, SPR_750_GQR6, "GQR6",
5236 SPR_NOACCESS, SPR_NOACCESS,
5237 &spr_read_generic, &spr_write_generic,
5238 0x00000000);
5239 /* XXX : not implemented */
5240 spr_register(env, SPR_750_GQR7, "GQR7",
5241 SPR_NOACCESS, SPR_NOACCESS,
5242 &spr_read_generic, &spr_write_generic,
5243 0x00000000);
5244 /* Memory management */
5245 register_low_BATs(env);
5246 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5247 register_high_BATs(env);
5248 init_excp_750cl(env);
5249 env->dcache_line_size = 32;
5250 env->icache_line_size = 32;
5251 /* Allocate hardware IRQ controller */
5252 ppc6xx_irq_init(env_archcpu(env));
5253 }
5255 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5256 {
5257 DeviceClass *dc = DEVICE_CLASS(oc);
5258 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5260 dc->desc = "PowerPC 750 CL";
5261 pcc->init_proc = init_proc_750cl;
5262 pcc->check_pow = check_pow_hid0;
5263 /*
5264 * XXX: not implemented:
5265 * cache lock instructions:
5266 * dcbz_l
5267 * floating point paired instructions
5268 * psq_lux
5269 * psq_lx
5270 * psq_stux
5271 * psq_stx
5272 * ps_abs
5273 * ps_add
5274 * ps_cmpo0
5275 * ps_cmpo1
5276 * ps_cmpu0
5277 * ps_cmpu1
5278 * ps_div
5279 * ps_madd
5280 * ps_madds0
5281 * ps_madds1
5282 * ps_merge00
5283 * ps_merge01
5284 * ps_merge10
5285 * ps_merge11
5286 * ps_mr
5287 * ps_msub
5288 * ps_mul
5289 * ps_muls0
5290 * ps_muls1
5291 * ps_nabs
5292 * ps_neg
5293 * ps_nmadd
5294 * ps_nmsub
5295 * ps_res
5296 * ps_rsqrte
5297 * ps_sel
5298 * ps_sub
5299 * ps_sum0
5300 * ps_sum1
5301 */
5302 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5303 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5304 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5305 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5306 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5307 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5308 PPC_SEGMENT | PPC_EXTERN;
5309 pcc->msr_mask = (1ull << MSR_POW) |
5310 (1ull << MSR_ILE) |
5311 (1ull << MSR_EE) |
5312 (1ull << MSR_PR) |
5313 (1ull << MSR_FP) |
5314 (1ull << MSR_ME) |
5315 (1ull << MSR_FE0) |
5316 (1ull << MSR_SE) |
5317 (1ull << MSR_DE) |
5318 (1ull << MSR_FE1) |
5319 (1ull << MSR_EP) |
5320 (1ull << MSR_IR) |
5321 (1ull << MSR_DR) |
5322 (1ull << MSR_PMM) |
5323 (1ull << MSR_RI) |
5324 (1ull << MSR_LE);
5325 pcc->mmu_model = POWERPC_MMU_32B;
5326 #if defined(CONFIG_SOFTMMU)
5327 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5328 #endif
5329 pcc->excp_model = POWERPC_EXCP_7x0;
5330 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5331 pcc->bfd_mach = bfd_mach_ppc_750;
5332 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5333 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5334 }
5336 static void init_proc_750cx(CPUPPCState *env)
5337 {
5338 register_ne_601_sprs(env);
5339 register_sdr1_sprs(env);
5340 register_7xx_sprs(env);
5341 /* XXX : not implemented */
5342 spr_register(env, SPR_L2CR, "L2CR",
5343 SPR_NOACCESS, SPR_NOACCESS,
5344 &spr_read_generic, spr_access_nop,
5345 0x00000000);
5346 /* Time base */
5347 register_tbl(env);
5348 /* Thermal management */
5349 register_thrm_sprs(env);
5350 /* This register is not implemented but is present for compatibility */
5351 spr_register(env, SPR_SDA, "SDA",
5352 SPR_NOACCESS, SPR_NOACCESS,
5353 &spr_read_generic, &spr_write_generic,
5354 0x00000000);
5355 /* Hardware implementation registers */
5356 /* XXX : not implemented */
5357 spr_register(env, SPR_HID0, "HID0",
5358 SPR_NOACCESS, SPR_NOACCESS,
5359 &spr_read_generic, &spr_write_generic,
5360 0x00000000);
5361 /* XXX : not implemented */
5362 spr_register(env, SPR_HID1, "HID1",
5363 SPR_NOACCESS, SPR_NOACCESS,
5364 &spr_read_generic, &spr_write_generic,
5365 0x00000000);
5366 /* Memory management */
5367 register_low_BATs(env);
5368 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5369 register_high_BATs(env);
5370 init_excp_750cx(env);
5371 env->dcache_line_size = 32;
5372 env->icache_line_size = 32;
5373 /* Allocate hardware IRQ controller */
5374 ppc6xx_irq_init(env_archcpu(env));
5375 }
5377 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5378 {
5379 DeviceClass *dc = DEVICE_CLASS(oc);
5380 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5382 dc->desc = "PowerPC 750CX";
5383 pcc->init_proc = init_proc_750cx;
5384 pcc->check_pow = check_pow_hid0;
5385 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5386 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5387 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5388 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5389 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5390 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5391 PPC_SEGMENT | PPC_EXTERN;
5392 pcc->msr_mask = (1ull << MSR_POW) |
5393 (1ull << MSR_ILE) |
5394 (1ull << MSR_EE) |
5395 (1ull << MSR_PR) |
5396 (1ull << MSR_FP) |
5397 (1ull << MSR_ME) |
5398 (1ull << MSR_FE0) |
5399 (1ull << MSR_SE) |
5400 (1ull << MSR_DE) |
5401 (1ull << MSR_FE1) |
5402 (1ull << MSR_EP) |
5403 (1ull << MSR_IR) |
5404 (1ull << MSR_DR) |
5405 (1ull << MSR_PMM) |
5406 (1ull << MSR_RI) |
5407 (1ull << MSR_LE);
5408 pcc->mmu_model = POWERPC_MMU_32B;
5409 #if defined(CONFIG_SOFTMMU)
5410 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5411 #endif
5412 pcc->excp_model = POWERPC_EXCP_7x0;
5413 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5414 pcc->bfd_mach = bfd_mach_ppc_750;
5415 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5416 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5417 }
5419 static void init_proc_750fx(CPUPPCState *env)
5420 {
5421 register_ne_601_sprs(env);
5422 register_sdr1_sprs(env);
5423 register_7xx_sprs(env);
5424 /* XXX : not implemented */
5425 spr_register(env, SPR_L2CR, "L2CR",
5426 SPR_NOACCESS, SPR_NOACCESS,
5427 &spr_read_generic, spr_access_nop,
5428 0x00000000);
5429 /* Time base */
5430 register_tbl(env);
5431 /* Thermal management */
5432 register_thrm_sprs(env);
5433 /* XXX : not implemented */
5434 spr_register(env, SPR_750_THRM4, "THRM4",
5435 SPR_NOACCESS, SPR_NOACCESS,
5436 &spr_read_generic, &spr_write_generic,
5437 0x00000000);
5438 /* Hardware implementation registers */
5439 /* XXX : not implemented */
5440 spr_register(env, SPR_HID0, "HID0",
5441 SPR_NOACCESS, SPR_NOACCESS,
5442 &spr_read_generic, &spr_write_generic,
5443 0x00000000);
5444 /* XXX : not implemented */
5445 spr_register(env, SPR_HID1, "HID1",
5446 SPR_NOACCESS, SPR_NOACCESS,
5447 &spr_read_generic, &spr_write_generic,
5448 0x00000000);
5449 /* XXX : not implemented */
5450 spr_register(env, SPR_750FX_HID2, "HID2",
5451 SPR_NOACCESS, SPR_NOACCESS,
5452 &spr_read_generic, &spr_write_generic,
5453 0x00000000);
5454 /* Memory management */
5455 register_low_BATs(env);
5456 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5457 register_high_BATs(env);
5458 init_excp_7x0(env);
5459 env->dcache_line_size = 32;
5460 env->icache_line_size = 32;
5461 /* Allocate hardware IRQ controller */
5462 ppc6xx_irq_init(env_archcpu(env));
5463 }
5465 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
5466 {
5467 DeviceClass *dc = DEVICE_CLASS(oc);
5468 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5470 dc->desc = "PowerPC 750FX";
5471 pcc->init_proc = init_proc_750fx;
5472 pcc->check_pow = check_pow_hid0;
5473 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5474 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5475 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5476 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5477 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5478 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5479 PPC_SEGMENT | PPC_EXTERN;
5480 pcc->msr_mask = (1ull << MSR_POW) |
5481 (1ull << MSR_ILE) |
5482 (1ull << MSR_EE) |
5483 (1ull << MSR_PR) |
5484 (1ull << MSR_FP) |
5485 (1ull << MSR_ME) |
5486 (1ull << MSR_FE0) |
5487 (1ull << MSR_SE) |
5488 (1ull << MSR_DE) |
5489 (1ull << MSR_FE1) |
5490 (1ull << MSR_EP) |
5491 (1ull << MSR_IR) |
5492 (1ull << MSR_DR) |
5493 (1ull << MSR_PMM) |
5494 (1ull << MSR_RI) |
5495 (1ull << MSR_LE);
5496 pcc->mmu_model = POWERPC_MMU_32B;
5497 #if defined(CONFIG_SOFTMMU)
5498 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5499 #endif
5500 pcc->excp_model = POWERPC_EXCP_7x0;
5501 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5502 pcc->bfd_mach = bfd_mach_ppc_750;
5503 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5504 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5505 }
5507 static void init_proc_750gx(CPUPPCState *env)
5508 {
5509 register_ne_601_sprs(env);
5510 register_sdr1_sprs(env);
5511 register_7xx_sprs(env);
5512 /* XXX : not implemented (XXX: different from 750fx) */
5513 spr_register(env, SPR_L2CR, "L2CR",
5514 SPR_NOACCESS, SPR_NOACCESS,
5515 &spr_read_generic, spr_access_nop,
5516 0x00000000);
5517 /* Time base */
5518 register_tbl(env);
5519 /* Thermal management */
5520 register_thrm_sprs(env);
5521 /* XXX : not implemented */
5522 spr_register(env, SPR_750_THRM4, "THRM4",
5523 SPR_NOACCESS, SPR_NOACCESS,
5524 &spr_read_generic, &spr_write_generic,
5525 0x00000000);
5526 /* Hardware implementation registers */
5527 /* XXX : not implemented (XXX: different from 750fx) */
5528 spr_register(env, SPR_HID0, "HID0",
5529 SPR_NOACCESS, SPR_NOACCESS,
5530 &spr_read_generic, &spr_write_generic,
5531 0x00000000);
5532 /* XXX : not implemented */
5533 spr_register(env, SPR_HID1, "HID1",
5534 SPR_NOACCESS, SPR_NOACCESS,
5535 &spr_read_generic, &spr_write_generic,
5536 0x00000000);
5537 /* XXX : not implemented (XXX: different from 750fx) */
5538 spr_register(env, SPR_750FX_HID2, "HID2",
5539 SPR_NOACCESS, SPR_NOACCESS,
5540 &spr_read_generic, &spr_write_generic,
5541 0x00000000);
5542 /* Memory management */
5543 register_low_BATs(env);
5544 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5545 register_high_BATs(env);
5546 init_excp_7x0(env);
5547 env->dcache_line_size = 32;
5548 env->icache_line_size = 32;
5549 /* Allocate hardware IRQ controller */
5550 ppc6xx_irq_init(env_archcpu(env));
5551 }
5553 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
5554 {
5555 DeviceClass *dc = DEVICE_CLASS(oc);
5556 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5558 dc->desc = "PowerPC 750GX";
5559 pcc->init_proc = init_proc_750gx;
5560 pcc->check_pow = check_pow_hid0;
5561 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5562 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5563 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5564 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5565 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5566 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5567 PPC_SEGMENT | PPC_EXTERN;
5568 pcc->msr_mask = (1ull << MSR_POW) |
5569 (1ull << MSR_ILE) |
5570 (1ull << MSR_EE) |
5571 (1ull << MSR_PR) |
5572 (1ull << MSR_FP) |
5573 (1ull << MSR_ME) |
5574 (1ull << MSR_FE0) |
5575 (1ull << MSR_SE) |
5576 (1ull << MSR_DE) |
5577 (1ull << MSR_FE1) |
5578 (1ull << MSR_EP) |
5579 (1ull << MSR_IR) |
5580 (1ull << MSR_DR) |
5581 (1ull << MSR_PMM) |
5582 (1ull << MSR_RI) |
5583 (1ull << MSR_LE);
5584 pcc->mmu_model = POWERPC_MMU_32B;
5585 #if defined(CONFIG_SOFTMMU)
5586 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5587 #endif
5588 pcc->excp_model = POWERPC_EXCP_7x0;
5589 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5590 pcc->bfd_mach = bfd_mach_ppc_750;
5591 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5592 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5593 }
5595 static void init_proc_745(CPUPPCState *env)
5596 {
5597 register_ne_601_sprs(env);
5598 register_sdr1_sprs(env);
5599 register_7xx_sprs(env);
5600 register_G2_755_sprs(env);
5601 /* Time base */
5602 register_tbl(env);
5603 /* Thermal management */
5604 register_thrm_sprs(env);
5605 /* Hardware implementation registers */
5606 /* XXX : not implemented */
5607 spr_register(env, SPR_HID0, "HID0",
5608 SPR_NOACCESS, SPR_NOACCESS,
5609 &spr_read_generic, &spr_write_generic,
5610 0x00000000);
5611 /* XXX : not implemented */
5612 spr_register(env, SPR_HID1, "HID1",
5613 SPR_NOACCESS, SPR_NOACCESS,
5614 &spr_read_generic, &spr_write_generic,
5615 0x00000000);
5616 /* XXX : not implemented */
5617 spr_register(env, SPR_HID2, "HID2",
5618 SPR_NOACCESS, SPR_NOACCESS,
5619 &spr_read_generic, &spr_write_generic,
5620 0x00000000);
5621 /* Memory management */
5622 register_low_BATs(env);
5623 register_high_BATs(env);
5624 register_6xx_7xx_soft_tlb(env, 64, 2);
5625 init_excp_7x5(env);
5626 env->dcache_line_size = 32;
5627 env->icache_line_size = 32;
5628 /* Allocate hardware IRQ controller */
5629 ppc6xx_irq_init(env_archcpu(env));
5630 }
5632 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
5633 {
5634 DeviceClass *dc = DEVICE_CLASS(oc);
5635 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5637 dc->desc = "PowerPC 745";
5638 pcc->init_proc = init_proc_745;
5639 pcc->check_pow = check_pow_hid0;
5640 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5641 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5642 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5643 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5644 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5645 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5646 PPC_SEGMENT | PPC_EXTERN;
5647 pcc->msr_mask = (1ull << MSR_POW) |
5648 (1ull << MSR_ILE) |
5649 (1ull << MSR_EE) |
5650 (1ull << MSR_PR) |
5651 (1ull << MSR_FP) |
5652 (1ull << MSR_ME) |
5653 (1ull << MSR_FE0) |
5654 (1ull << MSR_SE) |
5655 (1ull << MSR_DE) |
5656 (1ull << MSR_FE1) |
5657 (1ull << MSR_EP) |
5658 (1ull << MSR_IR) |
5659 (1ull << MSR_DR) |
5660 (1ull << MSR_PMM) |
5661 (1ull << MSR_RI) |
5662 (1ull << MSR_LE);
5663 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5664 pcc->excp_model = POWERPC_EXCP_7x5;
5665 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5666 pcc->bfd_mach = bfd_mach_ppc_750;
5667 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5668 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5669 }
5671 static void init_proc_755(CPUPPCState *env)
5672 {
5673 register_ne_601_sprs(env);
5674 register_sdr1_sprs(env);
5675 register_7xx_sprs(env);
5676 register_G2_755_sprs(env);
5677 /* Time base */
5678 register_tbl(env);
5679 /* L2 cache control */
5680 /* XXX : not implemented */
5681 spr_register(env, SPR_L2CR, "L2CR",
5682 SPR_NOACCESS, SPR_NOACCESS,
5683 &spr_read_generic, spr_access_nop,
5684 0x00000000);
5685 /* XXX : not implemented */
5686 spr_register(env, SPR_L2PMCR, "L2PMCR",
5687 SPR_NOACCESS, SPR_NOACCESS,
5688 &spr_read_generic, &spr_write_generic,
5689 0x00000000);
5690 /* Thermal management */
5691 register_thrm_sprs(env);
5692 /* Hardware implementation registers */
5693 /* XXX : not implemented */
5694 spr_register(env, SPR_HID0, "HID0",
5695 SPR_NOACCESS, SPR_NOACCESS,
5696 &spr_read_generic, &spr_write_generic,
5697 0x00000000);
5698 /* XXX : not implemented */
5699 spr_register(env, SPR_HID1, "HID1",
5700 SPR_NOACCESS, SPR_NOACCESS,
5701 &spr_read_generic, &spr_write_generic,
5702 0x00000000);
5703 /* XXX : not implemented */
5704 spr_register(env, SPR_HID2, "HID2",
5705 SPR_NOACCESS, SPR_NOACCESS,
5706 &spr_read_generic, &spr_write_generic,
5707 0x00000000);
5708 /* Memory management */
5709 register_low_BATs(env);
5710 register_high_BATs(env);
5711 register_6xx_7xx_soft_tlb(env, 64, 2);
5712 init_excp_7x5(env);
5713 env->dcache_line_size = 32;
5714 env->icache_line_size = 32;
5715 /* Allocate hardware IRQ controller */
5716 ppc6xx_irq_init(env_archcpu(env));
5717 }
5719 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
5720 {
5721 DeviceClass *dc = DEVICE_CLASS(oc);
5722 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5724 dc->desc = "PowerPC 755";
5725 pcc->init_proc = init_proc_755;
5726 pcc->check_pow = check_pow_hid0;
5727 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5728 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5729 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5730 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5731 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5732 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5733 PPC_SEGMENT | PPC_EXTERN;
5734 pcc->msr_mask = (1ull << MSR_POW) |
5735 (1ull << MSR_ILE) |
5736 (1ull << MSR_EE) |
5737 (1ull << MSR_PR) |
5738 (1ull << MSR_FP) |
5739 (1ull << MSR_ME) |
5740 (1ull << MSR_FE0) |
5741 (1ull << MSR_SE) |
5742 (1ull << MSR_DE) |
5743 (1ull << MSR_FE1) |
5744 (1ull << MSR_EP) |
5745 (1ull << MSR_IR) |
5746 (1ull << MSR_DR) |
5747 (1ull << MSR_PMM) |
5748 (1ull << MSR_RI) |
5749 (1ull << MSR_LE);
5750 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5751 pcc->excp_model = POWERPC_EXCP_7x5;
5752 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5753 pcc->bfd_mach = bfd_mach_ppc_750;
5754 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5755 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5756 }
5758 static void init_proc_7400(CPUPPCState *env)
5759 {
5760 register_ne_601_sprs(env);
5761 register_sdr1_sprs(env);
5762 register_7xx_sprs(env);
5763 /* Time base */
5764 register_tbl(env);
5765 /* 74xx specific SPR */
5766 register_74xx_sprs(env);
5767 vscr_init(env, 0x00010000);
5768 /* XXX : not implemented */
5769 spr_register(env, SPR_UBAMR, "UBAMR",
5770 &spr_read_ureg, SPR_NOACCESS,
5771 &spr_read_ureg, SPR_NOACCESS,
5772 0x00000000);
5773 /* XXX: this seems not implemented on all revisions. */
5774 /* XXX : not implemented */
5775 spr_register(env, SPR_MSSCR1, "MSSCR1",
5776 SPR_NOACCESS, SPR_NOACCESS,
5777 &spr_read_generic, &spr_write_generic,
5778 0x00000000);
5779 /* Thermal management */
5780 register_thrm_sprs(env);
5781 /* Memory management */
5782 register_low_BATs(env);
5783 init_excp_7400(env);
5784 env->dcache_line_size = 32;
5785 env->icache_line_size = 32;
5786 /* Allocate hardware IRQ controller */
5787 ppc6xx_irq_init(env_archcpu(env));
5788 }
5790 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
5791 {
5792 DeviceClass *dc = DEVICE_CLASS(oc);
5793 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5795 dc->desc = "PowerPC 7400 (aka G4)";
5796 pcc->init_proc = init_proc_7400;
5797 pcc->check_pow = check_pow_hid0;
5798 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5799 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5800 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5801 PPC_FLOAT_STFIWX |
5802 PPC_CACHE | PPC_CACHE_ICBI |
5803 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5804 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5805 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5806 PPC_MEM_TLBIA |
5807 PPC_SEGMENT | PPC_EXTERN |
5808 PPC_ALTIVEC;
5809 pcc->msr_mask = (1ull << MSR_VR) |
5810 (1ull << MSR_POW) |
5811 (1ull << MSR_ILE) |
5812 (1ull << MSR_EE) |
5813 (1ull << MSR_PR) |
5814 (1ull << MSR_FP) |
5815 (1ull << MSR_ME) |
5816 (1ull << MSR_FE0) |
5817 (1ull << MSR_SE) |
5818 (1ull << MSR_DE) |
5819 (1ull << MSR_FE1) |
5820 (1ull << MSR_EP) |
5821 (1ull << MSR_IR) |
5822 (1ull << MSR_DR) |
5823 (1ull << MSR_PMM) |
5824 (1ull << MSR_RI) |
5825 (1ull << MSR_LE);
5826 pcc->mmu_model = POWERPC_MMU_32B;
5827 #if defined(CONFIG_SOFTMMU)
5828 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5829 #endif
5830 pcc->excp_model = POWERPC_EXCP_74xx;
5831 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5832 pcc->bfd_mach = bfd_mach_ppc_7400;
5833 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5834 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5835 POWERPC_FLAG_BUS_CLK;
5836 }
5838 static void init_proc_7410(CPUPPCState *env)
5839 {
5840 register_ne_601_sprs(env);
5841 register_sdr1_sprs(env);
5842 register_7xx_sprs(env);
5843 /* Time base */
5844 register_tbl(env);
5845 /* 74xx specific SPR */
5846 register_74xx_sprs(env);
5847 vscr_init(env, 0x00010000);
5848 /* XXX : not implemented */
5849 spr_register(env, SPR_UBAMR, "UBAMR",
5850 &spr_read_ureg, SPR_NOACCESS,
5851 &spr_read_ureg, SPR_NOACCESS,
5852 0x00000000);
5853 /* Thermal management */
5854 register_thrm_sprs(env);
5855 /* L2PMCR */
5856 /* XXX : not implemented */
5857 spr_register(env, SPR_L2PMCR, "L2PMCR",
5858 SPR_NOACCESS, SPR_NOACCESS,
5859 &spr_read_generic, &spr_write_generic,
5860 0x00000000);
5861 /* LDSTDB */
5862 /* XXX : not implemented */
5863 spr_register(env, SPR_LDSTDB, "LDSTDB",
5864 SPR_NOACCESS, SPR_NOACCESS,
5865 &spr_read_generic, &spr_write_generic,
5866 0x00000000);
5867 /* Memory management */
5868 register_low_BATs(env);
5869 init_excp_7400(env);
5870 env->dcache_line_size = 32;
5871 env->icache_line_size = 32;
5872 /* Allocate hardware IRQ controller */
5873 ppc6xx_irq_init(env_archcpu(env));
5874 }
5876 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
5877 {
5878 DeviceClass *dc = DEVICE_CLASS(oc);
5879 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5881 dc->desc = "PowerPC 7410 (aka G4)";
5882 pcc->init_proc = init_proc_7410;
5883 pcc->check_pow = check_pow_hid0;
5884 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5885 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5886 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5887 PPC_FLOAT_STFIWX |
5888 PPC_CACHE | PPC_CACHE_ICBI |
5889 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5890 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5891 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5892 PPC_MEM_TLBIA |
5893 PPC_SEGMENT | PPC_EXTERN |
5894 PPC_ALTIVEC;
5895 pcc->msr_mask = (1ull << MSR_VR) |
5896 (1ull << MSR_POW) |
5897 (1ull << MSR_ILE) |
5898 (1ull << MSR_EE) |
5899 (1ull << MSR_PR) |
5900 (1ull << MSR_FP) |
5901 (1ull << MSR_ME) |
5902 (1ull << MSR_FE0) |
5903 (1ull << MSR_SE) |
5904 (1ull << MSR_DE) |
5905 (1ull << MSR_FE1) |
5906 (1ull << MSR_EP) |
5907 (1ull << MSR_IR) |
5908 (1ull << MSR_DR) |
5909 (1ull << MSR_PMM) |
5910 (1ull << MSR_RI) |
5911 (1ull << MSR_LE);
5912 pcc->mmu_model = POWERPC_MMU_32B;
5913 #if defined(CONFIG_SOFTMMU)
5914 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5915 #endif
5916 pcc->excp_model = POWERPC_EXCP_74xx;
5917 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5918 pcc->bfd_mach = bfd_mach_ppc_7400;
5919 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5920 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5921 POWERPC_FLAG_BUS_CLK;
5922 }
5924 static void init_proc_7440(CPUPPCState *env)
5925 {
5926 register_ne_601_sprs(env);
5927 register_sdr1_sprs(env);
5928 register_7xx_sprs(env);
5929 /* Time base */
5930 register_tbl(env);
5931 /* 74xx specific SPR */
5932 register_74xx_sprs(env);
5933 vscr_init(env, 0x00010000);
5934 /* XXX : not implemented */
5935 spr_register(env, SPR_UBAMR, "UBAMR",
5936 &spr_read_ureg, SPR_NOACCESS,
5937 &spr_read_ureg, SPR_NOACCESS,
5938 0x00000000);
5939 /* LDSTCR */
5940 /* XXX : not implemented */
5941 spr_register(env, SPR_LDSTCR, "LDSTCR",
5942 SPR_NOACCESS, SPR_NOACCESS,
5943 &spr_read_generic, &spr_write_generic,
5944 0x00000000);
5945 /* ICTRL */
5946 /* XXX : not implemented */
5947 spr_register(env, SPR_ICTRL, "ICTRL",
5948 SPR_NOACCESS, SPR_NOACCESS,
5949 &spr_read_generic, &spr_write_generic,
5950 0x00000000);
5951 /* MSSSR0 */
5952 /* XXX : not implemented */
5953 spr_register(env, SPR_MSSSR0, "MSSSR0",
5954 SPR_NOACCESS, SPR_NOACCESS,
5955 &spr_read_generic, &spr_write_generic,
5956 0x00000000);
5957 /* PMC */
5958 /* XXX : not implemented */
5959 spr_register(env, SPR_7XX_PMC5, "PMC5",
5960 SPR_NOACCESS, SPR_NOACCESS,
5961 &spr_read_generic, &spr_write_generic,
5962 0x00000000);
5963 /* XXX : not implemented */
5964 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5965 &spr_read_ureg, SPR_NOACCESS,
5966 &spr_read_ureg, SPR_NOACCESS,
5967 0x00000000);
5968 /* XXX : not implemented */
5969 spr_register(env, SPR_7XX_PMC6, "PMC6",
5970 SPR_NOACCESS, SPR_NOACCESS,
5971 &spr_read_generic, &spr_write_generic,
5972 0x00000000);
5973 /* XXX : not implemented */
5974 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5975 &spr_read_ureg, SPR_NOACCESS,
5976 &spr_read_ureg, SPR_NOACCESS,
5977 0x00000000);
5978 /* Memory management */
5979 register_low_BATs(env);
5980 register_74xx_soft_tlb(env, 128, 2);
5981 init_excp_7450(env);
5982 env->dcache_line_size = 32;
5983 env->icache_line_size = 32;
5984 /* Allocate hardware IRQ controller */
5985 ppc6xx_irq_init(env_archcpu(env));
5986 }
5988 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
5989 {
5990 DeviceClass *dc = DEVICE_CLASS(oc);
5991 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5993 dc->desc = "PowerPC 7440 (aka G4)";
5994 pcc->init_proc = init_proc_7440;
5995 pcc->check_pow = check_pow_hid0_74xx;
5996 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5997 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5998 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5999 PPC_FLOAT_STFIWX |
6000 PPC_CACHE | PPC_CACHE_ICBI |
6001 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6002 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6003 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6004 PPC_MEM_TLBIA | PPC_74xx_TLB |
6005 PPC_SEGMENT | PPC_EXTERN |
6006 PPC_ALTIVEC;
6007 pcc->msr_mask = (1ull << MSR_VR) |
6008 (1ull << MSR_POW) |
6009 (1ull << MSR_ILE) |
6010 (1ull << MSR_EE) |
6011 (1ull << MSR_PR) |
6012 (1ull << MSR_FP) |
6013 (1ull << MSR_ME) |
6014 (1ull << MSR_FE0) |
6015 (1ull << MSR_SE) |
6016 (1ull << MSR_DE) |
6017 (1ull << MSR_FE1) |
6018 (1ull << MSR_EP) |
6019 (1ull << MSR_IR) |
6020 (1ull << MSR_DR) |
6021 (1ull << MSR_PMM) |
6022 (1ull << MSR_RI) |
6023 (1ull << MSR_LE);
6024 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6025 pcc->excp_model = POWERPC_EXCP_74xx;
6026 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6027 pcc->bfd_mach = bfd_mach_ppc_7400;
6028 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6029 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6030 POWERPC_FLAG_BUS_CLK;
6031 }
6033 static void init_proc_7450(CPUPPCState *env)
6034 {
6035 register_ne_601_sprs(env);
6036 register_sdr1_sprs(env);
6037 register_7xx_sprs(env);
6038 /* Time base */
6039 register_tbl(env);
6040 /* 74xx specific SPR */
6041 register_74xx_sprs(env);
6042 vscr_init(env, 0x00010000);
6043 /* Level 3 cache control */
6044 register_l3_ctrl(env);
6045 /* L3ITCR1 */
6046 /* XXX : not implemented */
6047 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6048 SPR_NOACCESS, SPR_NOACCESS,
6049 &spr_read_generic, &spr_write_generic,
6050 0x00000000);
6051 /* L3ITCR2 */
6052 /* XXX : not implemented */
6053 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6054 SPR_NOACCESS, SPR_NOACCESS,
6055 &spr_read_generic, &spr_write_generic,
6056 0x00000000);
6057 /* L3ITCR3 */
6058 /* XXX : not implemented */
6059 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6060 SPR_NOACCESS, SPR_NOACCESS,
6061 &spr_read_generic, &spr_write_generic,
6062 0x00000000);
6063 /* L3OHCR */
6064 /* XXX : not implemented */
6065 spr_register(env, SPR_L3OHCR, "L3OHCR",
6066 SPR_NOACCESS, SPR_NOACCESS,
6067 &spr_read_generic, &spr_write_generic,
6068 0x00000000);
6069 /* XXX : not implemented */
6070 spr_register(env, SPR_UBAMR, "UBAMR",
6071 &spr_read_ureg, SPR_NOACCESS,
6072 &spr_read_ureg, SPR_NOACCESS,
6073 0x00000000);
6074 /* LDSTCR */
6075 /* XXX : not implemented */
6076 spr_register(env, SPR_LDSTCR, "LDSTCR",
6077 SPR_NOACCESS, SPR_NOACCESS,
6078 &spr_read_generic, &spr_write_generic,
6079 0x00000000);
6080 /* ICTRL */
6081 /* XXX : not implemented */
6082 spr_register(env, SPR_ICTRL, "ICTRL",
6083 SPR_NOACCESS, SPR_NOACCESS,
6084 &spr_read_generic, &spr_write_generic,
6085 0x00000000);
6086 /* MSSSR0 */
6087 /* XXX : not implemented */
6088 spr_register(env, SPR_MSSSR0, "MSSSR0",
6089 SPR_NOACCESS, SPR_NOACCESS,
6090 &spr_read_generic, &spr_write_generic,
6091 0x00000000);
6092 /* PMC */
6093 /* XXX : not implemented */
6094 spr_register(env, SPR_7XX_PMC5, "PMC5",
6095 SPR_NOACCESS, SPR_NOACCESS,
6096 &spr_read_generic, &spr_write_generic,
6097 0x00000000);
6098 /* XXX : not implemented */
6099 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6100 &spr_read_ureg, SPR_NOACCESS,
6101 &spr_read_ureg, SPR_NOACCESS,
6102 0x00000000);
6103 /* XXX : not implemented */
6104 spr_register(env, SPR_7XX_PMC6, "PMC6",
6105 SPR_NOACCESS, SPR_NOACCESS,
6106 &spr_read_generic, &spr_write_generic,
6107 0x00000000);
6108 /* XXX : not implemented */
6109 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6110 &spr_read_ureg, SPR_NOACCESS,
6111 &spr_read_ureg, SPR_NOACCESS,
6112 0x00000000);
6113 /* Memory management */
6114 register_low_BATs(env);
6115 register_74xx_soft_tlb(env, 128, 2);
6116 init_excp_7450(env);
6117 env->dcache_line_size = 32;
6118 env->icache_line_size = 32;
6119 /* Allocate hardware IRQ controller */
6120 ppc6xx_irq_init(env_archcpu(env));
6121 }
6123 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6124 {
6125 DeviceClass *dc = DEVICE_CLASS(oc);
6126 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6128 dc->desc = "PowerPC 7450 (aka G4)";
6129 pcc->init_proc = init_proc_7450;
6130 pcc->check_pow = check_pow_hid0_74xx;
6131 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6132 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6133 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6134 PPC_FLOAT_STFIWX |
6135 PPC_CACHE | PPC_CACHE_ICBI |
6136 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6137 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6138 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6139 PPC_MEM_TLBIA | PPC_74xx_TLB |
6140 PPC_SEGMENT | PPC_EXTERN |
6141 PPC_ALTIVEC;
6142 pcc->msr_mask = (1ull << MSR_VR) |
6143 (1ull << MSR_POW) |
6144 (1ull << MSR_ILE) |
6145 (1ull << MSR_EE) |
6146 (1ull << MSR_PR) |
6147 (1ull << MSR_FP) |
6148 (1ull << MSR_ME) |
6149 (1ull << MSR_FE0) |
6150 (1ull << MSR_SE) |
6151 (1ull << MSR_DE) |
6152 (1ull << MSR_FE1) |
6153 (1ull << MSR_EP) |
6154 (1ull << MSR_IR) |
6155 (1ull << MSR_DR) |
6156 (1ull << MSR_PMM) |
6157 (1ull << MSR_RI) |
6158 (1ull << MSR_LE);
6159 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6160 pcc->excp_model = POWERPC_EXCP_74xx;
6161 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6162 pcc->bfd_mach = bfd_mach_ppc_7400;
6163 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6164 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6165 POWERPC_FLAG_BUS_CLK;
6166 }
6168 static void init_proc_7445(CPUPPCState *env)
6169 {
6170 register_ne_601_sprs(env);
6171 register_sdr1_sprs(env);
6172 register_7xx_sprs(env);
6173 /* Time base */
6174 register_tbl(env);
6175 /* 74xx specific SPR */
6176 register_74xx_sprs(env);
6177 vscr_init(env, 0x00010000);
6178 /* LDSTCR */
6179 /* XXX : not implemented */
6180 spr_register(env, SPR_LDSTCR, "LDSTCR",
6181 SPR_NOACCESS, SPR_NOACCESS,
6182 &spr_read_generic, &spr_write_generic,
6183 0x00000000);
6184 /* ICTRL */
6185 /* XXX : not implemented */
6186 spr_register(env, SPR_ICTRL, "ICTRL",
6187 SPR_NOACCESS, SPR_NOACCESS,
6188 &spr_read_generic, &spr_write_generic,
6189 0x00000000);
6190 /* MSSSR0 */
6191 /* XXX : not implemented */
6192 spr_register(env, SPR_MSSSR0, "MSSSR0",
6193 SPR_NOACCESS, SPR_NOACCESS,
6194 &spr_read_generic, &spr_write_generic,
6195 0x00000000);
6196 /* PMC */
6197 /* XXX : not implemented */
6198 spr_register(env, SPR_7XX_PMC5, "PMC5",
6199 SPR_NOACCESS, SPR_NOACCESS,
6200 &spr_read_generic, &spr_write_generic,
6201 0x00000000);
6202 /* XXX : not implemented */
6203 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6204 &spr_read_ureg, SPR_NOACCESS,
6205 &spr_read_ureg, SPR_NOACCESS,
6206 0x00000000);
6207 /* XXX : not implemented */
6208 spr_register(env, SPR_7XX_PMC6, "PMC6",
6209 SPR_NOACCESS, SPR_NOACCESS,
6210 &spr_read_generic, &spr_write_generic,
6211 0x00000000);
6212 /* XXX : not implemented */
6213 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6214 &spr_read_ureg, SPR_NOACCESS,
6215 &spr_read_ureg, SPR_NOACCESS,
6216 0x00000000);
6217 /* SPRGs */
6218 spr_register(env, SPR_SPRG4, "SPRG4",
6219 SPR_NOACCESS, SPR_NOACCESS,
6220 &spr_read_generic, &spr_write_generic,
6221 0x00000000);
6222 spr_register(env, SPR_USPRG4, "USPRG4",
6223 &spr_read_ureg, SPR_NOACCESS,
6224 &spr_read_ureg, SPR_NOACCESS,
6225 0x00000000);
6226 spr_register(env, SPR_SPRG5, "SPRG5",
6227 SPR_NOACCESS, SPR_NOACCESS,
6228 &spr_read_generic, &spr_write_generic,
6229 0x00000000);
6230 spr_register(env, SPR_USPRG5, "USPRG5",
6231 &spr_read_ureg, SPR_NOACCESS,
6232 &spr_read_ureg, SPR_NOACCESS,
6233 0x00000000);
6234 spr_register(env, SPR_SPRG6, "SPRG6",
6235 SPR_NOACCESS, SPR_NOACCESS,
6236 &spr_read_generic, &spr_write_generic,
6237 0x00000000);
6238 spr_register(env, SPR_USPRG6, "USPRG6",
6239 &spr_read_ureg, SPR_NOACCESS,
6240 &spr_read_ureg, SPR_NOACCESS,
6241 0x00000000);
6242 spr_register(env, SPR_SPRG7, "SPRG7",
6243 SPR_NOACCESS, SPR_NOACCESS,
6244 &spr_read_generic, &spr_write_generic,
6245 0x00000000);
6246 spr_register(env, SPR_USPRG7, "USPRG7",
6247 &spr_read_ureg, SPR_NOACCESS,
6248 &spr_read_ureg, SPR_NOACCESS,
6249 0x00000000);
6250 /* Memory management */
6251 register_low_BATs(env);
6252 register_high_BATs(env);
6253 register_74xx_soft_tlb(env, 128, 2);
6254 init_excp_7450(env);
6255 env->dcache_line_size = 32;
6256 env->icache_line_size = 32;
6257 /* Allocate hardware IRQ controller */
6258 ppc6xx_irq_init(env_archcpu(env));
6259 }
6261 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6262 {
6263 DeviceClass *dc = DEVICE_CLASS(oc);
6264 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6266 dc->desc = "PowerPC 7445 (aka G4)";
6267 pcc->init_proc = init_proc_7445;
6268 pcc->check_pow = check_pow_hid0_74xx;
6269 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6270 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6271 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6272 PPC_FLOAT_STFIWX |
6273 PPC_CACHE | PPC_CACHE_ICBI |
6274 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6275 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6276 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6277 PPC_MEM_TLBIA | PPC_74xx_TLB |
6278 PPC_SEGMENT | PPC_EXTERN |
6279 PPC_ALTIVEC;
6280 pcc->msr_mask = (1ull << MSR_VR) |
6281 (1ull << MSR_POW) |
6282 (1ull << MSR_ILE) |
6283 (1ull << MSR_EE) |
6284 (1ull << MSR_PR) |
6285 (1ull << MSR_FP) |
6286 (1ull << MSR_ME) |
6287 (1ull << MSR_FE0) |
6288 (1ull << MSR_SE) |
6289 (1ull << MSR_DE) |
6290 (1ull << MSR_FE1) |
6291 (1ull << MSR_EP) |
6292 (1ull << MSR_IR) |
6293 (1ull << MSR_DR) |
6294 (1ull << MSR_PMM) |
6295 (1ull << MSR_RI) |
6296 (1ull << MSR_LE);
6297 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6298 pcc->excp_model = POWERPC_EXCP_74xx;
6299 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6300 pcc->bfd_mach = bfd_mach_ppc_7400;
6301 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6302 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6303 POWERPC_FLAG_BUS_CLK;
6304 }
6306 static void init_proc_7455(CPUPPCState *env)
6307 {
6308 register_ne_601_sprs(env);
6309 register_sdr1_sprs(env);
6310 register_7xx_sprs(env);
6311 /* Time base */
6312 register_tbl(env);
6313 /* 74xx specific SPR */
6314 register_74xx_sprs(env);
6315 vscr_init(env, 0x00010000);
6316 /* Level 3 cache control */
6317 register_l3_ctrl(env);
6318 /* LDSTCR */
6319 /* XXX : not implemented */
6320 spr_register(env, SPR_LDSTCR, "LDSTCR",
6321 SPR_NOACCESS, SPR_NOACCESS,
6322 &spr_read_generic, &spr_write_generic,
6323 0x00000000);
6324 /* ICTRL */
6325 /* XXX : not implemented */
6326 spr_register(env, SPR_ICTRL, "ICTRL",
6327 SPR_NOACCESS, SPR_NOACCESS,
6328 &spr_read_generic, &spr_write_generic,
6329 0x00000000);
6330 /* MSSSR0 */
6331 /* XXX : not implemented */
6332 spr_register(env, SPR_MSSSR0, "MSSSR0",
6333 SPR_NOACCESS, SPR_NOACCESS,
6334 &spr_read_generic, &spr_write_generic,
6335 0x00000000);
6336 /* PMC */
6337 /* XXX : not implemented */
6338 spr_register(env, SPR_7XX_PMC5, "PMC5",
6339 SPR_NOACCESS, SPR_NOACCESS,
6340 &spr_read_generic, &spr_write_generic,
6341 0x00000000);
6342 /* XXX : not implemented */
6343 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6344 &spr_read_ureg, SPR_NOACCESS,
6345 &spr_read_ureg, SPR_NOACCESS,
6346 0x00000000);
6347 /* XXX : not implemented */
6348 spr_register(env, SPR_7XX_PMC6, "PMC6",
6349 SPR_NOACCESS, SPR_NOACCESS,
6350 &spr_read_generic, &spr_write_generic,
6351 0x00000000);
6352 /* XXX : not implemented */
6353 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6354 &spr_read_ureg, SPR_NOACCESS,
6355 &spr_read_ureg, SPR_NOACCESS,
6356 0x00000000);
6357 /* SPRGs */
6358 spr_register(env, SPR_SPRG4, "SPRG4",
6359 SPR_NOACCESS, SPR_NOACCESS,
6360 &spr_read_generic, &spr_write_generic,
6361 0x00000000);
6362 spr_register(env, SPR_USPRG4, "USPRG4",
6363 &spr_read_ureg, SPR_NOACCESS,
6364 &spr_read_ureg, SPR_NOACCESS,
6365 0x00000000);
6366 spr_register(env, SPR_SPRG5, "SPRG5",
6367 SPR_NOACCESS, SPR_NOACCESS,
6368 &spr_read_generic, &spr_write_generic,
6369 0x00000000);
6370 spr_register(env, SPR_USPRG5, "USPRG5",
6371 &spr_read_ureg, SPR_NOACCESS,
6372 &spr_read_ureg, SPR_NOACCESS,
6373 0x00000000);
6374 spr_register(env, SPR_SPRG6, "SPRG6",
6375 SPR_NOACCESS, SPR_NOACCESS,
6376 &spr_read_generic, &spr_write_generic,
6377 0x00000000);
6378 spr_register(env, SPR_USPRG6, "USPRG6",
6379 &spr_read_ureg, SPR_NOACCESS,
6380 &spr_read_ureg, SPR_NOACCESS,
6381 0x00000000);
6382 spr_register(env, SPR_SPRG7, "SPRG7",
6383 SPR_NOACCESS, SPR_NOACCESS,
6384 &spr_read_generic, &spr_write_generic,
6385 0x00000000);
6386 spr_register(env, SPR_USPRG7, "USPRG7",
6387 &spr_read_ureg, SPR_NOACCESS,
6388 &spr_read_ureg, SPR_NOACCESS,
6389 0x00000000);
6390 /* Memory management */
6391 register_low_BATs(env);
6392 register_high_BATs(env);
6393 register_74xx_soft_tlb(env, 128, 2);
6394 init_excp_7450(env);
6395 env->dcache_line_size = 32;
6396 env->icache_line_size = 32;
6397 /* Allocate hardware IRQ controller */
6398 ppc6xx_irq_init(env_archcpu(env));
6399 }
6401 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6402 {
6403 DeviceClass *dc = DEVICE_CLASS(oc);
6404 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6406 dc->desc = "PowerPC 7455 (aka G4)";
6407 pcc->init_proc = init_proc_7455;
6408 pcc->check_pow = check_pow_hid0_74xx;
6409 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6410 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6411 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6412 PPC_FLOAT_STFIWX |
6413 PPC_CACHE | PPC_CACHE_ICBI |
6414 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6415 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6416 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6417 PPC_MEM_TLBIA | PPC_74xx_TLB |
6418 PPC_SEGMENT | PPC_EXTERN |
6419 PPC_ALTIVEC;
6420 pcc->msr_mask = (1ull << MSR_VR) |
6421 (1ull << MSR_POW) |
6422 (1ull << MSR_ILE) |
6423 (1ull << MSR_EE) |
6424 (1ull << MSR_PR) |
6425 (1ull << MSR_FP) |
6426 (1ull << MSR_ME) |
6427 (1ull << MSR_FE0) |
6428 (1ull << MSR_SE) |
6429 (1ull << MSR_DE) |
6430 (1ull << MSR_FE1) |
6431 (1ull << MSR_EP) |
6432 (1ull << MSR_IR) |
6433 (1ull << MSR_DR) |
6434 (1ull << MSR_PMM) |
6435 (1ull << MSR_RI) |
6436 (1ull << MSR_LE);
6437 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6438 pcc->excp_model = POWERPC_EXCP_74xx;
6439 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6440 pcc->bfd_mach = bfd_mach_ppc_7400;
6441 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6442 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6443 POWERPC_FLAG_BUS_CLK;
6444 }
6446 static void init_proc_7457(CPUPPCState *env)
6447 {
6448 register_ne_601_sprs(env);
6449 register_sdr1_sprs(env);
6450 register_7xx_sprs(env);
6451 /* Time base */
6452 register_tbl(env);
6453 /* 74xx specific SPR */
6454 register_74xx_sprs(env);
6455 vscr_init(env, 0x00010000);
6456 /* Level 3 cache control */
6457 register_l3_ctrl(env);
6458 /* L3ITCR1 */
6459 /* XXX : not implemented */
6460 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6461 SPR_NOACCESS, SPR_NOACCESS,
6462 &spr_read_generic, &spr_write_generic,
6463 0x00000000);
6464 /* L3ITCR2 */
6465 /* XXX : not implemented */
6466 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6467 SPR_NOACCESS, SPR_NOACCESS,
6468 &spr_read_generic, &spr_write_generic,
6469 0x00000000);
6470 /* L3ITCR3 */
6471 /* XXX : not implemented */
6472 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6473 SPR_NOACCESS, SPR_NOACCESS,
6474 &spr_read_generic, &spr_write_generic,
6475 0x00000000);
6476 /* L3OHCR */
6477 /* XXX : not implemented */
6478 spr_register(env, SPR_L3OHCR, "L3OHCR",
6479 SPR_NOACCESS, SPR_NOACCESS,
6480 &spr_read_generic, &spr_write_generic,
6481 0x00000000);
6482 /* LDSTCR */
6483 /* XXX : not implemented */
6484 spr_register(env, SPR_LDSTCR, "LDSTCR",
6485 SPR_NOACCESS, SPR_NOACCESS,
6486 &spr_read_generic, &spr_write_generic,
6487 0x00000000);
6488 /* ICTRL */
6489 /* XXX : not implemented */
6490 spr_register(env, SPR_ICTRL, "ICTRL",
6491 SPR_NOACCESS, SPR_NOACCESS,
6492 &spr_read_generic, &spr_write_generic,
6493 0x00000000);
6494 /* MSSSR0 */
6495 /* XXX : not implemented */
6496 spr_register(env, SPR_MSSSR0, "MSSSR0",
6497 SPR_NOACCESS, SPR_NOACCESS,
6498 &spr_read_generic, &spr_write_generic,
6499 0x00000000);
6500 /* PMC */
6501 /* XXX : not implemented */
6502 spr_register(env, SPR_7XX_PMC5, "PMC5",
6503 SPR_NOACCESS, SPR_NOACCESS,
6504 &spr_read_generic, &spr_write_generic,
6505 0x00000000);
6506 /* XXX : not implemented */
6507 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6508 &spr_read_ureg, SPR_NOACCESS,
6509 &spr_read_ureg, SPR_NOACCESS,
6510 0x00000000);
6511 /* XXX : not implemented */
6512 spr_register(env, SPR_7XX_PMC6, "PMC6",
6513 SPR_NOACCESS, SPR_NOACCESS,
6514 &spr_read_generic, &spr_write_generic,
6515 0x00000000);
6516 /* XXX : not implemented */
6517 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6518 &spr_read_ureg, SPR_NOACCESS,
6519 &spr_read_ureg, SPR_NOACCESS,
6520 0x00000000);
6521 /* SPRGs */
6522 spr_register(env, SPR_SPRG4, "SPRG4",
6523 SPR_NOACCESS, SPR_NOACCESS,
6524 &spr_read_generic, &spr_write_generic,
6525 0x00000000);
6526 spr_register(env, SPR_USPRG4, "USPRG4",
6527 &spr_read_ureg, SPR_NOACCESS,
6528 &spr_read_ureg, SPR_NOACCESS,
6529 0x00000000);
6530 spr_register(env, SPR_SPRG5, "SPRG5",
6531 SPR_NOACCESS, SPR_NOACCESS,
6532 &spr_read_generic, &spr_write_generic,
6533 0x00000000);
6534 spr_register(env, SPR_USPRG5, "USPRG5",
6535 &spr_read_ureg, SPR_NOACCESS,
6536 &spr_read_ureg, SPR_NOACCESS,
6537 0x00000000);
6538 spr_register(env, SPR_SPRG6, "SPRG6",
6539 SPR_NOACCESS, SPR_NOACCESS,
6540 &spr_read_generic, &spr_write_generic,
6541 0x00000000);
6542 spr_register(env, SPR_USPRG6, "USPRG6",
6543 &spr_read_ureg, SPR_NOACCESS,
6544 &spr_read_ureg, SPR_NOACCESS,
6545 0x00000000);
6546 spr_register(env, SPR_SPRG7, "SPRG7",
6547 SPR_NOACCESS, SPR_NOACCESS,
6548 &spr_read_generic, &spr_write_generic,
6549 0x00000000);
6550 spr_register(env, SPR_USPRG7, "USPRG7",
6551 &spr_read_ureg, SPR_NOACCESS,
6552 &spr_read_ureg, SPR_NOACCESS,
6553 0x00000000);
6554 /* Memory management */
6555 register_low_BATs(env);
6556 register_high_BATs(env);
6557 register_74xx_soft_tlb(env, 128, 2);
6558 init_excp_7450(env);
6559 env->dcache_line_size = 32;
6560 env->icache_line_size = 32;
6561 /* Allocate hardware IRQ controller */
6562 ppc6xx_irq_init(env_archcpu(env));
6563 }
6565 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
6566 {
6567 DeviceClass *dc = DEVICE_CLASS(oc);
6568 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6570 dc->desc = "PowerPC 7457 (aka G4)";
6571 pcc->init_proc = init_proc_7457;
6572 pcc->check_pow = check_pow_hid0_74xx;
6573 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6574 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6575 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6576 PPC_FLOAT_STFIWX |
6577 PPC_CACHE | PPC_CACHE_ICBI |
6578 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6579 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6580 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6581 PPC_MEM_TLBIA | PPC_74xx_TLB |
6582 PPC_SEGMENT | PPC_EXTERN |
6583 PPC_ALTIVEC;
6584 pcc->msr_mask = (1ull << MSR_VR) |
6585 (1ull << MSR_POW) |
6586 (1ull << MSR_ILE) |
6587 (1ull << MSR_EE) |
6588 (1ull << MSR_PR) |
6589 (1ull << MSR_FP) |
6590 (1ull << MSR_ME) |
6591 (1ull << MSR_FE0) |
6592 (1ull << MSR_SE) |
6593 (1ull << MSR_DE) |
6594 (1ull << MSR_FE1) |
6595 (1ull << MSR_EP) |
6596 (1ull << MSR_IR) |
6597 (1ull << MSR_DR) |
6598 (1ull << MSR_PMM) |
6599 (1ull << MSR_RI) |
6600 (1ull << MSR_LE);
6601 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6602 pcc->excp_model = POWERPC_EXCP_74xx;
6603 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6604 pcc->bfd_mach = bfd_mach_ppc_7400;
6605 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6606 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6607 POWERPC_FLAG_BUS_CLK;
6608 }
6610 static void init_proc_e600(CPUPPCState *env)
6611 {
6612 register_ne_601_sprs(env);
6613 register_sdr1_sprs(env);
6614 register_7xx_sprs(env);
6615 /* Time base */
6616 register_tbl(env);
6617 /* 74xx specific SPR */
6618 register_74xx_sprs(env);
6619 vscr_init(env, 0x00010000);
6620 /* XXX : not implemented */
6621 spr_register(env, SPR_UBAMR, "UBAMR",
6622 &spr_read_ureg, SPR_NOACCESS,
6623 &spr_read_ureg, SPR_NOACCESS,
6624 0x00000000);
6625 /* XXX : not implemented */
6626 spr_register(env, SPR_LDSTCR, "LDSTCR",
6627 SPR_NOACCESS, SPR_NOACCESS,
6628 &spr_read_generic, &spr_write_generic,
6629 0x00000000);
6630 /* XXX : not implemented */
6631 spr_register(env, SPR_ICTRL, "ICTRL",
6632 SPR_NOACCESS, SPR_NOACCESS,
6633 &spr_read_generic, &spr_write_generic,
6634 0x00000000);
6635 /* XXX : not implemented */
6636 spr_register(env, SPR_MSSSR0, "MSSSR0",
6637 SPR_NOACCESS, SPR_NOACCESS,
6638 &spr_read_generic, &spr_write_generic,
6639 0x00000000);
6640 /* XXX : not implemented */
6641 spr_register(env, SPR_7XX_PMC5, "PMC5",
6642 SPR_NOACCESS, SPR_NOACCESS,
6643 &spr_read_generic, &spr_write_generic,
6644 0x00000000);
6645 /* XXX : not implemented */
6646 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6647 &spr_read_ureg, SPR_NOACCESS,
6648 &spr_read_ureg, SPR_NOACCESS,
6649 0x00000000);
6650 /* XXX : not implemented */
6651 spr_register(env, SPR_7XX_PMC6, "PMC6",
6652 SPR_NOACCESS, SPR_NOACCESS,
6653 &spr_read_generic, &spr_write_generic,
6654 0x00000000);
6655 /* XXX : not implemented */
6656 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6657 &spr_read_ureg, SPR_NOACCESS,
6658 &spr_read_ureg, SPR_NOACCESS,
6659 0x00000000);
6660 /* SPRGs */
6661 spr_register(env, SPR_SPRG4, "SPRG4",
6662 SPR_NOACCESS, SPR_NOACCESS,
6663 &spr_read_generic, &spr_write_generic,
6664 0x00000000);
6665 spr_register(env, SPR_USPRG4, "USPRG4",
6666 &spr_read_ureg, SPR_NOACCESS,
6667 &spr_read_ureg, SPR_NOACCESS,
6668 0x00000000);
6669 spr_register(env, SPR_SPRG5, "SPRG5",
6670 SPR_NOACCESS, SPR_NOACCESS,
6671 &spr_read_generic, &spr_write_generic,
6672 0x00000000);
6673 spr_register(env, SPR_USPRG5, "USPRG5",
6674 &spr_read_ureg, SPR_NOACCESS,
6675 &spr_read_ureg, SPR_NOACCESS,
6676 0x00000000);
6677 spr_register(env, SPR_SPRG6, "SPRG6",
6678 SPR_NOACCESS, SPR_NOACCESS,
6679 &spr_read_generic, &spr_write_generic,
6680 0x00000000);
6681 spr_register(env, SPR_USPRG6, "USPRG6",
6682 &spr_read_ureg, SPR_NOACCESS,
6683 &spr_read_ureg, SPR_NOACCESS,
6684 0x00000000);
6685 spr_register(env, SPR_SPRG7, "SPRG7",
6686 SPR_NOACCESS, SPR_NOACCESS,
6687 &spr_read_generic, &spr_write_generic,
6688 0x00000000);
6689 spr_register(env, SPR_USPRG7, "USPRG7",
6690 &spr_read_ureg, SPR_NOACCESS,
6691 &spr_read_ureg, SPR_NOACCESS,
6692 0x00000000);
6693 /* Memory management */
6694 register_low_BATs(env);
6695 register_high_BATs(env);
6696 register_74xx_soft_tlb(env, 128, 2);
6697 init_excp_7450(env);
6698 env->dcache_line_size = 32;
6699 env->icache_line_size = 32;
6700 /* Allocate hardware IRQ controller */
6701 ppc6xx_irq_init(env_archcpu(env));
6702 }
6704 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
6705 {
6706 DeviceClass *dc = DEVICE_CLASS(oc);
6707 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6709 dc->desc = "PowerPC e600";
6710 pcc->init_proc = init_proc_e600;
6711 pcc->check_pow = check_pow_hid0_74xx;
6712 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6713 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6714 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6715 PPC_FLOAT_STFIWX |
6716 PPC_CACHE | PPC_CACHE_ICBI |
6717 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6718 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6719 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6720 PPC_MEM_TLBIA | PPC_74xx_TLB |
6721 PPC_SEGMENT | PPC_EXTERN |
6722 PPC_ALTIVEC;
6723 pcc->insns_flags2 = PPC_NONE;
6724 pcc->msr_mask = (1ull << MSR_VR) |
6725 (1ull << MSR_POW) |
6726 (1ull << MSR_ILE) |
6727 (1ull << MSR_EE) |
6728 (1ull << MSR_PR) |
6729 (1ull << MSR_FP) |
6730 (1ull << MSR_ME) |
6731 (1ull << MSR_FE0) |
6732 (1ull << MSR_SE) |
6733 (1ull << MSR_DE) |
6734 (1ull << MSR_FE1) |
6735 (1ull << MSR_EP) |
6736 (1ull << MSR_IR) |
6737 (1ull << MSR_DR) |
6738 (1ull << MSR_PMM) |
6739 (1ull << MSR_RI) |
6740 (1ull << MSR_LE);
6741 pcc->mmu_model = POWERPC_MMU_32B;
6742 #if defined(CONFIG_SOFTMMU)
6743 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6744 #endif
6745 pcc->excp_model = POWERPC_EXCP_74xx;
6746 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6747 pcc->bfd_mach = bfd_mach_ppc_7400;
6748 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6749 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6750 POWERPC_FLAG_BUS_CLK;
6751 }
6753 #if defined(TARGET_PPC64)
6754 #if defined(CONFIG_USER_ONLY)
6755 #define POWERPC970_HID5_INIT 0x00000080
6756 #else
6757 #define POWERPC970_HID5_INIT 0x00000000
6758 #endif
6760 static int check_pow_970(CPUPPCState *env)
6761 {
6762 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
6763 return 1;
6764 }
6766 return 0;
6767 }
6769 static void register_970_hid_sprs(CPUPPCState *env)
6770 {
6771 /* Hardware implementation registers */
6772 /* XXX : not implemented */
6773 spr_register(env, SPR_HID0, "HID0",
6774 SPR_NOACCESS, SPR_NOACCESS,
6775 &spr_read_generic, &spr_write_clear,
6776 0x60000000);
6777 spr_register(env, SPR_HID1, "HID1",
6778 SPR_NOACCESS, SPR_NOACCESS,
6779 &spr_read_generic, &spr_write_generic,
6780 0x00000000);
6781 spr_register(env, SPR_970_HID5, "HID5",
6782 SPR_NOACCESS, SPR_NOACCESS,
6783 &spr_read_generic, &spr_write_generic,
6784 POWERPC970_HID5_INIT);
6785 }
6787 static void register_970_hior_sprs(CPUPPCState *env)
6788 {
6789 spr_register(env, SPR_HIOR, "SPR_HIOR",
6790 SPR_NOACCESS, SPR_NOACCESS,
6791 &spr_read_hior, &spr_write_hior,
6792 0x00000000);
6793 }
6795 static void register_book3s_ctrl_sprs(CPUPPCState *env)
6796 {
6797 spr_register(env, SPR_CTRL, "SPR_CTRL",
6798 SPR_NOACCESS, SPR_NOACCESS,
6799 SPR_NOACCESS, &spr_write_generic,
6800 0x00000000);
6801 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6802 &spr_read_ureg, SPR_NOACCESS,
6803 &spr_read_ureg, SPR_NOACCESS,
6804 0x00000000);
6805 }
6807 static void register_book3s_altivec_sprs(CPUPPCState *env)
6808 {
6809 if (!(env->insns_flags & PPC_ALTIVEC)) {
6810 return;
6811 }
6813 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
6814 &spr_read_generic, &spr_write_generic,
6815 &spr_read_generic, &spr_write_generic,
6816 KVM_REG_PPC_VRSAVE, 0x00000000);
6818 }
6820 static void register_book3s_dbg_sprs(CPUPPCState *env)
6821 {
6822 /*
6823 * TODO: different specs define different scopes for these,
6824 * will have to address this:
6825 * 970: super/write and super/read
6826 * powerisa 2.03..2.04: hypv/write and super/read.
6827 * powerisa 2.05 and newer: hypv/write and hypv/read.
6828 */
6829 spr_register_kvm(env, SPR_DABR, "DABR",
6830 SPR_NOACCESS, SPR_NOACCESS,
6831 &spr_read_generic, &spr_write_generic,
6832 KVM_REG_PPC_DABR, 0x00000000);
6833 spr_register_kvm(env, SPR_DABRX, "DABRX",
6834 SPR_NOACCESS, SPR_NOACCESS,
6835 &spr_read_generic, &spr_write_generic,
6836 KVM_REG_PPC_DABRX, 0x00000000);
6837 }
6839 static void register_book3s_207_dbg_sprs(CPUPPCState *env)
6840 {
6841 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
6842 SPR_NOACCESS, SPR_NOACCESS,
6843 SPR_NOACCESS, SPR_NOACCESS,
6844 &spr_read_generic, &spr_write_generic,
6845 KVM_REG_PPC_DAWR, 0x00000000);
6846 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
6847 SPR_NOACCESS, SPR_NOACCESS,
6848 SPR_NOACCESS, SPR_NOACCESS,
6849 &spr_read_generic, &spr_write_generic,
6850 KVM_REG_PPC_DAWRX, 0x00000000);
6851 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
6852 SPR_NOACCESS, SPR_NOACCESS,
6853 SPR_NOACCESS, SPR_NOACCESS,
6854 &spr_read_generic, &spr_write_generic,
6855 KVM_REG_PPC_CIABR, 0x00000000);
6856 }
6858 static void register_970_dbg_sprs(CPUPPCState *env)
6859 {
6860 /* Breakpoints */
6861 spr_register(env, SPR_IABR, "IABR",
6862 SPR_NOACCESS, SPR_NOACCESS,
6863 &spr_read_generic, &spr_write_generic,
6864 0x00000000);
6865 }
6867 static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
6868 {
6869 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
6870 SPR_NOACCESS, SPR_NOACCESS,
6871 &spr_read_generic, &spr_write_generic,
6872 KVM_REG_PPC_MMCR0, 0x00000000);
6873 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
6874 SPR_NOACCESS, SPR_NOACCESS,
6875 &spr_read_generic, &spr_write_generic,
6876 KVM_REG_PPC_MMCR1, 0x00000000);
6877 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
6878 SPR_NOACCESS, SPR_NOACCESS,
6879 &spr_read_generic, &spr_write_generic,
6880 KVM_REG_PPC_MMCRA, 0x00000000);
6881 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
6882 SPR_NOACCESS, SPR_NOACCESS,
6883 &spr_read_generic, &spr_write_generic,
6884 KVM_REG_PPC_PMC1, 0x00000000);
6885 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
6886 SPR_NOACCESS, SPR_NOACCESS,
6887 &spr_read_generic, &spr_write_generic,
6888 KVM_REG_PPC_PMC2, 0x00000000);
6889 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
6890 SPR_NOACCESS, SPR_NOACCESS,
6891 &spr_read_generic, &spr_write_generic,
6892 KVM_REG_PPC_PMC3, 0x00000000);
6893 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
6894 SPR_NOACCESS, SPR_NOACCESS,
6895 &spr_read_generic, &spr_write_generic,
6896 KVM_REG_PPC_PMC4, 0x00000000);
6897 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
6898 SPR_NOACCESS, SPR_NOACCESS,
6899 &spr_read_generic, &spr_write_generic,
6900 KVM_REG_PPC_PMC5, 0x00000000);
6901 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
6902 SPR_NOACCESS, SPR_NOACCESS,
6903 &spr_read_generic, &spr_write_generic,
6904 KVM_REG_PPC_PMC6, 0x00000000);
6905 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
6906 SPR_NOACCESS, SPR_NOACCESS,
6907 &spr_read_generic, &spr_write_generic,
6908 KVM_REG_PPC_SIAR, 0x00000000);
6909 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
6910 SPR_NOACCESS, SPR_NOACCESS,
6911 &spr_read_generic, &spr_write_generic,
6912 KVM_REG_PPC_SDAR, 0x00000000);
6913 }
6915 static void register_book3s_pmu_user_sprs(CPUPPCState *env)
6916 {
6917 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
6918 &spr_read_ureg, SPR_NOACCESS,
6919 &spr_read_ureg, &spr_write_ureg,
6920 0x00000000);
6921 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
6922 &spr_read_ureg, SPR_NOACCESS,
6923 &spr_read_ureg, &spr_write_ureg,
6924 0x00000000);
6925 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
6926 &spr_read_ureg, SPR_NOACCESS,
6927 &spr_read_ureg, &spr_write_ureg,
6928 0x00000000);
6929 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
6930 &spr_read_ureg, SPR_NOACCESS,
6931 &spr_read_ureg, &spr_write_ureg,
6932 0x00000000);
6933 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
6934 &spr_read_ureg, SPR_NOACCESS,
6935 &spr_read_ureg, &spr_write_ureg,
6936 0x00000000);
6937 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
6938 &spr_read_ureg, SPR_NOACCESS,
6939 &spr_read_ureg, &spr_write_ureg,
6940 0x00000000);
6941 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
6942 &spr_read_ureg, SPR_NOACCESS,
6943 &spr_read_ureg, &spr_write_ureg,
6944 0x00000000);
6945 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
6946 &spr_read_ureg, SPR_NOACCESS,
6947 &spr_read_ureg, &spr_write_ureg,
6948 0x00000000);
6949 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
6950 &spr_read_ureg, SPR_NOACCESS,
6951 &spr_read_ureg, &spr_write_ureg,
6952 0x00000000);
6953 spr_register(env, SPR_POWER_USIAR, "USIAR",
6954 &spr_read_ureg, SPR_NOACCESS,
6955 &spr_read_ureg, &spr_write_ureg,
6956 0x00000000);
6957 spr_register(env, SPR_POWER_USDAR, "USDAR",
6958 &spr_read_ureg, SPR_NOACCESS,
6959 &spr_read_ureg, &spr_write_ureg,
6960 0x00000000);
6961 }
6963 static void register_970_pmu_sup_sprs(CPUPPCState *env)
6964 {
6965 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
6966 SPR_NOACCESS, SPR_NOACCESS,
6967 &spr_read_generic, &spr_write_generic,
6968 KVM_REG_PPC_PMC7, 0x00000000);
6969 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
6970 SPR_NOACCESS, SPR_NOACCESS,
6971 &spr_read_generic, &spr_write_generic,
6972 KVM_REG_PPC_PMC8, 0x00000000);
6973 }
6975 static void register_970_pmu_user_sprs(CPUPPCState *env)
6976 {
6977 spr_register(env, SPR_970_UPMC7, "UPMC7",
6978 &spr_read_ureg, SPR_NOACCESS,
6979 &spr_read_ureg, &spr_write_ureg,
6980 0x00000000);
6981 spr_register(env, SPR_970_UPMC8, "UPMC8",
6982 &spr_read_ureg, SPR_NOACCESS,
6983 &spr_read_ureg, &spr_write_ureg,
6984 0x00000000);
6985 }
6987 static void register_power8_pmu_sup_sprs(CPUPPCState *env)
6988 {
6989 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
6990 SPR_NOACCESS, SPR_NOACCESS,
6991 &spr_read_generic, &spr_write_generic,
6992 KVM_REG_PPC_MMCR2, 0x00000000);
6993 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
6994 SPR_NOACCESS, SPR_NOACCESS,
6995 &spr_read_generic, &spr_write_generic,
6996 KVM_REG_PPC_MMCRS, 0x00000000);
6997 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
6998 SPR_NOACCESS, SPR_NOACCESS,
6999 &spr_read_generic, &spr_write_generic,
7000 KVM_REG_PPC_SIER, 0x00000000);
7001 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
7002 SPR_NOACCESS, SPR_NOACCESS,
7003 &spr_read_generic, &spr_write_generic,
7004 KVM_REG_PPC_SPMC1, 0x00000000);
7005 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
7006 SPR_NOACCESS, SPR_NOACCESS,
7007 &spr_read_generic, &spr_write_generic,
7008 KVM_REG_PPC_SPMC2, 0x00000000);
7009 spr_register_kvm(env, SPR_TACR, "TACR",
7010 SPR_NOACCESS, SPR_NOACCESS,
7011 &spr_read_generic, &spr_write_generic,
7012 KVM_REG_PPC_TACR, 0x00000000);
7013 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
7014 SPR_NOACCESS, SPR_NOACCESS,
7015 &spr_read_generic, &spr_write_generic,
7016 KVM_REG_PPC_TCSCR, 0x00000000);
7017 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
7018 SPR_NOACCESS, SPR_NOACCESS,
7019 &spr_read_generic, &spr_write_generic,
7020 KVM_REG_PPC_CSIGR, 0x00000000);
7021 }
7023 static void register_power8_pmu_user_sprs(CPUPPCState *env)
7024 {
7025 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
7026 &spr_read_ureg, SPR_NOACCESS,
7027 &spr_read_ureg, &spr_write_ureg,
7028 0x00000000);
7029 spr_register(env, SPR_POWER_USIER, "USIER",
7030 &spr_read_generic, SPR_NOACCESS,
7031 &spr_read_generic, &spr_write_generic,
7032 0x00000000);
7033 }
7035 static void register_power5p_ear_sprs(CPUPPCState *env)
7036 {
7037 /* External access control */
7038 spr_register(env, SPR_EAR, "EAR",
7039 SPR_NOACCESS, SPR_NOACCESS,
7040 &spr_read_generic, &spr_write_generic,
7041 0x00000000);
7042 }
7044 static void register_power5p_tb_sprs(CPUPPCState *env)
7045 {
7046 /* TBU40 (High 40 bits of the Timebase register */
7047 spr_register_hv(env, SPR_TBU40, "TBU40",
7048 SPR_NOACCESS, SPR_NOACCESS,
7049 SPR_NOACCESS, SPR_NOACCESS,
7050 SPR_NOACCESS, &spr_write_tbu40,
7051 0x00000000);
7052 }
7054 static void register_970_lpar_sprs(CPUPPCState *env)
7055 {
7056 #if !defined(CONFIG_USER_ONLY)
7057 /*
7058 * PPC970: HID4 covers things later controlled by the LPCR and
7059 * RMOR in later CPUs, but with a different encoding. We only
7060 * support the 970 in "Apple mode" which has all hypervisor
7061 * facilities disabled by strapping, so we can basically just
7062 * ignore it
7063 */
7064 spr_register(env, SPR_970_HID4, "HID4",
7065 SPR_NOACCESS, SPR_NOACCESS,
7066 &spr_read_generic, &spr_write_generic,
7067 0x00000000);
7068 #endif
7069 }
7071 static void register_power5p_lpar_sprs(CPUPPCState *env)
7072 {
7073 #if !defined(CONFIG_USER_ONLY)
7074 /* Logical partitionning */
7075 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
7076 SPR_NOACCESS, SPR_NOACCESS,
7077 SPR_NOACCESS, SPR_NOACCESS,
7078 &spr_read_generic, &spr_write_lpcr,
7079 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
7080 spr_register_hv(env, SPR_HDEC, "HDEC",
7081 SPR_NOACCESS, SPR_NOACCESS,
7082 SPR_NOACCESS, SPR_NOACCESS,
7083 &spr_read_hdecr, &spr_write_hdecr, 0);
7084 #endif
7085 }
7087 static void register_book3s_ids_sprs(CPUPPCState *env)
7088 {
7089 /* FIXME: Will need to deal with thread vs core only SPRs */
7091 /* Processor identification */
7092 spr_register_hv(env, SPR_PIR, "PIR",
7093 SPR_NOACCESS, SPR_NOACCESS,
7094 &spr_read_generic, SPR_NOACCESS,
7095 &spr_read_generic, NULL,
7096 0x00000000);
7097 spr_register_hv(env, SPR_HID0, "HID0",
7098 SPR_NOACCESS, SPR_NOACCESS,
7099 SPR_NOACCESS, SPR_NOACCESS,
7100 &spr_read_generic, &spr_write_generic,
7101 0x00000000);
7102 spr_register_hv(env, SPR_TSCR, "TSCR",
7103 SPR_NOACCESS, SPR_NOACCESS,
7104 SPR_NOACCESS, SPR_NOACCESS,
7105 &spr_read_generic, &spr_write_generic,
7106 0x00000000);
7107 spr_register_hv(env, SPR_HMER, "HMER",
7108 SPR_NOACCESS, SPR_NOACCESS,
7109 SPR_NOACCESS, SPR_NOACCESS,
7110 &spr_read_generic, &spr_write_hmer,
7111 0x00000000);
7112 spr_register_hv(env, SPR_HMEER, "HMEER",
7113 SPR_NOACCESS, SPR_NOACCESS,
7114 SPR_NOACCESS, SPR_NOACCESS,
7115 &spr_read_generic, &spr_write_generic,
7116 0x00000000);
7117 spr_register_hv(env, SPR_TFMR, "TFMR",
7118 SPR_NOACCESS, SPR_NOACCESS,
7119 SPR_NOACCESS, SPR_NOACCESS,
7120 &spr_read_generic, &spr_write_generic,
7121 0x00000000);
7122 spr_register_hv(env, SPR_LPIDR, "LPIDR",
7123 SPR_NOACCESS, SPR_NOACCESS,
7124 SPR_NOACCESS, SPR_NOACCESS,
7125 &spr_read_generic, &spr_write_lpidr,
7126 0x00000000);
7127 spr_register_hv(env, SPR_HFSCR, "HFSCR",
7128 SPR_NOACCESS, SPR_NOACCESS,
7129 SPR_NOACCESS, SPR_NOACCESS,
7130 &spr_read_generic, &spr_write_generic,
7131 0x00000000);
7132 spr_register_hv(env, SPR_MMCRC, "MMCRC",
7133 SPR_NOACCESS, SPR_NOACCESS,
7134 SPR_NOACCESS, SPR_NOACCESS,
7135 &spr_read_generic, &spr_write_generic,
7136 0x00000000);
7137 spr_register_hv(env, SPR_MMCRH, "MMCRH",
7138 SPR_NOACCESS, SPR_NOACCESS,
7139 SPR_NOACCESS, SPR_NOACCESS,
7140 &spr_read_generic, &spr_write_generic,
7141 0x00000000);
7142 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
7143 SPR_NOACCESS, SPR_NOACCESS,
7144 SPR_NOACCESS, SPR_NOACCESS,
7145 &spr_read_generic, &spr_write_generic,
7146 0x00000000);
7147 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
7148 SPR_NOACCESS, SPR_NOACCESS,
7149 SPR_NOACCESS, SPR_NOACCESS,
7150 &spr_read_generic, &spr_write_generic,
7151 0x00000000);
7152 spr_register_hv(env, SPR_HSRR0, "HSRR0",
7153 SPR_NOACCESS, SPR_NOACCESS,
7154 SPR_NOACCESS, SPR_NOACCESS,
7155 &spr_read_generic, &spr_write_generic,
7156 0x00000000);
7157 spr_register_hv(env, SPR_HSRR1, "HSRR1",
7158 SPR_NOACCESS, SPR_NOACCESS,
7159 SPR_NOACCESS, SPR_NOACCESS,
7160 &spr_read_generic, &spr_write_generic,
7161 0x00000000);
7162 spr_register_hv(env, SPR_HDAR, "HDAR",
7163 SPR_NOACCESS, SPR_NOACCESS,
7164 SPR_NOACCESS, SPR_NOACCESS,
7165 &spr_read_generic, &spr_write_generic,
7166 0x00000000);
7167 spr_register_hv(env, SPR_HDSISR, "HDSISR",
7168 SPR_NOACCESS, SPR_NOACCESS,
7169 SPR_NOACCESS, SPR_NOACCESS,
7170 &spr_read_generic, &spr_write_generic,
7171 0x00000000);
7172 spr_register_hv(env, SPR_HRMOR, "HRMOR",
7173 SPR_NOACCESS, SPR_NOACCESS,
7174 SPR_NOACCESS, SPR_NOACCESS,
7175 &spr_read_generic, &spr_write_generic,
7176 0x00000000);
7177 }
7179 static void register_rmor_sprs(CPUPPCState *env)
7180 {
7181 spr_register_hv(env, SPR_RMOR, "RMOR",
7182 SPR_NOACCESS, SPR_NOACCESS,
7183 SPR_NOACCESS, SPR_NOACCESS,
7184 &spr_read_generic, &spr_write_generic,
7185 0x00000000);
7186 }
7188 static void register_power8_ids_sprs(CPUPPCState *env)
7189 {
7190 /* Thread identification */
7191 spr_register(env, SPR_TIR, "TIR",
7192 SPR_NOACCESS, SPR_NOACCESS,
7193 &spr_read_generic, SPR_NOACCESS,
7194 0x00000000);
7195 }
7197 static void register_book3s_purr_sprs(CPUPPCState *env)
7198 {
7199 #if !defined(CONFIG_USER_ONLY)
7200 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7201 spr_register_kvm_hv(env, SPR_PURR, "PURR",
7202 &spr_read_purr, SPR_NOACCESS,
7203 &spr_read_purr, SPR_NOACCESS,
7204 &spr_read_purr, &spr_write_purr,
7205 KVM_REG_PPC_PURR, 0x00000000);
7206 spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
7207 &spr_read_purr, SPR_NOACCESS,
7208 &spr_read_purr, SPR_NOACCESS,
7209 &spr_read_purr, &spr_write_purr,
7210 KVM_REG_PPC_SPURR, 0x00000000);
7211 #endif
7212 }
7214 static void register_power6_dbg_sprs(CPUPPCState *env)
7215 {
7216 #if !defined(CONFIG_USER_ONLY)
7217 spr_register(env, SPR_CFAR, "SPR_CFAR",
7218 SPR_NOACCESS, SPR_NOACCESS,
7219 &spr_read_cfar, &spr_write_cfar,
7220 0x00000000);
7221 #endif
7222 }
7224 static void register_power5p_common_sprs(CPUPPCState *env)
7225 {
7226 spr_register_kvm(env, SPR_PPR, "PPR",
7227 &spr_read_generic, &spr_write_generic,
7228 &spr_read_generic, &spr_write_generic,
7229 KVM_REG_PPC_PPR, 0x00000000);
7230 }
7232 static void register_power6_common_sprs(CPUPPCState *env)
7233 {
7234 #if !defined(CONFIG_USER_ONLY)
7235 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
7236 SPR_NOACCESS, SPR_NOACCESS,
7237 &spr_read_generic, &spr_write_generic,
7238 KVM_REG_PPC_DSCR, 0x00000000);
7239 #endif
7240 /*
7241 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
7242 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
7243 */
7244 spr_register_hv(env, SPR_PCR, "PCR",
7245 SPR_NOACCESS, SPR_NOACCESS,
7246 SPR_NOACCESS, SPR_NOACCESS,
7247 &spr_read_generic, &spr_write_pcr,
7248 0x00000000);
7249 }
7251 static void register_power8_tce_address_control_sprs(CPUPPCState *env)
7252 {
7253 spr_register_kvm(env, SPR_TAR, "TAR",
7254 &spr_read_tar, &spr_write_tar,
7255 &spr_read_generic, &spr_write_generic,
7256 KVM_REG_PPC_TAR, 0x00000000);
7257 }
7259 static void register_power8_tm_sprs(CPUPPCState *env)
7260 {
7261 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
7262 &spr_read_tm, &spr_write_tm,
7263 &spr_read_tm, &spr_write_tm,
7264 KVM_REG_PPC_TFHAR, 0x00000000);
7265 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
7266 &spr_read_tm, &spr_write_tm,
7267 &spr_read_tm, &spr_write_tm,
7268 KVM_REG_PPC_TFIAR, 0x00000000);
7269 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
7270 &spr_read_tm, &spr_write_tm,
7271 &spr_read_tm, &spr_write_tm,
7272 KVM_REG_PPC_TEXASR, 0x00000000);
7273 spr_register(env, SPR_TEXASRU, "TEXASRU",
7274 &spr_read_tm_upper32, &spr_write_tm_upper32,
7275 &spr_read_tm_upper32, &spr_write_tm_upper32,
7276 0x00000000);
7277 }
7279 static void register_power8_ebb_sprs(CPUPPCState *env)
7280 {
7281 spr_register(env, SPR_BESCRS, "BESCRS",
7282 &spr_read_ebb, &spr_write_ebb,
7283 &spr_read_generic, &spr_write_generic,
7284 0x00000000);
7285 spr_register(env, SPR_BESCRSU, "BESCRSU",
7286 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
7287 &spr_read_prev_upper32, &spr_write_prev_upper32,
7288 0x00000000);
7289 spr_register(env, SPR_BESCRR, "BESCRR",
7290 &spr_read_ebb, &spr_write_ebb,
7291 &spr_read_generic, &spr_write_generic,
7292 0x00000000);
7293 spr_register(env, SPR_BESCRRU, "BESCRRU",
7294 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
7295 &spr_read_prev_upper32, &spr_write_prev_upper32,
7296 0x00000000);
7297 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
7298 &spr_read_ebb, &spr_write_ebb,
7299 &spr_read_generic, &spr_write_generic,
7300 KVM_REG_PPC_EBBHR, 0x00000000);
7301 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
7302 &spr_read_ebb, &spr_write_ebb,
7303 &spr_read_generic, &spr_write_generic,
7304 KVM_REG_PPC_EBBRR, 0x00000000);
7305 spr_register_kvm(env, SPR_BESCR, "BESCR",
7306 &spr_read_ebb, &spr_write_ebb,
7307 &spr_read_generic, &spr_write_generic,
7308 KVM_REG_PPC_BESCR, 0x00000000);
7309 }
7311 /* Virtual Time Base */
7312 static void register_vtb_sprs(CPUPPCState *env)
7313 {
7314 spr_register_kvm_hv(env, SPR_VTB, "VTB",
7315 SPR_NOACCESS, SPR_NOACCESS,
7316 &spr_read_vtb, SPR_NOACCESS,
7317 &spr_read_vtb, &spr_write_vtb,
7318 KVM_REG_PPC_VTB, 0x00000000);
7319 }
7321 static void register_power8_fscr_sprs(CPUPPCState *env)
7322 {
7323 #if defined(CONFIG_USER_ONLY)
7324 target_ulong initval = 1ULL << FSCR_TAR;
7325 #else
7326 target_ulong initval = 0;
7327 #endif
7328 spr_register_kvm(env, SPR_FSCR, "FSCR",
7329 SPR_NOACCESS, SPR_NOACCESS,
7330 &spr_read_generic, &spr_write_generic,
7331 KVM_REG_PPC_FSCR, initval);
7332 }
7334 static void register_power8_pspb_sprs(CPUPPCState *env)
7335 {
7336 spr_register_kvm(env, SPR_PSPB, "PSPB",
7337 SPR_NOACCESS, SPR_NOACCESS,
7338 &spr_read_generic, &spr_write_generic32,
7339 KVM_REG_PPC_PSPB, 0);
7340 }
7342 static void register_power8_dpdes_sprs(CPUPPCState *env)
7343 {
7344 #if !defined(CONFIG_USER_ONLY)
7345 /* Directed Privileged Door-bell Exception State, used for IPI */
7346 spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
7347 SPR_NOACCESS, SPR_NOACCESS,
7348 &spr_read_dpdes, SPR_NOACCESS,
7349 &spr_read_dpdes, &spr_write_dpdes,
7350 KVM_REG_PPC_DPDES, 0x00000000);
7351 #endif
7352 }
7354 static void register_power8_ic_sprs(CPUPPCState *env)
7355 {
7356 #if !defined(CONFIG_USER_ONLY)
7357 spr_register_hv(env, SPR_IC, "IC",
7358 SPR_NOACCESS, SPR_NOACCESS,
7359 &spr_read_generic, SPR_NOACCESS,
7360 &spr_read_generic, &spr_write_generic,
7361 0);
7362 #endif
7363 }
7365 static void register_power8_book4_sprs(CPUPPCState *env)
7366 {
7367 /* Add a number of P8 book4 registers */
7368 #if !defined(CONFIG_USER_ONLY)
7369 spr_register_kvm(env, SPR_ACOP, "ACOP",
7370 SPR_NOACCESS, SPR_NOACCESS,
7371 &spr_read_generic, &spr_write_generic,
7372 KVM_REG_PPC_ACOP, 0);
7373 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
7374 SPR_NOACCESS, SPR_NOACCESS,
7375 &spr_read_generic, &spr_write_pidr,
7376 KVM_REG_PPC_PID, 0);
7377 spr_register_kvm(env, SPR_WORT, "WORT",
7378 SPR_NOACCESS, SPR_NOACCESS,
7379 &spr_read_generic, &spr_write_generic,
7380 KVM_REG_PPC_WORT, 0);
7381 #endif
7382 }
7384 static void register_power7_book4_sprs(CPUPPCState *env)
7385 {
7386 /* Add a number of P7 book4 registers */
7387 #if !defined(CONFIG_USER_ONLY)
7388 spr_register_kvm(env, SPR_ACOP, "ACOP",
7389 SPR_NOACCESS, SPR_NOACCESS,
7390 &spr_read_generic, &spr_write_generic,
7391 KVM_REG_PPC_ACOP, 0);
7392 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
7393 SPR_NOACCESS, SPR_NOACCESS,
7394 &spr_read_generic, &spr_write_generic,
7395 KVM_REG_PPC_PID, 0);
7396 #endif
7397 }
7399 static void register_power8_rpr_sprs(CPUPPCState *env)
7400 {
7401 #if !defined(CONFIG_USER_ONLY)
7402 spr_register_hv(env, SPR_RPR, "RPR",
7403 SPR_NOACCESS, SPR_NOACCESS,
7404 SPR_NOACCESS, SPR_NOACCESS,
7405 &spr_read_generic, &spr_write_generic,
7406 0x00000103070F1F3F);
7407 #endif
7408 }
7410 static void register_power9_mmu_sprs(CPUPPCState *env)
7411 {
7412 #if !defined(CONFIG_USER_ONLY)
7413 /* Partition Table Control */
7414 spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
7415 SPR_NOACCESS, SPR_NOACCESS,
7416 SPR_NOACCESS, SPR_NOACCESS,
7417 &spr_read_generic, &spr_write_ptcr,
7418 KVM_REG_PPC_PTCR, 0x00000000);
7419 /* Address Segment Descriptor Register */
7420 spr_register_hv(env, SPR_ASDR, "ASDR",
7421 SPR_NOACCESS, SPR_NOACCESS,
7422 SPR_NOACCESS, SPR_NOACCESS,
7423 &spr_read_generic, &spr_write_generic,
7424 0x0000000000000000);
7425 #endif
7426 }
7428 static void init_proc_book3s_common(CPUPPCState *env)
7429 {
7430 register_ne_601_sprs(env);
7431 register_tbl(env);
7432 register_usprg3_sprs(env);
7433 register_book3s_altivec_sprs(env);
7434 register_book3s_pmu_sup_sprs(env);
7435 register_book3s_pmu_user_sprs(env);
7436 register_book3s_ctrl_sprs(env);
7437 /*
7438 * Can't find information on what this should be on reset. This
7439 * value is the one used by 74xx processors.
7440 */
7441 vscr_init(env, 0x00010000);
7442 }
7444 static void init_proc_970(CPUPPCState *env)
7445 {
7446 /* Common Registers */
7447 init_proc_book3s_common(env);
7448 register_sdr1_sprs(env);
7449 register_book3s_dbg_sprs(env);
7451 /* 970 Specific Registers */
7452 register_970_hid_sprs(env);
7453 register_970_hior_sprs(env);
7454 register_low_BATs(env);
7455 register_970_pmu_sup_sprs(env);
7456 register_970_pmu_user_sprs(env);
7457 register_970_lpar_sprs(env);
7458 register_970_dbg_sprs(env);
7460 /* env variables */
7461 env->dcache_line_size = 128;
7462 env->icache_line_size = 128;
7464 /* Allocate hardware IRQ controller */
7465 init_excp_970(env);
7466 ppc970_irq_init(env_archcpu(env));
7467 }
7469 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
7470 {
7471 DeviceClass *dc = DEVICE_CLASS(oc);
7472 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7474 dc->desc = "PowerPC 970";
7475 pcc->init_proc = init_proc_970;
7476 pcc->check_pow = check_pow_970;
7477 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7478 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7479 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7480 PPC_FLOAT_STFIWX |
7481 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7482 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7483 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7484 PPC_64B | PPC_ALTIVEC |
7485 PPC_SEGMENT_64B | PPC_SLBI;
7486 pcc->insns_flags2 = PPC2_FP_CVT_S64;
7487 pcc->msr_mask = (1ull << MSR_SF) |
7488 (1ull << MSR_VR) |
7489 (1ull << MSR_POW) |
7490 (1ull << MSR_EE) |
7491 (1ull << MSR_PR) |
7492 (1ull << MSR_FP) |
7493 (1ull << MSR_ME) |
7494 (1ull << MSR_FE0) |
7495 (1ull << MSR_SE) |
7496 (1ull << MSR_DE) |
7497 (1ull << MSR_FE1) |
7498 (1ull << MSR_IR) |
7499 (1ull << MSR_DR) |
7500 (1ull << MSR_PMM) |
7501 (1ull << MSR_RI);
7502 pcc->mmu_model = POWERPC_MMU_64B;
7503 #if defined(CONFIG_SOFTMMU)
7504 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7505 pcc->hash64_opts = &ppc_hash64_opts_basic;
7506 #endif
7507 pcc->excp_model = POWERPC_EXCP_970;
7508 pcc->bus_model = PPC_FLAGS_INPUT_970;
7509 pcc->bfd_mach = bfd_mach_ppc64;
7510 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7511 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7512 POWERPC_FLAG_BUS_CLK;
7513 pcc->l1_dcache_size = 0x8000;
7514 pcc->l1_icache_size = 0x10000;
7515 }
7517 static void init_proc_power5plus(CPUPPCState *env)
7518 {
7519 /* Common Registers */
7520 init_proc_book3s_common(env);
7521 register_sdr1_sprs(env);
7522 register_book3s_dbg_sprs(env);
7524 /* POWER5+ Specific Registers */
7525 register_970_hid_sprs(env);
7526 register_970_hior_sprs(env);
7527 register_low_BATs(env);
7528 register_970_pmu_sup_sprs(env);
7529 register_970_pmu_user_sprs(env);
7530 register_power5p_common_sprs(env);
7531 register_power5p_lpar_sprs(env);
7532 register_power5p_ear_sprs(env);
7533 register_power5p_tb_sprs(env);
7535 /* env variables */
7536 env->dcache_line_size = 128;
7537 env->icache_line_size = 128;
7539 /* Allocate hardware IRQ controller */
7540 init_excp_970(env);
7541 ppc970_irq_init(env_archcpu(env));
7542 }
7544 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
7545 {
7546 DeviceClass *dc = DEVICE_CLASS(oc);
7547 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7549 dc->fw_name = "PowerPC,POWER5";
7550 dc->desc = "POWER5+";
7551 pcc->init_proc = init_proc_power5plus;
7552 pcc->check_pow = check_pow_970;
7553 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7554 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7555 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7556 PPC_FLOAT_STFIWX |
7557 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7558 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7559 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7560 PPC_64B |
7561 PPC_SEGMENT_64B | PPC_SLBI;
7562 pcc->insns_flags2 = PPC2_FP_CVT_S64;
7563 pcc->msr_mask = (1ull << MSR_SF) |
7564 (1ull << MSR_VR) |
7565 (1ull << MSR_POW) |
7566 (1ull << MSR_EE) |
7567 (1ull << MSR_PR) |
7568 (1ull << MSR_FP) |
7569 (1ull << MSR_ME) |
7570 (1ull << MSR_FE0) |
7571 (1ull << MSR_SE) |
7572 (1ull << MSR_DE) |
7573 (1ull << MSR_FE1) |
7574 (1ull << MSR_IR) |
7575 (1ull << MSR_DR) |
7576 (1ull << MSR_PMM) |
7577 (1ull << MSR_RI);
7578 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
7579 LPCR_RMI | LPCR_HDICE;
7580 pcc->mmu_model = POWERPC_MMU_2_03;
7581 #if defined(CONFIG_SOFTMMU)
7582 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7583 pcc->hash64_opts = &ppc_hash64_opts_basic;
7584 pcc->lrg_decr_bits = 32;
7585 #endif
7586 pcc->excp_model = POWERPC_EXCP_970;
7587 pcc->bus_model = PPC_FLAGS_INPUT_970;
7588 pcc->bfd_mach = bfd_mach_ppc64;
7589 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7590 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7591 POWERPC_FLAG_BUS_CLK;
7592 pcc->l1_dcache_size = 0x8000;
7593 pcc->l1_icache_size = 0x10000;
7594 }
7596 static void init_proc_POWER7(CPUPPCState *env)
7597 {
7598 /* Common Registers */
7599 init_proc_book3s_common(env);
7600 register_sdr1_sprs(env);
7601 register_book3s_dbg_sprs(env);
7603 /* POWER7 Specific Registers */
7604 register_book3s_ids_sprs(env);
7605 register_rmor_sprs(env);
7606 register_amr_sprs(env);
7607 register_book3s_purr_sprs(env);
7608 register_power5p_common_sprs(env);
7609 register_power5p_lpar_sprs(env);
7610 register_power5p_ear_sprs(env);
7611 register_power5p_tb_sprs(env);
7612 register_power6_common_sprs(env);
7613 register_power6_dbg_sprs(env);
7614 register_power7_book4_sprs(env);
7616 /* env variables */
7617 env->dcache_line_size = 128;
7618 env->icache_line_size = 128;
7620 /* Allocate hardware IRQ controller */
7621 init_excp_POWER7(env);
7622 ppcPOWER7_irq_init(env_archcpu(env));
7623 }
7625 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
7626 {
7627 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
7628 return true;
7629 }
7630 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
7631 return true;
7632 }
7633 return false;
7634 }
7636 static bool cpu_has_work_POWER7(CPUState *cs)
7637 {
7638 PowerPCCPU *cpu = POWERPC_CPU(cs);
7639 CPUPPCState *env = &cpu->env;
7641 if (cs->halted) {
7642 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
7643 return false;
7644 }
7645 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
7646 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
7647 return true;
7648 }
7649 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
7650 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
7651 return true;
7652 }
7653 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
7654 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
7655 return true;
7656 }
7657 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
7658 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
7659 return true;
7660 }
7661 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7662 return true;
7663 }
7664 return false;
7665 } else {
7666 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7667 }
7668 }
7670 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
7671 {
7672 DeviceClass *dc = DEVICE_CLASS(oc);
7673 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7674 CPUClass *cc = CPU_CLASS(oc);
7676 dc->fw_name = "PowerPC,POWER7";
7677 dc->desc = "POWER7";
7678 pcc->pvr_match = ppc_pvr_match_power7;
7679 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
7680 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7681 pcc->init_proc = init_proc_POWER7;
7682 pcc->check_pow = check_pow_nocheck;
7683 cc->has_work = cpu_has_work_POWER7;
7684 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7685 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7686 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7687 PPC_FLOAT_FRSQRTES |
7688 PPC_FLOAT_STFIWX |
7689 PPC_FLOAT_EXT |
7690 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7691 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7692 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7693 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
7694 PPC_SEGMENT_64B | PPC_SLBI |
7695 PPC_POPCNTB | PPC_POPCNTWD |
7696 PPC_CILDST;
7697 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
7698 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7699 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7700 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
7701 PPC2_PM_ISA206;
7702 pcc->msr_mask = (1ull << MSR_SF) |
7703 (1ull << MSR_VR) |
7704 (1ull << MSR_VSX) |
7705 (1ull << MSR_EE) |
7706 (1ull << MSR_PR) |
7707 (1ull << MSR_FP) |
7708 (1ull << MSR_ME) |
7709 (1ull << MSR_FE0) |
7710 (1ull << MSR_SE) |
7711 (1ull << MSR_DE) |
7712 (1ull << MSR_FE1) |
7713 (1ull << MSR_IR) |
7714 (1ull << MSR_DR) |
7715 (1ull << MSR_PMM) |
7716 (1ull << MSR_RI) |
7717 (1ull << MSR_LE);
7718 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
7719 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
7720 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
7721 LPCR_MER | LPCR_TC |
7722 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
7723 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
7724 pcc->mmu_model = POWERPC_MMU_2_06;
7725 #if defined(CONFIG_SOFTMMU)
7726 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7727 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
7728 pcc->lrg_decr_bits = 32;
7729 #endif
7730 pcc->excp_model = POWERPC_EXCP_POWER7;
7731 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7732 pcc->bfd_mach = bfd_mach_ppc64;
7733 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7734 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7735 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7736 POWERPC_FLAG_VSX;
7737 pcc->l1_dcache_size = 0x8000;
7738 pcc->l1_icache_size = 0x8000;
7739 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
7740 }
7742 static void init_proc_POWER8(CPUPPCState *env)
7743 {
7744 /* Common Registers */
7745 init_proc_book3s_common(env);
7746 register_sdr1_sprs(env);
7747 register_book3s_207_dbg_sprs(env);
7749 /* POWER8 Specific Registers */
7750 register_book3s_ids_sprs(env);
7751 register_rmor_sprs(env);
7752 register_amr_sprs(env);
7753 register_iamr_sprs(env);
7754 register_book3s_purr_sprs(env);
7755 register_power5p_common_sprs(env);
7756 register_power5p_lpar_sprs(env);
7757 register_power5p_ear_sprs(env);
7758 register_power5p_tb_sprs(env);
7759 register_power6_common_sprs(env);
7760 register_power6_dbg_sprs(env);
7761 register_power8_tce_address_control_sprs(env);
7762 register_power8_ids_sprs(env);
7763 register_power8_ebb_sprs(env);
7764 register_power8_fscr_sprs(env);
7765 register_power8_pmu_sup_sprs(env);
7766 register_power8_pmu_user_sprs(env);
7767 register_power8_tm_sprs(env);
7768 register_power8_pspb_sprs(env);
7769 register_power8_dpdes_sprs(env);
7770 register_vtb_sprs(env);
7771 register_power8_ic_sprs(env);
7772 register_power8_book4_sprs(env);
7773 register_power8_rpr_sprs(env);
7775 /* env variables */
7776 env->dcache_line_size = 128;
7777 env->icache_line_size = 128;
7779 /* Allocate hardware IRQ controller */
7780 init_excp_POWER8(env);
7781 ppcPOWER7_irq_init(env_archcpu(env));
7782 }
7784 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
7785 {
7786 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
7787 return true;
7788 }
7789 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
7790 return true;
7791 }
7792 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
7793 return true;
7794 }
7795 return false;
7796 }
7798 static bool cpu_has_work_POWER8(CPUState *cs)
7799 {
7800 PowerPCCPU *cpu = POWERPC_CPU(cs);
7801 CPUPPCState *env = &cpu->env;
7803 if (cs->halted) {
7804 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
7805 return false;
7806 }
7807 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
7808 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
7809 return true;
7810 }
7811 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
7812 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
7813 return true;
7814 }
7815 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
7816 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
7817 return true;
7818 }
7819 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
7820 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
7821 return true;
7822 }
7823 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
7824 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
7825 return true;
7826 }
7827 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
7828 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
7829 return true;
7830 }
7831 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7832 return true;
7833 }
7834 return false;
7835 } else {
7836 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7837 }
7838 }
7840 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
7841 {
7842 DeviceClass *dc = DEVICE_CLASS(oc);
7843 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7844 CPUClass *cc = CPU_CLASS(oc);
7846 dc->fw_name = "PowerPC,POWER8";
7847 dc->desc = "POWER8";
7848 pcc->pvr_match = ppc_pvr_match_power8;
7849 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7850 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7851 pcc->init_proc = init_proc_POWER8;
7852 pcc->check_pow = check_pow_nocheck;
7853 cc->has_work = cpu_has_work_POWER8;
7854 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7855 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7856 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7857 PPC_FLOAT_FRSQRTES |
7858 PPC_FLOAT_STFIWX |
7859 PPC_FLOAT_EXT |
7860 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7861 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7862 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7863 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
7864 PPC_SEGMENT_64B | PPC_SLBI |
7865 PPC_POPCNTB | PPC_POPCNTWD |
7866 PPC_CILDST;
7867 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
7868 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7869 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7870 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
7871 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
7872 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
7873 PPC2_TM | PPC2_PM_ISA206;
7874 pcc->msr_mask = (1ull << MSR_SF) |
7875 (1ull << MSR_HV) |
7876 (1ull << MSR_TM) |
7877 (1ull << MSR_VR) |
7878 (1ull << MSR_VSX) |
7879 (1ull << MSR_EE) |
7880 (1ull << MSR_PR) |
7881 (1ull << MSR_FP) |
7882 (1ull << MSR_ME) |
7883 (1ull << MSR_FE0) |
7884 (1ull << MSR_SE) |
7885 (1ull << MSR_DE) |
7886 (1ull << MSR_FE1) |
7887 (1ull << MSR_IR) |
7888 (1ull << MSR_DR) |
7889 (1ull << MSR_PMM) |
7890 (1ull << MSR_RI) |
7891 (1ull << MSR_TS0) |
7892 (1ull << MSR_TS1) |
7893 (1ull << MSR_LE);
7894 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
7895 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
7896 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
7897 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
7898 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
7899 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
7900 LPCR_P8_PECE3 | LPCR_P8_PECE4;
7901 pcc->mmu_model = POWERPC_MMU_2_07;
7902 #if defined(CONFIG_SOFTMMU)
7903 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7904 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
7905 pcc->lrg_decr_bits = 32;
7906 pcc->n_host_threads = 8;
7907 #endif
7908 pcc->excp_model = POWERPC_EXCP_POWER8;
7909 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7910 pcc->bfd_mach = bfd_mach_ppc64;
7911 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7912 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7913 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7914 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
7915 pcc->l1_dcache_size = 0x8000;
7916 pcc->l1_icache_size = 0x8000;
7917 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
7918 }
7920 #ifdef CONFIG_SOFTMMU
7921 /*
7922 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
7923 * Encoded as array of int_32s in the form:
7924 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
7925 * x -> AP encoding
7926 * y -> radix mode supported page size (encoded as a shift)
7927 */
7928 static struct ppc_radix_page_info POWER9_radix_page_info = {
7929 .count = 4,
7930 .entries = {
7931 0x0000000c, /* 4K - enc: 0x0 */
7932 0xa0000010, /* 64K - enc: 0x5 */
7933 0x20000015, /* 2M - enc: 0x1 */
7934 0x4000001e /* 1G - enc: 0x2 */
7935 }
7936 };
7937 #endif /* CONFIG_SOFTMMU */
7939 static void init_proc_POWER9(CPUPPCState *env)
7940 {
7941 /* Common Registers */
7942 init_proc_book3s_common(env);
7943 register_book3s_207_dbg_sprs(env);
7945 /* POWER8 Specific Registers */
7946 register_book3s_ids_sprs(env);
7947 register_amr_sprs(env);
7948 register_iamr_sprs(env);
7949 register_book3s_purr_sprs(env);
7950 register_power5p_common_sprs(env);
7951 register_power5p_lpar_sprs(env);
7952 register_power5p_ear_sprs(env);
7953 register_power5p_tb_sprs(env);
7954 register_power6_common_sprs(env);
7955 register_power6_dbg_sprs(env);
7956 register_power8_tce_address_control_sprs(env);
7957 register_power8_ids_sprs(env);
7958 register_power8_ebb_sprs(env);
7959 register_power8_fscr_sprs(env);
7960 register_power8_pmu_sup_sprs(env);
7961 register_power8_pmu_user_sprs(env);
7962 register_power8_tm_sprs(env);
7963 register_power8_pspb_sprs(env);
7964 register_power8_dpdes_sprs(env);
7965 register_vtb_sprs(env);
7966 register_power8_ic_sprs(env);
7967 register_power8_book4_sprs(env);
7968 register_power8_rpr_sprs(env);
7969 register_power9_mmu_sprs(env);
7971 /* POWER9 Specific registers */
7972 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
7973 spr_read_generic, spr_write_generic,
7974 KVM_REG_PPC_TIDR, 0);
7976 /* FIXME: Filter fields properly based on privilege level */
7977 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
7978 spr_read_generic, spr_write_generic,
7979 KVM_REG_PPC_PSSCR, 0);
7981 /* env variables */
7982 env->dcache_line_size = 128;
7983 env->icache_line_size = 128;
7985 /* Allocate hardware IRQ controller */
7986 init_excp_POWER9(env);
7987 ppcPOWER9_irq_init(env_archcpu(env));
7988 }
7990 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
7991 {
7992 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
7993 return true;
7994 }
7995 return false;
7996 }
7998 static bool cpu_has_work_POWER9(CPUState *cs)
7999 {
8000 PowerPCCPU *cpu = POWERPC_CPU(cs);
8001 CPUPPCState *env = &cpu->env;
8003 if (cs->halted) {
8004 uint64_t psscr = env->spr[SPR_PSSCR];
8006 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8007 return false;
8008 }
8010 /* If EC is clear, just return true on any pending interrupt */
8011 if (!(psscr & PSSCR_EC)) {
8012 return true;
8013 }
8014 /* External Exception */
8015 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8016 (env->spr[SPR_LPCR] & LPCR_EEE)) {
8017 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
8018 if (heic == 0 || !msr_hv || msr_pr) {
8019 return true;
8020 }
8021 }
8022 /* Decrementer Exception */
8023 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8024 (env->spr[SPR_LPCR] & LPCR_DEE)) {
8025 return true;
8026 }
8027 /* Machine Check or Hypervisor Maintenance Exception */
8028 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
8029 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
8030 return true;
8031 }
8032 /* Privileged Doorbell Exception */
8033 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
8034 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
8035 return true;
8036 }
8037 /* Hypervisor Doorbell Exception */
8038 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
8039 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
8040 return true;
8041 }
8042 /* Hypervisor virtualization exception */
8043 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
8044 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
8045 return true;
8046 }
8047 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8048 return true;
8049 }
8050 return false;
8051 } else {
8052 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8053 }
8054 }
8056 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
8057 {
8058 DeviceClass *dc = DEVICE_CLASS(oc);
8059 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8060 CPUClass *cc = CPU_CLASS(oc);
8062 dc->fw_name = "PowerPC,POWER9";
8063 dc->desc = "POWER9";
8064 pcc->pvr_match = ppc_pvr_match_power9;
8065 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
8066 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
8067 PCR_COMPAT_2_05;
8068 pcc->init_proc = init_proc_POWER9;
8069 pcc->check_pow = check_pow_nocheck;
8070 cc->has_work = cpu_has_work_POWER9;
8071 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8072 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8073 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8074 PPC_FLOAT_FRSQRTES |
8075 PPC_FLOAT_STFIWX |
8076 PPC_FLOAT_EXT |
8077 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8078 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8079 PPC_MEM_TLBSYNC |
8080 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8081 PPC_SEGMENT_64B | PPC_SLBI |
8082 PPC_POPCNTB | PPC_POPCNTWD |
8083 PPC_CILDST;
8084 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8085 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8086 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8087 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8088 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8089 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8090 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
8091 pcc->msr_mask = (1ull << MSR_SF) |
8092 (1ull << MSR_HV) |
8093 (1ull << MSR_TM) |
8094 (1ull << MSR_VR) |
8095 (1ull << MSR_VSX) |
8096 (1ull << MSR_EE) |
8097 (1ull << MSR_PR) |
8098 (1ull << MSR_FP) |
8099 (1ull << MSR_ME) |
8100 (1ull << MSR_FE0) |
8101 (1ull << MSR_SE) |
8102 (1ull << MSR_DE) |
8103 (1ull << MSR_FE1) |
8104 (1ull << MSR_IR) |
8105 (1ull << MSR_DR) |
8106 (1ull << MSR_PMM) |
8107 (1ull << MSR_RI) |
8108 (1ull << MSR_LE);
8109 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
8110 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
8111 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
8112 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
8113 LPCR_DEE | LPCR_OEE))
8114 | LPCR_MER | LPCR_GTSE | LPCR_TC |
8115 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
8116 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
8117 pcc->mmu_model = POWERPC_MMU_3_00;
8118 #if defined(CONFIG_SOFTMMU)
8119 pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
8120 /* segment page size remain the same */
8121 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
8122 pcc->radix_page_info = &POWER9_radix_page_info;
8123 pcc->lrg_decr_bits = 56;
8124 pcc->n_host_threads = 4;
8125 #endif
8126 pcc->excp_model = POWERPC_EXCP_POWER9;
8127 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
8128 pcc->bfd_mach = bfd_mach_ppc64;
8129 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8130 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8131 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8132 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
8133 pcc->l1_dcache_size = 0x8000;
8134 pcc->l1_icache_size = 0x8000;
8135 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8136 }
8138 #ifdef CONFIG_SOFTMMU
8139 /*
8140 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
8141 * Encoded as array of int_32s in the form:
8142 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
8143 * x -> AP encoding
8144 * y -> radix mode supported page size (encoded as a shift)
8145 */
8146 static struct ppc_radix_page_info POWER10_radix_page_info = {
8147 .count = 4,
8148 .entries = {
8149 0x0000000c, /* 4K - enc: 0x0 */
8150 0xa0000010, /* 64K - enc: 0x5 */
8151 0x20000015, /* 2M - enc: 0x1 */
8152 0x4000001e /* 1G - enc: 0x2 */
8153 }
8154 };
8155 #endif /* CONFIG_SOFTMMU */
8157 static void init_proc_POWER10(CPUPPCState *env)
8158 {
8159 /* Common Registers */
8160 init_proc_book3s_common(env);
8161 register_book3s_207_dbg_sprs(env);
8163 /* POWER8 Specific Registers */
8164 register_book3s_ids_sprs(env);
8165 register_amr_sprs(env);
8166 register_iamr_sprs(env);
8167 register_book3s_purr_sprs(env);
8168 register_power5p_common_sprs(env);
8169 register_power5p_lpar_sprs(env);
8170 register_power5p_ear_sprs(env);
8171 register_power6_common_sprs(env);
8172 register_power6_dbg_sprs(env);
8173 register_power8_tce_address_control_sprs(env);
8174 register_power8_ids_sprs(env);
8175 register_power8_ebb_sprs(env);
8176 register_power8_fscr_sprs(env);
8177 register_power8_pmu_sup_sprs(env);
8178 register_power8_pmu_user_sprs(env);
8179 register_power8_tm_sprs(env);
8180 register_power8_pspb_sprs(env);
8181 register_vtb_sprs(env);
8182 register_power8_ic_sprs(env);
8183 register_power8_book4_sprs(env);
8184 register_power8_rpr_sprs(env);
8185 register_power9_mmu_sprs(env);
8187 /* FIXME: Filter fields properly based on privilege level */
8188 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
8189 spr_read_generic, spr_write_generic,
8190 KVM_REG_PPC_PSSCR, 0);
8192 /* env variables */
8193 env->dcache_line_size = 128;
8194 env->icache_line_size = 128;
8196 /* Allocate hardware IRQ controller */
8197 init_excp_POWER10(env);
8198 ppcPOWER9_irq_init(env_archcpu(env));
8199 }
8201 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
8202 {
8203 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) {
8204 return true;
8205 }
8206 return false;
8207 }
8209 static bool cpu_has_work_POWER10(CPUState *cs)
8210 {
8211 PowerPCCPU *cpu = POWERPC_CPU(cs);
8212 CPUPPCState *env = &cpu->env;
8214 if (cs->halted) {
8215 uint64_t psscr = env->spr[SPR_PSSCR];
8217 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8218 return false;
8219 }
8221 /* If EC is clear, just return true on any pending interrupt */
8222 if (!(psscr & PSSCR_EC)) {
8223 return true;
8224 }
8225 /* External Exception */
8226 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8227 (env->spr[SPR_LPCR] & LPCR_EEE)) {
8228 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
8229 if (heic == 0 || !msr_hv || msr_pr) {
8230 return true;
8231 }
8232 }
8233 /* Decrementer Exception */
8234 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8235 (env->spr[SPR_LPCR] & LPCR_DEE)) {
8236 return true;
8237 }
8238 /* Machine Check or Hypervisor Maintenance Exception */
8239 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
8240 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
8241 return true;
8242 }
8243 /* Privileged Doorbell Exception */
8244 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
8245 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
8246 return true;
8247 }
8248 /* Hypervisor Doorbell Exception */
8249 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
8250 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
8251 return true;
8252 }
8253 /* Hypervisor virtualization exception */
8254 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
8255 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
8256 return true;
8257 }
8258 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8259 return true;
8260 }
8261 return false;
8262 } else {
8263 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8264 }
8265 }
8267 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
8268 {
8269 DeviceClass *dc = DEVICE_CLASS(oc);
8270 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8271 CPUClass *cc = CPU_CLASS(oc);
8273 dc->fw_name = "PowerPC,POWER10";
8274 dc->desc = "POWER10";
8275 pcc->pvr_match = ppc_pvr_match_power10;
8276 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
8277 PCR_COMPAT_3_00;
8278 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
8279 PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8280 pcc->init_proc = init_proc_POWER10;
8281 pcc->check_pow = check_pow_nocheck;
8282 cc->has_work = cpu_has_work_POWER10;
8283 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8284 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8285 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8286 PPC_FLOAT_FRSQRTES |
8287 PPC_FLOAT_STFIWX |
8288 PPC_FLOAT_EXT |
8289 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8290 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8291 PPC_MEM_TLBSYNC |
8292 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8293 PPC_SEGMENT_64B | PPC_SLBI |
8294 PPC_POPCNTB | PPC_POPCNTWD |
8295 PPC_CILDST;
8296 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8297 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8298 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8299 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8300 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8301 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8302 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
8303 pcc->msr_mask = (1ull << MSR_SF) |
8304 (1ull << MSR_HV) |
8305 (1ull << MSR_TM) |
8306 (1ull << MSR_VR) |
8307 (1ull << MSR_VSX) |
8308 (1ull << MSR_EE) |
8309 (1ull << MSR_PR) |
8310 (1ull << MSR_FP) |
8311 (1ull << MSR_ME) |
8312 (1ull << MSR_FE0) |
8313 (1ull << MSR_SE) |
8314 (1ull << MSR_DE) |
8315 (1ull << MSR_FE1) |
8316 (1ull << MSR_IR) |
8317 (1ull << MSR_DR) |
8318 (1ull << MSR_PMM) |
8319 (1ull << MSR_RI) |
8320 (1ull << MSR_LE);
8321 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
8322 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
8323 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
8324 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
8325 LPCR_DEE | LPCR_OEE))
8326 | LPCR_MER | LPCR_GTSE | LPCR_TC |
8327 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
8328 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
8329 pcc->mmu_model = POWERPC_MMU_3_00;
8330 #if defined(CONFIG_SOFTMMU)
8331 pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
8332 /* segment page size remain the same */
8333 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
8334 pcc->radix_page_info = &POWER10_radix_page_info;
8335 pcc->lrg_decr_bits = 56;
8336 #endif
8337 pcc->excp_model = POWERPC_EXCP_POWER10;
8338 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
8339 pcc->bfd_mach = bfd_mach_ppc64;
8340 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8341 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8342 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8343 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
8344 pcc->l1_dcache_size = 0x8000;
8345 pcc->l1_icache_size = 0x8000;
8346 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8347 }
8349 #if !defined(CONFIG_USER_ONLY)
8350 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
8351 {
8352 CPUPPCState *env = &cpu->env;
8354 cpu->vhyp = vhyp;
8356 /*
8357 * With a virtual hypervisor mode we never allow the CPU to go
8358 * hypervisor mode itself
8359 */
8360 env->msr_mask &= ~MSR_HVB;
8361 }
8363 #endif /* !defined(CONFIG_USER_ONLY) */
8365 #endif /* defined(TARGET_PPC64) */
8367 /*****************************************************************************/
8368 /* Generic CPU instantiation routine */
8369 static void init_ppc_proc(PowerPCCPU *cpu)
8370 {
8371 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8372 CPUPPCState *env = &cpu->env;
8373 #if !defined(CONFIG_USER_ONLY)
8374 int i;
8376 env->irq_inputs = NULL;
8377 /* Set all exception vectors to an invalid address */
8378 for (i = 0; i < POWERPC_EXCP_NB; i++) {
8379 env->excp_vectors[i] = (target_ulong)(-1ULL);
8380 }
8381 env->ivor_mask = 0x00000000;
8382 env->ivpr_mask = 0x00000000;
8383 /* Default MMU definitions */
8384 env->nb_BATs = 0;
8385 env->nb_tlb = 0;
8386 env->nb_ways = 0;
8387 env->tlb_type = TLB_NONE;
8388 #endif
8389 /* Register SPR common to all PowerPC implementations */
8390 register_generic_sprs(env);
8391 spr_register(env, SPR_PVR, "PVR",
8392 /* Linux permits userspace to read PVR */
8393 #if defined(CONFIG_LINUX_USER)
8394 &spr_read_generic,
8395 #else
8396 SPR_NOACCESS,
8397 #endif
8398 SPR_NOACCESS,
8399 &spr_read_generic, SPR_NOACCESS,
8400 pcc->pvr);
8401 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8402 if (pcc->svr != POWERPC_SVR_NONE) {
8403 if (pcc->svr & POWERPC_SVR_E500) {
8404 spr_register(env, SPR_E500_SVR, "SVR",
8405 SPR_NOACCESS, SPR_NOACCESS,
8406 &spr_read_generic, SPR_NOACCESS,
8407 pcc->svr & ~POWERPC_SVR_E500);
8408 } else {
8409 spr_register(env, SPR_SVR, "SVR",
8410 SPR_NOACCESS, SPR_NOACCESS,
8411 &spr_read_generic, SPR_NOACCESS,
8412 pcc->svr);
8413 }
8414 }
8415 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8416 (*pcc->init_proc)(env);
8418 #if !defined(CONFIG_USER_ONLY)
8419 ppc_gdb_gen_spr_xml(cpu);
8420 #endif
8422 /* MSR bits & flags consistency checks */
8423 if (env->msr_mask & (1 << 25)) {
8424 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8425 case POWERPC_FLAG_SPE:
8426 case POWERPC_FLAG_VRE:
8427 break;
8428 default:
8429 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8430 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8431 exit(1);
8432 }
8433 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8434 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8435 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8436 exit(1);
8437 }
8438 if (env->msr_mask & (1 << 17)) {
8439 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8440 case POWERPC_FLAG_TGPR:
8441 case POWERPC_FLAG_CE:
8442 break;
8443 default:
8444 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8445 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8446 exit(1);
8447 }
8448 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8449 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8450 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8451 exit(1);
8452 }
8453 if (env->msr_mask & (1 << 10)) {
8454 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8455 POWERPC_FLAG_UBLE)) {
8456 case POWERPC_FLAG_SE:
8457 case POWERPC_FLAG_DWE:
8458 case POWERPC_FLAG_UBLE:
8459 break;
8460 default:
8461 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8462 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8463 "POWERPC_FLAG_UBLE\n");
8464 exit(1);
8465 }
8466 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8467 POWERPC_FLAG_UBLE)) {
8468 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8469 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8470 "POWERPC_FLAG_UBLE\n");
8471 exit(1);
8472 }
8473 if (env->msr_mask & (1 << 9)) {
8474 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8475 case POWERPC_FLAG_BE:
8476 case POWERPC_FLAG_DE:
8477 break;
8478 default:
8479 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8480 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8481 exit(1);
8482 }
8483 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8484 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8485 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8486 exit(1);
8487 }
8488 if (env->msr_mask & (1 << 2)) {
8489 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8490 case POWERPC_FLAG_PX:
8491 case POWERPC_FLAG_PMM:
8492 break;
8493 default:
8494 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8495 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8496 exit(1);
8497 }
8498 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8499 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8500 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8501 exit(1);
8502 }
8503 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8504 fprintf(stderr, "PowerPC flags inconsistency\n"
8505 "Should define the time-base and decrementer clock source\n");
8506 exit(1);
8507 }
8508 /* Allocate TLBs buffer when needed */
8509 #if !defined(CONFIG_USER_ONLY)
8510 if (env->nb_tlb != 0) {
8511 int nb_tlb = env->nb_tlb;
8512 if (env->id_tlbs != 0) {
8513 nb_tlb *= 2;
8514 }
8515 switch (env->tlb_type) {
8516 case TLB_6XX:
8517 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
8518 break;
8519 case TLB_EMB:
8520 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
8521 break;
8522 case TLB_MAS:
8523 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
8524 break;
8525 }
8526 /* Pre-compute some useful values */
8527 env->tlb_per_way = env->nb_tlb / env->nb_ways;
8528 }
8529 if (env->irq_inputs == NULL) {
8530 warn_report("no internal IRQ controller registered."
8531 " Attempt QEMU to crash very soon !");
8532 }
8533 #endif
8534 if (env->check_pow == NULL) {
8535 warn_report("no power management check handler registered."
8536 " Attempt QEMU to crash very soon !");
8537 }
8538 }
8540 #if defined(PPC_DUMP_CPU)
8541 static void dump_ppc_sprs(CPUPPCState *env)
8542 {
8543 ppc_spr_t *spr;
8544 #if !defined(CONFIG_USER_ONLY)
8545 uint32_t sr, sw;
8546 #endif
8547 uint32_t ur, uw;
8548 int i, j, n;
8550 printf("Special purpose registers:\n");
8551 for (i = 0; i < 32; i++) {
8552 for (j = 0; j < 32; j++) {
8553 n = (i << 5) | j;
8554 spr = &env->spr_cb[n];
8555 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
8556 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
8557 #if !defined(CONFIG_USER_ONLY)
8558 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
8559 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
8560 if (sw || sr || uw || ur) {
8561 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
8562 (i << 5) | j, (i << 5) | j, spr->name,
8563 sw ? 'w' : '-', sr ? 'r' : '-',
8564 uw ? 'w' : '-', ur ? 'r' : '-');
8565 }
8566 #else
8567 if (uw || ur) {
8568 printf("SPR: %4d (%03x) %-8s u%c%c\n",
8569 (i << 5) | j, (i << 5) | j, spr->name,
8570 uw ? 'w' : '-', ur ? 'r' : '-');
8571 }
8572 #endif
8573 }
8574 }
8575 fflush(stdout);
8576 fflush(stderr);
8577 }
8578 #endif
8580 static void ppc_cpu_realize(DeviceState *dev, Error **errp)
8581 {
8582 CPUState *cs = CPU(dev);
8583 PowerPCCPU *cpu = POWERPC_CPU(dev);
8584 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8585 Error *local_err = NULL;
8587 cpu_exec_realizefn(cs, &local_err);
8588 if (local_err != NULL) {
8589 error_propagate(errp, local_err);
8590 return;
8591 }
8592 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
8593 cpu->vcpu_id = cs->cpu_index;
8594 }
8596 if (tcg_enabled()) {
8597 if (ppc_fixup_cpu(cpu) != 0) {
8598 error_setg(errp, "Unable to emulate selected CPU with TCG");
8599 goto unrealize;
8600 }
8601 }
8603 create_ppc_opcodes(cpu, &local_err);
8604 if (local_err != NULL) {
8605 error_propagate(errp, local_err);
8606 goto unrealize;
8607 }
8608 init_ppc_proc(cpu);
8610 ppc_gdb_init(cs, pcc);
8611 qemu_init_vcpu(cs);
8613 pcc->parent_realize(dev, errp);
8615 #if defined(PPC_DUMP_CPU)
8616 {
8617 CPUPPCState *env = &cpu->env;
8618 const char *mmu_model, *excp_model, *bus_model;
8619 switch (env->mmu_model) {
8620 case POWERPC_MMU_32B:
8621 mmu_model = "PowerPC 32";
8622 break;
8623 case POWERPC_MMU_SOFT_6xx:
8624 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
8625 break;
8626 case POWERPC_MMU_SOFT_74xx:
8627 mmu_model = "PowerPC 74xx with software driven TLBs";
8628 break;
8629 case POWERPC_MMU_SOFT_4xx:
8630 mmu_model = "PowerPC 4xx with software driven TLBs";
8631 break;
8632 case POWERPC_MMU_SOFT_4xx_Z:
8633 mmu_model = "PowerPC 4xx with software driven TLBs "
8634 "and zones protections";
8635 break;
8636 case POWERPC_MMU_REAL:
8637 mmu_model = "PowerPC real mode only";
8638 break;
8639 case POWERPC_MMU_MPC8xx:
8640 mmu_model = "PowerPC MPC8xx";
8641 break;
8642 case POWERPC_MMU_BOOKE:
8643 mmu_model = "PowerPC BookE";
8644 break;
8645 case POWERPC_MMU_BOOKE206:
8646 mmu_model = "PowerPC BookE 2.06";
8647 break;
8648 case POWERPC_MMU_601:
8649 mmu_model = "PowerPC 601";
8650 break;
8651 #if defined(TARGET_PPC64)
8652 case POWERPC_MMU_64B:
8653 mmu_model = "PowerPC 64";
8654 break;
8655 #endif
8656 default:
8657 mmu_model = "Unknown or invalid";
8658 break;
8659 }
8660 switch (env->excp_model) {
8661 case POWERPC_EXCP_STD:
8662 excp_model = "PowerPC";
8663 break;
8664 case POWERPC_EXCP_40x:
8665 excp_model = "PowerPC 40x";
8666 break;
8667 case POWERPC_EXCP_601:
8668 excp_model = "PowerPC 601";
8669 break;
8670 case POWERPC_EXCP_602:
8671 excp_model = "PowerPC 602";
8672 break;
8673 case POWERPC_EXCP_603:
8674 excp_model = "PowerPC 603";
8675 break;
8676 case POWERPC_EXCP_603E:
8677 excp_model = "PowerPC 603e";
8678 break;
8679 case POWERPC_EXCP_604:
8680 excp_model = "PowerPC 604";
8681 break;
8682 case POWERPC_EXCP_7x0:
8683 excp_model = "PowerPC 740/750";
8684 break;
8685 case POWERPC_EXCP_7x5:
8686 excp_model = "PowerPC 745/755";
8687 break;
8688 case POWERPC_EXCP_74xx:
8689 excp_model = "PowerPC 74xx";
8690 break;
8691 case POWERPC_EXCP_BOOKE:
8692 excp_model = "PowerPC BookE";
8693 break;
8694 #if defined(TARGET_PPC64)
8695 case POWERPC_EXCP_970:
8696 excp_model = "PowerPC 970";
8697 break;
8698 #endif
8699 default:
8700 excp_model = "Unknown or invalid";
8701 break;
8702 }
8703 switch (env->bus_model) {
8704 case PPC_FLAGS_INPUT_6xx:
8705 bus_model = "PowerPC 6xx";
8706 break;
8707 case PPC_FLAGS_INPUT_BookE:
8708 bus_model = "PowerPC BookE";
8709 break;
8710 case PPC_FLAGS_INPUT_405:
8711 bus_model = "PowerPC 405";
8712 break;
8713 case PPC_FLAGS_INPUT_401:
8714 bus_model = "PowerPC 401/403";
8715 break;
8716 case PPC_FLAGS_INPUT_RCPU:
8717 bus_model = "RCPU / MPC8xx";
8718 break;
8719 #if defined(TARGET_PPC64)
8720 case PPC_FLAGS_INPUT_970:
8721 bus_model = "PowerPC 970";
8722 break;
8723 #endif
8724 default:
8725 bus_model = "Unknown or invalid";
8726 break;
8727 }
8728 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
8729 " MMU model : %s\n",
8730 object_class_get_name(OBJECT_CLASS(pcc)),
8731 pcc->pvr, pcc->msr_mask, mmu_model);
8732 #if !defined(CONFIG_USER_ONLY)
8733 if (env->tlb.tlb6) {
8734 printf(" %d %s TLB in %d ways\n",
8735 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
8736 env->nb_ways);
8737 }
8738 #endif
8739 printf(" Exceptions model : %s\n"
8740 " Bus model : %s\n",
8741 excp_model, bus_model);
8742 printf(" MSR features :\n");
8743 if (env->flags & POWERPC_FLAG_SPE) {
8744 printf(" signal processing engine enable"
8745 "\n");
8746 } else if (env->flags & POWERPC_FLAG_VRE) {
8747 printf(" vector processor enable\n");
8748 }
8749 if (env->flags & POWERPC_FLAG_TGPR) {
8750 printf(" temporary GPRs\n");
8751 } else if (env->flags & POWERPC_FLAG_CE) {
8752 printf(" critical input enable\n");
8753 }
8754 if (env->flags & POWERPC_FLAG_SE) {
8755 printf(" single-step trace mode\n");
8756 } else if (env->flags & POWERPC_FLAG_DWE) {
8757 printf(" debug wait enable\n");
8758 } else if (env->flags & POWERPC_FLAG_UBLE) {
8759 printf(" user BTB lock enable\n");
8760 }
8761 if (env->flags & POWERPC_FLAG_BE) {
8762 printf(" branch-step trace mode\n");
8763 } else if (env->flags & POWERPC_FLAG_DE) {
8764 printf(" debug interrupt enable\n");
8765 }
8766 if (env->flags & POWERPC_FLAG_PX) {
8767 printf(" inclusive protection\n");
8768 } else if (env->flags & POWERPC_FLAG_PMM) {
8769 printf(" performance monitor mark\n");
8770 }
8771 if (env->flags == POWERPC_FLAG_NONE) {
8772 printf(" none\n");
8773 }
8774 printf(" Time-base/decrementer clock source: %s\n",
8775 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
8776 dump_ppc_insns(env);
8777 dump_ppc_sprs(env);
8778 fflush(stdout);
8779 }
8780 #endif
8781 return;
8783 unrealize:
8784 cpu_exec_unrealizefn(cs);
8785 }
8787 static void ppc_cpu_unrealize(DeviceState *dev)
8788 {
8789 PowerPCCPU *cpu = POWERPC_CPU(dev);
8790 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8792 pcc->parent_unrealize(dev);
8794 cpu_remove_sync(CPU(cpu));
8796 destroy_ppc_opcodes(cpu);
8797 }
8799 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
8800 {
8801 ObjectClass *oc = (ObjectClass *)a;
8802 uint32_t pvr = *(uint32_t *)b;
8803 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8805 /* -cpu host does a PVR lookup during construction */
8806 if (unlikely(strcmp(object_class_get_name(oc),
8807 TYPE_HOST_POWERPC_CPU) == 0)) {
8808 return -1;
8809 }
8811 return pcc->pvr == pvr ? 0 : -1;
8812 }
8814 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
8815 {
8816 GSList *list, *item;
8817 PowerPCCPUClass *pcc = NULL;
8819 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8820 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
8821 if (item != NULL) {
8822 pcc = POWERPC_CPU_CLASS(item->data);
8823 }
8824 g_slist_free(list);
8826 return pcc;
8827 }
8829 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
8830 {
8831 ObjectClass *oc = (ObjectClass *)a;
8832 uint32_t pvr = *(uint32_t *)b;
8833 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8835 /* -cpu host does a PVR lookup during construction */
8836 if (unlikely(strcmp(object_class_get_name(oc),
8837 TYPE_HOST_POWERPC_CPU) == 0)) {
8838 return -1;
8839 }
8841 if (pcc->pvr_match(pcc, pvr)) {
8842 return 0;
8843 }
8845 return -1;
8846 }
8848 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
8849 {
8850 GSList *list, *item;
8851 PowerPCCPUClass *pcc = NULL;
8853 list = object_class_get_list(TYPE_POWERPC_CPU, true);
8854 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
8855 if (item != NULL) {
8856 pcc = POWERPC_CPU_CLASS(item->data);
8857 }
8858 g_slist_free(list);
8860 return pcc;
8861 }
8863 static const char *ppc_cpu_lookup_alias(const char *alias)
8864 {
8865 int ai;
8867 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
8868 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
8869 return ppc_cpu_aliases[ai].model;
8870 }
8871 }
8873 return NULL;
8874 }
8876 static ObjectClass *ppc_cpu_class_by_name(const char *name)
8877 {
8878 char *cpu_model, *typename;
8879 ObjectClass *oc;
8880 const char *p;
8881 unsigned long pvr;
8883 /*
8884 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
8885 * 0x prefix if present)
8886 */
8887 if (!qemu_strtoul(name, &p, 16, &pvr)) {
8888 int len = p - name;
8889 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
8890 if ((len == 8) && (*p == '\0')) {
8891 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
8892 }
8893 }
8895 cpu_model = g_ascii_strdown(name, -1);
8896 p = ppc_cpu_lookup_alias(cpu_model);
8897 if (p) {
8898 g_free(cpu_model);
8899 cpu_model = g_strdup(p);
8900 }
8902 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
8903 oc = object_class_by_name(typename);
8904 g_free(typename);
8905 g_free(cpu_model);
8907 return oc;
8908 }
8910 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
8911 {
8912 ObjectClass *oc = OBJECT_CLASS(pcc);
8914 while (oc && !object_class_is_abstract(oc)) {
8915 oc = object_class_get_parent(oc);
8916 }
8917 assert(oc);
8919 return POWERPC_CPU_CLASS(oc);
8920 }
8922 /* Sort by PVR, ordering special case "host" last. */
8923 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
8924 {
8925 ObjectClass *oc_a = (ObjectClass *)a;
8926 ObjectClass *oc_b = (ObjectClass *)b;
8927 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
8928 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
8929 const char *name_a = object_class_get_name(oc_a);
8930 const char *name_b = object_class_get_name(oc_b);
8932 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
8933 return 1;
8934 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
8935 return -1;
8936 } else {
8937 /* Avoid an integer overflow during subtraction */
8938 if (pcc_a->pvr < pcc_b->pvr) {
8939 return -1;
8940 } else if (pcc_a->pvr > pcc_b->pvr) {
8941 return 1;
8942 } else {
8943 return 0;
8944 }
8945 }
8946 }
8948 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
8949 {
8950 ObjectClass *oc = data;
8951 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8952 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
8953 const char *typename = object_class_get_name(oc);
8954 char *name;
8955 int i;
8957 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
8958 return;
8959 }
8961 name = g_strndup(typename,
8962 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
8963 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
8964 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8965 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8966 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
8968 if (alias_oc != oc) {
8969 continue;
8970 }
8971 /*
8972 * If running with KVM, we might update the family alias later, so
8973 * avoid printing the wrong alias here and use "preferred" instead
8974 */
8975 if (strcmp(alias->alias, family->desc) == 0) {
8976 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
8977 alias->alias, family->desc);
8978 } else {
8979 qemu_printf("PowerPC %-16s (alias for %s)\n",
8980 alias->alias, name);
8981 }
8982 }
8983 g_free(name);
8984 }
8986 void ppc_cpu_list(void)
8987 {
8988 GSList *list;
8990 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8991 list = g_slist_sort(list, ppc_cpu_list_compare);
8992 g_slist_foreach(list, ppc_cpu_list_entry, NULL);
8993 g_slist_free(list);
8995 #ifdef CONFIG_KVM
8996 qemu_printf("\n");
8997 qemu_printf("PowerPC %-16s\n", "host");
8998 #endif
8999 }
9001 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
9002 {
9003 ObjectClass *oc = data;
9004 CpuDefinitionInfoList **first = user_data;
9005 const char *typename;
9006 CpuDefinitionInfo *info;
9008 typename = object_class_get_name(oc);
9009 info = g_malloc0(sizeof(*info));
9010 info->name = g_strndup(typename,
9011 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
9013 QAPI_LIST_PREPEND(*first, info);
9014 }
9016 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
9017 {
9018 CpuDefinitionInfoList *cpu_list = NULL;
9019 GSList *list;
9020 int i;
9022 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9023 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
9024 g_slist_free(list);
9026 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9027 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
9028 ObjectClass *oc;
9029 CpuDefinitionInfo *info;
9031 oc = ppc_cpu_class_by_name(alias->model);
9032 if (oc == NULL) {
9033 continue;
9034 }
9036 info = g_malloc0(sizeof(*info));
9037 info->name = g_strdup(alias->alias);
9038 info->q_typename = g_strdup(object_class_get_name(oc));
9040 QAPI_LIST_PREPEND(cpu_list, info);
9041 }
9043 return cpu_list;
9044 }
9046 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
9047 {
9048 PowerPCCPU *cpu = POWERPC_CPU(cs);
9050 cpu->env.nip = value;
9051 }
9053 static bool ppc_cpu_has_work(CPUState *cs)
9054 {
9055 PowerPCCPU *cpu = POWERPC_CPU(cs);
9056 CPUPPCState *env = &cpu->env;
9058 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
9059 }
9061 static void ppc_cpu_reset(DeviceState *dev)
9062 {
9063 CPUState *s = CPU(dev);
9064 PowerPCCPU *cpu = POWERPC_CPU(s);
9065 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9066 CPUPPCState *env = &cpu->env;
9067 target_ulong msr;
9068 int i;
9070 pcc->parent_reset(dev);
9072 msr = (target_ulong)0;
9073 msr |= (target_ulong)MSR_HVB;
9074 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
9075 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
9076 msr |= (target_ulong)1 << MSR_EP;
9077 #if defined(DO_SINGLE_STEP) && 0
9078 /* Single step trace mode */
9079 msr |= (target_ulong)1 << MSR_SE;
9080 msr |= (target_ulong)1 << MSR_BE;
9081 #endif
9082 #if defined(CONFIG_USER_ONLY)
9083 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
9084 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
9085 msr |= (target_ulong)1 << MSR_FE1;
9086 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
9087 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
9088 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
9089 msr |= (target_ulong)1 << MSR_PR;
9090 #if defined(TARGET_PPC64)
9091 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
9092 #endif
9093 #if !defined(TARGET_WORDS_BIGENDIAN)
9094 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
9095 if (!((env->msr_mask >> MSR_LE) & 1)) {
9096 fprintf(stderr, "Selected CPU does not support little-endian.\n");
9097 exit(1);
9098 }
9099 #endif
9100 #endif
9102 #if defined(TARGET_PPC64)
9103 if (mmu_is_64bit(env->mmu_model)) {
9104 msr |= (1ULL << MSR_SF);
9105 }
9106 #endif
9108 hreg_store_msr(env, msr, 1);
9110 #if !defined(CONFIG_USER_ONLY)
9111 env->nip = env->hreset_vector | env->excp_prefix;
9112 if (env->mmu_model != POWERPC_MMU_REAL) {
9113 ppc_tlb_invalidate_all(env);
9114 }
9115 #endif
9117 hreg_compute_hflags(env);
9118 env->reserve_addr = (target_ulong)-1ULL;
9119 /* Be sure no exception or interrupt is pending */
9120 env->pending_interrupts = 0;
9121 s->exception_index = POWERPC_EXCP_NONE;
9122 env->error_code = 0;
9123 ppc_irq_reset(cpu);
9125 /* tininess for underflow is detected before rounding */
9126 set_float_detect_tininess(float_tininess_before_rounding,
9127 &env->fp_status);
9129 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
9130 ppc_spr_t *spr = &env->spr_cb[i];
9132 if (!spr->name) {
9133 continue;
9134 }
9135 env->spr[i] = spr->default_value;
9136 }
9137 }
9139 #ifndef CONFIG_USER_ONLY
9141 static bool ppc_cpu_is_big_endian(CPUState *cs)
9142 {
9143 PowerPCCPU *cpu = POWERPC_CPU(cs);
9144 CPUPPCState *env = &cpu->env;
9146 cpu_synchronize_state(cs);
9148 return !msr_le;
9149 }
9151 #ifdef CONFIG_TCG
9152 static void ppc_cpu_exec_enter(CPUState *cs)
9153 {
9154 PowerPCCPU *cpu = POWERPC_CPU(cs);
9156 if (cpu->vhyp) {
9157 PPCVirtualHypervisorClass *vhc =
9158 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
9159 vhc->cpu_exec_enter(cpu->vhyp, cpu);
9160 }
9161 }
9163 static void ppc_cpu_exec_exit(CPUState *cs)
9164 {
9165 PowerPCCPU *cpu = POWERPC_CPU(cs);
9167 if (cpu->vhyp) {
9168 PPCVirtualHypervisorClass *vhc =
9169 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
9170 vhc->cpu_exec_exit(cpu->vhyp, cpu);
9171 }
9172 }
9173 #endif /* CONFIG_TCG */
9175 #endif /* !CONFIG_USER_ONLY */
9177 static void ppc_cpu_instance_init(Object *obj)
9178 {
9179 PowerPCCPU *cpu = POWERPC_CPU(obj);
9180 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9181 CPUPPCState *env = &cpu->env;
9183 cpu_set_cpustate_pointers(cpu);
9184 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
9186 env->msr_mask = pcc->msr_mask;
9187 env->mmu_model = pcc->mmu_model;
9188 env->excp_model = pcc->excp_model;
9189 env->bus_model = pcc->bus_model;
9190 env->insns_flags = pcc->insns_flags;
9191 env->insns_flags2 = pcc->insns_flags2;
9192 env->flags = pcc->flags;
9193 env->bfd_mach = pcc->bfd_mach;
9194 env->check_pow = pcc->check_pow;
9196 /*
9197 * Mark HV mode as supported if the CPU has an MSR_HV bit in the
9198 * msr_mask. The mask can later be cleared by PAPR mode but the hv
9199 * mode support will remain, thus enforcing that we cannot use
9200 * priv. instructions in guest in PAPR mode. For 970 we currently
9201 * simply don't set HV in msr_mask thus simulating an "Apple mode"
9202 * 970. If we ever want to support 970 HV mode, we'll have to add
9203 * a processor attribute of some sort.
9204 */
9205 #if !defined(CONFIG_USER_ONLY)
9206 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
9207 #endif
9209 ppc_hash64_init(cpu);
9210 }
9212 static void ppc_cpu_instance_finalize(Object *obj)
9213 {
9214 PowerPCCPU *cpu = POWERPC_CPU(obj);
9216 ppc_hash64_finalize(cpu);
9217 }
9219 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
9220 {
9221 return pcc->pvr == pvr;
9222 }
9224 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
9225 {
9226 PowerPCCPU *cpu = POWERPC_CPU(cs);
9227 CPUPPCState *env = &cpu->env;
9229 if ((env->hflags >> MSR_LE) & 1) {
9230 info->endian = BFD_ENDIAN_LITTLE;
9231 }
9232 info->mach = env->bfd_mach;
9233 if (!env->bfd_mach) {
9234 #ifdef TARGET_PPC64
9235 info->mach = bfd_mach_ppc64;
9236 #else
9237 info->mach = bfd_mach_ppc;
9238 #endif
9239 }
9240 info->disassembler_options = (char *)"any";
9241 info->print_insn = print_insn_ppc;
9243 info->cap_arch = CS_ARCH_PPC;
9244 #ifdef TARGET_PPC64
9245 info->cap_mode = CS_MODE_64;
9246 #endif
9247 }
9249 static Property ppc_cpu_properties[] = {
9250 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
9251 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
9252 false),
9253 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
9254 false),
9255 DEFINE_PROP_END_OF_LIST(),
9256 };
9258 #ifdef CONFIG_TCG
9259 #include "hw/core/tcg-cpu-ops.h"
9261 static struct TCGCPUOps ppc_tcg_ops = {
9262 .initialize = ppc_translate_init,
9263 .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
9264 .tlb_fill = ppc_cpu_tlb_fill,
9266 #ifndef CONFIG_USER_ONLY
9267 .do_interrupt = ppc_cpu_do_interrupt,
9268 .cpu_exec_enter = ppc_cpu_exec_enter,
9269 .cpu_exec_exit = ppc_cpu_exec_exit,
9270 .do_unaligned_access = ppc_cpu_do_unaligned_access,
9271 #endif /* !CONFIG_USER_ONLY */
9272 };
9273 #endif /* CONFIG_TCG */
9275 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
9276 {
9277 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9278 CPUClass *cc = CPU_CLASS(oc);
9279 DeviceClass *dc = DEVICE_CLASS(oc);
9281 device_class_set_parent_realize(dc, ppc_cpu_realize,
9282 &pcc->parent_realize);
9283 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
9284 &pcc->parent_unrealize);
9285 pcc->pvr_match = ppc_pvr_match_default;
9286 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
9287 device_class_set_props(dc, ppc_cpu_properties);
9289 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
9291 cc->class_by_name = ppc_cpu_class_by_name;
9292 cc->has_work = ppc_cpu_has_work;
9293 cc->dump_state = ppc_cpu_dump_state;
9294 cc->dump_statistics = ppc_cpu_dump_statistics;
9295 cc->set_pc = ppc_cpu_set_pc;
9296 cc->gdb_read_register = ppc_cpu_gdb_read_register;
9297 cc->gdb_write_register = ppc_cpu_gdb_write_register;
9298 #ifndef CONFIG_USER_ONLY
9299 cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
9300 cc->vmsd = &vmstate_ppc_cpu;
9301 #endif
9302 #if defined(CONFIG_SOFTMMU)
9303 cc->write_elf64_note = ppc64_cpu_write_elf64_note;
9304 cc->write_elf32_note = ppc32_cpu_write_elf32_note;
9305 #endif
9307 cc->gdb_num_core_regs = 71;
9308 #ifndef CONFIG_USER_ONLY
9309 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
9310 #endif
9311 #ifdef USE_APPLE_GDB
9312 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
9313 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
9314 cc->gdb_num_core_regs = 71 + 32;
9315 #endif
9317 cc->gdb_arch_name = ppc_gdb_arch_name;
9318 #if defined(TARGET_PPC64)
9319 cc->gdb_core_xml_file = "power64-core.xml";
9320 #else
9321 cc->gdb_core_xml_file = "power-core.xml";
9322 #endif
9323 #ifndef CONFIG_USER_ONLY
9324 cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
9325 #endif
9326 cc->disas_set_info = ppc_disas_set_info;
9328 dc->fw_name = "PowerPC,UNKNOWN";
9330 #ifdef CONFIG_TCG
9331 cc->tcg_ops = &ppc_tcg_ops;
9332 #endif /* CONFIG_TCG */
9333 }
9335 static const TypeInfo ppc_cpu_type_info = {
9336 .name = TYPE_POWERPC_CPU,
9337 .parent = TYPE_CPU,
9338 .instance_size = sizeof(PowerPCCPU),
9339 .instance_align = __alignof__(PowerPCCPU),
9340 .instance_init = ppc_cpu_instance_init,
9341 .instance_finalize = ppc_cpu_instance_finalize,
9342 .abstract = true,
9343 .class_size = sizeof(PowerPCCPUClass),
9344 .class_init = ppc_cpu_class_init,
9345 };
9347 #ifndef CONFIG_USER_ONLY
9348 static const TypeInfo ppc_vhyp_type_info = {
9349 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
9350 .parent = TYPE_INTERFACE,
9351 .class_size = sizeof(PPCVirtualHypervisorClass),
9352 };
9353 #endif
9355 static void ppc_cpu_register_types(void)
9356 {
9357 type_register_static(&ppc_cpu_type_info);
9358 #ifndef CONFIG_USER_ONLY
9359 type_register_static(&ppc_vhyp_type_info);
9360 #endif
9361 }
9363 type_init(ppc_cpu_register_types)