2 * ARM IoTKit system control element
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
13 * This is a model of the "system control element" which is part of the
14 * Arm IoTKit and documented in
15 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
16 * Specifically, it implements the "system control register" blocks.
19 #include "qemu/osdep.h"
20 #include "qemu/bitops.h"
23 #include "qapi/error.h"
24 #include "sysemu/sysemu.h"
25 #include "hw/sysbus.h"
26 #include "hw/registerfields.h"
27 #include "hw/misc/iotkit-sysctl.h"
28 #include "target/arm/arm-powerctl.h"
29 #include "target/arm/cpu.h"
31 REG32(SECDBGSTAT
, 0x0)
36 REG32(SYSCLK_DIV
, 0x14)
37 REG32(CLOCK_FORCE
, 0x18)
38 REG32(RESET_SYNDROME
, 0x100)
39 REG32(RESET_MASK
, 0x104)
41 FIELD(SWRESET
, SWRESETREQ
, 9, 1)
43 REG32(INITSVTOR0
, 0x110)
44 REG32(INITSVTOR1
, 0x114)
46 REG32(NMI_ENABLE
, 0x11c) /* BUSWAIT in IoTKit */
49 REG32(PDCM_PD_SYS_SENSE
, 0x200)
50 REG32(PDCM_PD_SRAM0_SENSE
, 0x20c)
51 REG32(PDCM_PD_SRAM1_SENSE
, 0x210)
52 REG32(PDCM_PD_SRAM2_SENSE
, 0x214)
53 REG32(PDCM_PD_SRAM3_SENSE
, 0x218)
68 static const int sysctl_id
[] = {
69 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
70 0x54, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
71 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
75 * Set the initial secure vector table offset address for the core.
76 * This will take effect when the CPU next resets.
78 static void set_init_vtor(uint64_t cpuid
, uint32_t vtor
)
80 Object
*cpuobj
= OBJECT(arm_get_cpu_by_id(cpuid
));
83 if (object_property_find(cpuobj
, "init-svtor", NULL
)) {
84 object_property_set_uint(cpuobj
, vtor
, "init-svtor", &error_abort
);
89 static uint64_t iotkit_sysctl_read(void *opaque
, hwaddr offset
,
92 IoTKitSysCtl
*s
= IOTKIT_SYSCTL(opaque
);
123 case A_RESET_SYNDROME
:
124 r
= s
->reset_syndrome
;
145 /* In IoTKit this is named BUSWAIT but is marked reserved, R/O, zero */
161 case A_PDCM_PD_SYS_SENSE
:
165 r
= s
->pdcm_pd_sys_sense
;
167 case A_PDCM_PD_SRAM0_SENSE
:
171 r
= s
->pdcm_pd_sram0_sense
;
173 case A_PDCM_PD_SRAM1_SENSE
:
177 r
= s
->pdcm_pd_sram1_sense
;
179 case A_PDCM_PD_SRAM2_SENSE
:
183 r
= s
->pdcm_pd_sram2_sense
;
185 case A_PDCM_PD_SRAM3_SENSE
:
189 r
= s
->pdcm_pd_sram3_sense
;
191 case A_PID4
... A_CID3
:
192 r
= sysctl_id
[(offset
- A_PID4
) / 4];
197 qemu_log_mask(LOG_GUEST_ERROR
,
198 "IoTKit SysCtl read: read of WO offset %x\n",
204 qemu_log_mask(LOG_GUEST_ERROR
,
205 "IoTKit SysCtl read: bad offset %x\n", (int)offset
);
209 trace_iotkit_sysctl_read(offset
, r
, size
);
213 static void iotkit_sysctl_write(void *opaque
, hwaddr offset
,
214 uint64_t value
, unsigned size
)
216 IoTKitSysCtl
*s
= IOTKIT_SYSCTL(opaque
);
218 trace_iotkit_sysctl_write(offset
, value
, size
);
221 * Most of the state here has to do with control of reset and
222 * similar kinds of power up -- for instance the guest can ask
223 * what the reason for the last reset was, or forbid reset for
224 * some causes (like the non-secure watchdog). Most of this is
225 * not relevant to QEMU, which doesn't really model anything other
226 * than a full power-on reset.
227 * We just model the registers as reads-as-written.
231 case A_RESET_SYNDROME
:
232 qemu_log_mask(LOG_UNIMP
,
233 "IoTKit SysCtl RESET_SYNDROME unimplemented\n");
234 s
->reset_syndrome
= value
;
237 qemu_log_mask(LOG_UNIMP
, "IoTKit SysCtl RESET_MASK unimplemented\n");
238 s
->reset_mask
= value
;
242 * General retention register, which is only reset by a power-on
243 * reset. Technically this implementation is complete, since
244 * QEMU only supports power-on resets...
249 s
->initsvtor0
= value
;
250 set_init_vtor(0, s
->initsvtor0
);
253 if ((s
->cpuwait
& 1) && !(value
& 1)) {
254 /* Powering up CPU 0 */
255 arm_set_cpu_on_and_reset(0);
257 if ((s
->cpuwait
& 2) && !(value
& 2)) {
258 /* Powering up CPU 1 */
259 arm_set_cpu_on_and_reset(1);
264 qemu_log_mask(LOG_UNIMP
, "IoTKit SysCtl WICCTRL unimplemented\n");
269 qemu_log_mask(LOG_UNIMP
, "IoTKit SysCtl SECDBGSET unimplemented\n");
270 s
->secure_debug
|= value
;
273 /* write-1-to-clear */
274 s
->secure_debug
&= ~value
;
277 /* One w/o bit to request a reset; all other bits reserved */
278 if (value
& R_SWRESET_SWRESETREQ_MASK
) {
279 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
286 qemu_log_mask(LOG_UNIMP
, "IoTKit SysCtl SCSECCTRL unimplemented\n");
287 s
->scsecctrl
= value
;
293 qemu_log_mask(LOG_UNIMP
, "IoTKit SysCtl FCLK_DIV unimplemented\n");
300 qemu_log_mask(LOG_UNIMP
, "IoTKit SysCtl SYSCLK_DIV unimplemented\n");
301 s
->sysclk_div
= value
;
307 qemu_log_mask(LOG_UNIMP
, "IoTKit SysCtl CLOCK_FORCE unimplemented\n");
308 s
->clock_force
= value
;
314 s
->initsvtor1
= value
;
315 set_init_vtor(1, s
->initsvtor1
);
321 qemu_log_mask(LOG_UNIMP
, "IoTKit SysCtl EWCTRL unimplemented\n");
324 case A_PDCM_PD_SYS_SENSE
:
328 qemu_log_mask(LOG_UNIMP
,
329 "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n");
330 s
->pdcm_pd_sys_sense
= value
;
332 case A_PDCM_PD_SRAM0_SENSE
:
336 qemu_log_mask(LOG_UNIMP
,
337 "IoTKit SysCtl PDCM_PD_SRAM0_SENSE unimplemented\n");
338 s
->pdcm_pd_sram0_sense
= value
;
340 case A_PDCM_PD_SRAM1_SENSE
:
344 qemu_log_mask(LOG_UNIMP
,
345 "IoTKit SysCtl PDCM_PD_SRAM1_SENSE unimplemented\n");
346 s
->pdcm_pd_sram1_sense
= value
;
348 case A_PDCM_PD_SRAM2_SENSE
:
352 qemu_log_mask(LOG_UNIMP
,
353 "IoTKit SysCtl PDCM_PD_SRAM2_SENSE unimplemented\n");
354 s
->pdcm_pd_sram2_sense
= value
;
356 case A_PDCM_PD_SRAM3_SENSE
:
360 qemu_log_mask(LOG_UNIMP
,
361 "IoTKit SysCtl PDCM_PD_SRAM3_SENSE unimplemented\n");
362 s
->pdcm_pd_sram3_sense
= value
;
365 /* In IoTKit this is BUSWAIT: reserved, R/O, zero */
369 qemu_log_mask(LOG_UNIMP
, "IoTKit SysCtl NMI_ENABLE unimplemented\n");
370 s
->nmi_enable
= value
;
373 case A_PID4
... A_CID3
:
375 qemu_log_mask(LOG_GUEST_ERROR
,
376 "IoTKit SysCtl write: write of RO offset %x\n",
381 qemu_log_mask(LOG_GUEST_ERROR
,
382 "IoTKit SysCtl write: bad offset %x\n", (int)offset
);
387 static const MemoryRegionOps iotkit_sysctl_ops
= {
388 .read
= iotkit_sysctl_read
,
389 .write
= iotkit_sysctl_write
,
390 .endianness
= DEVICE_LITTLE_ENDIAN
,
391 /* byte/halfword accesses are just zero-padded on reads and writes */
392 .impl
.min_access_size
= 4,
393 .impl
.max_access_size
= 4,
394 .valid
.min_access_size
= 1,
395 .valid
.max_access_size
= 4,
398 static void iotkit_sysctl_reset(DeviceState
*dev
)
400 IoTKitSysCtl
*s
= IOTKIT_SYSCTL(dev
);
402 trace_iotkit_sysctl_reset();
404 s
->reset_syndrome
= 1;
407 s
->initsvtor0
= s
->initsvtor0_rst
;
408 s
->initsvtor1
= s
->initsvtor1_rst
;
409 s
->cpuwait
= s
->cpuwait_rst
;
417 s
->pdcm_pd_sys_sense
= 0x7f;
418 s
->pdcm_pd_sram0_sense
= 0;
419 s
->pdcm_pd_sram1_sense
= 0;
420 s
->pdcm_pd_sram2_sense
= 0;
421 s
->pdcm_pd_sram3_sense
= 0;
424 static void iotkit_sysctl_init(Object
*obj
)
426 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
427 IoTKitSysCtl
*s
= IOTKIT_SYSCTL(obj
);
429 memory_region_init_io(&s
->iomem
, obj
, &iotkit_sysctl_ops
,
430 s
, "iotkit-sysctl", 0x1000);
431 sysbus_init_mmio(sbd
, &s
->iomem
);
434 static void iotkit_sysctl_realize(DeviceState
*dev
, Error
**errp
)
436 IoTKitSysCtl
*s
= IOTKIT_SYSCTL(dev
);
438 /* The top 4 bits of the SYS_VERSION register tell us if we're an SSE-200 */
439 if (extract32(s
->sys_version
, 28, 4) == 2) {
444 static bool sse200_needed(void *opaque
)
446 IoTKitSysCtl
*s
= IOTKIT_SYSCTL(opaque
);
451 static const VMStateDescription iotkit_sysctl_sse200_vmstate
= {
452 .name
= "iotkit-sysctl/sse-200",
454 .minimum_version_id
= 1,
455 .needed
= sse200_needed
,
456 .fields
= (VMStateField
[]) {
457 VMSTATE_UINT32(scsecctrl
, IoTKitSysCtl
),
458 VMSTATE_UINT32(fclk_div
, IoTKitSysCtl
),
459 VMSTATE_UINT32(sysclk_div
, IoTKitSysCtl
),
460 VMSTATE_UINT32(clock_force
, IoTKitSysCtl
),
461 VMSTATE_UINT32(initsvtor1
, IoTKitSysCtl
),
462 VMSTATE_UINT32(nmi_enable
, IoTKitSysCtl
),
463 VMSTATE_UINT32(pdcm_pd_sys_sense
, IoTKitSysCtl
),
464 VMSTATE_UINT32(pdcm_pd_sram0_sense
, IoTKitSysCtl
),
465 VMSTATE_UINT32(pdcm_pd_sram1_sense
, IoTKitSysCtl
),
466 VMSTATE_UINT32(pdcm_pd_sram2_sense
, IoTKitSysCtl
),
467 VMSTATE_UINT32(pdcm_pd_sram3_sense
, IoTKitSysCtl
),
468 VMSTATE_END_OF_LIST()
472 static const VMStateDescription iotkit_sysctl_vmstate
= {
473 .name
= "iotkit-sysctl",
475 .minimum_version_id
= 1,
476 .fields
= (VMStateField
[]) {
477 VMSTATE_UINT32(secure_debug
, IoTKitSysCtl
),
478 VMSTATE_UINT32(reset_syndrome
, IoTKitSysCtl
),
479 VMSTATE_UINT32(reset_mask
, IoTKitSysCtl
),
480 VMSTATE_UINT32(gretreg
, IoTKitSysCtl
),
481 VMSTATE_UINT32(initsvtor0
, IoTKitSysCtl
),
482 VMSTATE_UINT32(cpuwait
, IoTKitSysCtl
),
483 VMSTATE_UINT32(wicctrl
, IoTKitSysCtl
),
484 VMSTATE_END_OF_LIST()
486 .subsections
= (const VMStateDescription
*[]) {
487 &iotkit_sysctl_sse200_vmstate
,
492 static Property iotkit_sysctl_props
[] = {
493 DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysCtl
, sys_version
, 0),
494 DEFINE_PROP_UINT32("CPUWAIT_RST", IoTKitSysCtl
, cpuwait_rst
, 0),
495 DEFINE_PROP_UINT32("INITSVTOR0_RST", IoTKitSysCtl
, initsvtor0_rst
,
497 DEFINE_PROP_UINT32("INITSVTOR1_RST", IoTKitSysCtl
, initsvtor1_rst
,
499 DEFINE_PROP_END_OF_LIST()
502 static void iotkit_sysctl_class_init(ObjectClass
*klass
, void *data
)
504 DeviceClass
*dc
= DEVICE_CLASS(klass
);
506 dc
->vmsd
= &iotkit_sysctl_vmstate
;
507 dc
->reset
= iotkit_sysctl_reset
;
508 dc
->props
= iotkit_sysctl_props
;
509 dc
->realize
= iotkit_sysctl_realize
;
512 static const TypeInfo iotkit_sysctl_info
= {
513 .name
= TYPE_IOTKIT_SYSCTL
,
514 .parent
= TYPE_SYS_BUS_DEVICE
,
515 .instance_size
= sizeof(IoTKitSysCtl
),
516 .instance_init
= iotkit_sysctl_init
,
517 .class_init
= iotkit_sysctl_class_init
,
520 static void iotkit_sysctl_register_types(void)
522 type_register_static(&iotkit_sysctl_info
);
525 type_init(iotkit_sysctl_register_types
);