target-cris/helper.c

   1 /*
   2  *  CRIS helper routines.
   3  *
   4  *  Copyright (c) 2007 AXIS Communications AB
   5  *  Written by Edgar E. Iglesias.
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "cpu.h"
  22 #include "mmu.h"
  23 #include "qemu/host-utils.h"
  24 #include "exec/cpu_ldst.h"
  25
  26
  27 //#define CRIS_HELPER_DEBUG
  28
  29
  30 #ifdef CRIS_HELPER_DEBUG
  31 #define D(x) x
  32 #define D_LOG(...) qemu_log(__VA_ARGS__)
  33 #else
  34 #define D(x)
  35 #define D_LOG(...) do { } while (0)
  36 #endif
  37
  38 #if defined(CONFIG_USER_ONLY)
  39
  40 void cris_cpu_do_interrupt(CPUState *cs)
  41 {
  42     CRISCPU *cpu = CRIS_CPU(cs);
  43     CPUCRISState *env = &cpu->env;
  44
  45     cs->exception_index = -1;
  46     env->pregs[PR_ERP] = env->pc;
  47 }
  48
  49 void crisv10_cpu_do_interrupt(CPUState *cs)
  50 {
  51     cris_cpu_do_interrupt(cs);
  52 }
  53
  54 int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  55                               int mmu_idx)
  56 {
  57     CRISCPU *cpu = CRIS_CPU(cs);
  58
  59     cs->exception_index = 0xaa;
  60     cpu->env.pregs[PR_EDA] = address;
  61     cpu_dump_state(cs, stderr, fprintf, 0);
  62     return 1;
  63 }
  64
  65 #else /* !CONFIG_USER_ONLY */
  66
  67
  68 static void cris_shift_ccs(CPUCRISState *env)
  69 {
  70     uint32_t ccs;
  71     /* Apply the ccs shift.  */
  72     ccs = env->pregs[PR_CCS];
  73     ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
  74     env->pregs[PR_CCS] = ccs;
  75 }
  76
  77 int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  78                               int mmu_idx)
  79 {
  80     CRISCPU *cpu = CRIS_CPU(cs);
  81     CPUCRISState *env = &cpu->env;
  82     struct cris_mmu_result res;
  83     int prot, miss;
  84     int r = -1;
  85     target_ulong phy;
  86
  87     qemu_log_mask(CPU_LOG_MMU, "%s addr=%" VADDR_PRIx " pc=%x rw=%x\n",
  88             __func__, address, env->pc, rw);
  89     miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
  90                               rw, mmu_idx, 0);
  91     if (miss) {
  92         if (cs->exception_index == EXCP_BUSFAULT) {
  93             cpu_abort(cs,
  94                       "CRIS: Illegal recursive bus fault."
  95                       "addr=%" VADDR_PRIx " rw=%d\n",
  96                       address, rw);
  97         }
  98
  99         env->pregs[PR_EDA] = address;
 100         cs->exception_index = EXCP_BUSFAULT;
 101         env->fault_vector = res.bf_vec;
 102         r = 1;
 103     } else {
 104         /*
 105          * Mask off the cache selection bit. The ETRAX busses do not
 106          * see the top bit.
 107          */
 108         phy = res.phy & ~0x80000000;
 109         prot = res.prot;
 110         tlb_set_page(cs, address & TARGET_PAGE_MASK, phy,
 111                      prot, mmu_idx, TARGET_PAGE_SIZE);
 112         r = 0;
 113     }
 114     if (r > 0) {
 115         qemu_log_mask(CPU_LOG_MMU,
 116                 "%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x"
 117                 " pc=%x\n", __func__, r, cs->interrupt_request, address,
 118                 res.phy, res.bf_vec, env->pc);
 119     }
 120     return r;
 121 }
 122
 123 void crisv10_cpu_do_interrupt(CPUState *cs)
 124 {
 125     CRISCPU *cpu = CRIS_CPU(cs);
 126     CPUCRISState *env = &cpu->env;
 127     int ex_vec = -1;
 128
 129     D_LOG("exception index=%d interrupt_req=%d\n",
 130           cs->exception_index,
 131           cs->interrupt_request);
 132
 133     if (env->dslot) {
 134         /* CRISv10 never takes interrupts while in a delay-slot.  */
 135         cpu_abort(cs, "CRIS: Interrupt on delay-slot\n");
 136     }
 137
 138     assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
 139     switch (cs->exception_index) {
 140     case EXCP_BREAK:
 141         /* These exceptions are genereated by the core itself.
 142            ERP should point to the insn following the brk.  */
 143         ex_vec = env->trap_vector;
 144         env->pregs[PRV10_BRP] = env->pc;
 145         break;
 146
 147     case EXCP_NMI:
 148         /* NMI is hardwired to vector zero.  */
 149         ex_vec = 0;
 150         env->pregs[PR_CCS] &= ~M_FLAG_V10;
 151         env->pregs[PRV10_BRP] = env->pc;
 152         break;
 153
 154     case EXCP_BUSFAULT:
 155         cpu_abort(cs, "Unhandled busfault");
 156         break;
 157
 158     default:
 159         /* The interrupt controller gives us the vector.  */
 160         ex_vec = env->interrupt_vector;
 161         /* Normal interrupts are taken between
 162            TB's.  env->pc is valid here.  */
 163         env->pregs[PR_ERP] = env->pc;
 164         break;
 165     }
 166
 167     if (env->pregs[PR_CCS] & U_FLAG) {
 168         /* Swap stack pointers.  */
 169         env->pregs[PR_USP] = env->regs[R_SP];
 170         env->regs[R_SP] = env->ksp;
 171     }
 172
 173     /* Now that we are in kernel mode, load the handlers address.  */
 174     env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
 175     env->locked_irq = 1;
 176     env->pregs[PR_CCS] |= F_FLAG_V10; /* set F.  */
 177
 178     qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
 179                   __func__, env->pc, ex_vec,
 180                   env->pregs[PR_CCS],
 181                   env->pregs[PR_PID],
 182                   env->pregs[PR_ERP]);
 183 }
 184
 185 void cris_cpu_do_interrupt(CPUState *cs)
 186 {
 187     CRISCPU *cpu = CRIS_CPU(cs);
 188     CPUCRISState *env = &cpu->env;
 189     int ex_vec = -1;
 190
 191     D_LOG("exception index=%d interrupt_req=%d\n",
 192           cs->exception_index,
 193           cs->interrupt_request);
 194
 195     switch (cs->exception_index) {
 196     case EXCP_BREAK:
 197         /* These exceptions are genereated by the core itself.
 198            ERP should point to the insn following the brk.  */
 199         ex_vec = env->trap_vector;
 200         env->pregs[PR_ERP] = env->pc;
 201         break;
 202
 203     case EXCP_NMI:
 204         /* NMI is hardwired to vector zero.  */
 205         ex_vec = 0;
 206         env->pregs[PR_CCS] &= ~M_FLAG_V32;
 207         env->pregs[PR_NRP] = env->pc;
 208         break;
 209
 210     case EXCP_BUSFAULT:
 211         ex_vec = env->fault_vector;
 212         env->pregs[PR_ERP] = env->pc;
 213         break;
 214
 215     default:
 216         /* The interrupt controller gives us the vector.  */
 217         ex_vec = env->interrupt_vector;
 218         /* Normal interrupts are taken between
 219            TB's.  env->pc is valid here.  */
 220         env->pregs[PR_ERP] = env->pc;
 221         break;
 222     }
 223
 224     /* Fill in the IDX field.  */
 225     env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
 226
 227     if (env->dslot) {
 228         D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
 229               " ERP=%x pid=%x ccs=%x cc=%d %x\n",
 230               ex_vec, env->pc, env->dslot,
 231               env->regs[R_SP],
 232               env->pregs[PR_ERP], env->pregs[PR_PID],
 233               env->pregs[PR_CCS],
 234               env->cc_op, env->cc_mask);
 235         /* We loose the btarget, btaken state here so rexec the
 236            branch.  */
 237         env->pregs[PR_ERP] -= env->dslot;
 238         /* Exception starts with dslot cleared.  */
 239         env->dslot = 0;
 240     }
 241
 242     if (env->pregs[PR_CCS] & U_FLAG) {
 243         /* Swap stack pointers.  */
 244         env->pregs[PR_USP] = env->regs[R_SP];
 245         env->regs[R_SP] = env->ksp;
 246     }
 247
 248     /* Apply the CRIS CCS shift. Clears U if set.  */
 249     cris_shift_ccs(env);
 250
 251     /* Now that we are in kernel mode, load the handlers address.
 252        This load may not fault, real hw leaves that behaviour as
 253        undefined.  */
 254     env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
 255
 256     /* Clear the excption_index to avoid spurios hw_aborts for recursive
 257        bus faults.  */
 258     cs->exception_index = -1;
 259
 260     D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
 261           __func__, env->pc, ex_vec,
 262           env->pregs[PR_CCS],
 263           env->pregs[PR_PID],
 264           env->pregs[PR_ERP]);
 265 }
 266
 267 hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 268 {
 269     CRISCPU *cpu = CRIS_CPU(cs);
 270     uint32_t phy = addr;
 271     struct cris_mmu_result res;
 272     int miss;
 273
 274     miss = cris_mmu_translate(&res, &cpu->env, addr, 0, 0, 1);
 275     /* If D TLB misses, try I TLB.  */
 276     if (miss) {
 277         miss = cris_mmu_translate(&res, &cpu->env, addr, 2, 0, 1);
 278     }
 279
 280     if (!miss) {
 281         phy = res.phy;
 282     }
 283     D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
 284     return phy;
 285 }
 286 #endif
 287
 288 bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 289 {
 290     CPUClass *cc = CPU_GET_CLASS(cs);
 291     CRISCPU *cpu = CRIS_CPU(cs);
 292     CPUCRISState *env = &cpu->env;
 293     bool ret = false;
 294
 295     if (interrupt_request & CPU_INTERRUPT_HARD
 296         && (env->pregs[PR_CCS] & I_FLAG)
 297         && !env->locked_irq) {
 298         cs->exception_index = EXCP_IRQ;
 299         cc->do_interrupt(cs);
 300         ret = true;
 301     }
 302     if (interrupt_request & CPU_INTERRUPT_NMI) {
 303         unsigned int m_flag_archval;
 304         if (env->pregs[PR_VR] < 32) {
 305             m_flag_archval = M_FLAG_V10;
 306         } else {
 307             m_flag_archval = M_FLAG_V32;
 308         }
 309         if ((env->pregs[PR_CCS] & m_flag_archval)) {
 310             cs->exception_index = EXCP_NMI;
 311             cc->do_interrupt(cs);
 312             ret = true;
 313         }
 314     }
 315
 316     return ret;
 317 }