target-microblaze/helper.c

   1 /*
   2  *  MicroBlaze helper routines.
   3  *
   4  *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
   5  *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu/host-utils.h"
  23
  24 #define D(x)
  25 #define DMMU(x)
  26
  27 #if defined(CONFIG_USER_ONLY)
  28
  29 void mb_cpu_do_interrupt(CPUState *cs)
  30 {
  31     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  32     CPUMBState *env = &cpu->env;
  33
  34     env->exception_index = -1;
  35     env->res_addr = RES_ADDR_NONE;
  36     env->regs[14] = env->sregs[SR_PC];
  37 }
  38
  39 int cpu_mb_handle_mmu_fault(CPUMBState * env, target_ulong address, int rw,
  40                             int mmu_idx)
  41 {
  42     env->exception_index = 0xaa;
  43     cpu_dump_state(env, stderr, fprintf, 0);
  44     return 1;
  45 }
  46
  47 #else /* !CONFIG_USER_ONLY */
  48
  49 int cpu_mb_handle_mmu_fault (CPUMBState *env, target_ulong address, int rw,
  50                              int mmu_idx)
  51 {
  52     unsigned int hit;
  53     unsigned int mmu_available;
  54     int r = 1;
  55     int prot;
  56
  57     mmu_available = 0;
  58     if (env->pvr.regs[0] & PVR0_USE_MMU) {
  59         mmu_available = 1;
  60         if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
  61             && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
  62             mmu_available = 0;
  63         }
  64     }
  65
  66     /* Translate if the MMU is available and enabled.  */
  67     if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {
  68         target_ulong vaddr, paddr;
  69         struct microblaze_mmu_lookup lu;
  70
  71         hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);
  72         if (hit) {
  73             vaddr = address & TARGET_PAGE_MASK;
  74             paddr = lu.paddr + vaddr - lu.vaddr;
  75
  76             DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n",
  77                      mmu_idx, vaddr, paddr, lu.prot));
  78             tlb_set_page(env, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
  79             r = 0;
  80         } else {
  81             env->sregs[SR_EAR] = address;
  82             DMMU(qemu_log("mmu=%d miss v=%x\n", mmu_idx, address));
  83
  84             switch (lu.err) {
  85                 case ERR_PROT:
  86                     env->sregs[SR_ESR] = rw == 2 ? 17 : 16;
  87                     env->sregs[SR_ESR] |= (rw == 1) << 10;
  88                     break;
  89                 case ERR_MISS:
  90                     env->sregs[SR_ESR] = rw == 2 ? 19 : 18;
  91                     env->sregs[SR_ESR] |= (rw == 1) << 10;
  92                     break;
  93                 default:
  94                     abort();
  95                     break;
  96             }
  97
  98             if (env->exception_index == EXCP_MMU) {
  99                 cpu_abort(env, "recursive faults\n");
 100             }
 101
 102             /* TLB miss.  */
 103             env->exception_index = EXCP_MMU;
 104         }
 105     } else {
 106         /* MMU disabled or not available.  */
 107         address &= TARGET_PAGE_MASK;
 108         prot = PAGE_BITS;
 109         tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
 110         r = 0;
 111     }
 112     return r;
 113 }
 114
 115 void mb_cpu_do_interrupt(CPUState *cs)
 116 {
 117     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 118     CPUMBState *env = &cpu->env;
 119     uint32_t t;
 120
 121     /* IMM flag cannot propagate across a branch and into the dslot.  */
 122     assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
 123     assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
 124 /*    assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions.  */
 125     env->res_addr = RES_ADDR_NONE;
 126     switch (env->exception_index) {
 127         case EXCP_HW_EXCP:
 128             if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
 129                 qemu_log("Exception raised on system without exceptions!\n");
 130                 return;
 131             }
 132
 133             env->regs[17] = env->sregs[SR_PC] + 4;
 134             env->sregs[SR_ESR] &= ~(1 << 12);
 135
 136             /* Exception breaks branch + dslot sequence?  */
 137             if (env->iflags & D_FLAG) {
 138                 env->sregs[SR_ESR] |= 1 << 12 ;
 139                 env->sregs[SR_BTR] = env->btarget;
 140             }
 141
 142             /* Disable the MMU.  */
 143             t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 144             env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 145             env->sregs[SR_MSR] |= t;
 146             /* Exception in progress.  */
 147             env->sregs[SR_MSR] |= MSR_EIP;
 148
 149             qemu_log_mask(CPU_LOG_INT,
 150                           "hw exception at pc=%x ear=%x esr=%x iflags=%x\n",
 151                           env->sregs[SR_PC], env->sregs[SR_EAR],
 152                           env->sregs[SR_ESR], env->iflags);
 153             log_cpu_state_mask(CPU_LOG_INT, env, 0);
 154             env->iflags &= ~(IMM_FLAG | D_FLAG);
 155             env->sregs[SR_PC] = cpu->base_vectors + 0x20;
 156             break;
 157
 158         case EXCP_MMU:
 159             env->regs[17] = env->sregs[SR_PC];
 160
 161             env->sregs[SR_ESR] &= ~(1 << 12);
 162             /* Exception breaks branch + dslot sequence?  */
 163             if (env->iflags & D_FLAG) {
 164                 D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
 165                 env->sregs[SR_ESR] |= 1 << 12 ;
 166                 env->sregs[SR_BTR] = env->btarget;
 167
 168                 /* Reexecute the branch.  */
 169                 env->regs[17] -= 4;
 170                 /* was the branch immprefixed?.  */
 171                 if (env->bimm) {
 172                     qemu_log_mask(CPU_LOG_INT,
 173                                   "bimm exception at pc=%x iflags=%x\n",
 174                                   env->sregs[SR_PC], env->iflags);
 175                     env->regs[17] -= 4;
 176                     log_cpu_state_mask(CPU_LOG_INT, env, 0);
 177                 }
 178             } else if (env->iflags & IMM_FLAG) {
 179                 D(qemu_log("IMM_FLAG set at exception\n"));
 180                 env->regs[17] -= 4;
 181             }
 182
 183             /* Disable the MMU.  */
 184             t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 185             env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 186             env->sregs[SR_MSR] |= t;
 187             /* Exception in progress.  */
 188             env->sregs[SR_MSR] |= MSR_EIP;
 189
 190             qemu_log_mask(CPU_LOG_INT,
 191                           "exception at pc=%x ear=%x iflags=%x\n",
 192                           env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
 193             log_cpu_state_mask(CPU_LOG_INT, env, 0);
 194             env->iflags &= ~(IMM_FLAG | D_FLAG);
 195             env->sregs[SR_PC] = cpu->base_vectors + 0x20;
 196             break;
 197
 198         case EXCP_IRQ:
 199             assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)));
 200             assert(env->sregs[SR_MSR] & MSR_IE);
 201             assert(!(env->iflags & D_FLAG));
 202
 203             t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 204
 205 #if 0
 206 #include "disas/disas.h"
 207
 208 /* Useful instrumentation when debugging interrupt issues in either
 209    the models or in sw.  */
 210             {
 211                 const char *sym;
 212
 213                 sym = lookup_symbol(env->sregs[SR_PC]);
 214                 if (sym
 215                     && (!strcmp("netif_rx", sym)
 216                         || !strcmp("process_backlog", sym))) {
 217
 218                     qemu_log(
 219                          "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
 220                          env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
 221                          sym);
 222
 223                     log_cpu_state(env, 0);
 224                 }
 225             }
 226 #endif
 227             qemu_log_mask(CPU_LOG_INT,
 228                          "interrupt at pc=%x msr=%x %x iflags=%x\n",
 229                          env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
 230
 231             env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \
 232                                     | MSR_UM | MSR_IE);
 233             env->sregs[SR_MSR] |= t;
 234
 235             env->regs[14] = env->sregs[SR_PC];
 236             env->sregs[SR_PC] = cpu->base_vectors + 0x10;
 237             //log_cpu_state_mask(CPU_LOG_INT, env, 0);
 238             break;
 239
 240         case EXCP_BREAK:
 241         case EXCP_HW_BREAK:
 242             assert(!(env->iflags & IMM_FLAG));
 243             assert(!(env->iflags & D_FLAG));
 244             t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 245             qemu_log_mask(CPU_LOG_INT,
 246                         "break at pc=%x msr=%x %x iflags=%x\n",
 247                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
 248             log_cpu_state_mask(CPU_LOG_INT, env, 0);
 249             env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 250             env->sregs[SR_MSR] |= t;
 251             env->sregs[SR_MSR] |= MSR_BIP;
 252             if (env->exception_index == EXCP_HW_BREAK) {
 253                 env->regs[16] = env->sregs[SR_PC];
 254                 env->sregs[SR_MSR] |= MSR_BIP;
 255                 env->sregs[SR_PC] = cpu->base_vectors + 0x18;
 256             } else
 257                 env->sregs[SR_PC] = env->btarget;
 258             break;
 259         default:
 260             cpu_abort(env, "unhandled exception type=%d\n",
 261                       env->exception_index);
 262             break;
 263     }
 264 }
 265
 266 hwaddr cpu_get_phys_page_debug(CPUMBState * env, target_ulong addr)
 267 {
 268     target_ulong vaddr, paddr = 0;
 269     struct microblaze_mmu_lookup lu;
 270     unsigned int hit;
 271
 272     if (env->sregs[SR_MSR] & MSR_VM) {
 273         hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
 274         if (hit) {
 275             vaddr = addr & TARGET_PAGE_MASK;
 276             paddr = lu.paddr + vaddr - lu.vaddr;
 277         } else
 278             paddr = 0; /* ???.  */
 279     } else
 280         paddr = addr & TARGET_PAGE_MASK;
 281
 282     return paddr;
 283 }
 284 #endif