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target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c
[qemu/ar7.git] / target / riscv / cpu.c
blob943aca2c20557e098ec2458d9cf4cf2baae44ebb
1 /*
2 * QEMU RISC-V CPU
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/qemu-print.h"
22 #include "qemu/ctype.h"
23 #include "qemu/log.h"
24 #include "cpu.h"
25 #include "cpu_vendorid.h"
26 #include "internals.h"
27 #include "exec/exec-all.h"
28 #include "qapi/error.h"
29 #include "qapi/visitor.h"
30 #include "qemu/error-report.h"
31 #include "hw/qdev-properties.h"
32 #include "migration/vmstate.h"
33 #include "fpu/softfloat-helpers.h"
34 #include "sysemu/kvm.h"
35 #include "sysemu/tcg.h"
36 #include "kvm_riscv.h"
37 #include "tcg/tcg.h"
38
39 /* RISC-V CPU definitions */
40 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
41
42 struct isa_ext_data {
43 const char *name;
44 int min_version;
45 int ext_enable_offset;
46 };
47
48 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
49 {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
50
51 /*
52 * From vector_helper.c
53 * Note that vector data is stored in host-endian 64-bit chunks,
54 * so addressing bytes needs a host-endian fixup.
55 */
56 #if HOST_BIG_ENDIAN
57 #define BYTE(x) ((x) ^ 7)
58 #else
59 #define BYTE(x) (x)
60 #endif
61
62 /*
63 * Here are the ordering rules of extension naming defined by RISC-V
64 * specification :
65 * 1. All extensions should be separated from other multi-letter extensions
66 * by an underscore.
67 * 2. The first letter following the 'Z' conventionally indicates the most
68 * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
69 * If multiple 'Z' extensions are named, they should be ordered first
70 * by category, then alphabetically within a category.
71 * 3. Standard supervisor-level extensions (starts with 'S') should be
72 * listed after standard unprivileged extensions. If multiple
73 * supervisor-level extensions are listed, they should be ordered
74 * alphabetically.
75 * 4. Non-standard extensions (starts with 'X') must be listed after all
76 * standard extensions. They must be separated from other multi-letter
77 * extensions by an underscore.
78 *
79 * Single letter extensions are checked in riscv_cpu_validate_misa_priv()
80 * instead.
81 */
82 static const struct isa_ext_data isa_edata_arr[] = {
83 ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
84 ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
85 ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
86 ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),
87 ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),
88 ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
89 ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
90 ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
91 ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
92 ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),
93 ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin),
94 ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh),
95 ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin),
96 ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx),
97 ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx),
98 ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca),
99 ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb),
100 ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf),
101 ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd),
102 ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce),
103 ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp),
104 ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt),
105 ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba),
106 ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb),
107 ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc),
108 ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb),
109 ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc),
110 ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx),
111 ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs),
112 ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk),
113 ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn),
114 ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd),
115 ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne),
116 ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh),
117 ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr),
118 ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks),
119 ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
120 ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
121 ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
122 ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
123 ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
124 ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
125 ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
126 ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
127 ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
128 ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
129 ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
130 ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
131 ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg),
132 ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
133 ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
134 ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
135 ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed),
136 ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
137 ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
138 ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
139 ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
140 ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, epmp),
141 ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
142 ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
143 ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
144 ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
145 ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
146 ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
147 ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
148 ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
149 ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
150 ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
151 ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
152 ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo),
153 ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
154 ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx),
155 ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv),
156 ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac),
157 ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx),
158 ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
159 ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
160 ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
161 };
162
163 /* Hash that stores user set extensions */
164 static GHashTable *multi_ext_user_opts;
165
166 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
167 {
168 bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
169
170 return *ext_enabled;
171 }
172
173 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
174 {
175 bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
176
177 *ext_enabled = en;
178 }
179
180 int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
181 {
182 int i;
183
184 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
185 if (isa_edata_arr[i].ext_enable_offset != ext_offset) {
186 continue;
187 }
188
189 return isa_edata_arr[i].min_version;
190 }
191
192 g_assert_not_reached();
193 }
194
195 bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
196 {
197 return g_hash_table_contains(multi_ext_user_opts,
198 GUINT_TO_POINTER(ext_offset));
199 }
200
201 const char * const riscv_int_regnames[] = {
202 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
203 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
204 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
205 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
206 "x28/t3", "x29/t4", "x30/t5", "x31/t6"
207 };
208
209 const char * const riscv_int_regnamesh[] = {
210 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h",
211 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h",
212 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h",
213 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h",
214 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h",
215 "x30h/t5h", "x31h/t6h"
216 };
217
218 const char * const riscv_fpr_regnames[] = {
219 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
220 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
221 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
222 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
223 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
224 "f30/ft10", "f31/ft11"
225 };
226
227 const char * const riscv_rvv_regnames[] = {
228 "v0", "v1", "v2", "v3", "v4", "v5", "v6",
229 "v7", "v8", "v9", "v10", "v11", "v12", "v13",
230 "v14", "v15", "v16", "v17", "v18", "v19", "v20",
231 "v21", "v22", "v23", "v24", "v25", "v26", "v27",
232 "v28", "v29", "v30", "v31"
233 };
234
235 static const char * const riscv_excp_names[] = {
236 "misaligned_fetch",
237 "fault_fetch",
238 "illegal_instruction",
239 "breakpoint",
240 "misaligned_load",
241 "fault_load",
242 "misaligned_store",
243 "fault_store",
244 "user_ecall",
245 "supervisor_ecall",
246 "hypervisor_ecall",
247 "machine_ecall",
248 "exec_page_fault",
249 "load_page_fault",
250 "reserved",
251 "store_page_fault",
252 "reserved",
253 "reserved",
254 "reserved",
255 "reserved",
256 "guest_exec_page_fault",
257 "guest_load_page_fault",
258 "reserved",
259 "guest_store_page_fault",
260 };
261
262 static const char * const riscv_intr_names[] = {
263 "u_software",
264 "s_software",
265 "vs_software",
266 "m_software",
267 "u_timer",
268 "s_timer",
269 "vs_timer",
270 "m_timer",
271 "u_external",
272 "s_external",
273 "vs_external",
274 "m_external",
275 "reserved",
276 "reserved",
277 "reserved",
278 "reserved"
279 };
280
281 static void riscv_cpu_add_user_properties(Object *obj);
282 static void riscv_init_max_cpu_extensions(Object *obj);
283
284 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
285 {
286 if (async) {
287 return (cause < ARRAY_SIZE(riscv_intr_names)) ?
288 riscv_intr_names[cause] : "(unknown)";
289 } else {
290 return (cause < ARRAY_SIZE(riscv_excp_names)) ?
291 riscv_excp_names[cause] : "(unknown)";
292 }
293 }
294
295 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
296 {
297 env->misa_mxl_max = env->misa_mxl = mxl;
298 env->misa_ext_mask = env->misa_ext = ext;
299 }
300
301 #ifndef CONFIG_USER_ONLY
302 static uint8_t satp_mode_from_str(const char *satp_mode_str)
303 {
304 if (!strncmp(satp_mode_str, "mbare", 5)) {
305 return VM_1_10_MBARE;
306 }
307
308 if (!strncmp(satp_mode_str, "sv32", 4)) {
309 return VM_1_10_SV32;
310 }
311
312 if (!strncmp(satp_mode_str, "sv39", 4)) {
313 return VM_1_10_SV39;
314 }
315
316 if (!strncmp(satp_mode_str, "sv48", 4)) {
317 return VM_1_10_SV48;
318 }
319
320 if (!strncmp(satp_mode_str, "sv57", 4)) {
321 return VM_1_10_SV57;
322 }
323
324 if (!strncmp(satp_mode_str, "sv64", 4)) {
325 return VM_1_10_SV64;
326 }
327
328 g_assert_not_reached();
329 }
330
331 uint8_t satp_mode_max_from_map(uint32_t map)
332 {
333 /*
334 * 'map = 0' will make us return (31 - 32), which C will
335 * happily overflow to UINT_MAX. There's no good result to
336 * return if 'map = 0' (e.g. returning 0 will be ambiguous
337 * with the result for 'map = 1').
338 *
339 * Assert out if map = 0. Callers will have to deal with
340 * it outside of this function.
341 */
342 g_assert(map > 0);
343
344 /* map here has at least one bit set, so no problem with clz */
345 return 31 - __builtin_clz(map);
346 }
347
348 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit)
349 {
350 if (is_32_bit) {
351 switch (satp_mode) {
352 case VM_1_10_SV32:
353 return "sv32";
354 case VM_1_10_MBARE:
355 return "none";
356 }
357 } else {
358 switch (satp_mode) {
359 case VM_1_10_SV64:
360 return "sv64";
361 case VM_1_10_SV57:
362 return "sv57";
363 case VM_1_10_SV48:
364 return "sv48";
365 case VM_1_10_SV39:
366 return "sv39";
367 case VM_1_10_MBARE:
368 return "none";
369 }
370 }
371
372 g_assert_not_reached();
373 }
374
375 static void set_satp_mode_max_supported(RISCVCPU *cpu,
376 uint8_t satp_mode)
377 {
378 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
379 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
380
381 for (int i = 0; i <= satp_mode; ++i) {
382 if (valid_vm[i]) {
383 cpu->cfg.satp_mode.supported |= (1 << i);
384 }
385 }
386 }
387
388 /* Set the satp mode to the max supported */
389 static void set_satp_mode_default_map(RISCVCPU *cpu)
390 {
391 cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported;
392 }
393 #endif
394
395 static void riscv_any_cpu_init(Object *obj)
396 {
397 RISCVCPU *cpu = RISCV_CPU(obj);
398 CPURISCVState *env = &cpu->env;
399 #if defined(TARGET_RISCV32)
400 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
401 #elif defined(TARGET_RISCV64)
402 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
403 #endif
404
405 #ifndef CONFIG_USER_ONLY
406 set_satp_mode_max_supported(RISCV_CPU(obj),
407 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
408 VM_1_10_SV32 : VM_1_10_SV57);
409 #endif
410
411 env->priv_ver = PRIV_VERSION_LATEST;
412
413 /* inherited from parent obj via riscv_cpu_init() */
414 cpu->cfg.ext_ifencei = true;
415 cpu->cfg.ext_icsr = true;
416 cpu->cfg.mmu = true;
417 cpu->cfg.pmp = true;
418 }
419
420 static void riscv_max_cpu_init(Object *obj)
421 {
422 RISCVCPU *cpu = RISCV_CPU(obj);
423 CPURISCVState *env = &cpu->env;
424 RISCVMXL mlx = MXL_RV64;
425
426 #ifdef TARGET_RISCV32
427 mlx = MXL_RV32;
428 #endif
429 set_misa(env, mlx, 0);
430 riscv_cpu_add_user_properties(obj);
431 riscv_init_max_cpu_extensions(obj);
432 env->priv_ver = PRIV_VERSION_LATEST;
433 #ifndef CONFIG_USER_ONLY
434 set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
435 VM_1_10_SV32 : VM_1_10_SV57);
436 #endif
437 }
438
439 #if defined(TARGET_RISCV64)
440 static void rv64_base_cpu_init(Object *obj)
441 {
442 CPURISCVState *env = &RISCV_CPU(obj)->env;
443 /* We set this in the realise function */
444 set_misa(env, MXL_RV64, 0);
445 riscv_cpu_add_user_properties(obj);
446 /* Set latest version of privileged specification */
447 env->priv_ver = PRIV_VERSION_LATEST;
448 #ifndef CONFIG_USER_ONLY
449 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
450 #endif
451 }
452
453 static void rv64_sifive_u_cpu_init(Object *obj)
454 {
455 RISCVCPU *cpu = RISCV_CPU(obj);
456 CPURISCVState *env = &cpu->env;
457 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
458 env->priv_ver = PRIV_VERSION_1_10_0;
459 #ifndef CONFIG_USER_ONLY
460 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
461 #endif
462
463 /* inherited from parent obj via riscv_cpu_init() */
464 cpu->cfg.ext_ifencei = true;
465 cpu->cfg.ext_icsr = true;
466 cpu->cfg.mmu = true;
467 cpu->cfg.pmp = true;
468 }
469
470 static void rv64_sifive_e_cpu_init(Object *obj)
471 {
472 CPURISCVState *env = &RISCV_CPU(obj)->env;
473 RISCVCPU *cpu = RISCV_CPU(obj);
474
475 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
476 env->priv_ver = PRIV_VERSION_1_10_0;
477 #ifndef CONFIG_USER_ONLY
478 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
479 #endif
480
481 /* inherited from parent obj via riscv_cpu_init() */
482 cpu->cfg.ext_ifencei = true;
483 cpu->cfg.ext_icsr = true;
484 cpu->cfg.pmp = true;
485 }
486
487 static void rv64_thead_c906_cpu_init(Object *obj)
488 {
489 CPURISCVState *env = &RISCV_CPU(obj)->env;
490 RISCVCPU *cpu = RISCV_CPU(obj);
491
492 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
493 env->priv_ver = PRIV_VERSION_1_11_0;
494
495 cpu->cfg.ext_zfa = true;
496 cpu->cfg.ext_zfh = true;
497 cpu->cfg.mmu = true;
498 cpu->cfg.ext_xtheadba = true;
499 cpu->cfg.ext_xtheadbb = true;
500 cpu->cfg.ext_xtheadbs = true;
501 cpu->cfg.ext_xtheadcmo = true;
502 cpu->cfg.ext_xtheadcondmov = true;
503 cpu->cfg.ext_xtheadfmemidx = true;
504 cpu->cfg.ext_xtheadmac = true;
505 cpu->cfg.ext_xtheadmemidx = true;
506 cpu->cfg.ext_xtheadmempair = true;
507 cpu->cfg.ext_xtheadsync = true;
508
509 cpu->cfg.mvendorid = THEAD_VENDOR_ID;
510 #ifndef CONFIG_USER_ONLY
511 set_satp_mode_max_supported(cpu, VM_1_10_SV39);
512 #endif
513
514 /* inherited from parent obj via riscv_cpu_init() */
515 cpu->cfg.pmp = true;
516 }
517
518 static void rv64_veyron_v1_cpu_init(Object *obj)
519 {
520 CPURISCVState *env = &RISCV_CPU(obj)->env;
521 RISCVCPU *cpu = RISCV_CPU(obj);
522
523 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
524 env->priv_ver = PRIV_VERSION_1_12_0;
525
526 /* Enable ISA extensions */
527 cpu->cfg.mmu = true;
528 cpu->cfg.ext_ifencei = true;
529 cpu->cfg.ext_icsr = true;
530 cpu->cfg.pmp = true;
531 cpu->cfg.ext_icbom = true;
532 cpu->cfg.cbom_blocksize = 64;
533 cpu->cfg.cboz_blocksize = 64;
534 cpu->cfg.ext_icboz = true;
535 cpu->cfg.ext_smaia = true;
536 cpu->cfg.ext_ssaia = true;
537 cpu->cfg.ext_sscofpmf = true;
538 cpu->cfg.ext_sstc = true;
539 cpu->cfg.ext_svinval = true;
540 cpu->cfg.ext_svnapot = true;
541 cpu->cfg.ext_svpbmt = true;
542 cpu->cfg.ext_smstateen = true;
543 cpu->cfg.ext_zba = true;
544 cpu->cfg.ext_zbb = true;
545 cpu->cfg.ext_zbc = true;
546 cpu->cfg.ext_zbs = true;
547 cpu->cfg.ext_XVentanaCondOps = true;
548
549 cpu->cfg.mvendorid = VEYRON_V1_MVENDORID;
550 cpu->cfg.marchid = VEYRON_V1_MARCHID;
551 cpu->cfg.mimpid = VEYRON_V1_MIMPID;
552
553 #ifndef CONFIG_USER_ONLY
554 set_satp_mode_max_supported(cpu, VM_1_10_SV48);
555 #endif
556 }
557
558 static void rv128_base_cpu_init(Object *obj)
559 {
560 if (qemu_tcg_mttcg_enabled()) {
561 /* Missing 128-bit aligned atomics */
562 error_report("128-bit RISC-V currently does not work with Multi "
563 "Threaded TCG. Please use: -accel tcg,thread=single");
564 exit(EXIT_FAILURE);
565 }
566 CPURISCVState *env = &RISCV_CPU(obj)->env;
567 /* We set this in the realise function */
568 set_misa(env, MXL_RV128, 0);
569 riscv_cpu_add_user_properties(obj);
570 /* Set latest version of privileged specification */
571 env->priv_ver = PRIV_VERSION_LATEST;
572 #ifndef CONFIG_USER_ONLY
573 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
574 #endif
575 }
576 #else
577 static void rv32_base_cpu_init(Object *obj)
578 {
579 CPURISCVState *env = &RISCV_CPU(obj)->env;
580 /* We set this in the realise function */
581 set_misa(env, MXL_RV32, 0);
582 riscv_cpu_add_user_properties(obj);
583 /* Set latest version of privileged specification */
584 env->priv_ver = PRIV_VERSION_LATEST;
585 #ifndef CONFIG_USER_ONLY
586 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
587 #endif
588 }
589
590 static void rv32_sifive_u_cpu_init(Object *obj)
591 {
592 RISCVCPU *cpu = RISCV_CPU(obj);
593 CPURISCVState *env = &cpu->env;
594 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
595 env->priv_ver = PRIV_VERSION_1_10_0;
596 #ifndef CONFIG_USER_ONLY
597 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
598 #endif
599
600 /* inherited from parent obj via riscv_cpu_init() */
601 cpu->cfg.ext_ifencei = true;
602 cpu->cfg.ext_icsr = true;
603 cpu->cfg.mmu = true;
604 cpu->cfg.pmp = true;
605 }
606
607 static void rv32_sifive_e_cpu_init(Object *obj)
608 {
609 CPURISCVState *env = &RISCV_CPU(obj)->env;
610 RISCVCPU *cpu = RISCV_CPU(obj);
611
612 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
613 env->priv_ver = PRIV_VERSION_1_10_0;
614 #ifndef CONFIG_USER_ONLY
615 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
616 #endif
617
618 /* inherited from parent obj via riscv_cpu_init() */
619 cpu->cfg.ext_ifencei = true;
620 cpu->cfg.ext_icsr = true;
621 cpu->cfg.pmp = true;
622 }
623
624 static void rv32_ibex_cpu_init(Object *obj)
625 {
626 CPURISCVState *env = &RISCV_CPU(obj)->env;
627 RISCVCPU *cpu = RISCV_CPU(obj);
628
629 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
630 env->priv_ver = PRIV_VERSION_1_11_0;
631 #ifndef CONFIG_USER_ONLY
632 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
633 #endif
634 cpu->cfg.epmp = true;
635
636 /* inherited from parent obj via riscv_cpu_init() */
637 cpu->cfg.ext_ifencei = true;
638 cpu->cfg.ext_icsr = true;
639 cpu->cfg.pmp = true;
640 }
641
642 static void rv32_imafcu_nommu_cpu_init(Object *obj)
643 {
644 CPURISCVState *env = &RISCV_CPU(obj)->env;
645 RISCVCPU *cpu = RISCV_CPU(obj);
646
647 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
648 env->priv_ver = PRIV_VERSION_1_10_0;
649 #ifndef CONFIG_USER_ONLY
650 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
651 #endif
652
653 /* inherited from parent obj via riscv_cpu_init() */
654 cpu->cfg.ext_ifencei = true;
655 cpu->cfg.ext_icsr = true;
656 cpu->cfg.pmp = true;
657 }
658 #endif
659
660 #if defined(CONFIG_KVM)
661 static void riscv_host_cpu_init(Object *obj)
662 {
663 CPURISCVState *env = &RISCV_CPU(obj)->env;
664 #if defined(TARGET_RISCV32)
665 set_misa(env, MXL_RV32, 0);
666 #elif defined(TARGET_RISCV64)
667 set_misa(env, MXL_RV64, 0);
668 #endif
669 riscv_cpu_add_user_properties(obj);
670 }
671 #endif /* CONFIG_KVM */
672
673 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
674 {
675 ObjectClass *oc;
676 char *typename;
677 char **cpuname;
678
679 cpuname = g_strsplit(cpu_model, ",", 1);
680 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
681 oc = object_class_by_name(typename);
682 g_strfreev(cpuname);
683 g_free(typename);
684 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
685 object_class_is_abstract(oc)) {
686 return NULL;
687 }
688 return oc;
689 }
690
691 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
692 {
693 RISCVCPU *cpu = RISCV_CPU(cs);
694 CPURISCVState *env = &cpu->env;
695 int i, j;
696 uint8_t *p;
697
698 #if !defined(CONFIG_USER_ONLY)
699 if (riscv_has_ext(env, RVH)) {
700 qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled);
701 }
702 #endif
703 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
704 #ifndef CONFIG_USER_ONLY
705 {
706 static const int dump_csrs[] = {
707 CSR_MHARTID,
708 CSR_MSTATUS,
709 CSR_MSTATUSH,
710 /*
711 * CSR_SSTATUS is intentionally omitted here as its value
712 * can be figured out by looking at CSR_MSTATUS
713 */
714 CSR_HSTATUS,
715 CSR_VSSTATUS,
716 CSR_MIP,
717 CSR_MIE,
718 CSR_MIDELEG,
719 CSR_HIDELEG,
720 CSR_MEDELEG,
721 CSR_HEDELEG,
722 CSR_MTVEC,
723 CSR_STVEC,
724 CSR_VSTVEC,
725 CSR_MEPC,
726 CSR_SEPC,
727 CSR_VSEPC,
728 CSR_MCAUSE,
729 CSR_SCAUSE,
730 CSR_VSCAUSE,
731 CSR_MTVAL,
732 CSR_STVAL,
733 CSR_HTVAL,
734 CSR_MTVAL2,
735 CSR_MSCRATCH,
736 CSR_SSCRATCH,
737 CSR_SATP,
738 CSR_MMTE,
739 CSR_UPMBASE,
740 CSR_UPMMASK,
741 CSR_SPMBASE,
742 CSR_SPMMASK,
743 CSR_MPMBASE,
744 CSR_MPMMASK,
745 };
746
747 for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
748 int csrno = dump_csrs[i];
749 target_ulong val = 0;
750 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
751
752 /*
753 * Rely on the smode, hmode, etc, predicates within csr.c
754 * to do the filtering of the registers that are present.
755 */
756 if (res == RISCV_EXCP_NONE) {
757 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
758 csr_ops[csrno].name, val);
759 }
760 }
761 }
762 #endif
763
764 for (i = 0; i < 32; i++) {
765 qemu_fprintf(f, " %-8s " TARGET_FMT_lx,
766 riscv_int_regnames[i], env->gpr[i]);
767 if ((i & 3) == 3) {
768 qemu_fprintf(f, "\n");
769 }
770 }
771 if (flags & CPU_DUMP_FPU) {
772 for (i = 0; i < 32; i++) {
773 qemu_fprintf(f, " %-8s %016" PRIx64,
774 riscv_fpr_regnames[i], env->fpr[i]);
775 if ((i & 3) == 3) {
776 qemu_fprintf(f, "\n");
777 }
778 }
779 }
780 if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) {
781 static const int dump_rvv_csrs[] = {
782 CSR_VSTART,
783 CSR_VXSAT,
784 CSR_VXRM,
785 CSR_VCSR,
786 CSR_VL,
787 CSR_VTYPE,
788 CSR_VLENB,
789 };
790 for (i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
791 int csrno = dump_rvv_csrs[i];
792 target_ulong val = 0;
793 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
794
795 /*
796 * Rely on the smode, hmode, etc, predicates within csr.c
797 * to do the filtering of the registers that are present.
798 */
799 if (res == RISCV_EXCP_NONE) {
800 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
801 csr_ops[csrno].name, val);
802 }
803 }
804 uint16_t vlenb = cpu->cfg.vlen >> 3;
805
806 for (i = 0; i < 32; i++) {
807 qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
808 p = (uint8_t *)env->vreg;
809 for (j = vlenb - 1 ; j >= 0; j--) {
810 qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j)));
811 }
812 qemu_fprintf(f, "\n");
813 }
814 }
815 }
816
817 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
818 {
819 RISCVCPU *cpu = RISCV_CPU(cs);
820 CPURISCVState *env = &cpu->env;
821
822 if (env->xl == MXL_RV32) {
823 env->pc = (int32_t)value;
824 } else {
825 env->pc = value;
826 }
827 }
828
829 static vaddr riscv_cpu_get_pc(CPUState *cs)
830 {
831 RISCVCPU *cpu = RISCV_CPU(cs);
832 CPURISCVState *env = &cpu->env;
833
834 /* Match cpu_get_tb_cpu_state. */
835 if (env->xl == MXL_RV32) {
836 return env->pc & UINT32_MAX;
837 }
838 return env->pc;
839 }
840
841 static void riscv_cpu_synchronize_from_tb(CPUState *cs,
842 const TranslationBlock *tb)
843 {
844 if (!(tb_cflags(tb) & CF_PCREL)) {
845 RISCVCPU *cpu = RISCV_CPU(cs);
846 CPURISCVState *env = &cpu->env;
847 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
848
849 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
850
851 if (xl == MXL_RV32) {
852 env->pc = (int32_t) tb->pc;
853 } else {
854 env->pc = tb->pc;
855 }
856 }
857 }
858
859 static bool riscv_cpu_has_work(CPUState *cs)
860 {
861 #ifndef CONFIG_USER_ONLY
862 RISCVCPU *cpu = RISCV_CPU(cs);
863 CPURISCVState *env = &cpu->env;
864 /*
865 * Definition of the WFI instruction requires it to ignore the privilege
866 * mode and delegation registers, but respect individual enables
867 */
868 return riscv_cpu_all_pending(env) != 0;
869 #else
870 return true;
871 #endif
872 }
873
874 static void riscv_restore_state_to_opc(CPUState *cs,
875 const TranslationBlock *tb,
876 const uint64_t *data)
877 {
878 RISCVCPU *cpu = RISCV_CPU(cs);
879 CPURISCVState *env = &cpu->env;
880 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
881 target_ulong pc;
882
883 if (tb_cflags(tb) & CF_PCREL) {
884 pc = (env->pc & TARGET_PAGE_MASK) | data[0];
885 } else {
886 pc = data[0];
887 }
888
889 if (xl == MXL_RV32) {
890 env->pc = (int32_t)pc;
891 } else {
892 env->pc = pc;
893 }
894 env->bins = data[1];
895 }
896
897 static void riscv_cpu_reset_hold(Object *obj)
898 {
899 #ifndef CONFIG_USER_ONLY
900 uint8_t iprio;
901 int i, irq, rdzero;
902 #endif
903 CPUState *cs = CPU(obj);
904 RISCVCPU *cpu = RISCV_CPU(cs);
905 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
906 CPURISCVState *env = &cpu->env;
907
908 if (mcc->parent_phases.hold) {
909 mcc->parent_phases.hold(obj);
910 }
911 #ifndef CONFIG_USER_ONLY
912 env->misa_mxl = env->misa_mxl_max;
913 env->priv = PRV_M;
914 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
915 if (env->misa_mxl > MXL_RV32) {
916 /*
917 * The reset status of SXL/UXL is undefined, but mstatus is WARL
918 * and we must ensure that the value after init is valid for read.
919 */
920 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
921 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
922 if (riscv_has_ext(env, RVH)) {
923 env->vsstatus = set_field(env->vsstatus,
924 MSTATUS64_SXL, env->misa_mxl);
925 env->vsstatus = set_field(env->vsstatus,
926 MSTATUS64_UXL, env->misa_mxl);
927 env->mstatus_hs = set_field(env->mstatus_hs,
928 MSTATUS64_SXL, env->misa_mxl);
929 env->mstatus_hs = set_field(env->mstatus_hs,
930 MSTATUS64_UXL, env->misa_mxl);
931 }
932 }
933 env->mcause = 0;
934 env->miclaim = MIP_SGEIP;
935 env->pc = env->resetvec;
936 env->bins = 0;
937 env->two_stage_lookup = false;
938
939 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
940 (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0);
941 env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
942 (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0);
943
944 /* Initialized default priorities of local interrupts. */
945 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
946 iprio = riscv_cpu_default_priority(i);
947 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio;
948 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio;
949 env->hviprio[i] = 0;
950 }
951 i = 0;
952 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) {
953 if (!rdzero) {
954 env->hviprio[irq] = env->miprio[irq];
955 }
956 i++;
957 }
958 /* mmte is supposed to have pm.current hardwired to 1 */
959 env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT);
960 #endif
961 env->xl = riscv_cpu_mxl(env);
962 riscv_cpu_update_mask(env);
963 cs->exception_index = RISCV_EXCP_NONE;
964 env->load_res = -1;
965 set_default_nan_mode(1, &env->fp_status);
966
967 #ifndef CONFIG_USER_ONLY
968 if (cpu->cfg.debug) {
969 riscv_trigger_reset_hold(env);
970 }
971
972 if (kvm_enabled()) {
973 kvm_riscv_reset_vcpu(cpu);
974 }
975 #endif
976 }
977
978 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
979 {
980 RISCVCPU *cpu = RISCV_CPU(s);
981 CPURISCVState *env = &cpu->env;
982 info->target_info = &cpu->cfg;
983
984 switch (env->xl) {
985 case MXL_RV32:
986 info->print_insn = print_insn_riscv32;
987 break;
988 case MXL_RV64:
989 info->print_insn = print_insn_riscv64;
990 break;
991 case MXL_RV128:
992 info->print_insn = print_insn_riscv128;
993 break;
994 default:
995 g_assert_not_reached();
996 }
997 }
998
999 void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
1000 {
1001 CPURISCVState *env = &cpu->env;
1002 int i;
1003
1004 /* Force disable extensions if priv spec version does not match */
1005 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
1006 if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) &&
1007 (env->priv_ver < isa_edata_arr[i].min_version)) {
1008 isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset,
1009 false);
1010 #ifndef CONFIG_USER_ONLY
1011 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
1012 " because privilege spec version does not match",
1013 isa_edata_arr[i].name, env->mhartid);
1014 #else
1015 warn_report("disabling %s extension because "
1016 "privilege spec version does not match",
1017 isa_edata_arr[i].name);
1018 #endif
1019 }
1020 }
1021 }
1022
1023 #ifndef CONFIG_USER_ONLY
1024 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
1025 {
1026 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
1027 uint8_t satp_mode_map_max, satp_mode_supported_max;
1028
1029 /* The CPU wants the OS to decide which satp mode to use */
1030 if (cpu->cfg.satp_mode.supported == 0) {
1031 return;
1032 }
1033
1034 satp_mode_supported_max =
1035 satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
1036
1037 if (cpu->cfg.satp_mode.map == 0) {
1038 if (cpu->cfg.satp_mode.init == 0) {
1039 /* If unset by the user, we fallback to the default satp mode. */
1040 set_satp_mode_default_map(cpu);
1041 } else {
1042 /*
1043 * Find the lowest level that was disabled and then enable the
1044 * first valid level below which can be found in
1045 * valid_vm_1_10_32/64.
1046 */
1047 for (int i = 1; i < 16; ++i) {
1048 if ((cpu->cfg.satp_mode.init & (1 << i)) &&
1049 (cpu->cfg.satp_mode.supported & (1 << i))) {
1050 for (int j = i - 1; j >= 0; --j) {
1051 if (cpu->cfg.satp_mode.supported & (1 << j)) {
1052 cpu->cfg.satp_mode.map |= (1 << j);
1053 break;
1054 }
1055 }
1056 break;
1057 }
1058 }
1059 }
1060 }
1061
1062 satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
1063
1064 /* Make sure the user asked for a supported configuration (HW and qemu) */
1065 if (satp_mode_map_max > satp_mode_supported_max) {
1066 error_setg(errp, "satp_mode %s is higher than hw max capability %s",
1067 satp_mode_str(satp_mode_map_max, rv32),
1068 satp_mode_str(satp_mode_supported_max, rv32));
1069 return;
1070 }
1071
1072 /*
1073 * Make sure the user did not ask for an invalid configuration as per
1074 * the specification.
1075 */
1076 if (!rv32) {
1077 for (int i = satp_mode_map_max - 1; i >= 0; --i) {
1078 if (!(cpu->cfg.satp_mode.map & (1 << i)) &&
1079 (cpu->cfg.satp_mode.init & (1 << i)) &&
1080 (cpu->cfg.satp_mode.supported & (1 << i))) {
1081 error_setg(errp, "cannot disable %s satp mode if %s "
1082 "is enabled", satp_mode_str(i, false),
1083 satp_mode_str(satp_mode_map_max, false));
1084 return;
1085 }
1086 }
1087 }
1088
1089 /* Finally expand the map so that all valid modes are set */
1090 for (int i = satp_mode_map_max - 1; i >= 0; --i) {
1091 if (cpu->cfg.satp_mode.supported & (1 << i)) {
1092 cpu->cfg.satp_mode.map |= (1 << i);
1093 }
1094 }
1095 }
1096 #endif
1097
1098 static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
1099 {
1100 #ifndef CONFIG_USER_ONLY
1101 Error *local_err = NULL;
1102
1103 riscv_cpu_satp_mode_finalize(cpu, &local_err);
1104 if (local_err != NULL) {
1105 error_propagate(errp, local_err);
1106 return;
1107 }
1108 #endif
1109 }
1110
1111 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
1112 {
1113 CPUState *cs = CPU(dev);
1114 RISCVCPU *cpu = RISCV_CPU(dev);
1115 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
1116 Error *local_err = NULL;
1117
1118 if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_ANY) != NULL) {
1119 warn_report("The 'any' CPU is deprecated and will be "
1120 "removed in the future.");
1121 }
1122
1123 cpu_exec_realizefn(cs, &local_err);
1124 if (local_err != NULL) {
1125 error_propagate(errp, local_err);
1126 return;
1127 }
1128
1129 riscv_cpu_finalize_features(cpu, &local_err);
1130 if (local_err != NULL) {
1131 error_propagate(errp, local_err);
1132 return;
1133 }
1134
1135 riscv_cpu_register_gdb_regs_for_features(cs);
1136
1137 #ifndef CONFIG_USER_ONLY
1138 if (cpu->cfg.debug) {
1139 riscv_trigger_realize(&cpu->env);
1140 }
1141 #endif
1142
1143 qemu_init_vcpu(cs);
1144 cpu_reset(cs);
1145
1146 mcc->parent_realize(dev, errp);
1147 }
1148
1149 #ifndef CONFIG_USER_ONLY
1150 static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name,
1151 void *opaque, Error **errp)
1152 {
1153 RISCVSATPMap *satp_map = opaque;
1154 uint8_t satp = satp_mode_from_str(name);
1155 bool value;
1156
1157 value = satp_map->map & (1 << satp);
1158
1159 visit_type_bool(v, name, &value, errp);
1160 }
1161
1162 static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name,
1163 void *opaque, Error **errp)
1164 {
1165 RISCVSATPMap *satp_map = opaque;
1166 uint8_t satp = satp_mode_from_str(name);
1167 bool value;
1168
1169 if (!visit_type_bool(v, name, &value, errp)) {
1170 return;
1171 }
1172
1173 satp_map->map = deposit32(satp_map->map, satp, 1, value);
1174 satp_map->init |= 1 << satp;
1175 }
1176
1177 static void riscv_add_satp_mode_properties(Object *obj)
1178 {
1179 RISCVCPU *cpu = RISCV_CPU(obj);
1180
1181 if (cpu->env.misa_mxl == MXL_RV32) {
1182 object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp,
1183 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1184 } else {
1185 object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp,
1186 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1187 object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp,
1188 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1189 object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp,
1190 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1191 object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp,
1192 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1193 }
1194 }
1195
1196 static void riscv_cpu_set_irq(void *opaque, int irq, int level)
1197 {
1198 RISCVCPU *cpu = RISCV_CPU(opaque);
1199 CPURISCVState *env = &cpu->env;
1200
1201 if (irq < IRQ_LOCAL_MAX) {
1202 switch (irq) {
1203 case IRQ_U_SOFT:
1204 case IRQ_S_SOFT:
1205 case IRQ_VS_SOFT:
1206 case IRQ_M_SOFT:
1207 case IRQ_U_TIMER:
1208 case IRQ_S_TIMER:
1209 case IRQ_VS_TIMER:
1210 case IRQ_M_TIMER:
1211 case IRQ_U_EXT:
1212 case IRQ_VS_EXT:
1213 case IRQ_M_EXT:
1214 if (kvm_enabled()) {
1215 kvm_riscv_set_irq(cpu, irq, level);
1216 } else {
1217 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level));
1218 }
1219 break;
1220 case IRQ_S_EXT:
1221 if (kvm_enabled()) {
1222 kvm_riscv_set_irq(cpu, irq, level);
1223 } else {
1224 env->external_seip = level;
1225 riscv_cpu_update_mip(env, 1 << irq,
1226 BOOL_TO_MASK(level | env->software_seip));
1227 }
1228 break;
1229 default:
1230 g_assert_not_reached();
1231 }
1232 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) {
1233 /* Require H-extension for handling guest local interrupts */
1234 if (!riscv_has_ext(env, RVH)) {
1235 g_assert_not_reached();
1236 }
1237
1238 /* Compute bit position in HGEIP CSR */
1239 irq = irq - IRQ_LOCAL_MAX + 1;
1240 if (env->geilen < irq) {
1241 g_assert_not_reached();
1242 }
1243
1244 /* Update HGEIP CSR */
1245 env->hgeip &= ~((target_ulong)1 << irq);
1246 if (level) {
1247 env->hgeip |= (target_ulong)1 << irq;
1248 }
1249
1250 /* Update mip.SGEIP bit */
1251 riscv_cpu_update_mip(env, MIP_SGEIP,
1252 BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
1253 } else {
1254 g_assert_not_reached();
1255 }
1256 }
1257 #endif /* CONFIG_USER_ONLY */
1258
1259 static void riscv_cpu_init(Object *obj)
1260 {
1261 #ifndef CONFIG_USER_ONLY
1262 qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
1263 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
1264 #endif /* CONFIG_USER_ONLY */
1265
1266 multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
1267 }
1268
1269 typedef struct RISCVCPUMisaExtConfig {
1270 const char *name;
1271 const char *description;
1272 target_ulong misa_bit;
1273 bool enabled;
1274 } RISCVCPUMisaExtConfig;
1275
1276 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
1277 void *opaque, Error **errp)
1278 {
1279 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
1280 target_ulong misa_bit = misa_ext_cfg->misa_bit;
1281 RISCVCPU *cpu = RISCV_CPU(obj);
1282 CPURISCVState *env = &cpu->env;
1283 bool value;
1284
1285 if (!visit_type_bool(v, name, &value, errp)) {
1286 return;
1287 }
1288
1289 if (value) {
1290 env->misa_ext |= misa_bit;
1291 env->misa_ext_mask |= misa_bit;
1292 } else {
1293 env->misa_ext &= ~misa_bit;
1294 env->misa_ext_mask &= ~misa_bit;
1295 }
1296 }
1297
1298 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
1299 void *opaque, Error **errp)
1300 {
1301 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
1302 target_ulong misa_bit = misa_ext_cfg->misa_bit;
1303 RISCVCPU *cpu = RISCV_CPU(obj);
1304 CPURISCVState *env = &cpu->env;
1305 bool value;
1306
1307 value = env->misa_ext & misa_bit;
1308
1309 visit_type_bool(v, name, &value, errp);
1310 }
1311
1312 typedef struct misa_ext_info {
1313 const char *name;
1314 const char *description;
1315 } MISAExtInfo;
1316
1317 #define MISA_INFO_IDX(_bit) \
1318 __builtin_ctz(_bit)
1319
1320 #define MISA_EXT_INFO(_bit, _propname, _descr) \
1321 [MISA_INFO_IDX(_bit)] = {.name = _propname, .description = _descr}
1322
1323 static const MISAExtInfo misa_ext_info_arr[] = {
1324 MISA_EXT_INFO(RVA, "a", "Atomic instructions"),
1325 MISA_EXT_INFO(RVC, "c", "Compressed instructions"),
1326 MISA_EXT_INFO(RVD, "d", "Double-precision float point"),
1327 MISA_EXT_INFO(RVF, "f", "Single-precision float point"),
1328 MISA_EXT_INFO(RVI, "i", "Base integer instruction set"),
1329 MISA_EXT_INFO(RVE, "e", "Base integer instruction set (embedded)"),
1330 MISA_EXT_INFO(RVM, "m", "Integer multiplication and division"),
1331 MISA_EXT_INFO(RVS, "s", "Supervisor-level instructions"),
1332 MISA_EXT_INFO(RVU, "u", "User-level instructions"),
1333 MISA_EXT_INFO(RVH, "h", "Hypervisor"),
1334 MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
1335 MISA_EXT_INFO(RVV, "v", "Vector operations"),
1336 MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
1337 };
1338
1339 static int riscv_validate_misa_info_idx(uint32_t bit)
1340 {
1341 int idx;
1342
1343 /*
1344 * Our lowest valid input (RVA) is 1 and
1345 * __builtin_ctz() is UB with zero.
1346 */
1347 g_assert(bit != 0);
1348 idx = MISA_INFO_IDX(bit);
1349
1350 g_assert(idx < ARRAY_SIZE(misa_ext_info_arr));
1351 return idx;
1352 }
1353
1354 const char *riscv_get_misa_ext_name(uint32_t bit)
1355 {
1356 int idx = riscv_validate_misa_info_idx(bit);
1357 const char *val = misa_ext_info_arr[idx].name;
1358
1359 g_assert(val != NULL);
1360 return val;
1361 }
1362
1363 const char *riscv_get_misa_ext_description(uint32_t bit)
1364 {
1365 int idx = riscv_validate_misa_info_idx(bit);
1366 const char *val = misa_ext_info_arr[idx].description;
1367
1368 g_assert(val != NULL);
1369 return val;
1370 }
1371
1372 #define MISA_CFG(_bit, _enabled) \
1373 {.misa_bit = _bit, .enabled = _enabled}
1374
1375 static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
1376 MISA_CFG(RVA, true),
1377 MISA_CFG(RVC, true),
1378 MISA_CFG(RVD, true),
1379 MISA_CFG(RVF, true),
1380 MISA_CFG(RVI, true),
1381 MISA_CFG(RVE, false),
1382 MISA_CFG(RVM, true),
1383 MISA_CFG(RVS, true),
1384 MISA_CFG(RVU, true),
1385 MISA_CFG(RVH, true),
1386 MISA_CFG(RVJ, false),
1387 MISA_CFG(RVV, false),
1388 MISA_CFG(RVG, false),
1389 };
1390
1391 /*
1392 * We do not support user choice tracking for MISA
1393 * extensions yet because, so far, we do not silently
1394 * change MISA bits during realize() (RVG enables MISA
1395 * bits but the user is warned about it).
1396 */
1397 static void riscv_cpu_add_misa_properties(Object *cpu_obj)
1398 {
1399 int i;
1400
1401 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
1402 RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
1403 int bit = misa_cfg->misa_bit;
1404
1405 misa_cfg->name = riscv_get_misa_ext_name(bit);
1406 misa_cfg->description = riscv_get_misa_ext_description(bit);
1407
1408 /* Check if KVM already created the property */
1409 if (object_property_find(cpu_obj, misa_cfg->name)) {
1410 continue;
1411 }
1412
1413 object_property_add(cpu_obj, misa_cfg->name, "bool",
1414 cpu_get_misa_ext_cfg,
1415 cpu_set_misa_ext_cfg,
1416 NULL, (void *)misa_cfg);
1417 object_property_set_description(cpu_obj, misa_cfg->name,
1418 misa_cfg->description);
1419 object_property_set_bool(cpu_obj, misa_cfg->name,
1420 misa_cfg->enabled, NULL);
1421 }
1422 }
1423
1424 typedef struct RISCVCPUMultiExtConfig {
1425 const char *name;
1426 uint32_t offset;
1427 bool enabled;
1428 } RISCVCPUMultiExtConfig;
1429
1430 #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
1431 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
1432 .enabled = _defval}
1433
1434 static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
1435 /* Defaults for standard extensions */
1436 MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
1437 MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
1438 MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
1439 MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
1440 MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
1441 MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
1442 MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true),
1443 MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false),
1444 MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false),
1445 MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false),
1446 MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
1447 MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
1448 MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
1449
1450 MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
1451 MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
1452 MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
1453 MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
1454 MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
1455
1456 MULTI_EXT_CFG_BOOL("zba", ext_zba, true),
1457 MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true),
1458 MULTI_EXT_CFG_BOOL("zbc", ext_zbc, true),
1459 MULTI_EXT_CFG_BOOL("zbkb", ext_zbkb, false),
1460 MULTI_EXT_CFG_BOOL("zbkc", ext_zbkc, false),
1461 MULTI_EXT_CFG_BOOL("zbkx", ext_zbkx, false),
1462 MULTI_EXT_CFG_BOOL("zbs", ext_zbs, true),
1463 MULTI_EXT_CFG_BOOL("zk", ext_zk, false),
1464 MULTI_EXT_CFG_BOOL("zkn", ext_zkn, false),
1465 MULTI_EXT_CFG_BOOL("zknd", ext_zknd, false),
1466 MULTI_EXT_CFG_BOOL("zkne", ext_zkne, false),
1467 MULTI_EXT_CFG_BOOL("zknh", ext_zknh, false),
1468 MULTI_EXT_CFG_BOOL("zkr", ext_zkr, false),
1469 MULTI_EXT_CFG_BOOL("zks", ext_zks, false),
1470 MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false),
1471 MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false),
1472 MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false),
1473
1474 MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false),
1475 MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false),
1476 MULTI_EXT_CFG_BOOL("zhinx", ext_zhinx, false),
1477 MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false),
1478
1479 MULTI_EXT_CFG_BOOL("zicbom", ext_icbom, true),
1480 MULTI_EXT_CFG_BOOL("zicboz", ext_icboz, true),
1481
1482 MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
1483
1484 MULTI_EXT_CFG_BOOL("zca", ext_zca, false),
1485 MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false),
1486 MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false),
1487 MULTI_EXT_CFG_BOOL("zce", ext_zce, false),
1488 MULTI_EXT_CFG_BOOL("zcf", ext_zcf, false),
1489 MULTI_EXT_CFG_BOOL("zcmp", ext_zcmp, false),
1490 MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false),
1491 MULTI_EXT_CFG_BOOL("zicond", ext_zicond, false),
1492
1493 DEFINE_PROP_END_OF_LIST(),
1494 };
1495
1496 static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
1497 MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
1498 MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
1499 MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
1500 MULTI_EXT_CFG_BOOL("xtheadcmo", ext_xtheadcmo, false),
1501 MULTI_EXT_CFG_BOOL("xtheadcondmov", ext_xtheadcondmov, false),
1502 MULTI_EXT_CFG_BOOL("xtheadfmemidx", ext_xtheadfmemidx, false),
1503 MULTI_EXT_CFG_BOOL("xtheadfmv", ext_xtheadfmv, false),
1504 MULTI_EXT_CFG_BOOL("xtheadmac", ext_xtheadmac, false),
1505 MULTI_EXT_CFG_BOOL("xtheadmemidx", ext_xtheadmemidx, false),
1506 MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false),
1507 MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false),
1508 MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
1509
1510 DEFINE_PROP_END_OF_LIST(),
1511 };
1512
1513 /* These are experimental so mark with 'x-' */
1514 static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
1515 /* ePMP 0.9.3 */
1516 MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
1517 MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
1518 MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false),
1519
1520 MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false),
1521 MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false),
1522
1523 MULTI_EXT_CFG_BOOL("x-zfbfmin", ext_zfbfmin, false),
1524 MULTI_EXT_CFG_BOOL("x-zvfbfmin", ext_zvfbfmin, false),
1525 MULTI_EXT_CFG_BOOL("x-zvfbfwma", ext_zvfbfwma, false),
1526
1527 /* Vector cryptography extensions */
1528 MULTI_EXT_CFG_BOOL("x-zvbb", ext_zvbb, false),
1529 MULTI_EXT_CFG_BOOL("x-zvbc", ext_zvbc, false),
1530 MULTI_EXT_CFG_BOOL("x-zvkg", ext_zvkg, false),
1531 MULTI_EXT_CFG_BOOL("x-zvkned", ext_zvkned, false),
1532 MULTI_EXT_CFG_BOOL("x-zvknha", ext_zvknha, false),
1533 MULTI_EXT_CFG_BOOL("x-zvknhb", ext_zvknhb, false),
1534 MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false),
1535 MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false),
1536
1537 DEFINE_PROP_END_OF_LIST(),
1538 };
1539
1540 static Property riscv_cpu_options[] = {
1541 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
1542
1543 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
1544 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
1545
1546 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
1547 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
1548
1549 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
1550 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
1551
1552 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
1553 DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
1554
1555 DEFINE_PROP_END_OF_LIST(),
1556 };
1557
1558 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
1559 void *opaque, Error **errp)
1560 {
1561 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
1562 bool value;
1563
1564 if (!visit_type_bool(v, name, &value, errp)) {
1565 return;
1566 }
1567
1568 isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
1569
1570 g_hash_table_insert(multi_ext_user_opts,
1571 GUINT_TO_POINTER(multi_ext_cfg->offset),
1572 (gpointer)value);
1573 }
1574
1575 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
1576 void *opaque, Error **errp)
1577 {
1578 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
1579 bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
1580
1581 visit_type_bool(v, name, &value, errp);
1582 }
1583
1584 static void cpu_add_multi_ext_prop(Object *cpu_obj,
1585 RISCVCPUMultiExtConfig *multi_cfg)
1586 {
1587 object_property_add(cpu_obj, multi_cfg->name, "bool",
1588 cpu_get_multi_ext_cfg,
1589 cpu_set_multi_ext_cfg,
1590 NULL, (void *)multi_cfg);
1591
1592 /*
1593 * Set def val directly instead of using
1594 * object_property_set_bool() to save the set()
1595 * callback hash for user inputs.
1596 */
1597 isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
1598 multi_cfg->enabled);
1599 }
1600
1601 static void riscv_cpu_add_multiext_prop_array(Object *obj,
1602 RISCVCPUMultiExtConfig *array)
1603 {
1604 g_assert(array);
1605
1606 for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
1607 cpu_add_multi_ext_prop(obj, prop);
1608 }
1609 }
1610
1611 #ifdef CONFIG_KVM
1612 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
1613 const char *name,
1614 void *opaque, Error **errp)
1615 {
1616 const char *propname = opaque;
1617 bool value;
1618
1619 if (!visit_type_bool(v, name, &value, errp)) {
1620 return;
1621 }
1622
1623 if (value) {
1624 error_setg(errp, "extension %s is not available with KVM",
1625 propname);
1626 }
1627 }
1628
1629 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
1630 {
1631 /* Check if KVM created the property already */
1632 if (object_property_find(obj, prop_name)) {
1633 return;
1634 }
1635
1636 /*
1637 * Set the default to disabled for every extension
1638 * unknown to KVM and error out if the user attempts
1639 * to enable any of them.
1640 */
1641 object_property_add(obj, prop_name, "bool",
1642 NULL, cpu_set_cfg_unavailable,
1643 NULL, (void *)prop_name);
1644 }
1645
1646 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
1647 RISCVCPUMultiExtConfig *array)
1648 {
1649 g_assert(array);
1650
1651 for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
1652 riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
1653 }
1654 }
1655
1656 void kvm_riscv_cpu_add_kvm_properties(Object *obj)
1657 {
1658 Property *prop;
1659 DeviceState *dev = DEVICE(obj);
1660
1661 kvm_riscv_init_user_properties(obj);
1662 riscv_cpu_add_misa_properties(obj);
1663
1664 riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
1665 riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
1666 riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
1667
1668 for (prop = riscv_cpu_options; prop && prop->name; prop++) {
1669 /* Check if KVM created the property already */
1670 if (object_property_find(obj, prop->name)) {
1671 continue;
1672 }
1673 qdev_property_add_static(dev, prop);
1674 }
1675 }
1676 #endif
1677
1678 /*
1679 * Add CPU properties with user-facing flags.
1680 *
1681 * This will overwrite existing env->misa_ext values with the
1682 * defaults set via riscv_cpu_add_misa_properties().
1683 */
1684 static void riscv_cpu_add_user_properties(Object *obj)
1685 {
1686 #ifndef CONFIG_USER_ONLY
1687 riscv_add_satp_mode_properties(obj);
1688
1689 if (kvm_enabled()) {
1690 kvm_riscv_cpu_add_kvm_properties(obj);
1691 return;
1692 }
1693 #endif
1694
1695 riscv_cpu_add_misa_properties(obj);
1696
1697 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
1698 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
1699 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
1700
1701 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
1702 qdev_property_add_static(DEVICE(obj), prop);
1703 }
1704 }
1705
1706 /*
1707 * The 'max' type CPU will have all possible ratified
1708 * non-vendor extensions enabled.
1709 */
1710 static void riscv_init_max_cpu_extensions(Object *obj)
1711 {
1712 RISCVCPU *cpu = RISCV_CPU(obj);
1713 CPURISCVState *env = &cpu->env;
1714 RISCVCPUMultiExtConfig *prop;
1715
1716 /* Enable RVG, RVJ and RVV that are disabled by default */
1717 set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
1718
1719 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
1720 isa_ext_update_enabled(cpu, prop->offset, true);
1721 }
1722
1723 /* set vector version */
1724 env->vext_ver = VEXT_VERSION_1_00_0;
1725
1726 /* Zfinx is not compatible with F. Disable it */
1727 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
1728 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
1729 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
1730 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
1731
1732 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
1733 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
1734 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
1735
1736 if (env->misa_mxl != MXL_RV32) {
1737 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
1738 }
1739 }
1740
1741 static Property riscv_cpu_properties[] = {
1742 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
1743
1744 #ifndef CONFIG_USER_ONLY
1745 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
1746 #endif
1747
1748 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
1749
1750 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
1751 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false),
1752
1753 /*
1754 * write_misa() is marked as experimental for now so mark
1755 * it with -x and default to 'false'.
1756 */
1757 DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
1758 DEFINE_PROP_END_OF_LIST(),
1759 };
1760
1761 static const gchar *riscv_gdb_arch_name(CPUState *cs)
1762 {
1763 RISCVCPU *cpu = RISCV_CPU(cs);
1764 CPURISCVState *env = &cpu->env;
1765
1766 switch (riscv_cpu_mxl(env)) {
1767 case MXL_RV32:
1768 return "riscv:rv32";
1769 case MXL_RV64:
1770 case MXL_RV128:
1771 return "riscv:rv64";
1772 default:
1773 g_assert_not_reached();
1774 }
1775 }
1776
1777 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
1778 {
1779 RISCVCPU *cpu = RISCV_CPU(cs);
1780
1781 if (strcmp(xmlname, "riscv-csr.xml") == 0) {
1782 return cpu->dyn_csr_xml;
1783 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) {
1784 return cpu->dyn_vreg_xml;
1785 }
1786
1787 return NULL;
1788 }
1789
1790 #ifndef CONFIG_USER_ONLY
1791 static int64_t riscv_get_arch_id(CPUState *cs)
1792 {
1793 RISCVCPU *cpu = RISCV_CPU(cs);
1794
1795 return cpu->env.mhartid;
1796 }
1797
1798 #include "hw/core/sysemu-cpu-ops.h"
1799
1800 static const struct SysemuCPUOps riscv_sysemu_ops = {
1801 .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
1802 .write_elf64_note = riscv_cpu_write_elf64_note,
1803 .write_elf32_note = riscv_cpu_write_elf32_note,
1804 .legacy_vmsd = &vmstate_riscv_cpu,
1805 };
1806 #endif
1807
1808 const struct TCGCPUOps riscv_tcg_ops = {
1809 .initialize = riscv_translate_init,
1810 .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
1811 .restore_state_to_opc = riscv_restore_state_to_opc,
1812
1813 #ifndef CONFIG_USER_ONLY
1814 .tlb_fill = riscv_cpu_tlb_fill,
1815 .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
1816 .do_interrupt = riscv_cpu_do_interrupt,
1817 .do_transaction_failed = riscv_cpu_do_transaction_failed,
1818 .do_unaligned_access = riscv_cpu_do_unaligned_access,
1819 .debug_excp_handler = riscv_cpu_debug_excp_handler,
1820 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
1821 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
1822 #endif /* !CONFIG_USER_ONLY */
1823 };
1824
1825 static bool riscv_cpu_is_dynamic(Object *cpu_obj)
1826 {
1827 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
1828 }
1829
1830 static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name,
1831 void *opaque, Error **errp)
1832 {
1833 bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
1834 RISCVCPU *cpu = RISCV_CPU(obj);
1835 uint32_t prev_val = cpu->cfg.mvendorid;
1836 uint32_t value;
1837
1838 if (!visit_type_uint32(v, name, &value, errp)) {
1839 return;
1840 }
1841
1842 if (!dynamic_cpu && prev_val != value) {
1843 error_setg(errp, "Unable to change %s mvendorid (0x%x)",
1844 object_get_typename(obj), prev_val);
1845 return;
1846 }
1847
1848 cpu->cfg.mvendorid = value;
1849 }
1850
1851 static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name,
1852 void *opaque, Error **errp)
1853 {
1854 bool value = RISCV_CPU(obj)->cfg.mvendorid;
1855
1856 visit_type_bool(v, name, &value, errp);
1857 }
1858
1859 static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name,
1860 void *opaque, Error **errp)
1861 {
1862 bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
1863 RISCVCPU *cpu = RISCV_CPU(obj);
1864 uint64_t prev_val = cpu->cfg.mimpid;
1865 uint64_t value;
1866
1867 if (!visit_type_uint64(v, name, &value, errp)) {
1868 return;
1869 }
1870
1871 if (!dynamic_cpu && prev_val != value) {
1872 error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")",
1873 object_get_typename(obj), prev_val);
1874 return;
1875 }
1876
1877 cpu->cfg.mimpid = value;
1878 }
1879
1880 static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name,
1881 void *opaque, Error **errp)
1882 {
1883 bool value = RISCV_CPU(obj)->cfg.mimpid;
1884
1885 visit_type_bool(v, name, &value, errp);
1886 }
1887
1888 static void cpu_set_marchid(Object *obj, Visitor *v, const char *name,
1889 void *opaque, Error **errp)
1890 {
1891 bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
1892 RISCVCPU *cpu = RISCV_CPU(obj);
1893 uint64_t prev_val = cpu->cfg.marchid;
1894 uint64_t value, invalid_val;
1895 uint32_t mxlen = 0;
1896
1897 if (!visit_type_uint64(v, name, &value, errp)) {
1898 return;
1899 }
1900
1901 if (!dynamic_cpu && prev_val != value) {
1902 error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")",
1903 object_get_typename(obj), prev_val);
1904 return;
1905 }
1906
1907 switch (riscv_cpu_mxl(&cpu->env)) {
1908 case MXL_RV32:
1909 mxlen = 32;
1910 break;
1911 case MXL_RV64:
1912 case MXL_RV128:
1913 mxlen = 64;
1914 break;
1915 default:
1916 g_assert_not_reached();
1917 }
1918
1919 invalid_val = 1LL << (mxlen - 1);
1920
1921 if (value == invalid_val) {
1922 error_setg(errp, "Unable to set marchid with MSB (%u) bit set "
1923 "and the remaining bits zero", mxlen);
1924 return;
1925 }
1926
1927 cpu->cfg.marchid = value;
1928 }
1929
1930 static void cpu_get_marchid(Object *obj, Visitor *v, const char *name,
1931 void *opaque, Error **errp)
1932 {
1933 bool value = RISCV_CPU(obj)->cfg.marchid;
1934
1935 visit_type_bool(v, name, &value, errp);
1936 }
1937
1938 static void riscv_cpu_class_init(ObjectClass *c, void *data)
1939 {
1940 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
1941 CPUClass *cc = CPU_CLASS(c);
1942 DeviceClass *dc = DEVICE_CLASS(c);
1943 ResettableClass *rc = RESETTABLE_CLASS(c);
1944
1945 device_class_set_parent_realize(dc, riscv_cpu_realize,
1946 &mcc->parent_realize);
1947
1948 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL,
1949 &mcc->parent_phases);
1950
1951 cc->class_by_name = riscv_cpu_class_by_name;
1952 cc->has_work = riscv_cpu_has_work;
1953 cc->dump_state = riscv_cpu_dump_state;
1954 cc->set_pc = riscv_cpu_set_pc;
1955 cc->get_pc = riscv_cpu_get_pc;
1956 cc->gdb_read_register = riscv_cpu_gdb_read_register;
1957 cc->gdb_write_register = riscv_cpu_gdb_write_register;
1958 cc->gdb_num_core_regs = 33;
1959 cc->gdb_stop_before_watchpoint = true;
1960 cc->disas_set_info = riscv_cpu_disas_set_info;
1961 #ifndef CONFIG_USER_ONLY
1962 cc->sysemu_ops = &riscv_sysemu_ops;
1963 cc->get_arch_id = riscv_get_arch_id;
1964 #endif
1965 cc->gdb_arch_name = riscv_gdb_arch_name;
1966 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
1967
1968 object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid,
1969 cpu_set_mvendorid, NULL, NULL);
1970
1971 object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid,
1972 cpu_set_mimpid, NULL, NULL);
1973
1974 object_class_property_add(c, "marchid", "uint64", cpu_get_marchid,
1975 cpu_set_marchid, NULL, NULL);
1976
1977 device_class_set_props(dc, riscv_cpu_properties);
1978 }
1979
1980 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
1981 int max_str_len)
1982 {
1983 char *old = *isa_str;
1984 char *new = *isa_str;
1985 int i;
1986
1987 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
1988 if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) {
1989 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
1990 g_free(old);
1991 old = new;
1992 }
1993 }
1994
1995 *isa_str = new;
1996 }
1997
1998 char *riscv_isa_string(RISCVCPU *cpu)
1999 {
2000 int i;
2001 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts);
2002 char *isa_str = g_new(char, maxlen);
2003 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
2004 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {
2005 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) {
2006 *p++ = qemu_tolower(riscv_single_letter_exts[i]);
2007 }
2008 }
2009 *p = '\0';
2010 if (!cpu->cfg.short_isa_string) {
2011 riscv_isa_string_ext(cpu, &isa_str, maxlen);
2012 }
2013 return isa_str;
2014 }
2015
2016 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
2017 {
2018 ObjectClass *class_a = (ObjectClass *)a;
2019 ObjectClass *class_b = (ObjectClass *)b;
2020 const char *name_a, *name_b;
2021
2022 name_a = object_class_get_name(class_a);
2023 name_b = object_class_get_name(class_b);
2024 return strcmp(name_a, name_b);
2025 }
2026
2027 static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
2028 {
2029 const char *typename = object_class_get_name(OBJECT_CLASS(data));
2030 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
2031
2032 qemu_printf("%.*s\n", len, typename);
2033 }
2034
2035 void riscv_cpu_list(void)
2036 {
2037 GSList *list;
2038
2039 list = object_class_get_list(TYPE_RISCV_CPU, false);
2040 list = g_slist_sort(list, riscv_cpu_list_compare);
2041 g_slist_foreach(list, riscv_cpu_list_entry, NULL);
2042 g_slist_free(list);
2043 }
2044
2045 #define DEFINE_CPU(type_name, initfn) \
2046 { \
2047 .name = type_name, \
2048 .parent = TYPE_RISCV_CPU, \
2049 .instance_init = initfn \
2050 }
2051
2052 #define DEFINE_DYNAMIC_CPU(type_name, initfn) \
2053 { \
2054 .name = type_name, \
2055 .parent = TYPE_RISCV_DYNAMIC_CPU, \
2056 .instance_init = initfn \
2057 }
2058
2059 static const TypeInfo riscv_cpu_type_infos[] = {
2060 {
2061 .name = TYPE_RISCV_CPU,
2062 .parent = TYPE_CPU,
2063 .instance_size = sizeof(RISCVCPU),
2064 .instance_align = __alignof(RISCVCPU),
2065 .instance_init = riscv_cpu_init,
2066 .abstract = true,
2067 .class_size = sizeof(RISCVCPUClass),
2068 .class_init = riscv_cpu_class_init,
2069 },
2070 {
2071 .name = TYPE_RISCV_DYNAMIC_CPU,
2072 .parent = TYPE_RISCV_CPU,
2073 .abstract = true,
2074 },
2075 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
2076 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init),
2077 #if defined(CONFIG_KVM)
2078 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
2079 #endif
2080 #if defined(TARGET_RISCV32)
2081 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
2082 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
2083 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
2084 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
2085 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
2086 #elif defined(TARGET_RISCV64)
2087 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
2088 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
2089 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
2090 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
2091 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
2092 DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),
2093 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
2094 #endif
2095 };
2096
2097 DEFINE_TYPES(riscv_cpu_type_infos)
AR7 emulation for QEMU