4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/error-report.h"
23 #include "qapi/error.h"
25 #include "internals.h"
26 #include "qemu-common.h"
27 #include "exec/exec-all.h"
28 #include "hw/qdev-properties.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/loader.h"
32 #include "hw/arm/arm.h"
33 #include "sysemu/sysemu.h"
34 #include "sysemu/hw_accel.h"
37 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
39 ARMCPU
*cpu
= ARM_CPU(cs
);
41 cpu
->env
.regs
[15] = value
;
44 static bool arm_cpu_has_work(CPUState
*cs
)
46 ARMCPU
*cpu
= ARM_CPU(cs
);
48 return (cpu
->power_state
!= PSCI_OFF
)
49 && cs
->interrupt_request
&
50 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
51 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
52 | CPU_INTERRUPT_EXITTB
);
55 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHook
*hook
,
58 /* We currently only support registering a single hook function */
59 assert(!cpu
->el_change_hook
);
60 cpu
->el_change_hook
= hook
;
61 cpu
->el_change_hook_opaque
= opaque
;
64 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
66 /* Reset a single ARMCPRegInfo register */
67 ARMCPRegInfo
*ri
= value
;
70 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
75 ri
->resetfn(&cpu
->env
, ri
);
79 /* A zero offset is never possible as it would be regs[0]
80 * so we use it to indicate that reset is being handled elsewhere.
81 * This is basically only used for fields in non-core coprocessors
82 * (like the pxa2xx ones).
84 if (!ri
->fieldoffset
) {
88 if (cpreg_field_is_64bit(ri
)) {
89 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
91 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
95 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
97 /* Purely an assertion check: we've already done reset once,
98 * so now check that running the reset for the cpreg doesn't
99 * change its value. This traps bugs where two different cpregs
100 * both try to reset the same state field but to different values.
102 ARMCPRegInfo
*ri
= value
;
103 ARMCPU
*cpu
= opaque
;
104 uint64_t oldvalue
, newvalue
;
106 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
110 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
111 cp_reg_reset(key
, value
, opaque
);
112 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
113 assert(oldvalue
== newvalue
);
116 /* CPUClass::reset() */
117 static void arm_cpu_reset(CPUState
*s
)
119 ARMCPU
*cpu
= ARM_CPU(s
);
120 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
121 CPUARMState
*env
= &cpu
->env
;
123 acc
->parent_reset(s
);
125 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
127 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
128 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
130 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
131 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->mvfr0
;
132 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->mvfr1
;
133 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->mvfr2
;
135 cpu
->power_state
= cpu
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
136 s
->halted
= cpu
->start_powered_off
;
138 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
139 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
142 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
143 /* 64 bit CPUs always start in 64 bit mode */
145 #if defined(CONFIG_USER_ONLY)
146 env
->pstate
= PSTATE_MODE_EL0t
;
147 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
148 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
149 /* and to the FP/Neon instructions */
150 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
152 /* Reset into the highest available EL */
153 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
154 env
->pstate
= PSTATE_MODE_EL3h
;
155 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
156 env
->pstate
= PSTATE_MODE_EL2h
;
158 env
->pstate
= PSTATE_MODE_EL1h
;
160 env
->pc
= cpu
->rvbar
;
163 #if defined(CONFIG_USER_ONLY)
164 /* Userspace expects access to cp10 and cp11 for FP/Neon */
165 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
169 #if defined(CONFIG_USER_ONLY)
170 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
171 /* For user mode we must enable access to coprocessors */
172 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
173 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
174 env
->cp15
.c15_cpar
= 3;
175 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
176 env
->cp15
.c15_cpar
= 1;
179 /* SVC mode with interrupts disabled. */
180 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
181 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
183 if (arm_feature(env
, ARM_FEATURE_M
)) {
184 uint32_t initial_msp
; /* Loaded from 0x0 */
185 uint32_t initial_pc
; /* Loaded from 0x4 */
188 /* For M profile we store FAULTMASK and PRIMASK in the
189 * PSTATE F and I bits; these are both clear at reset.
191 env
->daif
&= ~(PSTATE_I
| PSTATE_F
);
193 /* The reset value of this bit is IMPDEF, but ARM recommends
194 * that it resets to 1, so QEMU always does that rather than making
195 * it dependent on CPU model.
197 env
->v7m
.ccr
= R_V7M_CCR_STKALIGN_MASK
;
199 /* Unlike A/R profile, M profile defines the reset LR value */
200 env
->regs
[14] = 0xffffffff;
202 /* Load the initial SP and PC from the vector table at address 0 */
205 /* Address zero is covered by ROM which hasn't yet been
206 * copied into physical memory.
208 initial_msp
= ldl_p(rom
);
209 initial_pc
= ldl_p(rom
+ 4);
211 /* Address zero not covered by a ROM blob, or the ROM blob
212 * is in non-modifiable memory and this is a second reset after
213 * it got copied into memory. In the latter case, rom_ptr
214 * will return a NULL pointer and we should use ldl_phys instead.
216 initial_msp
= ldl_phys(s
->as
, 0);
217 initial_pc
= ldl_phys(s
->as
, 4);
220 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
221 env
->regs
[15] = initial_pc
& ~1;
222 env
->thumb
= initial_pc
& 1;
225 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
226 * executing as AArch32 then check if highvecs are enabled and
227 * adjust the PC accordingly.
229 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
230 env
->regs
[15] = 0xFFFF0000;
233 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
235 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
236 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
237 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
238 set_float_detect_tininess(float_tininess_before_rounding
,
239 &env
->vfp
.fp_status
);
240 set_float_detect_tininess(float_tininess_before_rounding
,
241 &env
->vfp
.standard_fp_status
);
242 #ifndef CONFIG_USER_ONLY
244 kvm_arm_reset_vcpu(cpu
);
248 hw_breakpoint_update_all(cpu
);
249 hw_watchpoint_update_all(cpu
);
252 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
254 CPUClass
*cc
= CPU_GET_CLASS(cs
);
255 CPUARMState
*env
= cs
->env_ptr
;
256 uint32_t cur_el
= arm_current_el(env
);
257 bool secure
= arm_is_secure(env
);
262 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
264 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
265 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
266 cs
->exception_index
= excp_idx
;
267 env
->exception
.target_el
= target_el
;
268 cc
->do_interrupt(cs
);
272 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
274 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
275 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
276 cs
->exception_index
= excp_idx
;
277 env
->exception
.target_el
= target_el
;
278 cc
->do_interrupt(cs
);
282 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
283 excp_idx
= EXCP_VIRQ
;
285 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
286 cs
->exception_index
= excp_idx
;
287 env
->exception
.target_el
= target_el
;
288 cc
->do_interrupt(cs
);
292 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
293 excp_idx
= EXCP_VFIQ
;
295 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
296 cs
->exception_index
= excp_idx
;
297 env
->exception
.target_el
= target_el
;
298 cc
->do_interrupt(cs
);
306 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
307 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
309 CPUClass
*cc
= CPU_GET_CLASS(cs
);
310 ARMCPU
*cpu
= ARM_CPU(cs
);
311 CPUARMState
*env
= &cpu
->env
;
314 /* ARMv7-M interrupt masking works differently than -A or -R.
315 * There is no FIQ/IRQ distinction. Instead of I and F bits
316 * masking FIQ and IRQ interrupts, an exception is taken only
317 * if it is higher priority than the current execution priority
318 * (which depends on state like BASEPRI, FAULTMASK and the
319 * currently active exception).
321 if (interrupt_request
& CPU_INTERRUPT_HARD
322 && (armv7m_nvic_can_take_pending_exception(env
->nvic
))) {
323 cs
->exception_index
= EXCP_IRQ
;
324 cc
->do_interrupt(cs
);
331 #ifndef CONFIG_USER_ONLY
332 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
334 ARMCPU
*cpu
= opaque
;
335 CPUARMState
*env
= &cpu
->env
;
336 CPUState
*cs
= CPU(cpu
);
337 static const int mask
[] = {
338 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
339 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
340 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
341 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
347 assert(arm_feature(env
, ARM_FEATURE_EL2
));
352 cpu_interrupt(cs
, mask
[irq
]);
354 cpu_reset_interrupt(cs
, mask
[irq
]);
358 g_assert_not_reached();
362 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
365 ARMCPU
*cpu
= opaque
;
366 CPUState
*cs
= CPU(cpu
);
367 int kvm_irq
= KVM_ARM_IRQ_TYPE_CPU
<< KVM_ARM_IRQ_TYPE_SHIFT
;
371 kvm_irq
|= KVM_ARM_IRQ_CPU_IRQ
;
374 kvm_irq
|= KVM_ARM_IRQ_CPU_FIQ
;
377 g_assert_not_reached();
379 kvm_irq
|= cs
->cpu_index
<< KVM_ARM_IRQ_VCPU_SHIFT
;
380 kvm_set_irq(kvm_state
, kvm_irq
, level
? 1 : 0);
384 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
386 ARMCPU
*cpu
= ARM_CPU(cs
);
387 CPUARMState
*env
= &cpu
->env
;
389 cpu_synchronize_state(cs
);
390 return arm_cpu_data_is_big_endian(env
);
395 static inline void set_feature(CPUARMState
*env
, int feature
)
397 env
->features
|= 1ULL << feature
;
400 static inline void unset_feature(CPUARMState
*env
, int feature
)
402 env
->features
&= ~(1ULL << feature
);
406 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
408 return print_insn_arm(pc
| 1, info
);
411 static int arm_read_memory_func(bfd_vma memaddr
, bfd_byte
*b
,
412 int length
, struct disassemble_info
*info
)
414 assert(info
->read_memory_inner_func
);
415 assert((info
->flags
& INSN_ARM_BE32
) == 0 || length
== 2 || length
== 4);
417 if ((info
->flags
& INSN_ARM_BE32
) != 0 && length
== 2) {
418 assert(info
->endian
== BFD_ENDIAN_LITTLE
);
419 return info
->read_memory_inner_func(memaddr
^ 2, (bfd_byte
*)b
, 2,
422 return info
->read_memory_inner_func(memaddr
, b
, length
, info
);
426 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
428 ARMCPU
*ac
= ARM_CPU(cpu
);
429 CPUARMState
*env
= &ac
->env
;
432 /* We might not be compiled with the A64 disassembler
433 * because it needs a C++ compiler. Leave print_insn
434 * unset in this case to use the caller default behaviour.
436 #if defined(CONFIG_ARM_A64_DIS)
437 info
->print_insn
= print_insn_arm_a64
;
439 } else if (env
->thumb
) {
440 info
->print_insn
= print_insn_thumb1
;
442 info
->print_insn
= print_insn_arm
;
444 if (bswap_code(arm_sctlr_b(env
))) {
445 #ifdef TARGET_WORDS_BIGENDIAN
446 info
->endian
= BFD_ENDIAN_LITTLE
;
448 info
->endian
= BFD_ENDIAN_BIG
;
451 if (info
->read_memory_inner_func
== NULL
) {
452 info
->read_memory_inner_func
= info
->read_memory_func
;
453 info
->read_memory_func
= arm_read_memory_func
;
455 info
->flags
&= ~INSN_ARM_BE32
;
456 if (arm_sctlr_b(env
)) {
457 info
->flags
|= INSN_ARM_BE32
;
461 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
463 uint32_t Aff1
= idx
/ clustersz
;
464 uint32_t Aff0
= idx
% clustersz
;
465 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
468 static void arm_cpu_initfn(Object
*obj
)
470 CPUState
*cs
= CPU(obj
);
471 ARMCPU
*cpu
= ARM_CPU(obj
);
474 cs
->env_ptr
= &cpu
->env
;
475 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
478 #ifndef CONFIG_USER_ONLY
479 /* Our inbound IRQ and FIQ lines */
481 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
482 * the same interface as non-KVM CPUs.
484 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
486 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
489 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
490 arm_gt_ptimer_cb
, cpu
);
491 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
492 arm_gt_vtimer_cb
, cpu
);
493 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
494 arm_gt_htimer_cb
, cpu
);
495 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
496 arm_gt_stimer_cb
, cpu
);
497 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
498 ARRAY_SIZE(cpu
->gt_timer_outputs
));
500 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
501 "gicv3-maintenance-interrupt", 1);
504 /* DTB consumers generally don't in fact care what the 'compatible'
505 * string is, so always provide some string and trust that a hypothetical
506 * picky DTB consumer will also provide a helpful error message.
508 cpu
->dtb_compatible
= "qemu,unknown";
509 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
510 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
513 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
516 arm_translate_init();
521 static Property arm_cpu_reset_cbar_property
=
522 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
524 static Property arm_cpu_reset_hivecs_property
=
525 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
527 static Property arm_cpu_rvbar_property
=
528 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
530 static Property arm_cpu_has_el2_property
=
531 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
533 static Property arm_cpu_has_el3_property
=
534 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
536 static Property arm_cpu_cfgend_property
=
537 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
539 /* use property name "pmu" to match other archs and virt tools */
540 static Property arm_cpu_has_pmu_property
=
541 DEFINE_PROP_BOOL("pmu", ARMCPU
, has_pmu
, true);
543 static Property arm_cpu_has_mpu_property
=
544 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
546 static Property arm_cpu_pmsav7_dregion_property
=
547 DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU
, pmsav7_dregion
, 16);
549 static void arm_cpu_post_init(Object
*obj
)
551 ARMCPU
*cpu
= ARM_CPU(obj
);
553 /* M profile implies PMSA. We have to do this here rather than
554 * in realize with the other feature-implication checks because
555 * we look at the PMSA bit to see if we should add some properties.
557 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
558 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
561 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
562 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
563 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
,
567 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
568 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
,
572 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
573 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
,
577 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
578 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
579 * prevent "has_el3" from existing on CPUs which cannot support EL3.
581 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
,
584 #ifndef CONFIG_USER_ONLY
585 object_property_add_link(obj
, "secure-memory",
587 (Object
**)&cpu
->secure_memory
,
588 qdev_prop_allow_set_link_before_realize
,
589 OBJ_PROP_LINK_UNREF_ON_RELEASE
,
594 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
595 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
,
599 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
600 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_pmu_property
,
604 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
605 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
,
607 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
608 qdev_property_add_static(DEVICE(obj
),
609 &arm_cpu_pmsav7_dregion_property
,
614 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
,
618 static void arm_cpu_finalizefn(Object
*obj
)
620 ARMCPU
*cpu
= ARM_CPU(obj
);
621 g_hash_table_destroy(cpu
->cp_regs
);
624 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
626 CPUState
*cs
= CPU(dev
);
627 ARMCPU
*cpu
= ARM_CPU(dev
);
628 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
629 CPUARMState
*env
= &cpu
->env
;
631 Error
*local_err
= NULL
;
633 cpu_exec_realizefn(cs
, &local_err
);
634 if (local_err
!= NULL
) {
635 error_propagate(errp
, local_err
);
639 /* Some features automatically imply others: */
640 if (arm_feature(env
, ARM_FEATURE_V8
)) {
641 set_feature(env
, ARM_FEATURE_V7
);
642 set_feature(env
, ARM_FEATURE_ARM_DIV
);
643 set_feature(env
, ARM_FEATURE_LPAE
);
645 if (arm_feature(env
, ARM_FEATURE_V7
)) {
646 set_feature(env
, ARM_FEATURE_VAPA
);
647 set_feature(env
, ARM_FEATURE_THUMB2
);
648 set_feature(env
, ARM_FEATURE_MPIDR
);
649 if (!arm_feature(env
, ARM_FEATURE_M
)) {
650 set_feature(env
, ARM_FEATURE_V6K
);
652 set_feature(env
, ARM_FEATURE_V6
);
655 /* Always define VBAR for V7 CPUs even if it doesn't exist in
656 * non-EL3 configs. This is needed by some legacy boards.
658 set_feature(env
, ARM_FEATURE_VBAR
);
660 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
661 set_feature(env
, ARM_FEATURE_V6
);
662 set_feature(env
, ARM_FEATURE_MVFR
);
664 if (arm_feature(env
, ARM_FEATURE_V6
)) {
665 set_feature(env
, ARM_FEATURE_V5
);
666 if (!arm_feature(env
, ARM_FEATURE_M
)) {
667 set_feature(env
, ARM_FEATURE_AUXCR
);
670 if (arm_feature(env
, ARM_FEATURE_V5
)) {
671 set_feature(env
, ARM_FEATURE_V4T
);
673 if (arm_feature(env
, ARM_FEATURE_M
)) {
674 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
676 if (arm_feature(env
, ARM_FEATURE_ARM_DIV
)) {
677 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
679 if (arm_feature(env
, ARM_FEATURE_VFP4
)) {
680 set_feature(env
, ARM_FEATURE_VFP3
);
681 set_feature(env
, ARM_FEATURE_VFP_FP16
);
683 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
684 set_feature(env
, ARM_FEATURE_VFP
);
686 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
687 set_feature(env
, ARM_FEATURE_V7MP
);
688 set_feature(env
, ARM_FEATURE_PXN
);
690 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
691 set_feature(env
, ARM_FEATURE_CBAR
);
693 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
694 !arm_feature(env
, ARM_FEATURE_M
)) {
695 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
698 if (arm_feature(env
, ARM_FEATURE_V7
) &&
699 !arm_feature(env
, ARM_FEATURE_M
) &&
700 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
701 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
706 /* For CPUs which might have tiny 1K pages, or which have an
707 * MPU and might have small region sizes, stick with 1K pages.
711 if (!set_preferred_target_page_bits(pagebits
)) {
712 /* This can only ever happen for hotplugging a CPU, or if
713 * the board code incorrectly creates a CPU which it has
714 * promised via minimum_page_size that it will not.
716 error_setg(errp
, "This CPU requires a smaller page size than the "
721 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
722 * We don't support setting cluster ID ([16..23]) (known as Aff2
723 * in later ARM ARM versions), or any of the higher affinity level fields,
724 * so these bits always RAZ.
726 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
727 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
728 ARM_DEFAULT_CPUS_PER_CLUSTER
);
731 if (cpu
->reset_hivecs
) {
732 cpu
->reset_sctlr
|= (1 << 13);
736 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
737 cpu
->reset_sctlr
|= SCTLR_EE
;
739 cpu
->reset_sctlr
|= SCTLR_B
;
744 /* If the has_el3 CPU property is disabled then we need to disable the
747 unset_feature(env
, ARM_FEATURE_EL3
);
749 /* Disable the security extension feature bits in the processor feature
750 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
752 cpu
->id_pfr1
&= ~0xf0;
753 cpu
->id_aa64pfr0
&= ~0xf000;
757 unset_feature(env
, ARM_FEATURE_EL2
);
761 unset_feature(env
, ARM_FEATURE_PMU
);
762 cpu
->id_aa64dfr0
&= ~0xf00;
765 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
766 /* Disable the hypervisor feature bits in the processor feature
767 * registers if we don't have EL2. These are id_pfr1[15:12] and
768 * id_aa64pfr0_el1[11:8].
770 cpu
->id_aa64pfr0
&= ~0xf00;
771 cpu
->id_pfr1
&= ~0xf000;
774 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
775 * to false or by setting pmsav7-dregion to 0.
778 cpu
->pmsav7_dregion
= 0;
780 if (cpu
->pmsav7_dregion
== 0) {
781 cpu
->has_mpu
= false;
784 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
785 arm_feature(env
, ARM_FEATURE_V7
)) {
786 uint32_t nr
= cpu
->pmsav7_dregion
;
789 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
794 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
795 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
796 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
800 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
801 set_feature(env
, ARM_FEATURE_VBAR
);
804 register_cp_regs_for_features(cpu
);
805 arm_cpu_register_gdb_regs_for_features(cpu
);
807 init_cpreg_list(cpu
);
809 #ifndef CONFIG_USER_ONLY
819 if (!cpu
->secure_memory
) {
820 cpu
->secure_memory
= cs
->memory
;
822 as
= address_space_init_shareable(cpu
->secure_memory
,
823 "cpu-secure-memory");
824 cpu_address_space_init(cs
, as
, ARMASIdx_S
);
826 cpu_address_space_init(cs
,
827 address_space_init_shareable(cs
->memory
,
835 acc
->parent_realize(dev
, errp
);
838 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
848 cpuname
= g_strsplit(cpu_model
, ",", 1);
849 typename
= g_strdup_printf("%s-" TYPE_ARM_CPU
, cpuname
[0]);
850 oc
= object_class_by_name(typename
);
853 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
854 object_class_is_abstract(oc
)) {
860 /* CPU models. These are not needed for the AArch64 linux-user build. */
861 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
863 static void arm926_initfn(Object
*obj
)
865 ARMCPU
*cpu
= ARM_CPU(obj
);
867 cpu
->dtb_compatible
= "arm,arm926";
868 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
869 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
870 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
871 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
872 cpu
->midr
= 0x41069265;
873 cpu
->reset_fpsid
= 0x41011090;
874 cpu
->ctr
= 0x1dd20d2;
875 cpu
->reset_sctlr
= 0x00090078;
878 static void arm946_initfn(Object
*obj
)
880 ARMCPU
*cpu
= ARM_CPU(obj
);
882 cpu
->dtb_compatible
= "arm,arm946";
883 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
884 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
885 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
886 cpu
->midr
= 0x41059461;
887 cpu
->ctr
= 0x0f004006;
888 cpu
->reset_sctlr
= 0x00000078;
891 static void arm1026_initfn(Object
*obj
)
893 ARMCPU
*cpu
= ARM_CPU(obj
);
895 cpu
->dtb_compatible
= "arm,arm1026";
896 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
897 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
898 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
899 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
900 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
901 cpu
->midr
= 0x4106a262;
902 cpu
->reset_fpsid
= 0x410110a0;
903 cpu
->ctr
= 0x1dd20d2;
904 cpu
->reset_sctlr
= 0x00090078;
905 cpu
->reset_auxcr
= 1;
907 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
908 ARMCPRegInfo ifar
= {
909 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
911 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
914 define_one_arm_cp_reg(cpu
, &ifar
);
918 static void arm1136_r2_initfn(Object
*obj
)
920 ARMCPU
*cpu
= ARM_CPU(obj
);
921 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
922 * older core than plain "arm1136". In particular this does not
923 * have the v6K features.
924 * These ID register values are correct for 1136 but may be wrong
925 * for 1136_r2 (in particular r0p2 does not actually implement most
926 * of the ID registers).
929 cpu
->dtb_compatible
= "arm,arm1136";
930 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
931 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
932 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
933 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
934 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
935 cpu
->midr
= 0x4107b362;
936 cpu
->reset_fpsid
= 0x410120b4;
937 cpu
->mvfr0
= 0x11111111;
938 cpu
->mvfr1
= 0x00000000;
939 cpu
->ctr
= 0x1dd20d2;
940 cpu
->reset_sctlr
= 0x00050078;
941 cpu
->id_pfr0
= 0x111;
945 cpu
->id_mmfr0
= 0x01130003;
946 cpu
->id_mmfr1
= 0x10030302;
947 cpu
->id_mmfr2
= 0x01222110;
948 cpu
->id_isar0
= 0x00140011;
949 cpu
->id_isar1
= 0x12002111;
950 cpu
->id_isar2
= 0x11231111;
951 cpu
->id_isar3
= 0x01102131;
952 cpu
->id_isar4
= 0x141;
953 cpu
->reset_auxcr
= 7;
956 static void arm1136_initfn(Object
*obj
)
958 ARMCPU
*cpu
= ARM_CPU(obj
);
960 cpu
->dtb_compatible
= "arm,arm1136";
961 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
962 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
963 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
964 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
965 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
966 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
967 cpu
->midr
= 0x4117b363;
968 cpu
->reset_fpsid
= 0x410120b4;
969 cpu
->mvfr0
= 0x11111111;
970 cpu
->mvfr1
= 0x00000000;
971 cpu
->ctr
= 0x1dd20d2;
972 cpu
->reset_sctlr
= 0x00050078;
973 cpu
->id_pfr0
= 0x111;
977 cpu
->id_mmfr0
= 0x01130003;
978 cpu
->id_mmfr1
= 0x10030302;
979 cpu
->id_mmfr2
= 0x01222110;
980 cpu
->id_isar0
= 0x00140011;
981 cpu
->id_isar1
= 0x12002111;
982 cpu
->id_isar2
= 0x11231111;
983 cpu
->id_isar3
= 0x01102131;
984 cpu
->id_isar4
= 0x141;
985 cpu
->reset_auxcr
= 7;
988 static void arm1176_initfn(Object
*obj
)
990 ARMCPU
*cpu
= ARM_CPU(obj
);
992 cpu
->dtb_compatible
= "arm,arm1176";
993 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
994 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
995 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
996 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
997 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
998 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
999 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1000 cpu
->midr
= 0x410fb767;
1001 cpu
->reset_fpsid
= 0x410120b5;
1002 cpu
->mvfr0
= 0x11111111;
1003 cpu
->mvfr1
= 0x00000000;
1004 cpu
->ctr
= 0x1dd20d2;
1005 cpu
->reset_sctlr
= 0x00050078;
1006 cpu
->id_pfr0
= 0x111;
1007 cpu
->id_pfr1
= 0x11;
1008 cpu
->id_dfr0
= 0x33;
1010 cpu
->id_mmfr0
= 0x01130003;
1011 cpu
->id_mmfr1
= 0x10030302;
1012 cpu
->id_mmfr2
= 0x01222100;
1013 cpu
->id_isar0
= 0x0140011;
1014 cpu
->id_isar1
= 0x12002111;
1015 cpu
->id_isar2
= 0x11231121;
1016 cpu
->id_isar3
= 0x01102131;
1017 cpu
->id_isar4
= 0x01141;
1018 cpu
->reset_auxcr
= 7;
1021 static void arm11mpcore_initfn(Object
*obj
)
1023 ARMCPU
*cpu
= ARM_CPU(obj
);
1025 cpu
->dtb_compatible
= "arm,arm11mpcore";
1026 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1027 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1028 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1029 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
1030 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1031 cpu
->midr
= 0x410fb022;
1032 cpu
->reset_fpsid
= 0x410120b4;
1033 cpu
->mvfr0
= 0x11111111;
1034 cpu
->mvfr1
= 0x00000000;
1035 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
1036 cpu
->id_pfr0
= 0x111;
1040 cpu
->id_mmfr0
= 0x01100103;
1041 cpu
->id_mmfr1
= 0x10020302;
1042 cpu
->id_mmfr2
= 0x01222000;
1043 cpu
->id_isar0
= 0x00100011;
1044 cpu
->id_isar1
= 0x12002111;
1045 cpu
->id_isar2
= 0x11221011;
1046 cpu
->id_isar3
= 0x01102131;
1047 cpu
->id_isar4
= 0x141;
1048 cpu
->reset_auxcr
= 1;
1051 static void cortex_m3_initfn(Object
*obj
)
1053 ARMCPU
*cpu
= ARM_CPU(obj
);
1054 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1055 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1056 cpu
->midr
= 0x410fc231;
1059 static void cortex_m4_initfn(Object
*obj
)
1061 ARMCPU
*cpu
= ARM_CPU(obj
);
1063 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1064 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1065 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
1066 cpu
->midr
= 0x410fc240; /* r0p0 */
1068 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
1070 CPUClass
*cc
= CPU_CLASS(oc
);
1072 #ifndef CONFIG_USER_ONLY
1073 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
1076 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
1079 static const ARMCPRegInfo cortexr5_cp_reginfo
[] = {
1080 /* Dummy the TCM region regs for the moment */
1081 { .name
= "ATCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
1082 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1083 { .name
= "BTCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
1084 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1085 { .name
= "DCACHE_INVAL", .cp
= 15, .opc1
= 0, .crn
= 15, .crm
= 5,
1086 .opc2
= 0, .access
= PL1_W
, .type
= ARM_CP_NOP
},
1090 static void cortex_r5_initfn(Object
*obj
)
1092 ARMCPU
*cpu
= ARM_CPU(obj
);
1094 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1095 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DIV
);
1096 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1097 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1098 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1099 cpu
->midr
= 0x411fc153; /* r1p3 */
1100 cpu
->id_pfr0
= 0x0131;
1101 cpu
->id_pfr1
= 0x001;
1102 cpu
->id_dfr0
= 0x010400;
1104 cpu
->id_mmfr0
= 0x0210030;
1105 cpu
->id_mmfr1
= 0x00000000;
1106 cpu
->id_mmfr2
= 0x01200000;
1107 cpu
->id_mmfr3
= 0x0211;
1108 cpu
->id_isar0
= 0x2101111;
1109 cpu
->id_isar1
= 0x13112111;
1110 cpu
->id_isar2
= 0x21232141;
1111 cpu
->id_isar3
= 0x01112131;
1112 cpu
->id_isar4
= 0x0010142;
1113 cpu
->id_isar5
= 0x0;
1114 cpu
->mp_is_up
= true;
1115 define_arm_cp_regs(cpu
, cortexr5_cp_reginfo
);
1118 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
1119 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
1120 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1121 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1122 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1126 static void cortex_a8_initfn(Object
*obj
)
1128 ARMCPU
*cpu
= ARM_CPU(obj
);
1130 cpu
->dtb_compatible
= "arm,cortex-a8";
1131 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1132 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1133 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1134 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1135 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1136 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1137 cpu
->midr
= 0x410fc080;
1138 cpu
->reset_fpsid
= 0x410330c0;
1139 cpu
->mvfr0
= 0x11110222;
1140 cpu
->mvfr1
= 0x00011111;
1141 cpu
->ctr
= 0x82048004;
1142 cpu
->reset_sctlr
= 0x00c50078;
1143 cpu
->id_pfr0
= 0x1031;
1144 cpu
->id_pfr1
= 0x11;
1145 cpu
->id_dfr0
= 0x400;
1147 cpu
->id_mmfr0
= 0x31100003;
1148 cpu
->id_mmfr1
= 0x20000000;
1149 cpu
->id_mmfr2
= 0x01202000;
1150 cpu
->id_mmfr3
= 0x11;
1151 cpu
->id_isar0
= 0x00101111;
1152 cpu
->id_isar1
= 0x12112111;
1153 cpu
->id_isar2
= 0x21232031;
1154 cpu
->id_isar3
= 0x11112131;
1155 cpu
->id_isar4
= 0x00111142;
1156 cpu
->dbgdidr
= 0x15141000;
1157 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
1158 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
1159 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
1160 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
1161 cpu
->reset_auxcr
= 2;
1162 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
1165 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
1166 /* power_control should be set to maximum latency. Again,
1167 * default to 0 and set by private hook
1169 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
1170 .access
= PL1_RW
, .resetvalue
= 0,
1171 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
1172 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
1173 .access
= PL1_RW
, .resetvalue
= 0,
1174 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
1175 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
1176 .access
= PL1_RW
, .resetvalue
= 0,
1177 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
1178 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
1179 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1180 /* TLB lockdown control */
1181 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
1182 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1183 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
1184 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1185 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
1186 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1187 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
1188 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1189 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
1190 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1194 static void cortex_a9_initfn(Object
*obj
)
1196 ARMCPU
*cpu
= ARM_CPU(obj
);
1198 cpu
->dtb_compatible
= "arm,cortex-a9";
1199 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1200 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1201 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
1202 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1203 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1204 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1205 /* Note that A9 supports the MP extensions even for
1206 * A9UP and single-core A9MP (which are both different
1207 * and valid configurations; we don't model A9UP).
1209 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1210 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
1211 cpu
->midr
= 0x410fc090;
1212 cpu
->reset_fpsid
= 0x41033090;
1213 cpu
->mvfr0
= 0x11110222;
1214 cpu
->mvfr1
= 0x01111111;
1215 cpu
->ctr
= 0x80038003;
1216 cpu
->reset_sctlr
= 0x00c50078;
1217 cpu
->id_pfr0
= 0x1031;
1218 cpu
->id_pfr1
= 0x11;
1219 cpu
->id_dfr0
= 0x000;
1221 cpu
->id_mmfr0
= 0x00100103;
1222 cpu
->id_mmfr1
= 0x20000000;
1223 cpu
->id_mmfr2
= 0x01230000;
1224 cpu
->id_mmfr3
= 0x00002111;
1225 cpu
->id_isar0
= 0x00101111;
1226 cpu
->id_isar1
= 0x13112111;
1227 cpu
->id_isar2
= 0x21232041;
1228 cpu
->id_isar3
= 0x11112131;
1229 cpu
->id_isar4
= 0x00111142;
1230 cpu
->dbgdidr
= 0x35141000;
1231 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
1232 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
1233 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
1234 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
1237 #ifndef CONFIG_USER_ONLY
1238 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1240 /* Linux wants the number of processors from here.
1241 * Might as well set the interrupt-controller bit too.
1243 return ((smp_cpus
- 1) << 24) | (1 << 23);
1247 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
1248 #ifndef CONFIG_USER_ONLY
1249 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1250 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
1251 .writefn
= arm_cp_write_ignore
, },
1253 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
1254 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1258 static void cortex_a7_initfn(Object
*obj
)
1260 ARMCPU
*cpu
= ARM_CPU(obj
);
1262 cpu
->dtb_compatible
= "arm,cortex-a7";
1263 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1264 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1265 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1266 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1267 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1268 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1269 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1270 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1271 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
1272 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1273 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A7
;
1274 cpu
->midr
= 0x410fc075;
1275 cpu
->reset_fpsid
= 0x41023075;
1276 cpu
->mvfr0
= 0x10110222;
1277 cpu
->mvfr1
= 0x11111111;
1278 cpu
->ctr
= 0x84448003;
1279 cpu
->reset_sctlr
= 0x00c50078;
1280 cpu
->id_pfr0
= 0x00001131;
1281 cpu
->id_pfr1
= 0x00011011;
1282 cpu
->id_dfr0
= 0x02010555;
1283 cpu
->pmceid0
= 0x00000000;
1284 cpu
->pmceid1
= 0x00000000;
1285 cpu
->id_afr0
= 0x00000000;
1286 cpu
->id_mmfr0
= 0x10101105;
1287 cpu
->id_mmfr1
= 0x40000000;
1288 cpu
->id_mmfr2
= 0x01240000;
1289 cpu
->id_mmfr3
= 0x02102211;
1290 cpu
->id_isar0
= 0x01101110;
1291 cpu
->id_isar1
= 0x13112111;
1292 cpu
->id_isar2
= 0x21232041;
1293 cpu
->id_isar3
= 0x11112131;
1294 cpu
->id_isar4
= 0x10011142;
1295 cpu
->dbgdidr
= 0x3515f005;
1296 cpu
->clidr
= 0x0a200023;
1297 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1298 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1299 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1300 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
); /* Same as A15 */
1303 static void cortex_a15_initfn(Object
*obj
)
1305 ARMCPU
*cpu
= ARM_CPU(obj
);
1307 cpu
->dtb_compatible
= "arm,cortex-a15";
1308 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1309 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1310 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1311 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1312 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1313 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1314 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1315 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1316 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
1317 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1318 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
1319 cpu
->midr
= 0x412fc0f1;
1320 cpu
->reset_fpsid
= 0x410430f0;
1321 cpu
->mvfr0
= 0x10110222;
1322 cpu
->mvfr1
= 0x11111111;
1323 cpu
->ctr
= 0x8444c004;
1324 cpu
->reset_sctlr
= 0x00c50078;
1325 cpu
->id_pfr0
= 0x00001131;
1326 cpu
->id_pfr1
= 0x00011011;
1327 cpu
->id_dfr0
= 0x02010555;
1328 cpu
->pmceid0
= 0x0000000;
1329 cpu
->pmceid1
= 0x00000000;
1330 cpu
->id_afr0
= 0x00000000;
1331 cpu
->id_mmfr0
= 0x10201105;
1332 cpu
->id_mmfr1
= 0x20000000;
1333 cpu
->id_mmfr2
= 0x01240000;
1334 cpu
->id_mmfr3
= 0x02102211;
1335 cpu
->id_isar0
= 0x02101110;
1336 cpu
->id_isar1
= 0x13112111;
1337 cpu
->id_isar2
= 0x21232041;
1338 cpu
->id_isar3
= 0x11112131;
1339 cpu
->id_isar4
= 0x10011142;
1340 cpu
->dbgdidr
= 0x3515f021;
1341 cpu
->clidr
= 0x0a200023;
1342 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1343 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1344 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1345 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
1348 static void ti925t_initfn(Object
*obj
)
1350 ARMCPU
*cpu
= ARM_CPU(obj
);
1351 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
1352 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
1353 cpu
->midr
= ARM_CPUID_TI925T
;
1354 cpu
->ctr
= 0x5109149;
1355 cpu
->reset_sctlr
= 0x00000070;
1358 static void sa1100_initfn(Object
*obj
)
1360 ARMCPU
*cpu
= ARM_CPU(obj
);
1362 cpu
->dtb_compatible
= "intel,sa1100";
1363 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1364 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1365 cpu
->midr
= 0x4401A11B;
1366 cpu
->reset_sctlr
= 0x00000070;
1369 static void sa1110_initfn(Object
*obj
)
1371 ARMCPU
*cpu
= ARM_CPU(obj
);
1372 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1373 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1374 cpu
->midr
= 0x6901B119;
1375 cpu
->reset_sctlr
= 0x00000070;
1378 static void pxa250_initfn(Object
*obj
)
1380 ARMCPU
*cpu
= ARM_CPU(obj
);
1382 cpu
->dtb_compatible
= "marvell,xscale";
1383 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1384 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1385 cpu
->midr
= 0x69052100;
1386 cpu
->ctr
= 0xd172172;
1387 cpu
->reset_sctlr
= 0x00000078;
1390 static void pxa255_initfn(Object
*obj
)
1392 ARMCPU
*cpu
= ARM_CPU(obj
);
1394 cpu
->dtb_compatible
= "marvell,xscale";
1395 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1396 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1397 cpu
->midr
= 0x69052d00;
1398 cpu
->ctr
= 0xd172172;
1399 cpu
->reset_sctlr
= 0x00000078;
1402 static void pxa260_initfn(Object
*obj
)
1404 ARMCPU
*cpu
= ARM_CPU(obj
);
1406 cpu
->dtb_compatible
= "marvell,xscale";
1407 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1408 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1409 cpu
->midr
= 0x69052903;
1410 cpu
->ctr
= 0xd172172;
1411 cpu
->reset_sctlr
= 0x00000078;
1414 static void pxa261_initfn(Object
*obj
)
1416 ARMCPU
*cpu
= ARM_CPU(obj
);
1418 cpu
->dtb_compatible
= "marvell,xscale";
1419 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1420 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1421 cpu
->midr
= 0x69052d05;
1422 cpu
->ctr
= 0xd172172;
1423 cpu
->reset_sctlr
= 0x00000078;
1426 static void pxa262_initfn(Object
*obj
)
1428 ARMCPU
*cpu
= ARM_CPU(obj
);
1430 cpu
->dtb_compatible
= "marvell,xscale";
1431 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1432 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1433 cpu
->midr
= 0x69052d06;
1434 cpu
->ctr
= 0xd172172;
1435 cpu
->reset_sctlr
= 0x00000078;
1438 static void pxa270a0_initfn(Object
*obj
)
1440 ARMCPU
*cpu
= ARM_CPU(obj
);
1442 cpu
->dtb_compatible
= "marvell,xscale";
1443 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1444 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1445 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1446 cpu
->midr
= 0x69054110;
1447 cpu
->ctr
= 0xd172172;
1448 cpu
->reset_sctlr
= 0x00000078;
1451 static void pxa270a1_initfn(Object
*obj
)
1453 ARMCPU
*cpu
= ARM_CPU(obj
);
1455 cpu
->dtb_compatible
= "marvell,xscale";
1456 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1457 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1458 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1459 cpu
->midr
= 0x69054111;
1460 cpu
->ctr
= 0xd172172;
1461 cpu
->reset_sctlr
= 0x00000078;
1464 static void pxa270b0_initfn(Object
*obj
)
1466 ARMCPU
*cpu
= ARM_CPU(obj
);
1468 cpu
->dtb_compatible
= "marvell,xscale";
1469 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1470 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1471 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1472 cpu
->midr
= 0x69054112;
1473 cpu
->ctr
= 0xd172172;
1474 cpu
->reset_sctlr
= 0x00000078;
1477 static void pxa270b1_initfn(Object
*obj
)
1479 ARMCPU
*cpu
= ARM_CPU(obj
);
1481 cpu
->dtb_compatible
= "marvell,xscale";
1482 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1483 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1484 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1485 cpu
->midr
= 0x69054113;
1486 cpu
->ctr
= 0xd172172;
1487 cpu
->reset_sctlr
= 0x00000078;
1490 static void pxa270c0_initfn(Object
*obj
)
1492 ARMCPU
*cpu
= ARM_CPU(obj
);
1494 cpu
->dtb_compatible
= "marvell,xscale";
1495 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1496 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1497 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1498 cpu
->midr
= 0x69054114;
1499 cpu
->ctr
= 0xd172172;
1500 cpu
->reset_sctlr
= 0x00000078;
1503 static void pxa270c5_initfn(Object
*obj
)
1505 ARMCPU
*cpu
= ARM_CPU(obj
);
1507 cpu
->dtb_compatible
= "marvell,xscale";
1508 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1509 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1510 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1511 cpu
->midr
= 0x69054117;
1512 cpu
->ctr
= 0xd172172;
1513 cpu
->reset_sctlr
= 0x00000078;
1516 #ifdef CONFIG_USER_ONLY
1517 static void arm_any_initfn(Object
*obj
)
1519 ARMCPU
*cpu
= ARM_CPU(obj
);
1520 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
1521 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1522 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1523 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1524 set_feature(&cpu
->env
, ARM_FEATURE_V8_AES
);
1525 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA1
);
1526 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA256
);
1527 set_feature(&cpu
->env
, ARM_FEATURE_V8_PMULL
);
1528 set_feature(&cpu
->env
, ARM_FEATURE_CRC
);
1529 cpu
->midr
= 0xffffffff;
1533 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1535 typedef struct ARMCPUInfo
{
1537 void (*initfn
)(Object
*obj
);
1538 void (*class_init
)(ObjectClass
*oc
, void *data
);
1541 static const ARMCPUInfo arm_cpus
[] = {
1542 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1543 { .name
= "arm926", .initfn
= arm926_initfn
},
1544 { .name
= "arm946", .initfn
= arm946_initfn
},
1545 { .name
= "arm1026", .initfn
= arm1026_initfn
},
1546 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1547 * older core than plain "arm1136". In particular this does not
1548 * have the v6K features.
1550 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
1551 { .name
= "arm1136", .initfn
= arm1136_initfn
},
1552 { .name
= "arm1176", .initfn
= arm1176_initfn
},
1553 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
1554 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
1555 .class_init
= arm_v7m_class_init
},
1556 { .name
= "cortex-m4", .initfn
= cortex_m4_initfn
,
1557 .class_init
= arm_v7m_class_init
},
1558 { .name
= "cortex-r5", .initfn
= cortex_r5_initfn
},
1559 { .name
= "cortex-a7", .initfn
= cortex_a7_initfn
},
1560 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
1561 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
1562 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
1563 { .name
= "ti925t", .initfn
= ti925t_initfn
},
1564 { .name
= "sa1100", .initfn
= sa1100_initfn
},
1565 { .name
= "sa1110", .initfn
= sa1110_initfn
},
1566 { .name
= "pxa250", .initfn
= pxa250_initfn
},
1567 { .name
= "pxa255", .initfn
= pxa255_initfn
},
1568 { .name
= "pxa260", .initfn
= pxa260_initfn
},
1569 { .name
= "pxa261", .initfn
= pxa261_initfn
},
1570 { .name
= "pxa262", .initfn
= pxa262_initfn
},
1571 /* "pxa270" is an alias for "pxa270-a0" */
1572 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
1573 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
1574 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
1575 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
1576 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
1577 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
1578 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
1579 #ifdef CONFIG_USER_ONLY
1580 { .name
= "any", .initfn
= arm_any_initfn
},
1586 static Property arm_cpu_properties
[] = {
1587 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
1588 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
1589 DEFINE_PROP_UINT32("midr", ARMCPU
, midr
, 0),
1590 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
1591 mp_affinity
, ARM64_AFFINITY_INVALID
),
1592 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
1593 DEFINE_PROP_END_OF_LIST()
1596 #ifdef CONFIG_USER_ONLY
1597 static int arm_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int rw
,
1600 ARMCPU
*cpu
= ARM_CPU(cs
);
1601 CPUARMState
*env
= &cpu
->env
;
1603 env
->exception
.vaddress
= address
;
1605 cs
->exception_index
= EXCP_PREFETCH_ABORT
;
1607 cs
->exception_index
= EXCP_DATA_ABORT
;
1613 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
1615 ARMCPU
*cpu
= ARM_CPU(cs
);
1616 CPUARMState
*env
= &cpu
->env
;
1618 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
1619 return g_strdup("iwmmxt");
1621 return g_strdup("arm");
1624 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
1626 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
1627 CPUClass
*cc
= CPU_CLASS(acc
);
1628 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1630 acc
->parent_realize
= dc
->realize
;
1631 dc
->realize
= arm_cpu_realizefn
;
1632 dc
->props
= arm_cpu_properties
;
1634 acc
->parent_reset
= cc
->reset
;
1635 cc
->reset
= arm_cpu_reset
;
1637 cc
->class_by_name
= arm_cpu_class_by_name
;
1638 cc
->has_work
= arm_cpu_has_work
;
1639 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
1640 cc
->dump_state
= arm_cpu_dump_state
;
1641 cc
->set_pc
= arm_cpu_set_pc
;
1642 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
1643 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
1644 #ifdef CONFIG_USER_ONLY
1645 cc
->handle_mmu_fault
= arm_cpu_handle_mmu_fault
;
1647 cc
->do_interrupt
= arm_cpu_do_interrupt
;
1648 cc
->do_unaligned_access
= arm_cpu_do_unaligned_access
;
1649 cc
->get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
;
1650 cc
->asidx_from_attrs
= arm_asidx_from_attrs
;
1651 cc
->vmsd
= &vmstate_arm_cpu
;
1652 cc
->virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
;
1653 cc
->write_elf64_note
= arm_cpu_write_elf64_note
;
1654 cc
->write_elf32_note
= arm_cpu_write_elf32_note
;
1656 cc
->gdb_num_core_regs
= 26;
1657 cc
->gdb_core_xml_file
= "arm-core.xml";
1658 cc
->gdb_arch_name
= arm_gdb_arch_name
;
1659 cc
->gdb_stop_before_watchpoint
= true;
1660 cc
->debug_excp_handler
= arm_debug_excp_handler
;
1661 cc
->debug_check_watchpoint
= arm_debug_check_watchpoint
;
1662 #if !defined(CONFIG_USER_ONLY)
1663 cc
->adjust_watchpoint_address
= arm_adjust_watchpoint_address
;
1666 cc
->disas_set_info
= arm_disas_set_info
;
1669 static void cpu_register(const ARMCPUInfo
*info
)
1671 TypeInfo type_info
= {
1672 .parent
= TYPE_ARM_CPU
,
1673 .instance_size
= sizeof(ARMCPU
),
1674 .instance_init
= info
->initfn
,
1675 .class_size
= sizeof(ARMCPUClass
),
1676 .class_init
= info
->class_init
,
1679 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
1680 type_register(&type_info
);
1681 g_free((void *)type_info
.name
);
1684 static const TypeInfo arm_cpu_type_info
= {
1685 .name
= TYPE_ARM_CPU
,
1687 .instance_size
= sizeof(ARMCPU
),
1688 .instance_init
= arm_cpu_initfn
,
1689 .instance_post_init
= arm_cpu_post_init
,
1690 .instance_finalize
= arm_cpu_finalizefn
,
1692 .class_size
= sizeof(ARMCPUClass
),
1693 .class_init
= arm_cpu_class_init
,
1696 static void arm_cpu_register_types(void)
1698 const ARMCPUInfo
*info
= arm_cpus
;
1700 type_register_static(&arm_cpu_type_info
);
1702 while (info
->name
) {
1708 type_init(arm_cpu_register_types
)