target-ppc/machine.c

   1 #include "qemu/osdep.h"
   2 #include "qemu-common.h"
   3 #include "cpu.h"
   4 #include "exec/exec-all.h"
   5 #include "hw/hw.h"
   6 #include "hw/boards.h"
   7 #include "sysemu/kvm.h"
   8 #include "helper_regs.h"
   9 #include "mmu-hash64.h"
  10 #include "migration/cpu.h"
  11
  12 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
  13 {
  14     PowerPCCPU *cpu = opaque;
  15     CPUPPCState *env = &cpu->env;
  16     unsigned int i, j;
  17     target_ulong sdr1;
  18     uint32_t fpscr;
  19     target_ulong xer;
  20
  21     for (i = 0; i < 32; i++)
  22         qemu_get_betls(f, &env->gpr[i]);
  23 #if !defined(TARGET_PPC64)
  24     for (i = 0; i < 32; i++)
  25         qemu_get_betls(f, &env->gprh[i]);
  26 #endif
  27     qemu_get_betls(f, &env->lr);
  28     qemu_get_betls(f, &env->ctr);
  29     for (i = 0; i < 8; i++)
  30         qemu_get_be32s(f, &env->crf[i]);
  31     qemu_get_betls(f, &xer);
  32     cpu_write_xer(env, xer);
  33     qemu_get_betls(f, &env->reserve_addr);
  34     qemu_get_betls(f, &env->msr);
  35     for (i = 0; i < 4; i++)
  36         qemu_get_betls(f, &env->tgpr[i]);
  37     for (i = 0; i < 32; i++) {
  38         union {
  39             float64 d;
  40             uint64_t l;
  41         } u;
  42         u.l = qemu_get_be64(f);
  43         env->fpr[i] = u.d;
  44     }
  45     qemu_get_be32s(f, &fpscr);
  46     env->fpscr = fpscr;
  47     qemu_get_sbe32s(f, &env->access_type);
  48 #if defined(TARGET_PPC64)
  49     qemu_get_betls(f, &env->spr[SPR_ASR]);
  50     qemu_get_sbe32s(f, &env->slb_nr);
  51 #endif
  52     qemu_get_betls(f, &sdr1);
  53     for (i = 0; i < 32; i++)
  54         qemu_get_betls(f, &env->sr[i]);
  55     for (i = 0; i < 2; i++)
  56         for (j = 0; j < 8; j++)
  57             qemu_get_betls(f, &env->DBAT[i][j]);
  58     for (i = 0; i < 2; i++)
  59         for (j = 0; j < 8; j++)
  60             qemu_get_betls(f, &env->IBAT[i][j]);
  61     qemu_get_sbe32s(f, &env->nb_tlb);
  62     qemu_get_sbe32s(f, &env->tlb_per_way);
  63     qemu_get_sbe32s(f, &env->nb_ways);
  64     qemu_get_sbe32s(f, &env->last_way);
  65     qemu_get_sbe32s(f, &env->id_tlbs);
  66     qemu_get_sbe32s(f, &env->nb_pids);
  67     if (env->tlb.tlb6) {
  68         // XXX assumes 6xx
  69         for (i = 0; i < env->nb_tlb; i++) {
  70             qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
  71             qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
  72             qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
  73         }
  74     }
  75     for (i = 0; i < 4; i++)
  76         qemu_get_betls(f, &env->pb[i]);
  77     for (i = 0; i < 1024; i++)
  78         qemu_get_betls(f, &env->spr[i]);
  79     if (!env->external_htab) {
  80         ppc_store_sdr1(env, sdr1);
  81     }
  82     qemu_get_be32s(f, &env->vscr);
  83     qemu_get_be64s(f, &env->spe_acc);
  84     qemu_get_be32s(f, &env->spe_fscr);
  85     qemu_get_betls(f, &env->msr_mask);
  86     qemu_get_be32s(f, &env->flags);
  87     qemu_get_sbe32s(f, &env->error_code);
  88     qemu_get_be32s(f, &env->pending_interrupts);
  89     qemu_get_be32s(f, &env->irq_input_state);
  90     for (i = 0; i < POWERPC_EXCP_NB; i++)
  91         qemu_get_betls(f, &env->excp_vectors[i]);
  92     qemu_get_betls(f, &env->excp_prefix);
  93     qemu_get_betls(f, &env->ivor_mask);
  94     qemu_get_betls(f, &env->ivpr_mask);
  95     qemu_get_betls(f, &env->hreset_vector);
  96     qemu_get_betls(f, &env->nip);
  97     qemu_get_betls(f, &env->hflags);
  98     qemu_get_betls(f, &env->hflags_nmsr);
  99     qemu_get_sbe32(f); /* Discard unused mmu_idx */
 100     qemu_get_sbe32(f); /* Discard unused power_mode */
 101
 102     /* Recompute mmu indices */
 103     hreg_compute_mem_idx(env);
 104
 105     return 0;
 106 }
 107
 108 static int get_avr(QEMUFile *f, void *pv, size_t size)
 109 {
 110     ppc_avr_t *v = pv;
 111
 112     v->u64[0] = qemu_get_be64(f);
 113     v->u64[1] = qemu_get_be64(f);
 114
 115     return 0;
 116 }
 117
 118 static void put_avr(QEMUFile *f, void *pv, size_t size)
 119 {
 120     ppc_avr_t *v = pv;
 121
 122     qemu_put_be64(f, v->u64[0]);
 123     qemu_put_be64(f, v->u64[1]);
 124 }
 125
 126 static const VMStateInfo vmstate_info_avr = {
 127     .name = "avr",
 128     .get  = get_avr,
 129     .put  = put_avr,
 130 };
 131
 132 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v)                       \
 133     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)
 134
 135 #define VMSTATE_AVR_ARRAY(_f, _s, _n)                             \
 136     VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
 137
 138 static void cpu_pre_save(void *opaque)
 139 {
 140     PowerPCCPU *cpu = opaque;
 141     CPUPPCState *env = &cpu->env;
 142     int i;
 143
 144     env->spr[SPR_LR] = env->lr;
 145     env->spr[SPR_CTR] = env->ctr;
 146     env->spr[SPR_XER] = cpu_read_xer(env);
 147 #if defined(TARGET_PPC64)
 148     env->spr[SPR_CFAR] = env->cfar;
 149 #endif
 150     env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
 151
 152     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 153         env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
 154         env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
 155         env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
 156         env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
 157     }
 158     for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
 159         env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
 160         env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
 161         env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
 162         env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
 163     }
 164 }
 165
 166 static int cpu_post_load(void *opaque, int version_id)
 167 {
 168     PowerPCCPU *cpu = opaque;
 169     CPUPPCState *env = &cpu->env;
 170     int i;
 171     target_ulong msr;
 172
 173     /*
 174      * We always ignore the source PVR. The user or management
 175      * software has to take care of running QEMU in a compatible mode.
 176      */
 177     env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
 178     env->lr = env->spr[SPR_LR];
 179     env->ctr = env->spr[SPR_CTR];
 180     cpu_write_xer(env, env->spr[SPR_XER]);
 181 #if defined(TARGET_PPC64)
 182     env->cfar = env->spr[SPR_CFAR];
 183 #endif
 184     env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
 185
 186     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 187         env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
 188         env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
 189         env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
 190         env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
 191     }
 192     for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
 193         env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
 194         env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
 195         env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
 196         env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
 197     }
 198
 199     if (!env->external_htab) {
 200         /* Restore htab_base and htab_mask variables */
 201         ppc_store_sdr1(env, env->spr[SPR_SDR1]);
 202     }
 203
 204     /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */
 205     msr = env->msr;
 206     env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB);
 207     ppc_store_msr(env, msr);
 208
 209     hreg_compute_mem_idx(env);
 210
 211     return 0;
 212 }
 213
 214 static bool fpu_needed(void *opaque)
 215 {
 216     PowerPCCPU *cpu = opaque;
 217
 218     return (cpu->env.insns_flags & PPC_FLOAT);
 219 }
 220
 221 static const VMStateDescription vmstate_fpu = {
 222     .name = "cpu/fpu",
 223     .version_id = 1,
 224     .minimum_version_id = 1,
 225     .needed = fpu_needed,
 226     .fields = (VMStateField[]) {
 227         VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
 228         VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
 229         VMSTATE_END_OF_LIST()
 230     },
 231 };
 232
 233 static bool altivec_needed(void *opaque)
 234 {
 235     PowerPCCPU *cpu = opaque;
 236
 237     return (cpu->env.insns_flags & PPC_ALTIVEC);
 238 }
 239
 240 static const VMStateDescription vmstate_altivec = {
 241     .name = "cpu/altivec",
 242     .version_id = 1,
 243     .minimum_version_id = 1,
 244     .needed = altivec_needed,
 245     .fields = (VMStateField[]) {
 246         VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
 247         VMSTATE_UINT32(env.vscr, PowerPCCPU),
 248         VMSTATE_END_OF_LIST()
 249     },
 250 };
 251
 252 static bool vsx_needed(void *opaque)
 253 {
 254     PowerPCCPU *cpu = opaque;
 255
 256     return (cpu->env.insns_flags2 & PPC2_VSX);
 257 }
 258
 259 static const VMStateDescription vmstate_vsx = {
 260     .name = "cpu/vsx",
 261     .version_id = 1,
 262     .minimum_version_id = 1,
 263     .needed = vsx_needed,
 264     .fields = (VMStateField[]) {
 265         VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
 266         VMSTATE_END_OF_LIST()
 267     },
 268 };
 269
 270 #ifdef TARGET_PPC64
 271 /* Transactional memory state */
 272 static bool tm_needed(void *opaque)
 273 {
 274     PowerPCCPU *cpu = opaque;
 275     CPUPPCState *env = &cpu->env;
 276     return msr_ts;
 277 }
 278
 279 static const VMStateDescription vmstate_tm = {
 280     .name = "cpu/tm",
 281     .version_id = 1,
 282     .minimum_version_id = 1,
 283     .minimum_version_id_old = 1,
 284     .needed = tm_needed,
 285     .fields      = (VMStateField []) {
 286         VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
 287         VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
 288         VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
 289         VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
 290         VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
 291         VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
 292         VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
 293         VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
 294         VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
 295         VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
 296         VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
 297         VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
 298         VMSTATE_END_OF_LIST()
 299     },
 300 };
 301 #endif
 302
 303 static bool sr_needed(void *opaque)
 304 {
 305 #ifdef TARGET_PPC64
 306     PowerPCCPU *cpu = opaque;
 307
 308     return !(cpu->env.mmu_model & POWERPC_MMU_64);
 309 #else
 310     return true;
 311 #endif
 312 }
 313
 314 static const VMStateDescription vmstate_sr = {
 315     .name = "cpu/sr",
 316     .version_id = 1,
 317     .minimum_version_id = 1,
 318     .needed = sr_needed,
 319     .fields = (VMStateField[]) {
 320         VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
 321         VMSTATE_END_OF_LIST()
 322     },
 323 };
 324
 325 #ifdef TARGET_PPC64
 326 static int get_slbe(QEMUFile *f, void *pv, size_t size)
 327 {
 328     ppc_slb_t *v = pv;
 329
 330     v->esid = qemu_get_be64(f);
 331     v->vsid = qemu_get_be64(f);
 332
 333     return 0;
 334 }
 335
 336 static void put_slbe(QEMUFile *f, void *pv, size_t size)
 337 {
 338     ppc_slb_t *v = pv;
 339
 340     qemu_put_be64(f, v->esid);
 341     qemu_put_be64(f, v->vsid);
 342 }
 343
 344 static const VMStateInfo vmstate_info_slbe = {
 345     .name = "slbe",
 346     .get  = get_slbe,
 347     .put  = put_slbe,
 348 };
 349
 350 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v)                       \
 351     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
 352
 353 #define VMSTATE_SLB_ARRAY(_f, _s, _n)                             \
 354     VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
 355
 356 static bool slb_needed(void *opaque)
 357 {
 358     PowerPCCPU *cpu = opaque;
 359
 360     /* We don't support any of the old segment table based 64-bit CPUs */
 361     return (cpu->env.mmu_model & POWERPC_MMU_64);
 362 }
 363
 364 static int slb_post_load(void *opaque, int version_id)
 365 {
 366     PowerPCCPU *cpu = opaque;
 367     CPUPPCState *env = &cpu->env;
 368     int i;
 369
 370     /* We've pulled in the raw esid and vsid values from the migration
 371      * stream, but we need to recompute the page size pointers */
 372     for (i = 0; i < env->slb_nr; i++) {
 373         if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
 374             /* Migration source had bad values in its SLB */
 375             return -1;
 376         }
 377     }
 378
 379     return 0;
 380 }
 381
 382 static const VMStateDescription vmstate_slb = {
 383     .name = "cpu/slb",
 384     .version_id = 1,
 385     .minimum_version_id = 1,
 386     .needed = slb_needed,
 387     .post_load = slb_post_load,
 388     .fields = (VMStateField[]) {
 389         VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
 390         VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
 391         VMSTATE_END_OF_LIST()
 392     }
 393 };
 394 #endif /* TARGET_PPC64 */
 395
 396 static const VMStateDescription vmstate_tlb6xx_entry = {
 397     .name = "cpu/tlb6xx_entry",
 398     .version_id = 1,
 399     .minimum_version_id = 1,
 400     .fields = (VMStateField[]) {
 401         VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
 402         VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
 403         VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
 404         VMSTATE_END_OF_LIST()
 405     },
 406 };
 407
 408 static bool tlb6xx_needed(void *opaque)
 409 {
 410     PowerPCCPU *cpu = opaque;
 411     CPUPPCState *env = &cpu->env;
 412
 413     return env->nb_tlb && (env->tlb_type == TLB_6XX);
 414 }
 415
 416 static const VMStateDescription vmstate_tlb6xx = {
 417     .name = "cpu/tlb6xx",
 418     .version_id = 1,
 419     .minimum_version_id = 1,
 420     .needed = tlb6xx_needed,
 421     .fields = (VMStateField[]) {
 422         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 423         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
 424                                             env.nb_tlb,
 425                                             vmstate_tlb6xx_entry,
 426                                             ppc6xx_tlb_t),
 427         VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
 428         VMSTATE_END_OF_LIST()
 429     }
 430 };
 431
 432 static const VMStateDescription vmstate_tlbemb_entry = {
 433     .name = "cpu/tlbemb_entry",
 434     .version_id = 1,
 435     .minimum_version_id = 1,
 436     .fields = (VMStateField[]) {
 437         VMSTATE_UINT64(RPN, ppcemb_tlb_t),
 438         VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
 439         VMSTATE_UINTTL(PID, ppcemb_tlb_t),
 440         VMSTATE_UINTTL(size, ppcemb_tlb_t),
 441         VMSTATE_UINT32(prot, ppcemb_tlb_t),
 442         VMSTATE_UINT32(attr, ppcemb_tlb_t),
 443         VMSTATE_END_OF_LIST()
 444     },
 445 };
 446
 447 static bool tlbemb_needed(void *opaque)
 448 {
 449     PowerPCCPU *cpu = opaque;
 450     CPUPPCState *env = &cpu->env;
 451
 452     return env->nb_tlb && (env->tlb_type == TLB_EMB);
 453 }
 454
 455 static bool pbr403_needed(void *opaque)
 456 {
 457     PowerPCCPU *cpu = opaque;
 458     uint32_t pvr = cpu->env.spr[SPR_PVR];
 459
 460     return (pvr & 0xffff0000) == 0x00200000;
 461 }
 462
 463 static const VMStateDescription vmstate_pbr403 = {
 464     .name = "cpu/pbr403",
 465     .version_id = 1,
 466     .minimum_version_id = 1,
 467     .needed = pbr403_needed,
 468     .fields = (VMStateField[]) {
 469         VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
 470         VMSTATE_END_OF_LIST()
 471     },
 472 };
 473
 474 static const VMStateDescription vmstate_tlbemb = {
 475     .name = "cpu/tlb6xx",
 476     .version_id = 1,
 477     .minimum_version_id = 1,
 478     .needed = tlbemb_needed,
 479     .fields = (VMStateField[]) {
 480         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 481         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
 482                                             env.nb_tlb,
 483                                             vmstate_tlbemb_entry,
 484                                             ppcemb_tlb_t),
 485         /* 403 protection registers */
 486         VMSTATE_END_OF_LIST()
 487     },
 488     .subsections = (const VMStateDescription*[]) {
 489         &vmstate_pbr403,
 490         NULL
 491     }
 492 };
 493
 494 static const VMStateDescription vmstate_tlbmas_entry = {
 495     .name = "cpu/tlbmas_entry",
 496     .version_id = 1,
 497     .minimum_version_id = 1,
 498     .fields = (VMStateField[]) {
 499         VMSTATE_UINT32(mas8, ppcmas_tlb_t),
 500         VMSTATE_UINT32(mas1, ppcmas_tlb_t),
 501         VMSTATE_UINT64(mas2, ppcmas_tlb_t),
 502         VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
 503         VMSTATE_END_OF_LIST()
 504     },
 505 };
 506
 507 static bool tlbmas_needed(void *opaque)
 508 {
 509     PowerPCCPU *cpu = opaque;
 510     CPUPPCState *env = &cpu->env;
 511
 512     return env->nb_tlb && (env->tlb_type == TLB_MAS);
 513 }
 514
 515 static const VMStateDescription vmstate_tlbmas = {
 516     .name = "cpu/tlbmas",
 517     .version_id = 1,
 518     .minimum_version_id = 1,
 519     .needed = tlbmas_needed,
 520     .fields = (VMStateField[]) {
 521         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 522         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
 523                                             env.nb_tlb,
 524                                             vmstate_tlbmas_entry,
 525                                             ppcmas_tlb_t),
 526         VMSTATE_END_OF_LIST()
 527     }
 528 };
 529
 530 const VMStateDescription vmstate_ppc_cpu = {
 531     .name = "cpu",
 532     .version_id = 5,
 533     .minimum_version_id = 5,
 534     .minimum_version_id_old = 4,
 535     .load_state_old = cpu_load_old,
 536     .pre_save = cpu_pre_save,
 537     .post_load = cpu_post_load,
 538     .fields = (VMStateField[]) {
 539         VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */
 540
 541         /* User mode architected state */
 542         VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
 543 #if !defined(TARGET_PPC64)
 544         VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
 545 #endif
 546         VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
 547         VMSTATE_UINTTL(env.nip, PowerPCCPU),
 548
 549         /* SPRs */
 550         VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
 551         VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
 552
 553         /* Reservation */
 554         VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
 555
 556         /* Supervisor mode architected state */
 557         VMSTATE_UINTTL(env.msr, PowerPCCPU),
 558
 559         /* Internal state */
 560         VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
 561         /* FIXME: access_type? */
 562
 563         /* Sanity checking */
 564         VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU),
 565         VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU),
 566         VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU),
 567         VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU),
 568         VMSTATE_END_OF_LIST()
 569     },
 570     .subsections = (const VMStateDescription*[]) {
 571         &vmstate_fpu,
 572         &vmstate_altivec,
 573         &vmstate_vsx,
 574         &vmstate_sr,
 575 #ifdef TARGET_PPC64
 576         &vmstate_tm,
 577         &vmstate_slb,
 578 #endif /* TARGET_PPC64 */
 579         &vmstate_tlb6xx,
 580         &vmstate_tlbemb,
 581         &vmstate_tlbmas,
 582         NULL
 583     }
 584 };