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hw/ppc: Drop useless CONFIG_KVM ifdefery
[qemu/ar7.git] / hw / scsi / megasas.c
blob0c4399930a6e167c88c0277631409f248417e8df
1 /*
2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
3 * Based on the linux driver code at drivers/scsi/megaraid
4 *
5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu-common.h"
23 #include "hw/hw.h"
24 #include "hw/pci/pci.h"
25 #include "sysemu/dma.h"
26 #include "sysemu/block-backend.h"
27 #include "hw/pci/msi.h"
28 #include "hw/pci/msix.h"
29 #include "qemu/iov.h"
30 #include "qemu/module.h"
31 #include "hw/scsi/scsi.h"
32 #include "scsi/constants.h"
33 #include "trace.h"
34 #include "qapi/error.h"
35 #include "mfi.h"
36
37 #define MEGASAS_VERSION_GEN1 "1.70"
38 #define MEGASAS_VERSION_GEN2 "1.80"
39 #define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */
40 #define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */
41 #define MEGASAS_GEN2_DEFAULT_FRAMES 1008 /* Windows requires this */
42 #define MEGASAS_MAX_SGE 128 /* Firmware limit */
43 #define MEGASAS_DEFAULT_SGE 80
44 #define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */
45 #define MEGASAS_MAX_ARRAYS 128
46
47 #define MEGASAS_HBA_SERIAL "QEMU123456"
48 #define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
49 #define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
50
51 #define MEGASAS_FLAG_USE_JBOD 0
52 #define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD)
53 #define MEGASAS_FLAG_USE_QUEUE64 1
54 #define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64)
55
56 static const char *mfi_frame_desc[] = {
57 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
58 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"};
59
60 typedef struct MegasasCmd {
61 uint32_t index;
62 uint16_t flags;
63 uint16_t count;
64 uint64_t context;
65
66 hwaddr pa;
67 hwaddr pa_size;
68 uint32_t dcmd_opcode;
69 union mfi_frame *frame;
70 SCSIRequest *req;
71 QEMUSGList qsg;
72 void *iov_buf;
73 size_t iov_size;
74 size_t iov_offset;
75 struct MegasasState *state;
76 } MegasasCmd;
77
78 typedef struct MegasasState {
79 /*< private >*/
80 PCIDevice parent_obj;
81 /*< public >*/
82
83 MemoryRegion mmio_io;
84 MemoryRegion port_io;
85 MemoryRegion queue_io;
86 uint32_t frame_hi;
87
88 int fw_state;
89 uint32_t fw_sge;
90 uint32_t fw_cmds;
91 uint32_t flags;
92 int fw_luns;
93 int intr_mask;
94 int doorbell;
95 int busy;
96 int diag;
97 int adp_reset;
98 OnOffAuto msi;
99 OnOffAuto msix;
100
101 MegasasCmd *event_cmd;
102 int event_locale;
103 int event_class;
104 int event_count;
105 int shutdown_event;
106 int boot_event;
107
108 uint64_t sas_addr;
109 char *hba_serial;
110
111 uint64_t reply_queue_pa;
112 void *reply_queue;
113 int reply_queue_len;
114 int reply_queue_head;
115 int reply_queue_tail;
116 uint64_t consumer_pa;
117 uint64_t producer_pa;
118
119 MegasasCmd frames[MEGASAS_MAX_FRAMES];
120 DECLARE_BITMAP(frame_map, MEGASAS_MAX_FRAMES);
121 SCSIBus bus;
122 } MegasasState;
123
124 typedef struct MegasasBaseClass {
125 PCIDeviceClass parent_class;
126 const char *product_name;
127 const char *product_version;
128 int mmio_bar;
129 int ioport_bar;
130 int osts;
131 } MegasasBaseClass;
132
133 #define TYPE_MEGASAS_BASE "megasas-base"
134 #define TYPE_MEGASAS_GEN1 "megasas"
135 #define TYPE_MEGASAS_GEN2 "megasas-gen2"
136
137 #define MEGASAS(obj) \
138 OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS_BASE)
139
140 #define MEGASAS_DEVICE_CLASS(oc) \
141 OBJECT_CLASS_CHECK(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
142 #define MEGASAS_DEVICE_GET_CLASS(oc) \
143 OBJECT_GET_CLASS(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
144
145 #define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
146
147 static bool megasas_intr_enabled(MegasasState *s)
148 {
149 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
150 MEGASAS_INTR_DISABLED_MASK) {
151 return true;
152 }
153 return false;
154 }
155
156 static bool megasas_use_queue64(MegasasState *s)
157 {
158 return s->flags & MEGASAS_MASK_USE_QUEUE64;
159 }
160
161 static bool megasas_use_msix(MegasasState *s)
162 {
163 return s->msix != ON_OFF_AUTO_OFF;
164 }
165
166 static bool megasas_is_jbod(MegasasState *s)
167 {
168 return s->flags & MEGASAS_MASK_USE_JBOD;
169 }
170
171 static void megasas_frame_set_cmd_status(MegasasState *s,
172 unsigned long frame, uint8_t v)
173 {
174 PCIDevice *pci = &s->parent_obj;
175 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, cmd_status), v);
176 }
177
178 static void megasas_frame_set_scsi_status(MegasasState *s,
179 unsigned long frame, uint8_t v)
180 {
181 PCIDevice *pci = &s->parent_obj;
182 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, scsi_status), v);
183 }
184
185 /*
186 * Context is considered opaque, but the HBA firmware is running
187 * in little endian mode. So convert it to little endian, too.
188 */
189 static uint64_t megasas_frame_get_context(MegasasState *s,
190 unsigned long frame)
191 {
192 PCIDevice *pci = &s->parent_obj;
193 return ldq_le_pci_dma(pci, frame + offsetof(struct mfi_frame_header, context));
194 }
195
196 static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
197 {
198 return cmd->flags & MFI_FRAME_IEEE_SGL;
199 }
200
201 static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
202 {
203 return cmd->flags & MFI_FRAME_SGL64;
204 }
205
206 static bool megasas_frame_is_sense64(MegasasCmd *cmd)
207 {
208 return cmd->flags & MFI_FRAME_SENSE64;
209 }
210
211 static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
212 union mfi_sgl *sgl)
213 {
214 uint64_t addr;
215
216 if (megasas_frame_is_ieee_sgl(cmd)) {
217 addr = le64_to_cpu(sgl->sg_skinny->addr);
218 } else if (megasas_frame_is_sgl64(cmd)) {
219 addr = le64_to_cpu(sgl->sg64->addr);
220 } else {
221 addr = le32_to_cpu(sgl->sg32->addr);
222 }
223 return addr;
224 }
225
226 static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
227 union mfi_sgl *sgl)
228 {
229 uint32_t len;
230
231 if (megasas_frame_is_ieee_sgl(cmd)) {
232 len = le32_to_cpu(sgl->sg_skinny->len);
233 } else if (megasas_frame_is_sgl64(cmd)) {
234 len = le32_to_cpu(sgl->sg64->len);
235 } else {
236 len = le32_to_cpu(sgl->sg32->len);
237 }
238 return len;
239 }
240
241 static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
242 union mfi_sgl *sgl)
243 {
244 uint8_t *next = (uint8_t *)sgl;
245
246 if (megasas_frame_is_ieee_sgl(cmd)) {
247 next += sizeof(struct mfi_sg_skinny);
248 } else if (megasas_frame_is_sgl64(cmd)) {
249 next += sizeof(struct mfi_sg64);
250 } else {
251 next += sizeof(struct mfi_sg32);
252 }
253
254 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
255 return NULL;
256 }
257 return (union mfi_sgl *)next;
258 }
259
260 static void megasas_soft_reset(MegasasState *s);
261
262 static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
263 {
264 int i;
265 int iov_count = 0;
266 size_t iov_size = 0;
267
268 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
269 iov_count = cmd->frame->header.sge_count;
270 if (iov_count > MEGASAS_MAX_SGE) {
271 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
272 MEGASAS_MAX_SGE);
273 return iov_count;
274 }
275 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
276 for (i = 0; i < iov_count; i++) {
277 dma_addr_t iov_pa, iov_size_p;
278
279 if (!sgl) {
280 trace_megasas_iovec_sgl_underflow(cmd->index, i);
281 goto unmap;
282 }
283 iov_pa = megasas_sgl_get_addr(cmd, sgl);
284 iov_size_p = megasas_sgl_get_len(cmd, sgl);
285 if (!iov_pa || !iov_size_p) {
286 trace_megasas_iovec_sgl_invalid(cmd->index, i,
287 iov_pa, iov_size_p);
288 goto unmap;
289 }
290 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
291 sgl = megasas_sgl_next(cmd, sgl);
292 iov_size += (size_t)iov_size_p;
293 }
294 if (cmd->iov_size > iov_size) {
295 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
296 } else if (cmd->iov_size < iov_size) {
297 trace_megasas_iovec_underflow(cmd->index, iov_size, cmd->iov_size);
298 }
299 cmd->iov_offset = 0;
300 return 0;
301 unmap:
302 qemu_sglist_destroy(&cmd->qsg);
303 return iov_count - i;
304 }
305
306 /*
307 * passthrough sense and io sense are at the same offset
308 */
309 static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
310 uint8_t sense_len)
311 {
312 PCIDevice *pcid = PCI_DEVICE(cmd->state);
313 uint32_t pa_hi = 0, pa_lo;
314 hwaddr pa;
315 int frame_sense_len;
316
317 frame_sense_len = cmd->frame->header.sense_len;
318 if (sense_len > frame_sense_len) {
319 sense_len = frame_sense_len;
320 }
321 if (sense_len) {
322 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
323 if (megasas_frame_is_sense64(cmd)) {
324 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
325 }
326 pa = ((uint64_t) pa_hi << 32) | pa_lo;
327 pci_dma_write(pcid, pa, sense_ptr, sense_len);
328 cmd->frame->header.sense_len = sense_len;
329 }
330 return sense_len;
331 }
332
333 static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
334 {
335 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
336 uint8_t sense_len = 18;
337
338 memset(sense_buf, 0, sense_len);
339 sense_buf[0] = 0xf0;
340 sense_buf[2] = sense.key;
341 sense_buf[7] = 10;
342 sense_buf[12] = sense.asc;
343 sense_buf[13] = sense.ascq;
344 megasas_build_sense(cmd, sense_buf, sense_len);
345 }
346
347 static void megasas_copy_sense(MegasasCmd *cmd)
348 {
349 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
350 uint8_t sense_len;
351
352 sense_len = scsi_req_get_sense(cmd->req, sense_buf,
353 SCSI_SENSE_BUF_SIZE);
354 megasas_build_sense(cmd, sense_buf, sense_len);
355 }
356
357 /*
358 * Format an INQUIRY CDB
359 */
360 static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
361 {
362 memset(cdb, 0, 6);
363 cdb[0] = INQUIRY;
364 if (pg > 0) {
365 cdb[1] = 0x1;
366 cdb[2] = pg;
367 }
368 cdb[3] = (len >> 8) & 0xff;
369 cdb[4] = (len & 0xff);
370 return len;
371 }
372
373 /*
374 * Encode lba and len into a READ_16/WRITE_16 CDB
375 */
376 static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
377 uint32_t len, bool is_write)
378 {
379 memset(cdb, 0x0, 16);
380 if (is_write) {
381 cdb[0] = WRITE_16;
382 } else {
383 cdb[0] = READ_16;
384 }
385 cdb[2] = (lba >> 56) & 0xff;
386 cdb[3] = (lba >> 48) & 0xff;
387 cdb[4] = (lba >> 40) & 0xff;
388 cdb[5] = (lba >> 32) & 0xff;
389 cdb[6] = (lba >> 24) & 0xff;
390 cdb[7] = (lba >> 16) & 0xff;
391 cdb[8] = (lba >> 8) & 0xff;
392 cdb[9] = (lba) & 0xff;
393 cdb[10] = (len >> 24) & 0xff;
394 cdb[11] = (len >> 16) & 0xff;
395 cdb[12] = (len >> 8) & 0xff;
396 cdb[13] = (len) & 0xff;
397 }
398
399 /*
400 * Utility functions
401 */
402 static uint64_t megasas_fw_time(void)
403 {
404 struct tm curtime;
405
406 qemu_get_timedate(&curtime, 0);
407 return ((uint64_t)curtime.tm_sec & 0xff) << 48 |
408 ((uint64_t)curtime.tm_min & 0xff) << 40 |
409 ((uint64_t)curtime.tm_hour & 0xff) << 32 |
410 ((uint64_t)curtime.tm_mday & 0xff) << 24 |
411 ((uint64_t)curtime.tm_mon & 0xff) << 16 |
412 ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
413 }
414
415 /*
416 * Default disk sata address
417 * 0x1221 is the magic number as
418 * present in real hardware,
419 * so use it here, too.
420 */
421 static uint64_t megasas_get_sata_addr(uint16_t id)
422 {
423 uint64_t addr = (0x1221ULL << 48);
424 return addr | ((uint64_t)id << 24);
425 }
426
427 /*
428 * Frame handling
429 */
430 static int megasas_next_index(MegasasState *s, int index, int limit)
431 {
432 index++;
433 if (index == limit) {
434 index = 0;
435 }
436 return index;
437 }
438
439 static MegasasCmd *megasas_lookup_frame(MegasasState *s,
440 hwaddr frame)
441 {
442 MegasasCmd *cmd = NULL;
443 int num = 0, index;
444
445 index = s->reply_queue_head;
446
447 while (num < s->fw_cmds) {
448 if (s->frames[index].pa && s->frames[index].pa == frame) {
449 cmd = &s->frames[index];
450 break;
451 }
452 index = megasas_next_index(s, index, s->fw_cmds);
453 num++;
454 }
455
456 return cmd;
457 }
458
459 static void megasas_unmap_frame(MegasasState *s, MegasasCmd *cmd)
460 {
461 PCIDevice *p = PCI_DEVICE(s);
462
463 if (cmd->pa_size) {
464 pci_dma_unmap(p, cmd->frame, cmd->pa_size, 0, 0);
465 }
466 cmd->frame = NULL;
467 cmd->pa = 0;
468 cmd->pa_size = 0;
469 qemu_sglist_destroy(&cmd->qsg);
470 clear_bit(cmd->index, s->frame_map);
471 }
472
473 /*
474 * This absolutely needs to be locked if
475 * qemu ever goes multithreaded.
476 */
477 static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
478 hwaddr frame, uint64_t context, int count)
479 {
480 PCIDevice *pcid = PCI_DEVICE(s);
481 MegasasCmd *cmd = NULL;
482 int frame_size = MEGASAS_MAX_SGE * sizeof(union mfi_sgl);
483 hwaddr frame_size_p = frame_size;
484 unsigned long index;
485
486 index = 0;
487 while (index < s->fw_cmds) {
488 index = find_next_zero_bit(s->frame_map, s->fw_cmds, index);
489 if (!s->frames[index].pa)
490 break;
491 /* Busy frame found */
492 trace_megasas_qf_mapped(index);
493 }
494 if (index >= s->fw_cmds) {
495 /* All frames busy */
496 trace_megasas_qf_busy(frame);
497 return NULL;
498 }
499 cmd = &s->frames[index];
500 set_bit(index, s->frame_map);
501 trace_megasas_qf_new(index, frame);
502
503 cmd->pa = frame;
504 /* Map all possible frames */
505 cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0);
506 if (frame_size_p != frame_size) {
507 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
508 if (cmd->frame) {
509 megasas_unmap_frame(s, cmd);
510 }
511 s->event_count++;
512 return NULL;
513 }
514 cmd->pa_size = frame_size_p;
515 cmd->context = context;
516 if (!megasas_use_queue64(s)) {
517 cmd->context &= (uint64_t)0xFFFFFFFF;
518 }
519 cmd->count = count;
520 cmd->dcmd_opcode = -1;
521 s->busy++;
522
523 if (s->consumer_pa) {
524 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
525 }
526 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
527 s->reply_queue_head, s->reply_queue_tail, s->busy);
528
529 return cmd;
530 }
531
532 static void megasas_complete_frame(MegasasState *s, uint64_t context)
533 {
534 PCIDevice *pci_dev = PCI_DEVICE(s);
535 int tail, queue_offset;
536
537 /* Decrement busy count */
538 s->busy--;
539 if (s->reply_queue_pa) {
540 /*
541 * Put command on the reply queue.
542 * Context is opaque, but emulation is running in
543 * little endian. So convert it.
544 */
545 if (megasas_use_queue64(s)) {
546 queue_offset = s->reply_queue_head * sizeof(uint64_t);
547 stq_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
548 } else {
549 queue_offset = s->reply_queue_head * sizeof(uint32_t);
550 stl_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
551 }
552 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
553 trace_megasas_qf_complete(context, s->reply_queue_head,
554 s->reply_queue_tail, s->busy);
555 }
556
557 if (megasas_intr_enabled(s)) {
558 /* Update reply queue pointer */
559 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
560 tail = s->reply_queue_head;
561 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
562 trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail,
563 s->busy);
564 stl_le_pci_dma(pci_dev, s->producer_pa, s->reply_queue_head);
565 /* Notify HBA */
566 if (msix_enabled(pci_dev)) {
567 trace_megasas_msix_raise(0);
568 msix_notify(pci_dev, 0);
569 } else if (msi_enabled(pci_dev)) {
570 trace_megasas_msi_raise(0);
571 msi_notify(pci_dev, 0);
572 } else {
573 s->doorbell++;
574 if (s->doorbell == 1) {
575 trace_megasas_irq_raise();
576 pci_irq_assert(pci_dev);
577 }
578 }
579 } else {
580 trace_megasas_qf_complete_noirq(context);
581 }
582 }
583
584 static void megasas_complete_command(MegasasCmd *cmd)
585 {
586 cmd->iov_size = 0;
587 cmd->iov_offset = 0;
588
589 cmd->req->hba_private = NULL;
590 scsi_req_unref(cmd->req);
591 cmd->req = NULL;
592
593 megasas_unmap_frame(cmd->state, cmd);
594 megasas_complete_frame(cmd->state, cmd->context);
595 }
596
597 static void megasas_reset_frames(MegasasState *s)
598 {
599 int i;
600 MegasasCmd *cmd;
601
602 for (i = 0; i < s->fw_cmds; i++) {
603 cmd = &s->frames[i];
604 if (cmd->pa) {
605 megasas_unmap_frame(s, cmd);
606 }
607 }
608 bitmap_zero(s->frame_map, MEGASAS_MAX_FRAMES);
609 }
610
611 static void megasas_abort_command(MegasasCmd *cmd)
612 {
613 /* Never abort internal commands. */
614 if (cmd->dcmd_opcode != -1) {
615 return;
616 }
617 if (cmd->req != NULL) {
618 scsi_req_cancel(cmd->req);
619 }
620 }
621
622 static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
623 {
624 PCIDevice *pcid = PCI_DEVICE(s);
625 uint32_t pa_hi, pa_lo;
626 hwaddr iq_pa, initq_size = sizeof(struct mfi_init_qinfo);
627 struct mfi_init_qinfo *initq = NULL;
628 uint32_t flags;
629 int ret = MFI_STAT_OK;
630
631 if (s->reply_queue_pa) {
632 trace_megasas_initq_mapped(s->reply_queue_pa);
633 goto out;
634 }
635 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
636 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
637 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
638 trace_megasas_init_firmware((uint64_t)iq_pa);
639 initq = pci_dma_map(pcid, iq_pa, &initq_size, 0);
640 if (!initq || initq_size != sizeof(*initq)) {
641 trace_megasas_initq_map_failed(cmd->index);
642 s->event_count++;
643 ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
644 goto out;
645 }
646 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
647 if (s->reply_queue_len > s->fw_cmds) {
648 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
649 s->event_count++;
650 ret = MFI_STAT_INVALID_PARAMETER;
651 goto out;
652 }
653 pa_lo = le32_to_cpu(initq->rq_addr_lo);
654 pa_hi = le32_to_cpu(initq->rq_addr_hi);
655 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
656 pa_lo = le32_to_cpu(initq->ci_addr_lo);
657 pa_hi = le32_to_cpu(initq->ci_addr_hi);
658 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
659 pa_lo = le32_to_cpu(initq->pi_addr_lo);
660 pa_hi = le32_to_cpu(initq->pi_addr_hi);
661 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
662 s->reply_queue_head = ldl_le_pci_dma(pcid, s->producer_pa);
663 s->reply_queue_head %= MEGASAS_MAX_FRAMES;
664 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
665 s->reply_queue_tail %= MEGASAS_MAX_FRAMES;
666 flags = le32_to_cpu(initq->flags);
667 if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
668 s->flags |= MEGASAS_MASK_USE_QUEUE64;
669 }
670 trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
671 s->reply_queue_len, s->reply_queue_head,
672 s->reply_queue_tail, flags);
673 megasas_reset_frames(s);
674 s->fw_state = MFI_FWSTATE_OPERATIONAL;
675 out:
676 if (initq) {
677 pci_dma_unmap(pcid, initq, initq_size, 0, 0);
678 }
679 return ret;
680 }
681
682 static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
683 {
684 dma_addr_t iov_pa, iov_size;
685 int iov_count;
686
687 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
688 iov_count = cmd->frame->header.sge_count;
689 if (!iov_count) {
690 trace_megasas_dcmd_zero_sge(cmd->index);
691 cmd->iov_size = 0;
692 return 0;
693 } else if (iov_count > 1) {
694 trace_megasas_dcmd_invalid_sge(cmd->index, iov_count);
695 cmd->iov_size = 0;
696 return -EINVAL;
697 }
698 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
699 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
700 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
701 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
702 cmd->iov_size = iov_size;
703 return 0;
704 }
705
706 static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
707 {
708 trace_megasas_finish_dcmd(cmd->index, iov_size);
709
710 if (iov_size > cmd->iov_size) {
711 if (megasas_frame_is_ieee_sgl(cmd)) {
712 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
713 } else if (megasas_frame_is_sgl64(cmd)) {
714 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
715 } else {
716 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
717 }
718 }
719 }
720
721 static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
722 {
723 PCIDevice *pci_dev = PCI_DEVICE(s);
724 PCIDeviceClass *pci_class = PCI_DEVICE_GET_CLASS(pci_dev);
725 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
726 struct mfi_ctrl_info info;
727 size_t dcmd_size = sizeof(info);
728 BusChild *kid;
729 int num_pd_disks = 0;
730
731 memset(&info, 0x0, dcmd_size);
732 if (cmd->iov_size < dcmd_size) {
733 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
734 dcmd_size);
735 return MFI_STAT_INVALID_PARAMETER;
736 }
737
738 info.pci.vendor = cpu_to_le16(pci_class->vendor_id);
739 info.pci.device = cpu_to_le16(pci_class->device_id);
740 info.pci.subvendor = cpu_to_le16(pci_class->subsystem_vendor_id);
741 info.pci.subdevice = cpu_to_le16(pci_class->subsystem_id);
742
743 /*
744 * For some reason the firmware supports
745 * only up to 8 device ports.
746 * Despite supporting a far larger number
747 * of devices for the physical devices.
748 * So just display the first 8 devices
749 * in the device port list, independent
750 * of how many logical devices are actually
751 * present.
752 */
753 info.host.type = MFI_INFO_HOST_PCIE;
754 info.device.type = MFI_INFO_DEV_SAS3G;
755 info.device.port_count = 8;
756 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
757 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
758 uint16_t pd_id;
759
760 if (num_pd_disks < 8) {
761 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
762 info.device.port_addr[num_pd_disks] =
763 cpu_to_le64(megasas_get_sata_addr(pd_id));
764 }
765 num_pd_disks++;
766 }
767
768 memcpy(info.product_name, base_class->product_name, 24);
769 snprintf(info.serial_number, 32, "%s", s->hba_serial);
770 snprintf(info.package_version, 0x60, "%s-QEMU", qemu_hw_version());
771 memcpy(info.image_component[0].name, "APP", 3);
772 snprintf(info.image_component[0].version, 10, "%s-QEMU",
773 base_class->product_version);
774 memcpy(info.image_component[0].build_date, "Apr 1 2014", 11);
775 memcpy(info.image_component[0].build_time, "12:34:56", 8);
776 info.image_component_count = 1;
777 if (pci_dev->has_rom) {
778 uint8_t biosver[32];
779 uint8_t *ptr;
780
781 ptr = memory_region_get_ram_ptr(&pci_dev->rom);
782 memcpy(biosver, ptr + 0x41, 31);
783 biosver[31] = 0;
784 memcpy(info.image_component[1].name, "BIOS", 4);
785 memcpy(info.image_component[1].version, biosver,
786 strlen((const char *)biosver));
787 info.image_component_count++;
788 }
789 info.current_fw_time = cpu_to_le32(megasas_fw_time());
790 info.max_arms = 32;
791 info.max_spans = 8;
792 info.max_arrays = MEGASAS_MAX_ARRAYS;
793 info.max_lds = MFI_MAX_LD;
794 info.max_cmds = cpu_to_le16(s->fw_cmds);
795 info.max_sg_elements = cpu_to_le16(s->fw_sge);
796 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
797 if (!megasas_is_jbod(s))
798 info.lds_present = cpu_to_le16(num_pd_disks);
799 info.pd_present = cpu_to_le16(num_pd_disks);
800 info.pd_disks_present = cpu_to_le16(num_pd_disks);
801 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
802 MFI_INFO_HW_MEM |
803 MFI_INFO_HW_FLASH);
804 info.memory_size = cpu_to_le16(512);
805 info.nvram_size = cpu_to_le16(32);
806 info.flash_size = cpu_to_le16(16);
807 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
808 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
809 MFI_INFO_AOPS_SELF_DIAGNOSTIC |
810 MFI_INFO_AOPS_MIXED_ARRAY);
811 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
812 MFI_INFO_LDOPS_ACCESS_POLICY |
813 MFI_INFO_LDOPS_IO_POLICY |
814 MFI_INFO_LDOPS_WRITE_POLICY |
815 MFI_INFO_LDOPS_READ_POLICY);
816 info.max_strips_per_io = cpu_to_le16(s->fw_sge);
817 info.stripe_sz_ops.min = 3;
818 info.stripe_sz_ops.max = ctz32(MEGASAS_MAX_SECTORS + 1);
819 info.properties.pred_fail_poll_interval = cpu_to_le16(300);
820 info.properties.intr_throttle_cnt = cpu_to_le16(16);
821 info.properties.intr_throttle_timeout = cpu_to_le16(50);
822 info.properties.rebuild_rate = 30;
823 info.properties.patrol_read_rate = 30;
824 info.properties.bgi_rate = 30;
825 info.properties.cc_rate = 30;
826 info.properties.recon_rate = 30;
827 info.properties.cache_flush_interval = 4;
828 info.properties.spinup_drv_cnt = 2;
829 info.properties.spinup_delay = 6;
830 info.properties.ecc_bucket_size = 15;
831 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
832 info.properties.expose_encl_devices = 1;
833 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
834 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
835 MFI_INFO_PDOPS_FORCE_OFFLINE);
836 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
837 MFI_INFO_PDMIX_SATA |
838 MFI_INFO_PDMIX_LD);
839
840 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
841 return MFI_STAT_OK;
842 }
843
844 static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
845 {
846 struct mfi_defaults info;
847 size_t dcmd_size = sizeof(struct mfi_defaults);
848
849 memset(&info, 0x0, dcmd_size);
850 if (cmd->iov_size < dcmd_size) {
851 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
852 dcmd_size);
853 return MFI_STAT_INVALID_PARAMETER;
854 }
855
856 info.sas_addr = cpu_to_le64(s->sas_addr);
857 info.stripe_size = 3;
858 info.flush_time = 4;
859 info.background_rate = 30;
860 info.allow_mix_in_enclosure = 1;
861 info.allow_mix_in_ld = 1;
862 info.direct_pd_mapping = 1;
863 /* Enable for BIOS support */
864 info.bios_enumerate_lds = 1;
865 info.disable_ctrl_r = 1;
866 info.expose_enclosure_devices = 1;
867 info.disable_preboot_cli = 1;
868 info.cluster_disable = 1;
869
870 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
871 return MFI_STAT_OK;
872 }
873
874 static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
875 {
876 struct mfi_bios_data info;
877 size_t dcmd_size = sizeof(info);
878
879 memset(&info, 0x0, dcmd_size);
880 if (cmd->iov_size < dcmd_size) {
881 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
882 dcmd_size);
883 return MFI_STAT_INVALID_PARAMETER;
884 }
885 info.continue_on_error = 1;
886 info.verbose = 1;
887 if (megasas_is_jbod(s)) {
888 info.expose_all_drives = 1;
889 }
890
891 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
892 return MFI_STAT_OK;
893 }
894
895 static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
896 {
897 uint64_t fw_time;
898 size_t dcmd_size = sizeof(fw_time);
899
900 fw_time = cpu_to_le64(megasas_fw_time());
901
902 cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg);
903 return MFI_STAT_OK;
904 }
905
906 static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
907 {
908 uint64_t fw_time;
909
910 /* This is a dummy; setting of firmware time is not allowed */
911 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
912
913 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
914 fw_time = cpu_to_le64(megasas_fw_time());
915 return MFI_STAT_OK;
916 }
917
918 static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
919 {
920 struct mfi_evt_log_state info;
921 size_t dcmd_size = sizeof(info);
922
923 memset(&info, 0, dcmd_size);
924
925 info.newest_seq_num = cpu_to_le32(s->event_count);
926 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
927 info.boot_seq_num = cpu_to_le32(s->boot_event);
928
929 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
930 return MFI_STAT_OK;
931 }
932
933 static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
934 {
935 union mfi_evt event;
936
937 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
938 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
939 sizeof(struct mfi_evt_detail));
940 return MFI_STAT_INVALID_PARAMETER;
941 }
942 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
943 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
944 s->event_locale = event.members.locale;
945 s->event_class = event.members.class;
946 s->event_cmd = cmd;
947 /* Decrease busy count; event frame doesn't count here */
948 s->busy--;
949 cmd->iov_size = sizeof(struct mfi_evt_detail);
950 return MFI_STAT_INVALID_STATUS;
951 }
952
953 static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
954 {
955 struct mfi_pd_list info;
956 size_t dcmd_size = sizeof(info);
957 BusChild *kid;
958 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
959
960 memset(&info, 0, dcmd_size);
961 offset = 8;
962 dcmd_limit = offset + sizeof(struct mfi_pd_address);
963 if (cmd->iov_size < dcmd_limit) {
964 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
965 dcmd_limit);
966 return MFI_STAT_INVALID_PARAMETER;
967 }
968
969 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
970 if (max_pd_disks > MFI_MAX_SYS_PDS) {
971 max_pd_disks = MFI_MAX_SYS_PDS;
972 }
973 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
974 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
975 uint16_t pd_id;
976
977 if (num_pd_disks >= max_pd_disks)
978 break;
979
980 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
981 info.addr[num_pd_disks].device_id = cpu_to_le16(pd_id);
982 info.addr[num_pd_disks].encl_device_id = 0xFFFF;
983 info.addr[num_pd_disks].encl_index = 0;
984 info.addr[num_pd_disks].slot_number = sdev->id & 0xFF;
985 info.addr[num_pd_disks].scsi_dev_type = sdev->type;
986 info.addr[num_pd_disks].connect_port_bitmap = 0x1;
987 info.addr[num_pd_disks].sas_addr[0] =
988 cpu_to_le64(megasas_get_sata_addr(pd_id));
989 num_pd_disks++;
990 offset += sizeof(struct mfi_pd_address);
991 }
992 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
993 max_pd_disks, offset);
994
995 info.size = cpu_to_le32(offset);
996 info.count = cpu_to_le32(num_pd_disks);
997
998 cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg);
999 return MFI_STAT_OK;
1000 }
1001
1002 static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
1003 {
1004 uint16_t flags;
1005
1006 /* mbox0 contains flags */
1007 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1008 trace_megasas_dcmd_pd_list_query(cmd->index, flags);
1009 if (flags == MR_PD_QUERY_TYPE_ALL ||
1010 megasas_is_jbod(s)) {
1011 return megasas_dcmd_pd_get_list(s, cmd);
1012 }
1013
1014 return MFI_STAT_OK;
1015 }
1016
1017 static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
1018 MegasasCmd *cmd)
1019 {
1020 struct mfi_pd_info *info = cmd->iov_buf;
1021 size_t dcmd_size = sizeof(struct mfi_pd_info);
1022 uint64_t pd_size;
1023 uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
1024 uint8_t cmdbuf[6];
1025 size_t len, resid;
1026
1027 if (!cmd->iov_buf) {
1028 cmd->iov_buf = g_malloc0(dcmd_size);
1029 info = cmd->iov_buf;
1030 info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */
1031 info->vpd_page83[0] = 0x7f;
1032 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
1033 cmd->req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1034 if (!cmd->req) {
1035 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1036 "PD get info std inquiry");
1037 g_free(cmd->iov_buf);
1038 cmd->iov_buf = NULL;
1039 return MFI_STAT_FLASH_ALLOC_FAIL;
1040 }
1041 trace_megasas_dcmd_internal_submit(cmd->index,
1042 "PD get info std inquiry", lun);
1043 len = scsi_req_enqueue(cmd->req);
1044 if (len > 0) {
1045 cmd->iov_size = len;
1046 scsi_req_continue(cmd->req);
1047 }
1048 return MFI_STAT_INVALID_STATUS;
1049 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
1050 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
1051 cmd->req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1052 if (!cmd->req) {
1053 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1054 "PD get info vpd inquiry");
1055 return MFI_STAT_FLASH_ALLOC_FAIL;
1056 }
1057 trace_megasas_dcmd_internal_submit(cmd->index,
1058 "PD get info vpd inquiry", lun);
1059 len = scsi_req_enqueue(cmd->req);
1060 if (len > 0) {
1061 cmd->iov_size = len;
1062 scsi_req_continue(cmd->req);
1063 }
1064 return MFI_STAT_INVALID_STATUS;
1065 }
1066 /* Finished, set FW state */
1067 if ((info->inquiry_data[0] >> 5) == 0) {
1068 if (megasas_is_jbod(cmd->state)) {
1069 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1070 } else {
1071 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1072 }
1073 } else {
1074 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1075 }
1076
1077 info->ref.v.device_id = cpu_to_le16(pd_id);
1078 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1079 MFI_PD_DDF_TYPE_INTF_SAS);
1080 blk_get_geometry(sdev->conf.blk, &pd_size);
1081 info->raw_size = cpu_to_le64(pd_size);
1082 info->non_coerced_size = cpu_to_le64(pd_size);
1083 info->coerced_size = cpu_to_le64(pd_size);
1084 info->encl_device_id = 0xFFFF;
1085 info->slot_number = (sdev->id & 0xFF);
1086 info->path_info.count = 1;
1087 info->path_info.sas_addr[0] =
1088 cpu_to_le64(megasas_get_sata_addr(pd_id));
1089 info->connected_port_bitmap = 0x1;
1090 info->device_speed = 1;
1091 info->link_speed = 1;
1092 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1093 g_free(cmd->iov_buf);
1094 cmd->iov_size = dcmd_size - resid;
1095 cmd->iov_buf = NULL;
1096 return MFI_STAT_OK;
1097 }
1098
1099 static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1100 {
1101 size_t dcmd_size = sizeof(struct mfi_pd_info);
1102 uint16_t pd_id;
1103 uint8_t target_id, lun_id;
1104 SCSIDevice *sdev = NULL;
1105 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1106
1107 if (cmd->iov_size < dcmd_size) {
1108 return MFI_STAT_INVALID_PARAMETER;
1109 }
1110
1111 /* mbox0 has the ID */
1112 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1113 target_id = (pd_id >> 8) & 0xFF;
1114 lun_id = pd_id & 0xFF;
1115 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1116 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1117
1118 if (sdev) {
1119 /* Submit inquiry */
1120 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1121 }
1122
1123 return retval;
1124 }
1125
1126 static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1127 {
1128 struct mfi_ld_list info;
1129 size_t dcmd_size = sizeof(info), resid;
1130 uint32_t num_ld_disks = 0, max_ld_disks;
1131 uint64_t ld_size;
1132 BusChild *kid;
1133
1134 memset(&info, 0, dcmd_size);
1135 if (cmd->iov_size > dcmd_size) {
1136 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1137 dcmd_size);
1138 return MFI_STAT_INVALID_PARAMETER;
1139 }
1140
1141 max_ld_disks = (cmd->iov_size - 8) / 16;
1142 if (megasas_is_jbod(s)) {
1143 max_ld_disks = 0;
1144 }
1145 if (max_ld_disks > MFI_MAX_LD) {
1146 max_ld_disks = MFI_MAX_LD;
1147 }
1148 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1149 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1150
1151 if (num_ld_disks >= max_ld_disks) {
1152 break;
1153 }
1154 /* Logical device size is in blocks */
1155 blk_get_geometry(sdev->conf.blk, &ld_size);
1156 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
1157 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1158 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1159 num_ld_disks++;
1160 }
1161 info.ld_count = cpu_to_le32(num_ld_disks);
1162 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1163
1164 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1165 cmd->iov_size = dcmd_size - resid;
1166 return MFI_STAT_OK;
1167 }
1168
1169 static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
1170 {
1171 uint16_t flags;
1172 struct mfi_ld_targetid_list info;
1173 size_t dcmd_size = sizeof(info), resid;
1174 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1175 BusChild *kid;
1176
1177 /* mbox0 contains flags */
1178 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1179 trace_megasas_dcmd_ld_list_query(cmd->index, flags);
1180 if (flags != MR_LD_QUERY_TYPE_ALL &&
1181 flags != MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) {
1182 max_ld_disks = 0;
1183 }
1184
1185 memset(&info, 0, dcmd_size);
1186 if (cmd->iov_size < 12) {
1187 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1188 dcmd_size);
1189 return MFI_STAT_INVALID_PARAMETER;
1190 }
1191 dcmd_size = sizeof(uint32_t) * 2 + 3;
1192 max_ld_disks = cmd->iov_size - dcmd_size;
1193 if (megasas_is_jbod(s)) {
1194 max_ld_disks = 0;
1195 }
1196 if (max_ld_disks > MFI_MAX_LD) {
1197 max_ld_disks = MFI_MAX_LD;
1198 }
1199 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1200 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1201
1202 if (num_ld_disks >= max_ld_disks) {
1203 break;
1204 }
1205 info.targetid[num_ld_disks] = sdev->lun;
1206 num_ld_disks++;
1207 dcmd_size++;
1208 }
1209 info.ld_count = cpu_to_le32(num_ld_disks);
1210 info.size = dcmd_size;
1211 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1212
1213 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1214 cmd->iov_size = dcmd_size - resid;
1215 return MFI_STAT_OK;
1216 }
1217
1218 static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1219 MegasasCmd *cmd)
1220 {
1221 struct mfi_ld_info *info = cmd->iov_buf;
1222 size_t dcmd_size = sizeof(struct mfi_ld_info);
1223 uint8_t cdb[6];
1224 ssize_t len, resid;
1225 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
1226 uint64_t ld_size;
1227
1228 if (!cmd->iov_buf) {
1229 cmd->iov_buf = g_malloc0(dcmd_size);
1230 info = cmd->iov_buf;
1231 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
1232 cmd->req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd);
1233 if (!cmd->req) {
1234 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1235 "LD get info vpd inquiry");
1236 g_free(cmd->iov_buf);
1237 cmd->iov_buf = NULL;
1238 return MFI_STAT_FLASH_ALLOC_FAIL;
1239 }
1240 trace_megasas_dcmd_internal_submit(cmd->index,
1241 "LD get info vpd inquiry", lun);
1242 len = scsi_req_enqueue(cmd->req);
1243 if (len > 0) {
1244 cmd->iov_size = len;
1245 scsi_req_continue(cmd->req);
1246 }
1247 return MFI_STAT_INVALID_STATUS;
1248 }
1249
1250 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1251 info->ld_config.properties.ld.v.target_id = lun;
1252 info->ld_config.params.stripe_size = 3;
1253 info->ld_config.params.num_drives = 1;
1254 info->ld_config.params.is_consistent = 1;
1255 /* Logical device size is in blocks */
1256 blk_get_geometry(sdev->conf.blk, &ld_size);
1257 info->size = cpu_to_le64(ld_size);
1258 memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1259 info->ld_config.span[0].start_block = 0;
1260 info->ld_config.span[0].num_blocks = info->size;
1261 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1262
1263 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1264 g_free(cmd->iov_buf);
1265 cmd->iov_size = dcmd_size - resid;
1266 cmd->iov_buf = NULL;
1267 return MFI_STAT_OK;
1268 }
1269
1270 static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1271 {
1272 struct mfi_ld_info info;
1273 size_t dcmd_size = sizeof(info);
1274 uint16_t ld_id;
1275 uint32_t max_ld_disks = s->fw_luns;
1276 SCSIDevice *sdev = NULL;
1277 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1278
1279 if (cmd->iov_size < dcmd_size) {
1280 return MFI_STAT_INVALID_PARAMETER;
1281 }
1282
1283 /* mbox0 has the ID */
1284 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1285 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1286
1287 if (megasas_is_jbod(s)) {
1288 return MFI_STAT_DEVICE_NOT_FOUND;
1289 }
1290
1291 if (ld_id < max_ld_disks) {
1292 sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1293 }
1294
1295 if (sdev) {
1296 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1297 }
1298
1299 return retval;
1300 }
1301
1302 static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1303 {
1304 uint8_t data[4096] = { 0 };
1305 struct mfi_config_data *info;
1306 int num_pd_disks = 0, array_offset, ld_offset;
1307 BusChild *kid;
1308
1309 if (cmd->iov_size > 4096) {
1310 return MFI_STAT_INVALID_PARAMETER;
1311 }
1312
1313 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1314 num_pd_disks++;
1315 }
1316 info = (struct mfi_config_data *)&data;
1317 /*
1318 * Array mapping:
1319 * - One array per SCSI device
1320 * - One logical drive per SCSI device
1321 * spanning the entire device
1322 */
1323 info->array_count = num_pd_disks;
1324 info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1325 info->log_drv_count = num_pd_disks;
1326 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1327 info->spares_count = 0;
1328 info->spares_size = sizeof(struct mfi_spare);
1329 info->size = sizeof(struct mfi_config_data) + info->array_size +
1330 info->log_drv_size;
1331 if (info->size > 4096) {
1332 return MFI_STAT_INVALID_PARAMETER;
1333 }
1334
1335 array_offset = sizeof(struct mfi_config_data);
1336 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1337
1338 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1339 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1340 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
1341 struct mfi_array *array;
1342 struct mfi_ld_config *ld;
1343 uint64_t pd_size;
1344 int i;
1345
1346 array = (struct mfi_array *)(data + array_offset);
1347 blk_get_geometry(sdev->conf.blk, &pd_size);
1348 array->size = cpu_to_le64(pd_size);
1349 array->num_drives = 1;
1350 array->array_ref = cpu_to_le16(sdev_id);
1351 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1352 array->pd[0].ref.v.seq_num = 0;
1353 array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1354 array->pd[0].encl.pd = 0xFF;
1355 array->pd[0].encl.slot = (sdev->id & 0xFF);
1356 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1357 array->pd[i].ref.v.device_id = 0xFFFF;
1358 array->pd[i].ref.v.seq_num = 0;
1359 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1360 array->pd[i].encl.pd = 0xFF;
1361 array->pd[i].encl.slot = 0xFF;
1362 }
1363 array_offset += sizeof(struct mfi_array);
1364 ld = (struct mfi_ld_config *)(data + ld_offset);
1365 memset(ld, 0, sizeof(struct mfi_ld_config));
1366 ld->properties.ld.v.target_id = sdev->id;
1367 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1368 MR_LD_CACHE_READ_ADAPTIVE;
1369 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1370 MR_LD_CACHE_READ_ADAPTIVE;
1371 ld->params.state = MFI_LD_STATE_OPTIMAL;
1372 ld->params.stripe_size = 3;
1373 ld->params.num_drives = 1;
1374 ld->params.span_depth = 1;
1375 ld->params.is_consistent = 1;
1376 ld->span[0].start_block = 0;
1377 ld->span[0].num_blocks = cpu_to_le64(pd_size);
1378 ld->span[0].array_ref = cpu_to_le16(sdev_id);
1379 ld_offset += sizeof(struct mfi_ld_config);
1380 }
1381
1382 cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg);
1383 return MFI_STAT_OK;
1384 }
1385
1386 static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1387 {
1388 struct mfi_ctrl_props info;
1389 size_t dcmd_size = sizeof(info);
1390
1391 memset(&info, 0x0, dcmd_size);
1392 if (cmd->iov_size < dcmd_size) {
1393 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1394 dcmd_size);
1395 return MFI_STAT_INVALID_PARAMETER;
1396 }
1397 info.pred_fail_poll_interval = cpu_to_le16(300);
1398 info.intr_throttle_cnt = cpu_to_le16(16);
1399 info.intr_throttle_timeout = cpu_to_le16(50);
1400 info.rebuild_rate = 30;
1401 info.patrol_read_rate = 30;
1402 info.bgi_rate = 30;
1403 info.cc_rate = 30;
1404 info.recon_rate = 30;
1405 info.cache_flush_interval = 4;
1406 info.spinup_drv_cnt = 2;
1407 info.spinup_delay = 6;
1408 info.ecc_bucket_size = 15;
1409 info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1410 info.expose_encl_devices = 1;
1411
1412 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1413 return MFI_STAT_OK;
1414 }
1415
1416 static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1417 {
1418 blk_drain_all();
1419 return MFI_STAT_OK;
1420 }
1421
1422 static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1423 {
1424 s->fw_state = MFI_FWSTATE_READY;
1425 return MFI_STAT_OK;
1426 }
1427
1428 /* Some implementations use CLUSTER RESET LD to simulate a device reset */
1429 static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1430 {
1431 uint16_t target_id;
1432 int i;
1433
1434 /* mbox0 contains the device index */
1435 target_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1436 trace_megasas_dcmd_reset_ld(cmd->index, target_id);
1437 for (i = 0; i < s->fw_cmds; i++) {
1438 MegasasCmd *tmp_cmd = &s->frames[i];
1439 if (tmp_cmd->req && tmp_cmd->req->dev->id == target_id) {
1440 SCSIDevice *d = tmp_cmd->req->dev;
1441 qdev_reset_all(&d->qdev);
1442 }
1443 }
1444 return MFI_STAT_OK;
1445 }
1446
1447 static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1448 {
1449 struct mfi_ctrl_props info;
1450 size_t dcmd_size = sizeof(info);
1451
1452 if (cmd->iov_size < dcmd_size) {
1453 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1454 dcmd_size);
1455 return MFI_STAT_INVALID_PARAMETER;
1456 }
1457 dma_buf_write((uint8_t *)&info, dcmd_size, &cmd->qsg);
1458 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
1459 return MFI_STAT_OK;
1460 }
1461
1462 static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1463 {
1464 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1465 return MFI_STAT_OK;
1466 }
1467
1468 static const struct dcmd_cmd_tbl_t {
1469 int opcode;
1470 const char *desc;
1471 int (*func)(MegasasState *s, MegasasCmd *cmd);
1472 } dcmd_cmd_tbl[] = {
1473 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1474 megasas_dcmd_dummy },
1475 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1476 megasas_ctrl_get_info },
1477 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1478 megasas_dcmd_get_properties },
1479 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1480 megasas_dcmd_set_properties },
1481 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1482 megasas_dcmd_dummy },
1483 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1484 megasas_dcmd_dummy },
1485 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1486 megasas_dcmd_dummy },
1487 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1488 megasas_dcmd_dummy },
1489 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1490 megasas_dcmd_dummy },
1491 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1492 megasas_event_info },
1493 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1494 megasas_dcmd_dummy },
1495 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1496 megasas_event_wait },
1497 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1498 megasas_ctrl_shutdown },
1499 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1500 megasas_dcmd_dummy },
1501 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1502 megasas_dcmd_get_fw_time },
1503 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1504 megasas_dcmd_set_fw_time },
1505 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1506 megasas_dcmd_get_bios_info },
1507 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1508 megasas_dcmd_dummy },
1509 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1510 megasas_mfc_get_defaults },
1511 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1512 megasas_dcmd_dummy },
1513 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1514 megasas_cache_flush },
1515 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1516 megasas_dcmd_pd_get_list },
1517 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1518 megasas_dcmd_pd_list_query },
1519 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1520 megasas_dcmd_pd_get_info },
1521 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1522 megasas_dcmd_dummy },
1523 { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1524 megasas_dcmd_dummy },
1525 { MFI_DCMD_PD_BLINK, "PD_BLINK",
1526 megasas_dcmd_dummy },
1527 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1528 megasas_dcmd_dummy },
1529 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1530 megasas_dcmd_ld_get_list},
1531 { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY",
1532 megasas_dcmd_ld_list_query },
1533 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1534 megasas_dcmd_ld_get_info },
1535 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1536 megasas_dcmd_dummy },
1537 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1538 megasas_dcmd_dummy },
1539 { MFI_DCMD_LD_DELETE, "LD_DELETE",
1540 megasas_dcmd_dummy },
1541 { MFI_DCMD_CFG_READ, "CFG_READ",
1542 megasas_dcmd_cfg_read },
1543 { MFI_DCMD_CFG_ADD, "CFG_ADD",
1544 megasas_dcmd_dummy },
1545 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1546 megasas_dcmd_dummy },
1547 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1548 megasas_dcmd_dummy },
1549 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1550 megasas_dcmd_dummy },
1551 { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1552 megasas_dcmd_dummy },
1553 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1554 megasas_dcmd_dummy },
1555 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1556 megasas_dcmd_dummy },
1557 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1558 megasas_dcmd_dummy },
1559 { MFI_DCMD_CLUSTER, "CLUSTER",
1560 megasas_dcmd_dummy },
1561 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1562 megasas_dcmd_dummy },
1563 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1564 megasas_cluster_reset_ld },
1565 { -1, NULL, NULL }
1566 };
1567
1568 static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1569 {
1570 int retval = 0;
1571 size_t len;
1572 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1573
1574 cmd->dcmd_opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1575 trace_megasas_handle_dcmd(cmd->index, cmd->dcmd_opcode);
1576 if (megasas_map_dcmd(s, cmd) < 0) {
1577 return MFI_STAT_MEMORY_NOT_AVAILABLE;
1578 }
1579 while (cmdptr->opcode != -1 && cmdptr->opcode != cmd->dcmd_opcode) {
1580 cmdptr++;
1581 }
1582 len = cmd->iov_size;
1583 if (cmdptr->opcode == -1) {
1584 trace_megasas_dcmd_unhandled(cmd->index, cmd->dcmd_opcode, len);
1585 retval = megasas_dcmd_dummy(s, cmd);
1586 } else {
1587 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1588 retval = cmdptr->func(s, cmd);
1589 }
1590 if (retval != MFI_STAT_INVALID_STATUS) {
1591 megasas_finish_dcmd(cmd, len);
1592 }
1593 return retval;
1594 }
1595
1596 static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
1597 SCSIRequest *req, size_t resid)
1598 {
1599 int retval = MFI_STAT_OK;
1600 int lun = req->lun;
1601
1602 trace_megasas_dcmd_internal_finish(cmd->index, cmd->dcmd_opcode, lun);
1603 cmd->iov_size -= resid;
1604 switch (cmd->dcmd_opcode) {
1605 case MFI_DCMD_PD_GET_INFO:
1606 retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1607 break;
1608 case MFI_DCMD_LD_GET_INFO:
1609 retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1610 break;
1611 default:
1612 trace_megasas_dcmd_internal_invalid(cmd->index, cmd->dcmd_opcode);
1613 retval = MFI_STAT_INVALID_DCMD;
1614 break;
1615 }
1616 if (retval != MFI_STAT_INVALID_STATUS) {
1617 megasas_finish_dcmd(cmd, cmd->iov_size);
1618 }
1619 return retval;
1620 }
1621
1622 static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1623 {
1624 int len;
1625
1626 len = scsi_req_enqueue(cmd->req);
1627 if (len < 0) {
1628 len = -len;
1629 }
1630 if (len > 0) {
1631 if (len > cmd->iov_size) {
1632 if (is_write) {
1633 trace_megasas_iov_write_overflow(cmd->index, len,
1634 cmd->iov_size);
1635 } else {
1636 trace_megasas_iov_read_overflow(cmd->index, len,
1637 cmd->iov_size);
1638 }
1639 }
1640 if (len < cmd->iov_size) {
1641 if (is_write) {
1642 trace_megasas_iov_write_underflow(cmd->index, len,
1643 cmd->iov_size);
1644 } else {
1645 trace_megasas_iov_read_underflow(cmd->index, len,
1646 cmd->iov_size);
1647 }
1648 cmd->iov_size = len;
1649 }
1650 scsi_req_continue(cmd->req);
1651 }
1652 return len;
1653 }
1654
1655 static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
1656 int frame_cmd)
1657 {
1658 uint8_t *cdb;
1659 int target_id, lun_id, cdb_len;
1660 bool is_write;
1661 struct SCSIDevice *sdev = NULL;
1662 bool is_logical = (frame_cmd == MFI_CMD_LD_SCSI_IO);
1663
1664 cdb = cmd->frame->pass.cdb;
1665 target_id = cmd->frame->header.target_id;
1666 lun_id = cmd->frame->header.lun_id;
1667 cdb_len = cmd->frame->header.cdb_len;
1668
1669 if (is_logical) {
1670 if (target_id >= MFI_MAX_LD || lun_id != 0) {
1671 trace_megasas_scsi_target_not_present(
1672 mfi_frame_desc[frame_cmd], is_logical, target_id, lun_id);
1673 return MFI_STAT_DEVICE_NOT_FOUND;
1674 }
1675 }
1676 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1677
1678 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
1679 trace_megasas_handle_scsi(mfi_frame_desc[frame_cmd], is_logical,
1680 target_id, lun_id, sdev, cmd->iov_size);
1681
1682 if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1683 trace_megasas_scsi_target_not_present(
1684 mfi_frame_desc[frame_cmd], is_logical, target_id, lun_id);
1685 return MFI_STAT_DEVICE_NOT_FOUND;
1686 }
1687
1688 if (cdb_len > 16) {
1689 trace_megasas_scsi_invalid_cdb_len(
1690 mfi_frame_desc[frame_cmd], is_logical,
1691 target_id, lun_id, cdb_len);
1692 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1693 cmd->frame->header.scsi_status = CHECK_CONDITION;
1694 s->event_count++;
1695 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1696 }
1697
1698 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1699 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1700 cmd->frame->header.scsi_status = CHECK_CONDITION;
1701 s->event_count++;
1702 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1703 }
1704
1705 cmd->req = scsi_req_new(sdev, cmd->index, lun_id, cdb, cmd);
1706 if (!cmd->req) {
1707 trace_megasas_scsi_req_alloc_failed(
1708 mfi_frame_desc[frame_cmd], target_id, lun_id);
1709 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1710 cmd->frame->header.scsi_status = BUSY;
1711 s->event_count++;
1712 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1713 }
1714
1715 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
1716 if (cmd->iov_size) {
1717 if (is_write) {
1718 trace_megasas_scsi_write_start(cmd->index, cmd->iov_size);
1719 } else {
1720 trace_megasas_scsi_read_start(cmd->index, cmd->iov_size);
1721 }
1722 } else {
1723 trace_megasas_scsi_nodata(cmd->index);
1724 }
1725 megasas_enqueue_req(cmd, is_write);
1726 return MFI_STAT_INVALID_STATUS;
1727 }
1728
1729 static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd, int frame_cmd)
1730 {
1731 uint32_t lba_count, lba_start_hi, lba_start_lo;
1732 uint64_t lba_start;
1733 bool is_write = (frame_cmd == MFI_CMD_LD_WRITE);
1734 uint8_t cdb[16];
1735 int len;
1736 struct SCSIDevice *sdev = NULL;
1737 int target_id, lun_id, cdb_len;
1738
1739 lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1740 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1741 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1742 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1743
1744 target_id = cmd->frame->header.target_id;
1745 lun_id = cmd->frame->header.lun_id;
1746 cdb_len = cmd->frame->header.cdb_len;
1747
1748 if (target_id < MFI_MAX_LD && lun_id == 0) {
1749 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1750 }
1751
1752 trace_megasas_handle_io(cmd->index,
1753 mfi_frame_desc[frame_cmd], target_id, lun_id,
1754 (unsigned long)lba_start, (unsigned long)lba_count);
1755 if (!sdev) {
1756 trace_megasas_io_target_not_present(cmd->index,
1757 mfi_frame_desc[frame_cmd], target_id, lun_id);
1758 return MFI_STAT_DEVICE_NOT_FOUND;
1759 }
1760
1761 if (cdb_len > 16) {
1762 trace_megasas_scsi_invalid_cdb_len(
1763 mfi_frame_desc[frame_cmd], 1, target_id, lun_id, cdb_len);
1764 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1765 cmd->frame->header.scsi_status = CHECK_CONDITION;
1766 s->event_count++;
1767 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1768 }
1769
1770 cmd->iov_size = lba_count * sdev->blocksize;
1771 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1772 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1773 cmd->frame->header.scsi_status = CHECK_CONDITION;
1774 s->event_count++;
1775 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1776 }
1777
1778 megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1779 cmd->req = scsi_req_new(sdev, cmd->index,
1780 lun_id, cdb, cmd);
1781 if (!cmd->req) {
1782 trace_megasas_scsi_req_alloc_failed(
1783 mfi_frame_desc[frame_cmd], target_id, lun_id);
1784 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1785 cmd->frame->header.scsi_status = BUSY;
1786 s->event_count++;
1787 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1788 }
1789 len = megasas_enqueue_req(cmd, is_write);
1790 if (len > 0) {
1791 if (is_write) {
1792 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1793 } else {
1794 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1795 }
1796 }
1797 return MFI_STAT_INVALID_STATUS;
1798 }
1799
1800 static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1801 {
1802 MegasasCmd *cmd = req->hba_private;
1803
1804 if (cmd->dcmd_opcode != -1) {
1805 return NULL;
1806 } else {
1807 return &cmd->qsg;
1808 }
1809 }
1810
1811 static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1812 {
1813 MegasasCmd *cmd = req->hba_private;
1814 uint8_t *buf;
1815
1816 trace_megasas_io_complete(cmd->index, len);
1817
1818 if (cmd->dcmd_opcode != -1) {
1819 scsi_req_continue(req);
1820 return;
1821 }
1822
1823 buf = scsi_req_get_buf(req);
1824 if (cmd->dcmd_opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
1825 struct mfi_pd_info *info = cmd->iov_buf;
1826
1827 if (info->inquiry_data[0] == 0x7f) {
1828 memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1829 memcpy(info->inquiry_data, buf, len);
1830 } else if (info->vpd_page83[0] == 0x7f) {
1831 memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1832 memcpy(info->vpd_page83, buf, len);
1833 }
1834 scsi_req_continue(req);
1835 } else if (cmd->dcmd_opcode == MFI_DCMD_LD_GET_INFO) {
1836 struct mfi_ld_info *info = cmd->iov_buf;
1837
1838 if (cmd->iov_buf) {
1839 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1840 scsi_req_continue(req);
1841 }
1842 }
1843 }
1844
1845 static void megasas_command_complete(SCSIRequest *req, uint32_t status,
1846 size_t resid)
1847 {
1848 MegasasCmd *cmd = req->hba_private;
1849 uint8_t cmd_status = MFI_STAT_OK;
1850
1851 trace_megasas_command_complete(cmd->index, status, resid);
1852
1853 if (req->io_canceled) {
1854 return;
1855 }
1856
1857 if (cmd->dcmd_opcode != -1) {
1858 /*
1859 * Internal command complete
1860 */
1861 cmd_status = megasas_finish_internal_dcmd(cmd, req, resid);
1862 if (cmd_status == MFI_STAT_INVALID_STATUS) {
1863 return;
1864 }
1865 } else {
1866 req->status = status;
1867 trace_megasas_scsi_complete(cmd->index, req->status,
1868 cmd->iov_size, req->cmd.xfer);
1869 if (req->status != GOOD) {
1870 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1871 }
1872 if (req->status == CHECK_CONDITION) {
1873 megasas_copy_sense(cmd);
1874 }
1875
1876 cmd->frame->header.scsi_status = req->status;
1877 }
1878 cmd->frame->header.cmd_status = cmd_status;
1879 megasas_complete_command(cmd);
1880 }
1881
1882 static void megasas_command_cancelled(SCSIRequest *req)
1883 {
1884 MegasasCmd *cmd = req->hba_private;
1885
1886 if (!cmd) {
1887 return;
1888 }
1889 cmd->frame->header.cmd_status = MFI_STAT_SCSI_IO_FAILED;
1890 megasas_complete_command(cmd);
1891 }
1892
1893 static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1894 {
1895 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
1896 hwaddr abort_addr, addr_hi, addr_lo;
1897 MegasasCmd *abort_cmd;
1898
1899 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1900 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1901 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1902
1903 abort_cmd = megasas_lookup_frame(s, abort_addr);
1904 if (!abort_cmd) {
1905 trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1906 s->event_count++;
1907 return MFI_STAT_OK;
1908 }
1909 if (!megasas_use_queue64(s)) {
1910 abort_ctx &= (uint64_t)0xFFFFFFFF;
1911 }
1912 if (abort_cmd->context != abort_ctx) {
1913 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->context,
1914 abort_cmd->index);
1915 s->event_count++;
1916 return MFI_STAT_ABORT_NOT_POSSIBLE;
1917 }
1918 trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1919 megasas_abort_command(abort_cmd);
1920 if (!s->event_cmd || abort_cmd != s->event_cmd) {
1921 s->event_cmd = NULL;
1922 }
1923 s->event_count++;
1924 return MFI_STAT_OK;
1925 }
1926
1927 static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1928 uint32_t frame_count)
1929 {
1930 uint8_t frame_status = MFI_STAT_INVALID_CMD;
1931 uint64_t frame_context;
1932 int frame_cmd;
1933 MegasasCmd *cmd;
1934
1935 /*
1936 * Always read 64bit context, top bits will be
1937 * masked out if required in megasas_enqueue_frame()
1938 */
1939 frame_context = megasas_frame_get_context(s, frame_addr);
1940
1941 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1942 if (!cmd) {
1943 /* reply queue full */
1944 trace_megasas_frame_busy(frame_addr);
1945 megasas_frame_set_scsi_status(s, frame_addr, BUSY);
1946 megasas_frame_set_cmd_status(s, frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
1947 megasas_complete_frame(s, frame_context);
1948 s->event_count++;
1949 return;
1950 }
1951 frame_cmd = cmd->frame->header.frame_cmd;
1952 switch (frame_cmd) {
1953 case MFI_CMD_INIT:
1954 frame_status = megasas_init_firmware(s, cmd);
1955 break;
1956 case MFI_CMD_DCMD:
1957 frame_status = megasas_handle_dcmd(s, cmd);
1958 break;
1959 case MFI_CMD_ABORT:
1960 frame_status = megasas_handle_abort(s, cmd);
1961 break;
1962 case MFI_CMD_PD_SCSI_IO:
1963 case MFI_CMD_LD_SCSI_IO:
1964 frame_status = megasas_handle_scsi(s, cmd, frame_cmd);
1965 break;
1966 case MFI_CMD_LD_READ:
1967 case MFI_CMD_LD_WRITE:
1968 frame_status = megasas_handle_io(s, cmd, frame_cmd);
1969 break;
1970 default:
1971 trace_megasas_unhandled_frame_cmd(cmd->index, frame_cmd);
1972 s->event_count++;
1973 break;
1974 }
1975 if (frame_status != MFI_STAT_INVALID_STATUS) {
1976 if (cmd->frame) {
1977 cmd->frame->header.cmd_status = frame_status;
1978 } else {
1979 megasas_frame_set_cmd_status(s, frame_addr, frame_status);
1980 }
1981 megasas_unmap_frame(s, cmd);
1982 megasas_complete_frame(s, cmd->context);
1983 }
1984 }
1985
1986 static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
1987 unsigned size)
1988 {
1989 MegasasState *s = opaque;
1990 PCIDevice *pci_dev = PCI_DEVICE(s);
1991 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
1992 uint32_t retval = 0;
1993
1994 switch (addr) {
1995 case MFI_IDB:
1996 retval = 0;
1997 trace_megasas_mmio_readl("MFI_IDB", retval);
1998 break;
1999 case MFI_OMSG0:
2000 case MFI_OSP0:
2001 retval = (msix_present(pci_dev) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
2002 (s->fw_state & MFI_FWSTATE_MASK) |
2003 ((s->fw_sge & 0xff) << 16) |
2004 (s->fw_cmds & 0xFFFF);
2005 trace_megasas_mmio_readl(addr == MFI_OMSG0 ? "MFI_OMSG0" : "MFI_OSP0",
2006 retval);
2007 break;
2008 case MFI_OSTS:
2009 if (megasas_intr_enabled(s) && s->doorbell) {
2010 retval = base_class->osts;
2011 }
2012 trace_megasas_mmio_readl("MFI_OSTS", retval);
2013 break;
2014 case MFI_OMSK:
2015 retval = s->intr_mask;
2016 trace_megasas_mmio_readl("MFI_OMSK", retval);
2017 break;
2018 case MFI_ODCR0:
2019 retval = s->doorbell ? 1 : 0;
2020 trace_megasas_mmio_readl("MFI_ODCR0", retval);
2021 break;
2022 case MFI_DIAG:
2023 retval = s->diag;
2024 trace_megasas_mmio_readl("MFI_DIAG", retval);
2025 break;
2026 case MFI_OSP1:
2027 retval = 15;
2028 trace_megasas_mmio_readl("MFI_OSP1", retval);
2029 break;
2030 default:
2031 trace_megasas_mmio_invalid_readl(addr);
2032 break;
2033 }
2034 return retval;
2035 }
2036
2037 static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d};
2038
2039 static void megasas_mmio_write(void *opaque, hwaddr addr,
2040 uint64_t val, unsigned size)
2041 {
2042 MegasasState *s = opaque;
2043 PCIDevice *pci_dev = PCI_DEVICE(s);
2044 uint64_t frame_addr;
2045 uint32_t frame_count;
2046 int i;
2047
2048 switch (addr) {
2049 case MFI_IDB:
2050 trace_megasas_mmio_writel("MFI_IDB", val);
2051 if (val & MFI_FWINIT_ABORT) {
2052 /* Abort all pending cmds */
2053 for (i = 0; i < s->fw_cmds; i++) {
2054 megasas_abort_command(&s->frames[i]);
2055 }
2056 }
2057 if (val & MFI_FWINIT_READY) {
2058 /* move to FW READY */
2059 megasas_soft_reset(s);
2060 }
2061 if (val & MFI_FWINIT_MFIMODE) {
2062 /* discard MFIs */
2063 }
2064 if (val & MFI_FWINIT_STOP_ADP) {
2065 /* Terminal error, stop processing */
2066 s->fw_state = MFI_FWSTATE_FAULT;
2067 }
2068 break;
2069 case MFI_OMSK:
2070 trace_megasas_mmio_writel("MFI_OMSK", val);
2071 s->intr_mask = val;
2072 if (!megasas_intr_enabled(s) &&
2073 !msi_enabled(pci_dev) &&
2074 !msix_enabled(pci_dev)) {
2075 trace_megasas_irq_lower();
2076 pci_irq_deassert(pci_dev);
2077 }
2078 if (megasas_intr_enabled(s)) {
2079 if (msix_enabled(pci_dev)) {
2080 trace_megasas_msix_enabled(0);
2081 } else if (msi_enabled(pci_dev)) {
2082 trace_megasas_msi_enabled(0);
2083 } else {
2084 trace_megasas_intr_enabled();
2085 }
2086 } else {
2087 trace_megasas_intr_disabled();
2088 megasas_soft_reset(s);
2089 }
2090 break;
2091 case MFI_ODCR0:
2092 trace_megasas_mmio_writel("MFI_ODCR0", val);
2093 s->doorbell = 0;
2094 if (megasas_intr_enabled(s)) {
2095 if (!msix_enabled(pci_dev) && !msi_enabled(pci_dev)) {
2096 trace_megasas_irq_lower();
2097 pci_irq_deassert(pci_dev);
2098 }
2099 }
2100 break;
2101 case MFI_IQPH:
2102 trace_megasas_mmio_writel("MFI_IQPH", val);
2103 /* Received high 32 bits of a 64 bit MFI frame address */
2104 s->frame_hi = val;
2105 break;
2106 case MFI_IQPL:
2107 trace_megasas_mmio_writel("MFI_IQPL", val);
2108 /* Received low 32 bits of a 64 bit MFI frame address */
2109 /* Fallthrough */
2110 case MFI_IQP:
2111 if (addr == MFI_IQP) {
2112 trace_megasas_mmio_writel("MFI_IQP", val);
2113 /* Received 64 bit MFI frame address */
2114 s->frame_hi = 0;
2115 }
2116 frame_addr = (val & ~0x1F);
2117 /* Add possible 64 bit offset */
2118 frame_addr |= ((uint64_t)s->frame_hi << 32);
2119 s->frame_hi = 0;
2120 frame_count = (val >> 1) & 0xF;
2121 megasas_handle_frame(s, frame_addr, frame_count);
2122 break;
2123 case MFI_SEQ:
2124 trace_megasas_mmio_writel("MFI_SEQ", val);
2125 /* Magic sequence to start ADP reset */
2126 if (adp_reset_seq[s->adp_reset++] == val) {
2127 if (s->adp_reset == 6) {
2128 s->adp_reset = 0;
2129 s->diag = MFI_DIAG_WRITE_ENABLE;
2130 }
2131 } else {
2132 s->adp_reset = 0;
2133 s->diag = 0;
2134 }
2135 break;
2136 case MFI_DIAG:
2137 trace_megasas_mmio_writel("MFI_DIAG", val);
2138 /* ADP reset */
2139 if ((s->diag & MFI_DIAG_WRITE_ENABLE) &&
2140 (val & MFI_DIAG_RESET_ADP)) {
2141 s->diag |= MFI_DIAG_RESET_ADP;
2142 megasas_soft_reset(s);
2143 s->adp_reset = 0;
2144 s->diag = 0;
2145 }
2146 break;
2147 default:
2148 trace_megasas_mmio_invalid_writel(addr, val);
2149 break;
2150 }
2151 }
2152
2153 static const MemoryRegionOps megasas_mmio_ops = {
2154 .read = megasas_mmio_read,
2155 .write = megasas_mmio_write,
2156 .endianness = DEVICE_LITTLE_ENDIAN,
2157 .impl = {
2158 .min_access_size = 8,
2159 .max_access_size = 8,
2160 }
2161 };
2162
2163 static uint64_t megasas_port_read(void *opaque, hwaddr addr,
2164 unsigned size)
2165 {
2166 return megasas_mmio_read(opaque, addr & 0xff, size);
2167 }
2168
2169 static void megasas_port_write(void *opaque, hwaddr addr,
2170 uint64_t val, unsigned size)
2171 {
2172 megasas_mmio_write(opaque, addr & 0xff, val, size);
2173 }
2174
2175 static const MemoryRegionOps megasas_port_ops = {
2176 .read = megasas_port_read,
2177 .write = megasas_port_write,
2178 .endianness = DEVICE_LITTLE_ENDIAN,
2179 .impl = {
2180 .min_access_size = 4,
2181 .max_access_size = 4,
2182 }
2183 };
2184
2185 static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
2186 unsigned size)
2187 {
2188 return 0;
2189 }
2190
2191 static void megasas_queue_write(void *opaque, hwaddr addr,
2192 uint64_t val, unsigned size)
2193 {
2194 return;
2195 }
2196
2197 static const MemoryRegionOps megasas_queue_ops = {
2198 .read = megasas_queue_read,
2199 .write = megasas_queue_write,
2200 .endianness = DEVICE_LITTLE_ENDIAN,
2201 .impl = {
2202 .min_access_size = 8,
2203 .max_access_size = 8,
2204 }
2205 };
2206
2207 static void megasas_soft_reset(MegasasState *s)
2208 {
2209 int i;
2210 MegasasCmd *cmd;
2211
2212 trace_megasas_reset(s->fw_state);
2213 for (i = 0; i < s->fw_cmds; i++) {
2214 cmd = &s->frames[i];
2215 megasas_abort_command(cmd);
2216 }
2217 if (s->fw_state == MFI_FWSTATE_READY) {
2218 BusChild *kid;
2219
2220 /*
2221 * The EFI firmware doesn't handle UA,
2222 * so we need to clear the Power On/Reset UA
2223 * after the initial reset.
2224 */
2225 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
2226 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
2227
2228 sdev->unit_attention = SENSE_CODE(NO_SENSE);
2229 scsi_device_unit_attention_reported(sdev);
2230 }
2231 }
2232 megasas_reset_frames(s);
2233 s->reply_queue_len = s->fw_cmds;
2234 s->reply_queue_pa = 0;
2235 s->consumer_pa = 0;
2236 s->producer_pa = 0;
2237 s->fw_state = MFI_FWSTATE_READY;
2238 s->doorbell = 0;
2239 s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2240 s->frame_hi = 0;
2241 s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2242 s->event_count++;
2243 s->boot_event = s->event_count;
2244 }
2245
2246 static void megasas_scsi_reset(DeviceState *dev)
2247 {
2248 MegasasState *s = MEGASAS(dev);
2249
2250 megasas_soft_reset(s);
2251 }
2252
2253 static const VMStateDescription vmstate_megasas_gen1 = {
2254 .name = "megasas",
2255 .version_id = 0,
2256 .minimum_version_id = 0,
2257 .fields = (VMStateField[]) {
2258 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
2259 VMSTATE_MSIX(parent_obj, MegasasState),
2260
2261 VMSTATE_INT32(fw_state, MegasasState),
2262 VMSTATE_INT32(intr_mask, MegasasState),
2263 VMSTATE_INT32(doorbell, MegasasState),
2264 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2265 VMSTATE_UINT64(consumer_pa, MegasasState),
2266 VMSTATE_UINT64(producer_pa, MegasasState),
2267 VMSTATE_END_OF_LIST()
2268 }
2269 };
2270
2271 static const VMStateDescription vmstate_megasas_gen2 = {
2272 .name = "megasas-gen2",
2273 .version_id = 0,
2274 .minimum_version_id = 0,
2275 .minimum_version_id_old = 0,
2276 .fields = (VMStateField[]) {
2277 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
2278 VMSTATE_MSIX(parent_obj, MegasasState),
2279
2280 VMSTATE_INT32(fw_state, MegasasState),
2281 VMSTATE_INT32(intr_mask, MegasasState),
2282 VMSTATE_INT32(doorbell, MegasasState),
2283 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2284 VMSTATE_UINT64(consumer_pa, MegasasState),
2285 VMSTATE_UINT64(producer_pa, MegasasState),
2286 VMSTATE_END_OF_LIST()
2287 }
2288 };
2289
2290 static void megasas_scsi_uninit(PCIDevice *d)
2291 {
2292 MegasasState *s = MEGASAS(d);
2293
2294 if (megasas_use_msix(s)) {
2295 msix_uninit(d, &s->mmio_io, &s->mmio_io);
2296 }
2297 msi_uninit(d);
2298 }
2299
2300 static const struct SCSIBusInfo megasas_scsi_info = {
2301 .tcq = true,
2302 .max_target = MFI_MAX_LD,
2303 .max_lun = 255,
2304
2305 .transfer_data = megasas_xfer_complete,
2306 .get_sg_list = megasas_get_sg_list,
2307 .complete = megasas_command_complete,
2308 .cancel = megasas_command_cancelled,
2309 };
2310
2311 static void megasas_scsi_realize(PCIDevice *dev, Error **errp)
2312 {
2313 MegasasState *s = MEGASAS(dev);
2314 MegasasBaseClass *b = MEGASAS_DEVICE_GET_CLASS(s);
2315 uint8_t *pci_conf;
2316 int i, bar_type;
2317 Error *err = NULL;
2318 int ret;
2319
2320 pci_conf = dev->config;
2321
2322 /* PCI latency timer = 0 */
2323 pci_conf[PCI_LATENCY_TIMER] = 0;
2324 /* Interrupt pin 1 */
2325 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2326
2327 if (s->msi != ON_OFF_AUTO_OFF) {
2328 ret = msi_init(dev, 0x50, 1, true, false, &err);
2329 /* Any error other than -ENOTSUP(board's MSI support is broken)
2330 * is a programming error */
2331 assert(!ret || ret == -ENOTSUP);
2332 if (ret && s->msi == ON_OFF_AUTO_ON) {
2333 /* Can't satisfy user's explicit msi=on request, fail */
2334 error_append_hint(&err, "You have to use msi=auto (default) or "
2335 "msi=off with this machine type.\n");
2336 error_propagate(errp, err);
2337 return;
2338 } else if (ret) {
2339 /* With msi=auto, we fall back to MSI off silently */
2340 s->msi = ON_OFF_AUTO_OFF;
2341 error_free(err);
2342 }
2343 }
2344
2345 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
2346 "megasas-mmio", 0x4000);
2347 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
2348 "megasas-io", 256);
2349 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
2350 "megasas-queue", 0x40000);
2351
2352 if (megasas_use_msix(s) &&
2353 msix_init(dev, 15, &s->mmio_io, b->mmio_bar, 0x2000,
2354 &s->mmio_io, b->mmio_bar, 0x3800, 0x68, NULL)) {
2355 /* TODO: check msix_init's error, and should fail on msix=on */
2356 s->msix = ON_OFF_AUTO_OFF;
2357 }
2358
2359 if (pci_is_express(dev)) {
2360 pcie_endpoint_cap_init(dev, 0xa0);
2361 }
2362
2363 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
2364 pci_register_bar(dev, b->ioport_bar,
2365 PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2366 pci_register_bar(dev, b->mmio_bar, bar_type, &s->mmio_io);
2367 pci_register_bar(dev, 3, bar_type, &s->queue_io);
2368
2369 if (megasas_use_msix(s)) {
2370 msix_vector_use(dev, 0);
2371 }
2372
2373 s->fw_state = MFI_FWSTATE_READY;
2374 if (!s->sas_addr) {
2375 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2376 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
2377 s->sas_addr |= (pci_dev_bus_num(dev) << 16);
2378 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
2379 s->sas_addr |= PCI_FUNC(dev->devfn);
2380 }
2381 if (!s->hba_serial) {
2382 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
2383 }
2384 if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
2385 s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE;
2386 } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
2387 s->fw_sge = 128 - MFI_PASS_FRAME_SIZE;
2388 } else {
2389 s->fw_sge = 64 - MFI_PASS_FRAME_SIZE;
2390 }
2391 if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2392 s->fw_cmds = MEGASAS_MAX_FRAMES;
2393 }
2394 trace_megasas_init(s->fw_sge, s->fw_cmds,
2395 megasas_is_jbod(s) ? "jbod" : "raid");
2396
2397 if (megasas_is_jbod(s)) {
2398 s->fw_luns = MFI_MAX_SYS_PDS;
2399 } else {
2400 s->fw_luns = MFI_MAX_LD;
2401 }
2402 s->producer_pa = 0;
2403 s->consumer_pa = 0;
2404 for (i = 0; i < s->fw_cmds; i++) {
2405 s->frames[i].index = i;
2406 s->frames[i].context = -1;
2407 s->frames[i].pa = 0;
2408 s->frames[i].state = s;
2409 }
2410
2411 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
2412 &megasas_scsi_info, NULL);
2413 }
2414
2415 static Property megasas_properties_gen1[] = {
2416 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2417 MEGASAS_DEFAULT_SGE),
2418 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2419 MEGASAS_DEFAULT_FRAMES),
2420 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2421 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2422 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2423 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
2424 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2425 MEGASAS_FLAG_USE_JBOD, false),
2426 DEFINE_PROP_END_OF_LIST(),
2427 };
2428
2429 static Property megasas_properties_gen2[] = {
2430 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2431 MEGASAS_DEFAULT_SGE),
2432 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2433 MEGASAS_GEN2_DEFAULT_FRAMES),
2434 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2435 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2436 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2437 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
2438 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2439 MEGASAS_FLAG_USE_JBOD, false),
2440 DEFINE_PROP_END_OF_LIST(),
2441 };
2442
2443 typedef struct MegasasInfo {
2444 const char *name;
2445 const char *desc;
2446 const char *product_name;
2447 const char *product_version;
2448 uint16_t device_id;
2449 uint16_t subsystem_id;
2450 int ioport_bar;
2451 int mmio_bar;
2452 int osts;
2453 const VMStateDescription *vmsd;
2454 Property *props;
2455 InterfaceInfo *interfaces;
2456 } MegasasInfo;
2457
2458 static struct MegasasInfo megasas_devices[] = {
2459 {
2460 .name = TYPE_MEGASAS_GEN1,
2461 .desc = "LSI MegaRAID SAS 1078",
2462 .product_name = "LSI MegaRAID SAS 8708EM2",
2463 .product_version = MEGASAS_VERSION_GEN1,
2464 .device_id = PCI_DEVICE_ID_LSI_SAS1078,
2465 .subsystem_id = 0x1013,
2466 .ioport_bar = 2,
2467 .mmio_bar = 0,
2468 .osts = MFI_1078_RM | 1,
2469 .vmsd = &vmstate_megasas_gen1,
2470 .props = megasas_properties_gen1,
2471 .interfaces = (InterfaceInfo[]) {
2472 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2473 { },
2474 },
2475 },{
2476 .name = TYPE_MEGASAS_GEN2,
2477 .desc = "LSI MegaRAID SAS 2108",
2478 .product_name = "LSI MegaRAID SAS 9260-8i",
2479 .product_version = MEGASAS_VERSION_GEN2,
2480 .device_id = PCI_DEVICE_ID_LSI_SAS0079,
2481 .subsystem_id = 0x9261,
2482 .ioport_bar = 0,
2483 .mmio_bar = 1,
2484 .osts = MFI_GEN2_RM,
2485 .vmsd = &vmstate_megasas_gen2,
2486 .props = megasas_properties_gen2,
2487 .interfaces = (InterfaceInfo[]) {
2488 { INTERFACE_PCIE_DEVICE },
2489 { }
2490 },
2491 }
2492 };
2493
2494 static void megasas_class_init(ObjectClass *oc, void *data)
2495 {
2496 DeviceClass *dc = DEVICE_CLASS(oc);
2497 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
2498 MegasasBaseClass *e = MEGASAS_DEVICE_CLASS(oc);
2499 const MegasasInfo *info = data;
2500
2501 pc->realize = megasas_scsi_realize;
2502 pc->exit = megasas_scsi_uninit;
2503 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2504 pc->device_id = info->device_id;
2505 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2506 pc->subsystem_id = info->subsystem_id;
2507 pc->class_id = PCI_CLASS_STORAGE_RAID;
2508 e->mmio_bar = info->mmio_bar;
2509 e->ioport_bar = info->ioport_bar;
2510 e->osts = info->osts;
2511 e->product_name = info->product_name;
2512 e->product_version = info->product_version;
2513 dc->props = info->props;
2514 dc->reset = megasas_scsi_reset;
2515 dc->vmsd = info->vmsd;
2516 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2517 dc->desc = info->desc;
2518 }
2519
2520 static const TypeInfo megasas_info = {
2521 .name = TYPE_MEGASAS_BASE,
2522 .parent = TYPE_PCI_DEVICE,
2523 .instance_size = sizeof(MegasasState),
2524 .class_size = sizeof(MegasasBaseClass),
2525 .abstract = true,
2526 };
2527
2528 static void megasas_register_types(void)
2529 {
2530 int i;
2531
2532 type_register_static(&megasas_info);
2533 for (i = 0; i < ARRAY_SIZE(megasas_devices); i++) {
2534 const MegasasInfo *info = &megasas_devices[i];
2535 TypeInfo type_info = {};
2536
2537 type_info.name = info->name;
2538 type_info.parent = TYPE_MEGASAS_BASE;
2539 type_info.class_data = (void *)info;
2540 type_info.class_init = megasas_class_init;
2541 type_info.interfaces = info->interfaces;
2542
2543 type_register(&type_info);
2544 }
2545 }
2546
2547 type_init(megasas_register_types)
AR7 emulation for QEMU