hw/scsi/esp.c

   1 /*
   2  * QEMU ESP/NCR53C9x emulation
   3  *
   4  * Copyright (c) 2005-2006 Fabrice Bellard
   5  * Copyright (c) 2012 Herve Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/sysbus.h"
  28 #include "hw/scsi/esp.h"
  29 #include "trace.h"
  30 #include "qemu/log.h"
  31 #include "qemu/module.h"
  32
  33 /*
  34  * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
  35  * also produced as NCR89C100. See
  36  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  37  * and
  38  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
  39  */
  40
  41 static void esp_raise_irq(ESPState *s)
  42 {
  43     if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
  44         s->rregs[ESP_RSTAT] |= STAT_INT;
  45         qemu_irq_raise(s->irq);
  46         trace_esp_raise_irq();
  47     }
  48 }
  49
  50 static void esp_lower_irq(ESPState *s)
  51 {
  52     if (s->rregs[ESP_RSTAT] & STAT_INT) {
  53         s->rregs[ESP_RSTAT] &= ~STAT_INT;
  54         qemu_irq_lower(s->irq);
  55         trace_esp_lower_irq();
  56     }
  57 }
  58
  59 void esp_dma_enable(ESPState *s, int irq, int level)
  60 {
  61     if (level) {
  62         s->dma_enabled = 1;
  63         trace_esp_dma_enable();
  64         if (s->dma_cb) {
  65             s->dma_cb(s);
  66             s->dma_cb = NULL;
  67         }
  68     } else {
  69         trace_esp_dma_disable();
  70         s->dma_enabled = 0;
  71     }
  72 }
  73
  74 void esp_request_cancelled(SCSIRequest *req)
  75 {
  76     ESPState *s = req->hba_private;
  77
  78     if (req == s->current_req) {
  79         scsi_req_unref(s->current_req);
  80         s->current_req = NULL;
  81         s->current_dev = NULL;
  82     }
  83 }
  84
  85 static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen)
  86 {
  87     uint32_t dmalen;
  88     int target;
  89
  90     target = s->wregs[ESP_WBUSID] & BUSID_DID;
  91     if (s->dma) {
  92         dmalen = s->rregs[ESP_TCLO];
  93         dmalen |= s->rregs[ESP_TCMID] << 8;
  94         dmalen |= s->rregs[ESP_TCHI] << 16;
  95         if (dmalen > buflen) {
  96             return 0;
  97         }
  98         s->dma_memory_read(s->dma_opaque, buf, dmalen);
  99     } else {
 100         dmalen = s->ti_size;
 101         if (dmalen > TI_BUFSZ) {
 102             return 0;
 103         }
 104         memcpy(buf, s->ti_buf, dmalen);
 105         buf[0] = buf[2] >> 5;
 106     }
 107     trace_esp_get_cmd(dmalen, target);
 108
 109     s->ti_size = 0;
 110     s->ti_rptr = 0;
 111     s->ti_wptr = 0;
 112
 113     if (s->current_req) {
 114         /* Started a new command before the old one finished.  Cancel it.  */
 115         scsi_req_cancel(s->current_req);
 116         s->async_len = 0;
 117     }
 118
 119     s->current_dev = scsi_device_find(&s->bus, 0, target, 0);
 120     if (!s->current_dev) {
 121         // No such drive
 122         s->rregs[ESP_RSTAT] = 0;
 123         s->rregs[ESP_RINTR] = INTR_DC;
 124         s->rregs[ESP_RSEQ] = SEQ_0;
 125         esp_raise_irq(s);
 126         return 0;
 127     }
 128     return dmalen;
 129 }
 130
 131 static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid)
 132 {
 133     int32_t datalen;
 134     int lun;
 135     SCSIDevice *current_lun;
 136
 137     trace_esp_do_busid_cmd(busid);
 138     lun = busid & 7;
 139     current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun);
 140     s->current_req = scsi_req_new(current_lun, 0, lun, buf, s);
 141     datalen = scsi_req_enqueue(s->current_req);
 142     s->ti_size = datalen;
 143     if (datalen != 0) {
 144         s->rregs[ESP_RSTAT] = STAT_TC;
 145         s->dma_left = 0;
 146         s->dma_counter = 0;
 147         if (datalen > 0) {
 148             s->rregs[ESP_RSTAT] |= STAT_DI;
 149         } else {
 150             s->rregs[ESP_RSTAT] |= STAT_DO;
 151         }
 152         scsi_req_continue(s->current_req);
 153     }
 154     s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 155     s->rregs[ESP_RSEQ] = SEQ_CD;
 156     esp_raise_irq(s);
 157 }
 158
 159 static void do_cmd(ESPState *s, uint8_t *buf)
 160 {
 161     uint8_t busid = buf[0];
 162
 163     do_busid_cmd(s, &buf[1], busid);
 164 }
 165
 166 static void handle_satn(ESPState *s)
 167 {
 168     uint8_t buf[32];
 169     int len;
 170
 171     if (s->dma && !s->dma_enabled) {
 172         s->dma_cb = handle_satn;
 173         return;
 174     }
 175     len = get_cmd(s, buf, sizeof(buf));
 176     if (len)
 177         do_cmd(s, buf);
 178 }
 179
 180 static void handle_s_without_atn(ESPState *s)
 181 {
 182     uint8_t buf[32];
 183     int len;
 184
 185     if (s->dma && !s->dma_enabled) {
 186         s->dma_cb = handle_s_without_atn;
 187         return;
 188     }
 189     len = get_cmd(s, buf, sizeof(buf));
 190     if (len) {
 191         do_busid_cmd(s, buf, 0);
 192     }
 193 }
 194
 195 static void handle_satn_stop(ESPState *s)
 196 {
 197     if (s->dma && !s->dma_enabled) {
 198         s->dma_cb = handle_satn_stop;
 199         return;
 200     }
 201     s->cmdlen = get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf));
 202     if (s->cmdlen) {
 203         trace_esp_handle_satn_stop(s->cmdlen);
 204         s->do_cmd = 1;
 205         s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
 206         s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 207         s->rregs[ESP_RSEQ] = SEQ_CD;
 208         esp_raise_irq(s);
 209     }
 210 }
 211
 212 static void write_response(ESPState *s)
 213 {
 214     trace_esp_write_response(s->status);
 215     s->ti_buf[0] = s->status;
 216     s->ti_buf[1] = 0;
 217     if (s->dma) {
 218         s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
 219         s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
 220         s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 221         s->rregs[ESP_RSEQ] = SEQ_CD;
 222     } else {
 223         s->ti_size = 2;
 224         s->ti_rptr = 0;
 225         s->ti_wptr = 2;
 226         s->rregs[ESP_RFLAGS] = 2;
 227     }
 228     esp_raise_irq(s);
 229 }
 230
 231 static void esp_dma_done(ESPState *s)
 232 {
 233     s->rregs[ESP_RSTAT] |= STAT_TC;
 234     s->rregs[ESP_RINTR] = INTR_BS;
 235     s->rregs[ESP_RSEQ] = 0;
 236     s->rregs[ESP_RFLAGS] = 0;
 237     s->rregs[ESP_TCLO] = 0;
 238     s->rregs[ESP_TCMID] = 0;
 239     s->rregs[ESP_TCHI] = 0;
 240     esp_raise_irq(s);
 241 }
 242
 243 static void esp_do_dma(ESPState *s)
 244 {
 245     uint32_t len;
 246     int to_device;
 247
 248     len = s->dma_left;
 249     if (s->do_cmd) {
 250         trace_esp_do_dma(s->cmdlen, len);
 251         assert (s->cmdlen <= sizeof(s->cmdbuf) &&
 252                 len <= sizeof(s->cmdbuf) - s->cmdlen);
 253         s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
 254         return;
 255     }
 256     if (s->async_len == 0) {
 257         /* Defer until data is available.  */
 258         return;
 259     }
 260     if (len > s->async_len) {
 261         len = s->async_len;
 262     }
 263     to_device = (s->ti_size < 0);
 264     if (to_device) {
 265         s->dma_memory_read(s->dma_opaque, s->async_buf, len);
 266     } else {
 267         s->dma_memory_write(s->dma_opaque, s->async_buf, len);
 268     }
 269     s->dma_left -= len;
 270     s->async_buf += len;
 271     s->async_len -= len;
 272     if (to_device)
 273         s->ti_size += len;
 274     else
 275         s->ti_size -= len;
 276     if (s->async_len == 0) {
 277         scsi_req_continue(s->current_req);
 278         /* If there is still data to be read from the device then
 279            complete the DMA operation immediately.  Otherwise defer
 280            until the scsi layer has completed.  */
 281         if (to_device || s->dma_left != 0 || s->ti_size == 0) {
 282             return;
 283         }
 284     }
 285
 286     /* Partially filled a scsi buffer. Complete immediately.  */
 287     esp_dma_done(s);
 288 }
 289
 290 static void esp_report_command_complete(ESPState *s, uint32_t status)
 291 {
 292     trace_esp_command_complete();
 293     if (s->ti_size != 0) {
 294         trace_esp_command_complete_unexpected();
 295     }
 296     s->ti_size = 0;
 297     s->dma_left = 0;
 298     s->async_len = 0;
 299     if (status) {
 300         trace_esp_command_complete_fail();
 301     }
 302     s->status = status;
 303     s->rregs[ESP_RSTAT] = STAT_ST;
 304     esp_dma_done(s);
 305     if (s->current_req) {
 306         scsi_req_unref(s->current_req);
 307         s->current_req = NULL;
 308         s->current_dev = NULL;
 309     }
 310 }
 311
 312 void esp_command_complete(SCSIRequest *req, uint32_t status,
 313                           size_t resid)
 314 {
 315     ESPState *s = req->hba_private;
 316
 317     if (s->rregs[ESP_RSTAT] & STAT_INT) {
 318         /* Defer handling command complete until the previous
 319          * interrupt has been handled.
 320          */
 321         trace_esp_command_complete_deferred();
 322         s->deferred_status = status;
 323         s->deferred_complete = true;
 324         return;
 325     }
 326     esp_report_command_complete(s, status);
 327 }
 328
 329 void esp_transfer_data(SCSIRequest *req, uint32_t len)
 330 {
 331     ESPState *s = req->hba_private;
 332
 333     assert(!s->do_cmd);
 334     trace_esp_transfer_data(s->dma_left, s->ti_size);
 335     s->async_len = len;
 336     s->async_buf = scsi_req_get_buf(req);
 337     if (s->dma_left) {
 338         esp_do_dma(s);
 339     } else if (s->dma_counter != 0 && s->ti_size <= 0) {
 340         /* If this was the last part of a DMA transfer then the
 341            completion interrupt is deferred to here.  */
 342         esp_dma_done(s);
 343     }
 344 }
 345
 346 static void handle_ti(ESPState *s)
 347 {
 348     uint32_t dmalen, minlen;
 349
 350     if (s->dma && !s->dma_enabled) {
 351         s->dma_cb = handle_ti;
 352         return;
 353     }
 354
 355     dmalen = s->rregs[ESP_TCLO];
 356     dmalen |= s->rregs[ESP_TCMID] << 8;
 357     dmalen |= s->rregs[ESP_TCHI] << 16;
 358     if (dmalen==0) {
 359       dmalen=0x10000;
 360     }
 361     s->dma_counter = dmalen;
 362
 363     if (s->do_cmd)
 364         minlen = (dmalen < ESP_CMDBUF_SZ) ? dmalen : ESP_CMDBUF_SZ;
 365     else if (s->ti_size < 0)
 366         minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
 367     else
 368         minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
 369     trace_esp_handle_ti(minlen);
 370     if (s->dma) {
 371         s->dma_left = minlen;
 372         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 373         esp_do_dma(s);
 374     }
 375     if (s->do_cmd) {
 376         trace_esp_handle_ti_cmd(s->cmdlen);
 377         s->ti_size = 0;
 378         s->cmdlen = 0;
 379         s->do_cmd = 0;
 380         do_cmd(s, s->cmdbuf);
 381     }
 382 }
 383
 384 void esp_hard_reset(ESPState *s)
 385 {
 386     memset(s->rregs, 0, ESP_REGS);
 387     memset(s->wregs, 0, ESP_REGS);
 388     s->tchi_written = 0;
 389     s->ti_size = 0;
 390     s->ti_rptr = 0;
 391     s->ti_wptr = 0;
 392     s->dma = 0;
 393     s->do_cmd = 0;
 394     s->dma_cb = NULL;
 395
 396     s->rregs[ESP_CFG1] = 7;
 397 }
 398
 399 static void esp_soft_reset(ESPState *s)
 400 {
 401     qemu_irq_lower(s->irq);
 402     esp_hard_reset(s);
 403 }
 404
 405 static void parent_esp_reset(ESPState *s, int irq, int level)
 406 {
 407     if (level) {
 408         esp_soft_reset(s);
 409     }
 410 }
 411
 412 uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
 413 {
 414     uint32_t old_val;
 415
 416     trace_esp_mem_readb(saddr, s->rregs[saddr]);
 417     switch (saddr) {
 418     case ESP_FIFO:
 419         if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
 420             /* Data out.  */
 421             qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n");
 422             s->rregs[ESP_FIFO] = 0;
 423         } else if (s->ti_rptr < s->ti_wptr) {
 424             s->ti_size--;
 425             s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
 426         }
 427         if (s->ti_rptr == s->ti_wptr) {
 428             s->ti_rptr = 0;
 429             s->ti_wptr = 0;
 430         }
 431         break;
 432     case ESP_RINTR:
 433         /* Clear sequence step, interrupt register and all status bits
 434            except TC */
 435         old_val = s->rregs[ESP_RINTR];
 436         s->rregs[ESP_RINTR] = 0;
 437         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 438         s->rregs[ESP_RSEQ] = SEQ_CD;
 439         esp_lower_irq(s);
 440         if (s->deferred_complete) {
 441             esp_report_command_complete(s, s->deferred_status);
 442             s->deferred_complete = false;
 443         }
 444         return old_val;
 445     case ESP_TCHI:
 446         /* Return the unique id if the value has never been written */
 447         if (!s->tchi_written) {
 448             return s->chip_id;
 449         }
 450     default:
 451         break;
 452     }
 453     return s->rregs[saddr];
 454 }
 455
 456 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
 457 {
 458     trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
 459     switch (saddr) {
 460     case ESP_TCHI:
 461         s->tchi_written = true;
 462         /* fall through */
 463     case ESP_TCLO:
 464     case ESP_TCMID:
 465         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 466         break;
 467     case ESP_FIFO:
 468         if (s->do_cmd) {
 469             if (s->cmdlen < ESP_CMDBUF_SZ) {
 470                 s->cmdbuf[s->cmdlen++] = val & 0xff;
 471             } else {
 472                 trace_esp_error_fifo_overrun();
 473             }
 474         } else if (s->ti_wptr == TI_BUFSZ - 1) {
 475             trace_esp_error_fifo_overrun();
 476         } else {
 477             s->ti_size++;
 478             s->ti_buf[s->ti_wptr++] = val & 0xff;
 479         }
 480         break;
 481     case ESP_CMD:
 482         s->rregs[saddr] = val;
 483         if (val & CMD_DMA) {
 484             s->dma = 1;
 485             /* Reload DMA counter.  */
 486             s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
 487             s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
 488             s->rregs[ESP_TCHI] = s->wregs[ESP_TCHI];
 489         } else {
 490             s->dma = 0;
 491         }
 492         switch(val & CMD_CMD) {
 493         case CMD_NOP:
 494             trace_esp_mem_writeb_cmd_nop(val);
 495             break;
 496         case CMD_FLUSH:
 497             trace_esp_mem_writeb_cmd_flush(val);
 498             //s->ti_size = 0;
 499             s->rregs[ESP_RINTR] = INTR_FC;
 500             s->rregs[ESP_RSEQ] = 0;
 501             s->rregs[ESP_RFLAGS] = 0;
 502             break;
 503         case CMD_RESET:
 504             trace_esp_mem_writeb_cmd_reset(val);
 505             esp_soft_reset(s);
 506             break;
 507         case CMD_BUSRESET:
 508             trace_esp_mem_writeb_cmd_bus_reset(val);
 509             s->rregs[ESP_RINTR] = INTR_RST;
 510             if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
 511                 esp_raise_irq(s);
 512             }
 513             break;
 514         case CMD_TI:
 515             handle_ti(s);
 516             break;
 517         case CMD_ICCS:
 518             trace_esp_mem_writeb_cmd_iccs(val);
 519             write_response(s);
 520             s->rregs[ESP_RINTR] = INTR_FC;
 521             s->rregs[ESP_RSTAT] |= STAT_MI;
 522             break;
 523         case CMD_MSGACC:
 524             trace_esp_mem_writeb_cmd_msgacc(val);
 525             s->rregs[ESP_RINTR] = INTR_DC;
 526             s->rregs[ESP_RSEQ] = 0;
 527             s->rregs[ESP_RFLAGS] = 0;
 528             esp_raise_irq(s);
 529             break;
 530         case CMD_PAD:
 531             trace_esp_mem_writeb_cmd_pad(val);
 532             s->rregs[ESP_RSTAT] = STAT_TC;
 533             s->rregs[ESP_RINTR] = INTR_FC;
 534             s->rregs[ESP_RSEQ] = 0;
 535             break;
 536         case CMD_SATN:
 537             trace_esp_mem_writeb_cmd_satn(val);
 538             break;
 539         case CMD_RSTATN:
 540             trace_esp_mem_writeb_cmd_rstatn(val);
 541             break;
 542         case CMD_SEL:
 543             trace_esp_mem_writeb_cmd_sel(val);
 544             handle_s_without_atn(s);
 545             break;
 546         case CMD_SELATN:
 547             trace_esp_mem_writeb_cmd_selatn(val);
 548             handle_satn(s);
 549             break;
 550         case CMD_SELATNS:
 551             trace_esp_mem_writeb_cmd_selatns(val);
 552             handle_satn_stop(s);
 553             break;
 554         case CMD_ENSEL:
 555             trace_esp_mem_writeb_cmd_ensel(val);
 556             s->rregs[ESP_RINTR] = 0;
 557             break;
 558         case CMD_DISSEL:
 559             trace_esp_mem_writeb_cmd_dissel(val);
 560             s->rregs[ESP_RINTR] = 0;
 561             esp_raise_irq(s);
 562             break;
 563         default:
 564             trace_esp_error_unhandled_command(val);
 565             break;
 566         }
 567         break;
 568     case ESP_WBUSID ... ESP_WSYNO:
 569         break;
 570     case ESP_CFG1:
 571     case ESP_CFG2: case ESP_CFG3:
 572     case ESP_RES3: case ESP_RES4:
 573         s->rregs[saddr] = val;
 574         break;
 575     case ESP_WCCF ... ESP_WTEST:
 576         break;
 577     default:
 578         trace_esp_error_invalid_write(val, saddr);
 579         return;
 580     }
 581     s->wregs[saddr] = val;
 582 }
 583
 584 static bool esp_mem_accepts(void *opaque, hwaddr addr,
 585                             unsigned size, bool is_write,
 586                             MemTxAttrs attrs)
 587 {
 588     return (size == 1) || (is_write && size == 4);
 589 }
 590
 591 const VMStateDescription vmstate_esp = {
 592     .name ="esp",
 593     .version_id = 4,
 594     .minimum_version_id = 3,
 595     .fields = (VMStateField[]) {
 596         VMSTATE_BUFFER(rregs, ESPState),
 597         VMSTATE_BUFFER(wregs, ESPState),
 598         VMSTATE_INT32(ti_size, ESPState),
 599         VMSTATE_UINT32(ti_rptr, ESPState),
 600         VMSTATE_UINT32(ti_wptr, ESPState),
 601         VMSTATE_BUFFER(ti_buf, ESPState),
 602         VMSTATE_UINT32(status, ESPState),
 603         VMSTATE_UINT32(deferred_status, ESPState),
 604         VMSTATE_BOOL(deferred_complete, ESPState),
 605         VMSTATE_UINT32(dma, ESPState),
 606         VMSTATE_PARTIAL_BUFFER(cmdbuf, ESPState, 16),
 607         VMSTATE_BUFFER_START_MIDDLE_V(cmdbuf, ESPState, 16, 4),
 608         VMSTATE_UINT32(cmdlen, ESPState),
 609         VMSTATE_UINT32(do_cmd, ESPState),
 610         VMSTATE_UINT32(dma_left, ESPState),
 611         VMSTATE_END_OF_LIST()
 612     }
 613 };
 614
 615 static void sysbus_esp_mem_write(void *opaque, hwaddr addr,
 616                                  uint64_t val, unsigned int size)
 617 {
 618     SysBusESPState *sysbus = opaque;
 619     uint32_t saddr;
 620
 621     saddr = addr >> sysbus->it_shift;
 622     esp_reg_write(&sysbus->esp, saddr, val);
 623 }
 624
 625 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr,
 626                                     unsigned int size)
 627 {
 628     SysBusESPState *sysbus = opaque;
 629     uint32_t saddr;
 630
 631     saddr = addr >> sysbus->it_shift;
 632     return esp_reg_read(&sysbus->esp, saddr);
 633 }
 634
 635 static const MemoryRegionOps sysbus_esp_mem_ops = {
 636     .read = sysbus_esp_mem_read,
 637     .write = sysbus_esp_mem_write,
 638     .endianness = DEVICE_NATIVE_ENDIAN,
 639     .valid.accepts = esp_mem_accepts,
 640 };
 641
 642 static const struct SCSIBusInfo esp_scsi_info = {
 643     .tcq = false,
 644     .max_target = ESP_MAX_DEVS,
 645     .max_lun = 7,
 646
 647     .transfer_data = esp_transfer_data,
 648     .complete = esp_command_complete,
 649     .cancel = esp_request_cancelled
 650 };
 651
 652 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level)
 653 {
 654     SysBusESPState *sysbus = ESP_STATE(opaque);
 655     ESPState *s = &sysbus->esp;
 656
 657     switch (irq) {
 658     case 0:
 659         parent_esp_reset(s, irq, level);
 660         break;
 661     case 1:
 662         esp_dma_enable(opaque, irq, level);
 663         break;
 664     }
 665 }
 666
 667 static void sysbus_esp_realize(DeviceState *dev, Error **errp)
 668 {
 669     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 670     SysBusESPState *sysbus = ESP_STATE(dev);
 671     ESPState *s = &sysbus->esp;
 672
 673     sysbus_init_irq(sbd, &s->irq);
 674     assert(sysbus->it_shift != -1);
 675
 676     s->chip_id = TCHI_FAS100A;
 677     memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops,
 678                           sysbus, "esp", ESP_REGS << sysbus->it_shift);
 679     sysbus_init_mmio(sbd, &sysbus->iomem);
 680
 681     qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);
 682
 683     scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL);
 684 }
 685
 686 static void sysbus_esp_hard_reset(DeviceState *dev)
 687 {
 688     SysBusESPState *sysbus = ESP_STATE(dev);
 689     esp_hard_reset(&sysbus->esp);
 690 }
 691
 692 static const VMStateDescription vmstate_sysbus_esp_scsi = {
 693     .name = "sysbusespscsi",
 694     .version_id = 1,
 695     .minimum_version_id = 1,
 696     .fields = (VMStateField[]) {
 697         VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState),
 698         VMSTATE_END_OF_LIST()
 699     }
 700 };
 701
 702 static void sysbus_esp_class_init(ObjectClass *klass, void *data)
 703 {
 704     DeviceClass *dc = DEVICE_CLASS(klass);
 705
 706     dc->realize = sysbus_esp_realize;
 707     dc->reset = sysbus_esp_hard_reset;
 708     dc->vmsd = &vmstate_sysbus_esp_scsi;
 709     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 710 }
 711
 712 static const TypeInfo sysbus_esp_info = {
 713     .name          = TYPE_ESP,
 714     .parent        = TYPE_SYS_BUS_DEVICE,
 715     .instance_size = sizeof(SysBusESPState),
 716     .class_init    = sysbus_esp_class_init,
 717 };
 718
 719 static void esp_register_types(void)
 720 {
 721     type_register_static(&sysbus_esp_info);
 722 }
 723
 724 type_init(esp_register_types)