hw/pci-host/ppce500.c

   1 /*
   2  * QEMU PowerPC E500 embedded processors pci controller emulation
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author: Yu Liu,     <yu.liu@freescale.com>
   7  *
   8  * This file is derived from hw/ppc4xx_pci.c,
   9  * the copyright for that material belongs to the original owners.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of  the GNU General  Public License as published by
  13  * the Free Software Foundation;  either version 2 of the  License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include "qemu/osdep.h"
  18 #include "hw/hw.h"
  19 #include "hw/ppc/e500-ccsr.h"
  20 #include "hw/pci/pci.h"
  21 #include "hw/pci/pci_host.h"
  22 #include "qemu/bswap.h"
  23 #include "qemu/module.h"
  24 #include "hw/pci-host/ppce500.h"
  25
  26 #ifdef DEBUG_PCI
  27 #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
  28 #else
  29 #define pci_debug(fmt, ...)
  30 #endif
  31
  32 #define PCIE500_CFGADDR       0x0
  33 #define PCIE500_CFGDATA       0x4
  34 #define PCIE500_REG_BASE      0xC00
  35 #define PCIE500_ALL_SIZE      0x1000
  36 #define PCIE500_REG_SIZE      (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
  37
  38 #define PCIE500_PCI_IOLEN     0x10000ULL
  39
  40 #define PPCE500_PCI_CONFIG_ADDR         0x0
  41 #define PPCE500_PCI_CONFIG_DATA         0x4
  42 #define PPCE500_PCI_INTACK              0x8
  43
  44 #define PPCE500_PCI_OW1                 (0xC20 - PCIE500_REG_BASE)
  45 #define PPCE500_PCI_OW2                 (0xC40 - PCIE500_REG_BASE)
  46 #define PPCE500_PCI_OW3                 (0xC60 - PCIE500_REG_BASE)
  47 #define PPCE500_PCI_OW4                 (0xC80 - PCIE500_REG_BASE)
  48 #define PPCE500_PCI_IW3                 (0xDA0 - PCIE500_REG_BASE)
  49 #define PPCE500_PCI_IW2                 (0xDC0 - PCIE500_REG_BASE)
  50 #define PPCE500_PCI_IW1                 (0xDE0 - PCIE500_REG_BASE)
  51
  52 #define PPCE500_PCI_GASKET_TIMR         (0xE20 - PCIE500_REG_BASE)
  53
  54 #define PCI_POTAR               0x0
  55 #define PCI_POTEAR              0x4
  56 #define PCI_POWBAR              0x8
  57 #define PCI_POWAR               0x10
  58
  59 #define PCI_PITAR               0x0
  60 #define PCI_PIWBAR              0x8
  61 #define PCI_PIWBEAR             0xC
  62 #define PCI_PIWAR               0x10
  63
  64 #define PPCE500_PCI_NR_POBS     5
  65 #define PPCE500_PCI_NR_PIBS     3
  66
  67 #define PIWAR_EN                0x80000000      /* Enable */
  68 #define PIWAR_PF                0x20000000      /* prefetch */
  69 #define PIWAR_TGI_LOCAL         0x00f00000      /* target - local memory */
  70 #define PIWAR_READ_SNOOP        0x00050000
  71 #define PIWAR_WRITE_SNOOP       0x00005000
  72 #define PIWAR_SZ_MASK           0x0000003f
  73
  74 struct  pci_outbound {
  75     uint32_t potar;
  76     uint32_t potear;
  77     uint32_t powbar;
  78     uint32_t powar;
  79     MemoryRegion mem;
  80 };
  81
  82 struct pci_inbound {
  83     uint32_t pitar;
  84     uint32_t piwbar;
  85     uint32_t piwbear;
  86     uint32_t piwar;
  87     MemoryRegion mem;
  88 };
  89
  90 #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"
  91
  92 #define PPC_E500_PCI_HOST_BRIDGE(obj) \
  93     OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE)
  94
  95 struct PPCE500PCIState {
  96     PCIHostState parent_obj;
  97
  98     struct pci_outbound pob[PPCE500_PCI_NR_POBS];
  99     struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
 100     uint32_t gasket_time;
 101     qemu_irq irq[PCI_NUM_PINS];
 102     uint32_t irq_num[PCI_NUM_PINS];
 103     uint32_t first_slot;
 104     uint32_t first_pin_irq;
 105     AddressSpace bm_as;
 106     MemoryRegion bm;
 107     /* mmio maps */
 108     MemoryRegion container;
 109     MemoryRegion iomem;
 110     MemoryRegion pio;
 111     MemoryRegion busmem;
 112 };
 113
 114 #define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge"
 115 #define PPC_E500_PCI_BRIDGE(obj) \
 116     OBJECT_CHECK(PPCE500PCIBridgeState, (obj), TYPE_PPC_E500_PCI_BRIDGE)
 117
 118 struct PPCE500PCIBridgeState {
 119     /*< private >*/
 120     PCIDevice parent;
 121     /*< public >*/
 122
 123     MemoryRegion bar0;
 124 };
 125
 126 typedef struct PPCE500PCIBridgeState PPCE500PCIBridgeState;
 127 typedef struct PPCE500PCIState PPCE500PCIState;
 128
 129 static uint64_t pci_reg_read4(void *opaque, hwaddr addr,
 130                               unsigned size)
 131 {
 132     PPCE500PCIState *pci = opaque;
 133     unsigned long win;
 134     uint32_t value = 0;
 135     int idx;
 136
 137     win = addr & 0xfe0;
 138
 139     switch (win) {
 140     case PPCE500_PCI_OW1:
 141     case PPCE500_PCI_OW2:
 142     case PPCE500_PCI_OW3:
 143     case PPCE500_PCI_OW4:
 144         idx = (addr >> 5) & 0x7;
 145         switch (addr & 0x1F) {
 146         case PCI_POTAR:
 147             value = pci->pob[idx].potar;
 148             break;
 149         case PCI_POTEAR:
 150             value = pci->pob[idx].potear;
 151             break;
 152         case PCI_POWBAR:
 153             value = pci->pob[idx].powbar;
 154             break;
 155         case PCI_POWAR:
 156             value = pci->pob[idx].powar;
 157             break;
 158         default:
 159             break;
 160         }
 161         break;
 162
 163     case PPCE500_PCI_IW3:
 164     case PPCE500_PCI_IW2:
 165     case PPCE500_PCI_IW1:
 166         idx = ((addr >> 5) & 0x3) - 1;
 167         switch (addr & 0x1F) {
 168         case PCI_PITAR:
 169             value = pci->pib[idx].pitar;
 170             break;
 171         case PCI_PIWBAR:
 172             value = pci->pib[idx].piwbar;
 173             break;
 174         case PCI_PIWBEAR:
 175             value = pci->pib[idx].piwbear;
 176             break;
 177         case PCI_PIWAR:
 178             value = pci->pib[idx].piwar;
 179             break;
 180         default:
 181             break;
 182         };
 183         break;
 184
 185     case PPCE500_PCI_GASKET_TIMR:
 186         value = pci->gasket_time;
 187         break;
 188
 189     default:
 190         break;
 191     }
 192
 193     pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
 194               win, addr, value);
 195     return value;
 196 }
 197
 198 /* DMA mapping */
 199 static void e500_update_piw(PPCE500PCIState *pci, int idx)
 200 {
 201     uint64_t tar = ((uint64_t)pci->pib[idx].pitar) << 12;
 202     uint64_t wbar = ((uint64_t)pci->pib[idx].piwbar) << 12;
 203     uint64_t war = pci->pib[idx].piwar;
 204     uint64_t size = 2ULL << (war & PIWAR_SZ_MASK);
 205     MemoryRegion *address_space_mem = get_system_memory();
 206     MemoryRegion *mem = &pci->pib[idx].mem;
 207     MemoryRegion *bm = &pci->bm;
 208     char *name;
 209
 210     if (memory_region_is_mapped(mem)) {
 211         /* Before we modify anything, unmap and destroy the region */
 212         memory_region_del_subregion(bm, mem);
 213         object_unparent(OBJECT(mem));
 214     }
 215
 216     if (!(war & PIWAR_EN)) {
 217         /* Not enabled, nothing to do */
 218         return;
 219     }
 220
 221     name = g_strdup_printf("PCI Inbound Window %d", idx);
 222     memory_region_init_alias(mem, OBJECT(pci), name, address_space_mem, tar,
 223                              size);
 224     memory_region_add_subregion_overlap(bm, wbar, mem, -1);
 225     g_free(name);
 226
 227     pci_debug("%s: Added window of size=%#lx from PCI=%#lx to CPU=%#lx\n",
 228               __func__, size, wbar, tar);
 229 }
 230
 231 /* BAR mapping */
 232 static void e500_update_pow(PPCE500PCIState *pci, int idx)
 233 {
 234     uint64_t tar = ((uint64_t)pci->pob[idx].potar) << 12;
 235     uint64_t wbar = ((uint64_t)pci->pob[idx].powbar) << 12;
 236     uint64_t war = pci->pob[idx].powar;
 237     uint64_t size = 2ULL << (war & PIWAR_SZ_MASK);
 238     MemoryRegion *mem = &pci->pob[idx].mem;
 239     MemoryRegion *address_space_mem = get_system_memory();
 240     char *name;
 241
 242     if (memory_region_is_mapped(mem)) {
 243         /* Before we modify anything, unmap and destroy the region */
 244         memory_region_del_subregion(address_space_mem, mem);
 245         object_unparent(OBJECT(mem));
 246     }
 247
 248     if (!(war & PIWAR_EN)) {
 249         /* Not enabled, nothing to do */
 250         return;
 251     }
 252
 253     name = g_strdup_printf("PCI Outbound Window %d", idx);
 254     memory_region_init_alias(mem, OBJECT(pci), name, &pci->busmem, tar,
 255                              size);
 256     memory_region_add_subregion(address_space_mem, wbar, mem);
 257     g_free(name);
 258
 259     pci_debug("%s: Added window of size=%#lx from CPU=%#lx to PCI=%#lx\n",
 260               __func__, size, wbar, tar);
 261 }
 262
 263 static void pci_reg_write4(void *opaque, hwaddr addr,
 264                            uint64_t value, unsigned size)
 265 {
 266     PPCE500PCIState *pci = opaque;
 267     unsigned long win;
 268     int idx;
 269
 270     win = addr & 0xfe0;
 271
 272     pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
 273               __func__, (unsigned)value, win, addr);
 274
 275     switch (win) {
 276     case PPCE500_PCI_OW1:
 277     case PPCE500_PCI_OW2:
 278     case PPCE500_PCI_OW3:
 279     case PPCE500_PCI_OW4:
 280         idx = (addr >> 5) & 0x7;
 281         switch (addr & 0x1F) {
 282         case PCI_POTAR:
 283             pci->pob[idx].potar = value;
 284             e500_update_pow(pci, idx);
 285             break;
 286         case PCI_POTEAR:
 287             pci->pob[idx].potear = value;
 288             e500_update_pow(pci, idx);
 289             break;
 290         case PCI_POWBAR:
 291             pci->pob[idx].powbar = value;
 292             e500_update_pow(pci, idx);
 293             break;
 294         case PCI_POWAR:
 295             pci->pob[idx].powar = value;
 296             e500_update_pow(pci, idx);
 297             break;
 298         default:
 299             break;
 300         };
 301         break;
 302
 303     case PPCE500_PCI_IW3:
 304     case PPCE500_PCI_IW2:
 305     case PPCE500_PCI_IW1:
 306         idx = ((addr >> 5) & 0x3) - 1;
 307         switch (addr & 0x1F) {
 308         case PCI_PITAR:
 309             pci->pib[idx].pitar = value;
 310             e500_update_piw(pci, idx);
 311             break;
 312         case PCI_PIWBAR:
 313             pci->pib[idx].piwbar = value;
 314             e500_update_piw(pci, idx);
 315             break;
 316         case PCI_PIWBEAR:
 317             pci->pib[idx].piwbear = value;
 318             e500_update_piw(pci, idx);
 319             break;
 320         case PCI_PIWAR:
 321             pci->pib[idx].piwar = value;
 322             e500_update_piw(pci, idx);
 323             break;
 324         default:
 325             break;
 326         };
 327         break;
 328
 329     case PPCE500_PCI_GASKET_TIMR:
 330         pci->gasket_time = value;
 331         break;
 332
 333     default:
 334         break;
 335     };
 336 }
 337
 338 static const MemoryRegionOps e500_pci_reg_ops = {
 339     .read = pci_reg_read4,
 340     .write = pci_reg_write4,
 341     .endianness = DEVICE_BIG_ENDIAN,
 342 };
 343
 344 static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin)
 345 {
 346     int devno = pci_dev->devfn >> 3;
 347     int ret;
 348
 349     ret = ppce500_pci_map_irq_slot(devno, pin);
 350
 351     pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
 352            pci_dev->devfn, pin, ret, devno);
 353
 354     return ret;
 355 }
 356
 357 static void mpc85xx_pci_set_irq(void *opaque, int pin, int level)
 358 {
 359     PPCE500PCIState *s = opaque;
 360     qemu_irq *pic = s->irq;
 361
 362     pci_debug("%s: PCI irq %d, level:%d\n", __func__, pin , level);
 363
 364     qemu_set_irq(pic[pin], level);
 365 }
 366
 367 static PCIINTxRoute e500_route_intx_pin_to_irq(void *opaque, int pin)
 368 {
 369     PCIINTxRoute route;
 370     PPCE500PCIState *s = opaque;
 371
 372     route.mode = PCI_INTX_ENABLED;
 373     route.irq = s->irq_num[pin];
 374
 375     pci_debug("%s: PCI irq-pin = %d, irq_num= %d\n", __func__, pin, route.irq);
 376     return route;
 377 }
 378
 379 static const VMStateDescription vmstate_pci_outbound = {
 380     .name = "pci_outbound",
 381     .version_id = 0,
 382     .minimum_version_id = 0,
 383     .fields = (VMStateField[]) {
 384         VMSTATE_UINT32(potar, struct pci_outbound),
 385         VMSTATE_UINT32(potear, struct pci_outbound),
 386         VMSTATE_UINT32(powbar, struct pci_outbound),
 387         VMSTATE_UINT32(powar, struct pci_outbound),
 388         VMSTATE_END_OF_LIST()
 389     }
 390 };
 391
 392 static const VMStateDescription vmstate_pci_inbound = {
 393     .name = "pci_inbound",
 394     .version_id = 0,
 395     .minimum_version_id = 0,
 396     .fields = (VMStateField[]) {
 397         VMSTATE_UINT32(pitar, struct pci_inbound),
 398         VMSTATE_UINT32(piwbar, struct pci_inbound),
 399         VMSTATE_UINT32(piwbear, struct pci_inbound),
 400         VMSTATE_UINT32(piwar, struct pci_inbound),
 401         VMSTATE_END_OF_LIST()
 402     }
 403 };
 404
 405 static const VMStateDescription vmstate_ppce500_pci = {
 406     .name = "ppce500_pci",
 407     .version_id = 1,
 408     .minimum_version_id = 1,
 409     .fields = (VMStateField[]) {
 410         VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
 411                              vmstate_pci_outbound, struct pci_outbound),
 412         VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
 413                              vmstate_pci_inbound, struct pci_inbound),
 414         VMSTATE_UINT32(gasket_time, PPCE500PCIState),
 415         VMSTATE_END_OF_LIST()
 416     }
 417 };
 418
 419 #include "exec/address-spaces.h"
 420
 421 static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp)
 422 {
 423     PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d);
 424     PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(),
 425                                   "/e500-ccsr"));
 426
 427     memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space,
 428                              0, int128_get64(ccsr->ccsr_space.size));
 429     pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
 430 }
 431
 432 static AddressSpace *e500_pcihost_set_iommu(PCIBus *bus, void *opaque,
 433                                             int devfn)
 434 {
 435     PPCE500PCIState *s = opaque;
 436
 437     return &s->bm_as;
 438 }
 439
 440 static void e500_pcihost_realize(DeviceState *dev, Error **errp)
 441 {
 442     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 443     PCIHostState *h;
 444     PPCE500PCIState *s;
 445     PCIBus *b;
 446     int i;
 447
 448     h = PCI_HOST_BRIDGE(dev);
 449     s = PPC_E500_PCI_HOST_BRIDGE(dev);
 450
 451     for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
 452         sysbus_init_irq(sbd, &s->irq[i]);
 453     }
 454
 455     for (i = 0; i < PCI_NUM_PINS; i++) {
 456         s->irq_num[i] = s->first_pin_irq + i;
 457     }
 458
 459     memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN);
 460     memory_region_init(&s->busmem, OBJECT(s), "pci bus memory", UINT64_MAX);
 461
 462     /* PIO lives at the bottom of our bus space */
 463     memory_region_add_subregion_overlap(&s->busmem, 0, &s->pio, -2);
 464
 465     b = pci_register_root_bus(dev, NULL, mpc85xx_pci_set_irq,
 466                               mpc85xx_pci_map_irq, s, &s->busmem, &s->pio,
 467                               PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS);
 468     h->bus = b;
 469
 470     /* Set up PCI view of memory */
 471     memory_region_init(&s->bm, OBJECT(s), "bm-e500", UINT64_MAX);
 472     memory_region_add_subregion(&s->bm, 0x0, &s->busmem);
 473     address_space_init(&s->bm_as, &s->bm, "pci-bm");
 474     pci_setup_iommu(b, e500_pcihost_set_iommu, s);
 475
 476     pci_create_simple(b, 0, "e500-host-bridge");
 477
 478     memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE);
 479     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, h,
 480                           "pci-conf-idx", 4);
 481     memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, h,
 482                           "pci-conf-data", 4);
 483     memory_region_init_io(&s->iomem, OBJECT(s), &e500_pci_reg_ops, s,
 484                           "pci.reg", PCIE500_REG_SIZE);
 485     memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
 486     memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
 487     memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
 488     sysbus_init_mmio(sbd, &s->container);
 489     pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq);
 490 }
 491
 492 static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
 493 {
 494     DeviceClass *dc = DEVICE_CLASS(klass);
 495     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 496
 497     k->realize = e500_pcihost_bridge_realize;
 498     k->vendor_id = PCI_VENDOR_ID_FREESCALE;
 499     k->device_id = PCI_DEVICE_ID_MPC8533E;
 500     k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
 501     dc->desc = "Host bridge";
 502     /*
 503      * PCI-facing part of the host bridge, not usable without the
 504      * host-facing part, which can't be device_add'ed, yet.
 505      */
 506     dc->user_creatable = false;
 507 }
 508
 509 static const TypeInfo e500_host_bridge_info = {
 510     .name          = "e500-host-bridge",
 511     .parent        = TYPE_PCI_DEVICE,
 512     .instance_size = sizeof(PPCE500PCIBridgeState),
 513     .class_init    = e500_host_bridge_class_init,
 514     .interfaces = (InterfaceInfo[]) {
 515         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 516         { },
 517     },
 518 };
 519
 520 static Property pcihost_properties[] = {
 521     DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11),
 522     DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1),
 523     DEFINE_PROP_END_OF_LIST(),
 524 };
 525
 526 static void e500_pcihost_class_init(ObjectClass *klass, void *data)
 527 {
 528     DeviceClass *dc = DEVICE_CLASS(klass);
 529
 530     dc->realize = e500_pcihost_realize;
 531     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 532     dc->props = pcihost_properties;
 533     dc->vmsd = &vmstate_ppce500_pci;
 534 }
 535
 536 static const TypeInfo e500_pcihost_info = {
 537     .name          = TYPE_PPC_E500_PCI_HOST_BRIDGE,
 538     .parent        = TYPE_PCI_HOST_BRIDGE,
 539     .instance_size = sizeof(PPCE500PCIState),
 540     .class_init    = e500_pcihost_class_init,
 541 };
 542
 543 static void e500_pci_register_types(void)
 544 {
 545     type_register_static(&e500_pcihost_info);
 546     type_register_static(&e500_host_bridge_info);
 547 }
 548
 549 type_init(e500_pci_register_types)