hw/ide/sii3112.c

   1 /*
   2  * QEMU SiI3112A PCI to Serial ATA Controller Emulation
   3  *
   4  * Copyright (C) 2017 BALATON Zoltan <balaton@eik.bme.hu>
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  *
   9  */
  10
  11 /* For documentation on this and similar cards see:
  12  * http://wiki.osdev.org/User:Quok/Silicon_Image_Datasheets
  13  */
  14
  15 #include "qemu/osdep.h"
  16 #include "hw/ide/pci.h"
  17 #include "qemu/module.h"
  18 #include "trace.h"
  19
  20 #define TYPE_SII3112_PCI "sii3112"
  21 #define SII3112_PCI(obj) OBJECT_CHECK(SiI3112PCIState, (obj), \
  22                          TYPE_SII3112_PCI)
  23
  24 typedef struct SiI3112Regs {
  25     uint32_t confstat;
  26     uint32_t scontrol;
  27     uint16_t sien;
  28     uint8_t swdata;
  29 } SiI3112Regs;
  30
  31 typedef struct SiI3112PCIState {
  32     PCIIDEState i;
  33     MemoryRegion mmio;
  34     SiI3112Regs regs[2];
  35 } SiI3112PCIState;
  36
  37 /* The sii3112_reg_read and sii3112_reg_write functions implement the
  38  * Internal Register Space - BAR5 (section 6.7 of the data sheet).
  39  */
  40
  41 static uint64_t sii3112_reg_read(void *opaque, hwaddr addr,
  42                                 unsigned int size)
  43 {
  44     SiI3112PCIState *d = opaque;
  45     uint64_t val = 0;
  46
  47     switch (addr) {
  48     case 0x00:
  49         val = d->i.bmdma[0].cmd;
  50         break;
  51     case 0x01:
  52         val = d->regs[0].swdata;
  53         break;
  54     case 0x02:
  55         val = d->i.bmdma[0].status;
  56         break;
  57     case 0x03:
  58         val = 0;
  59         break;
  60     case 0x04 ... 0x07:
  61         val = bmdma_addr_ioport_ops.read(&d->i.bmdma[0], addr - 4, size);
  62         break;
  63     case 0x08:
  64         val = d->i.bmdma[1].cmd;
  65         break;
  66     case 0x09:
  67         val = d->regs[1].swdata;
  68         break;
  69     case 0x0a:
  70         val = d->i.bmdma[1].status;
  71         break;
  72     case 0x0b:
  73         val = 0;
  74         break;
  75     case 0x0c ... 0x0f:
  76         val = bmdma_addr_ioport_ops.read(&d->i.bmdma[1], addr - 12, size);
  77         break;
  78     case 0x10:
  79         val = d->i.bmdma[0].cmd;
  80         val |= (d->regs[0].confstat & (1UL << 11) ? (1 << 4) : 0); /*SATAINT0*/
  81         val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 6) : 0); /*SATAINT1*/
  82         val |= (d->i.bmdma[1].status & BM_STATUS_INT ? (1 << 14) : 0);
  83         val |= (uint32_t)d->i.bmdma[0].status << 16;
  84         val |= (uint32_t)d->i.bmdma[1].status << 24;
  85         break;
  86     case 0x18:
  87         val = d->i.bmdma[1].cmd;
  88         val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 4) : 0);
  89         val |= (uint32_t)d->i.bmdma[1].status << 16;
  90         break;
  91     case 0x80 ... 0x87:
  92         val = pci_ide_data_le_ops.read(&d->i.bus[0], addr - 0x80, size);
  93         break;
  94     case 0x8a:
  95         val = pci_ide_cmd_le_ops.read(&d->i.bus[0], 2, size);
  96         break;
  97     case 0xa0:
  98         val = d->regs[0].confstat;
  99         break;
 100     case 0xc0 ... 0xc7:
 101         val = pci_ide_data_le_ops.read(&d->i.bus[1], addr - 0xc0, size);
 102         break;
 103     case 0xca:
 104         val = pci_ide_cmd_le_ops.read(&d->i.bus[1], 2, size);
 105         break;
 106     case 0xe0:
 107         val = d->regs[1].confstat;
 108         break;
 109     case 0x100:
 110         val = d->regs[0].scontrol;
 111         break;
 112     case 0x104:
 113         val = (d->i.bus[0].ifs[0].blk) ? 0x113 : 0;
 114         break;
 115     case 0x148:
 116         val = (uint32_t)d->regs[0].sien << 16;
 117         break;
 118     case 0x180:
 119         val = d->regs[1].scontrol;
 120         break;
 121     case 0x184:
 122         val = (d->i.bus[1].ifs[0].blk) ? 0x113 : 0;
 123         break;
 124     case 0x1c8:
 125         val = (uint32_t)d->regs[1].sien << 16;
 126         break;
 127     default:
 128         val = 0;
 129     }
 130     trace_sii3112_read(size, addr, val);
 131     return val;
 132 }
 133
 134 static void sii3112_reg_write(void *opaque, hwaddr addr,
 135                               uint64_t val, unsigned int size)
 136 {
 137     SiI3112PCIState *d = opaque;
 138
 139     trace_sii3112_write(size, addr, val);
 140     switch (addr) {
 141     case 0x00:
 142     case 0x10:
 143         bmdma_cmd_writeb(&d->i.bmdma[0], val);
 144         break;
 145     case 0x01:
 146     case 0x11:
 147         d->regs[0].swdata = val & 0x3f;
 148         break;
 149     case 0x02:
 150     case 0x12:
 151         d->i.bmdma[0].status = (val & 0x60) | (d->i.bmdma[0].status & 1) |
 152                                (d->i.bmdma[0].status & ~val & 6);
 153         break;
 154     case 0x04 ... 0x07:
 155         bmdma_addr_ioport_ops.write(&d->i.bmdma[0], addr - 4, val, size);
 156         break;
 157     case 0x08:
 158     case 0x18:
 159         bmdma_cmd_writeb(&d->i.bmdma[1], val);
 160         break;
 161     case 0x09:
 162     case 0x19:
 163         d->regs[1].swdata = val & 0x3f;
 164         break;
 165     case 0x0a:
 166     case 0x1a:
 167         d->i.bmdma[1].status = (val & 0x60) | (d->i.bmdma[1].status & 1) |
 168                                (d->i.bmdma[1].status & ~val & 6);
 169         break;
 170     case 0x0c ... 0x0f:
 171         bmdma_addr_ioport_ops.write(&d->i.bmdma[1], addr - 12, val, size);
 172         break;
 173     case 0x80 ... 0x87:
 174         pci_ide_data_le_ops.write(&d->i.bus[0], addr - 0x80, val, size);
 175         break;
 176     case 0x8a:
 177         pci_ide_cmd_le_ops.write(&d->i.bus[0], 2, val, size);
 178         break;
 179     case 0xc0 ... 0xc7:
 180         pci_ide_data_le_ops.write(&d->i.bus[1], addr - 0xc0, val, size);
 181         break;
 182     case 0xca:
 183         pci_ide_cmd_le_ops.write(&d->i.bus[1], 2, val, size);
 184         break;
 185     case 0x100:
 186         d->regs[0].scontrol = val & 0xfff;
 187         if (val & 1) {
 188             ide_bus_reset(&d->i.bus[0]);
 189         }
 190         break;
 191     case 0x148:
 192         d->regs[0].sien = (val >> 16) & 0x3eed;
 193         break;
 194     case 0x180:
 195         d->regs[1].scontrol = val & 0xfff;
 196         if (val & 1) {
 197             ide_bus_reset(&d->i.bus[1]);
 198         }
 199         break;
 200     case 0x1c8:
 201         d->regs[1].sien = (val >> 16) & 0x3eed;
 202         break;
 203     default:
 204         val = 0;
 205     }
 206 }
 207
 208 static const MemoryRegionOps sii3112_reg_ops = {
 209     .read = sii3112_reg_read,
 210     .write = sii3112_reg_write,
 211     .endianness = DEVICE_LITTLE_ENDIAN,
 212 };
 213
 214 /* the PCI irq level is the logical OR of the two channels */
 215 static void sii3112_update_irq(SiI3112PCIState *s)
 216 {
 217     int i, set = 0;
 218
 219     for (i = 0; i < 2; i++) {
 220         set |= s->regs[i].confstat & (1UL << 11);
 221     }
 222     pci_set_irq(PCI_DEVICE(s), (set ? 1 : 0));
 223 }
 224
 225 static void sii3112_set_irq(void *opaque, int channel, int level)
 226 {
 227     SiI3112PCIState *s = opaque;
 228
 229     trace_sii3112_set_irq(channel, level);
 230     if (level) {
 231         s->regs[channel].confstat |= (1UL << 11);
 232     } else {
 233         s->regs[channel].confstat &= ~(1UL << 11);
 234     }
 235
 236     sii3112_update_irq(s);
 237 }
 238
 239 static void sii3112_reset(void *opaque)
 240 {
 241     SiI3112PCIState *s = opaque;
 242     int i;
 243
 244     for (i = 0; i < 2; i++) {
 245         s->regs[i].confstat = 0x6515 << 16;
 246         ide_bus_reset(&s->i.bus[i]);
 247     }
 248 }
 249
 250 static void sii3112_pci_realize(PCIDevice *dev, Error **errp)
 251 {
 252     SiI3112PCIState *d = SII3112_PCI(dev);
 253     PCIIDEState *s = PCI_IDE(dev);
 254     MemoryRegion *mr;
 255     qemu_irq *irq;
 256     int i;
 257
 258     pci_config_set_interrupt_pin(dev->config, 1);
 259     pci_set_byte(dev->config + PCI_CACHE_LINE_SIZE, 8);
 260
 261     /* BAR5 is in PCI memory space */
 262     memory_region_init_io(&d->mmio, OBJECT(d), &sii3112_reg_ops, d,
 263                          "sii3112.bar5", 0x200);
 264     pci_register_bar(dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
 265
 266     /* BAR0-BAR4 are PCI I/O space aliases into BAR5 */
 267     mr = g_new(MemoryRegion, 1);
 268     memory_region_init_alias(mr, OBJECT(d), "sii3112.bar0", &d->mmio, 0x80, 8);
 269     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, mr);
 270     mr = g_new(MemoryRegion, 1);
 271     memory_region_init_alias(mr, OBJECT(d), "sii3112.bar1", &d->mmio, 0x88, 4);
 272     pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, mr);
 273     mr = g_new(MemoryRegion, 1);
 274     memory_region_init_alias(mr, OBJECT(d), "sii3112.bar2", &d->mmio, 0xc0, 8);
 275     pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, mr);
 276     mr = g_new(MemoryRegion, 1);
 277     memory_region_init_alias(mr, OBJECT(d), "sii3112.bar3", &d->mmio, 0xc8, 4);
 278     pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, mr);
 279     mr = g_new(MemoryRegion, 1);
 280     memory_region_init_alias(mr, OBJECT(d), "sii3112.bar4", &d->mmio, 0, 16);
 281     pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, mr);
 282
 283     irq = qemu_allocate_irqs(sii3112_set_irq, d, 2);
 284     for (i = 0; i < 2; i++) {
 285         ide_bus_new(&s->bus[i], sizeof(s->bus[i]), DEVICE(dev), i, 1);
 286         ide_init2(&s->bus[i], irq[i]);
 287
 288         bmdma_init(&s->bus[i], &s->bmdma[i], s);
 289         s->bmdma[i].bus = &s->bus[i];
 290         ide_register_restart_cb(&s->bus[i]);
 291     }
 292     qemu_register_reset(sii3112_reset, s);
 293 }
 294
 295 static void sii3112_pci_class_init(ObjectClass *klass, void *data)
 296 {
 297     DeviceClass *dc = DEVICE_CLASS(klass);
 298     PCIDeviceClass *pd = PCI_DEVICE_CLASS(klass);
 299
 300     pd->vendor_id = 0x1095;
 301     pd->device_id = 0x3112;
 302     pd->class_id = PCI_CLASS_STORAGE_RAID;
 303     pd->revision = 1;
 304     pd->realize = sii3112_pci_realize;
 305     dc->desc = "SiI3112A SATA controller";
 306     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 307 }
 308
 309 static const TypeInfo sii3112_pci_info = {
 310     .name = TYPE_SII3112_PCI,
 311     .parent = TYPE_PCI_IDE,
 312     .instance_size = sizeof(SiI3112PCIState),
 313     .class_init = sii3112_pci_class_init,
 314 };
 315
 316 static void sii3112_register_types(void)
 317 {
 318     type_register_static(&sii3112_pci_info);
 319 }
 320
 321 type_init(sii3112_register_types)