2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (c) 2013 David Gibson, IBM Corporation
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "sysemu/kvm.h"
24 #include "mmu-hash64.h"
30 # define LOG_MMU(...) qemu_log(__VA_ARGS__)
31 # define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0)
33 # define LOG_MMU(...) do { } while (0)
34 # define LOG_MMU_STATE(cpu) do { } while (0)
38 # define LOG_SLB(...) qemu_log(__VA_ARGS__)
40 # define LOG_SLB(...) do { } while (0)
47 static ppc_slb_t
*slb_lookup(CPUPPCState
*env
, target_ulong eaddr
)
49 uint64_t esid_256M
, esid_1T
;
52 LOG_SLB("%s: eaddr " TARGET_FMT_lx
"\n", __func__
, eaddr
);
54 esid_256M
= (eaddr
& SEGMENT_MASK_256M
) | SLB_ESID_V
;
55 esid_1T
= (eaddr
& SEGMENT_MASK_1T
) | SLB_ESID_V
;
57 for (n
= 0; n
< env
->slb_nr
; n
++) {
58 ppc_slb_t
*slb
= &env
->slb
[n
];
60 LOG_SLB("%s: slot %d %016" PRIx64
" %016"
61 PRIx64
"\n", __func__
, n
, slb
->esid
, slb
->vsid
);
62 /* We check for 1T matches on all MMUs here - if the MMU
63 * doesn't have 1T segment support, we will have prevented 1T
64 * entries from being inserted in the slbmte code. */
65 if (((slb
->esid
== esid_256M
) &&
66 ((slb
->vsid
& SLB_VSID_B
) == SLB_VSID_B_256M
))
67 || ((slb
->esid
== esid_1T
) &&
68 ((slb
->vsid
& SLB_VSID_B
) == SLB_VSID_B_1T
))) {
76 void dump_slb(FILE *f
, fprintf_function cpu_fprintf
, CPUPPCState
*env
)
81 cpu_synchronize_state(CPU(ppc_env_get_cpu(env
)));
83 cpu_fprintf(f
, "SLB\tESID\t\t\tVSID\n");
84 for (i
= 0; i
< env
->slb_nr
; i
++) {
85 slbe
= env
->slb
[i
].esid
;
86 slbv
= env
->slb
[i
].vsid
;
87 if (slbe
== 0 && slbv
== 0) {
90 cpu_fprintf(f
, "%d\t0x%016" PRIx64
"\t0x%016" PRIx64
"\n",
95 void helper_slbia(CPUPPCState
*env
)
100 /* XXX: Warning: slbia never invalidates the first segment */
101 for (n
= 1; n
< env
->slb_nr
; n
++) {
102 ppc_slb_t
*slb
= &env
->slb
[n
];
104 if (slb
->esid
& SLB_ESID_V
) {
105 slb
->esid
&= ~SLB_ESID_V
;
106 /* XXX: given the fact that segment size is 256 MB or 1TB,
107 * and we still don't have a tlb_flush_mask(env, n, mask)
108 * in QEMU, we just invalidate all TLBs
118 void helper_slbie(CPUPPCState
*env
, target_ulong addr
)
122 slb
= slb_lookup(env
, addr
);
127 if (slb
->esid
& SLB_ESID_V
) {
128 slb
->esid
&= ~SLB_ESID_V
;
130 /* XXX: given the fact that segment size is 256 MB or 1TB,
131 * and we still don't have a tlb_flush_mask(env, n, mask)
132 * in QEMU, we just invalidate all TLBs
138 int ppc_store_slb(CPUPPCState
*env
, target_ulong rb
, target_ulong rs
)
140 int slot
= rb
& 0xfff;
141 ppc_slb_t
*slb
= &env
->slb
[slot
];
143 if (rb
& (0x1000 - env
->slb_nr
)) {
144 return -1; /* Reserved bits set or slot too high */
146 if (rs
& (SLB_VSID_B
& ~SLB_VSID_B_1T
)) {
147 return -1; /* Bad segment size */
149 if ((rs
& SLB_VSID_B
) && !(env
->mmu_model
& POWERPC_MMU_1TSEG
)) {
150 return -1; /* 1T segment on MMU that doesn't support it */
153 /* Mask out the slot number as we store the entry */
154 slb
->esid
= rb
& (SLB_ESID_ESID
| SLB_ESID_V
);
157 LOG_SLB("%s: %d " TARGET_FMT_lx
" - " TARGET_FMT_lx
" => %016" PRIx64
158 " %016" PRIx64
"\n", __func__
, slot
, rb
, rs
,
159 slb
->esid
, slb
->vsid
);
164 static int ppc_load_slb_esid(CPUPPCState
*env
, target_ulong rb
,
167 int slot
= rb
& 0xfff;
168 ppc_slb_t
*slb
= &env
->slb
[slot
];
170 if (slot
>= env
->slb_nr
) {
178 static int ppc_load_slb_vsid(CPUPPCState
*env
, target_ulong rb
,
181 int slot
= rb
& 0xfff;
182 ppc_slb_t
*slb
= &env
->slb
[slot
];
184 if (slot
>= env
->slb_nr
) {
192 void helper_store_slb(CPUPPCState
*env
, target_ulong rb
, target_ulong rs
)
194 if (ppc_store_slb(env
, rb
, rs
) < 0) {
195 helper_raise_exception_err(env
, POWERPC_EXCP_PROGRAM
,
200 target_ulong
helper_load_slb_esid(CPUPPCState
*env
, target_ulong rb
)
204 if (ppc_load_slb_esid(env
, rb
, &rt
) < 0) {
205 helper_raise_exception_err(env
, POWERPC_EXCP_PROGRAM
,
211 target_ulong
helper_load_slb_vsid(CPUPPCState
*env
, target_ulong rb
)
215 if (ppc_load_slb_vsid(env
, rb
, &rt
) < 0) {
216 helper_raise_exception_err(env
, POWERPC_EXCP_PROGRAM
,
223 * 64-bit hash table MMU handling
226 static int ppc_hash64_pte_prot(CPUPPCState
*env
,
227 ppc_slb_t
*slb
, ppc_hash_pte64_t pte
)
230 /* Some pp bit combinations have undefined behaviour, so default
231 * to no access in those cases */
234 key
= !!(msr_pr
? (slb
->vsid
& SLB_VSID_KP
)
235 : (slb
->vsid
& SLB_VSID_KS
));
236 pp
= (pte
.pte1
& HPTE64_R_PP
) | ((pte
.pte1
& HPTE64_R_PP0
) >> 61);
243 prot
= PAGE_READ
| PAGE_WRITE
;
264 prot
= PAGE_READ
| PAGE_WRITE
;
269 /* No execute if either noexec or guarded bits set */
270 if (!(pte
.pte1
& HPTE64_R_N
) || (pte
.pte1
& HPTE64_R_G
)
271 || (slb
->vsid
& SLB_VSID_N
)) {
278 static int ppc_hash64_amr_prot(CPUPPCState
*env
, ppc_hash_pte64_t pte
)
281 int prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
284 /* Only recent MMUs implement Virtual Page Class Key Protection */
285 if (!(env
->mmu_model
& POWERPC_MMU_AMR
)) {
289 key
= HPTE64_R_KEY(pte
.pte1
);
290 amrbits
= (env
->spr
[SPR_AMR
] >> 2*(31 - key
)) & 0x3;
292 /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */
293 /* env->spr[SPR_AMR]); */
296 * A store is permitted if the AMR bit is 0. Remove write
297 * protection if it is set.
303 * A load is permitted if the AMR bit is 0. Remove read
304 * protection if it is set.
313 static hwaddr
ppc_hash64_pteg_search(CPUPPCState
*env
, hwaddr pteg_off
,
314 bool secondary
, target_ulong ptem
,
315 ppc_hash_pte64_t
*pte
)
317 hwaddr pte_offset
= pteg_off
;
318 target_ulong pte0
, pte1
;
321 for (i
= 0; i
< HPTES_PER_GROUP
; i
++) {
322 pte0
= ppc_hash64_load_hpte0(env
, pte_offset
);
323 pte1
= ppc_hash64_load_hpte1(env
, pte_offset
);
325 if ((pte0
& HPTE64_V_VALID
)
326 && (secondary
== !!(pte0
& HPTE64_V_SECONDARY
))
327 && HPTE64_V_COMPARE(pte0
, ptem
)) {
333 pte_offset
+= HASH_PTE_SIZE_64
;
339 static hwaddr
ppc_hash64_htab_lookup(CPUPPCState
*env
,
340 ppc_slb_t
*slb
, target_ulong eaddr
,
341 ppc_hash_pte64_t
*pte
)
343 hwaddr pteg_off
, pte_offset
;
345 uint64_t vsid
, epnshift
, epnmask
, epn
, ptem
;
347 /* Page size according to the SLB, which we use to generate the
348 * EPN for hash table lookup.. When we implement more recent MMU
349 * extensions this might be different from the actual page size
350 * encoded in the PTE */
351 epnshift
= (slb
->vsid
& SLB_VSID_L
)
352 ? TARGET_PAGE_BITS_16M
: TARGET_PAGE_BITS
;
353 epnmask
= ~((1ULL << epnshift
) - 1);
355 if (slb
->vsid
& SLB_VSID_B
) {
357 vsid
= (slb
->vsid
& SLB_VSID_VSID
) >> SLB_VSID_SHIFT_1T
;
358 epn
= (eaddr
& ~SEGMENT_MASK_1T
) & epnmask
;
359 hash
= vsid
^ (vsid
<< 25) ^ (epn
>> epnshift
);
362 vsid
= (slb
->vsid
& SLB_VSID_VSID
) >> SLB_VSID_SHIFT
;
363 epn
= (eaddr
& ~SEGMENT_MASK_256M
) & epnmask
;
364 hash
= vsid
^ (epn
>> epnshift
);
366 ptem
= (slb
->vsid
& SLB_VSID_PTEM
) | ((epn
>> 16) & HPTE64_V_AVPN
);
368 /* Page address translation */
369 LOG_MMU("htab_base " TARGET_FMT_plx
" htab_mask " TARGET_FMT_plx
370 " hash " TARGET_FMT_plx
"\n",
371 env
->htab_base
, env
->htab_mask
, hash
);
373 /* Primary PTEG lookup */
374 LOG_MMU("0 htab=" TARGET_FMT_plx
"/" TARGET_FMT_plx
375 " vsid=" TARGET_FMT_lx
" ptem=" TARGET_FMT_lx
376 " hash=" TARGET_FMT_plx
"\n",
377 env
->htab_base
, env
->htab_mask
, vsid
, ptem
, hash
);
378 pteg_off
= (hash
* HASH_PTEG_SIZE_64
) & env
->htab_mask
;
379 pte_offset
= ppc_hash64_pteg_search(env
, pteg_off
, 0, ptem
, pte
);
381 if (pte_offset
== -1) {
382 /* Secondary PTEG lookup */
383 LOG_MMU("1 htab=" TARGET_FMT_plx
"/" TARGET_FMT_plx
384 " vsid=" TARGET_FMT_lx
" api=" TARGET_FMT_lx
385 " hash=" TARGET_FMT_plx
"\n", env
->htab_base
,
386 env
->htab_mask
, vsid
, ptem
, ~hash
);
388 pteg_off
= (~hash
* HASH_PTEG_SIZE_64
) & env
->htab_mask
;
389 pte_offset
= ppc_hash64_pteg_search(env
, pteg_off
, 1, ptem
, pte
);
395 static hwaddr
ppc_hash64_pte_raddr(ppc_slb_t
*slb
, ppc_hash_pte64_t pte
,
398 hwaddr rpn
= pte
.pte1
& HPTE64_R_RPN
;
399 /* FIXME: Add support for SLLP extended page sizes */
400 int target_page_bits
= (slb
->vsid
& SLB_VSID_L
)
401 ? TARGET_PAGE_BITS_16M
: TARGET_PAGE_BITS
;
402 hwaddr mask
= (1ULL << target_page_bits
) - 1;
404 return (rpn
& ~mask
) | (eaddr
& mask
);
407 int ppc_hash64_handle_mmu_fault(CPUPPCState
*env
, target_ulong eaddr
,
408 int rwx
, int mmu_idx
)
412 ppc_hash_pte64_t pte
;
413 int pp_prot
, amr_prot
, prot
;
415 const int need_prot
[] = {PAGE_READ
, PAGE_WRITE
, PAGE_EXEC
};
418 assert((rwx
== 0) || (rwx
== 1) || (rwx
== 2));
420 /* 1. Handle real mode accesses */
421 if (((rwx
== 2) && (msr_ir
== 0)) || ((rwx
!= 2) && (msr_dr
== 0))) {
422 /* Translation is off */
423 /* In real mode the top 4 effective address bits are ignored */
424 raddr
= eaddr
& 0x0FFFFFFFFFFFFFFFULL
;
425 tlb_set_page(env
, eaddr
& TARGET_PAGE_MASK
, raddr
& TARGET_PAGE_MASK
,
426 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
, mmu_idx
,
431 /* 2. Translation is on, so look up the SLB */
432 slb
= slb_lookup(env
, eaddr
);
436 env
->exception_index
= POWERPC_EXCP_ISEG
;
439 env
->exception_index
= POWERPC_EXCP_DSEG
;
441 env
->spr
[SPR_DAR
] = eaddr
;
446 /* 3. Check for segment level no-execute violation */
447 if ((rwx
== 2) && (slb
->vsid
& SLB_VSID_N
)) {
448 env
->exception_index
= POWERPC_EXCP_ISI
;
449 env
->error_code
= 0x10000000;
453 /* 4. Locate the PTE in the hash table */
454 pte_offset
= ppc_hash64_htab_lookup(env
, slb
, eaddr
, &pte
);
455 if (pte_offset
== -1) {
457 env
->exception_index
= POWERPC_EXCP_ISI
;
458 env
->error_code
= 0x40000000;
460 env
->exception_index
= POWERPC_EXCP_DSI
;
462 env
->spr
[SPR_DAR
] = eaddr
;
464 env
->spr
[SPR_DSISR
] = 0x42000000;
466 env
->spr
[SPR_DSISR
] = 0x40000000;
471 LOG_MMU("found PTE at offset %08" HWADDR_PRIx
"\n", pte_offset
);
473 /* 5. Check access permissions */
475 pp_prot
= ppc_hash64_pte_prot(env
, slb
, pte
);
476 amr_prot
= ppc_hash64_amr_prot(env
, pte
);
477 prot
= pp_prot
& amr_prot
;
479 if ((need_prot
[rwx
] & ~prot
) != 0) {
480 /* Access right violation */
481 LOG_MMU("PTE access rejected\n");
483 env
->exception_index
= POWERPC_EXCP_ISI
;
484 env
->error_code
= 0x08000000;
486 target_ulong dsisr
= 0;
488 env
->exception_index
= POWERPC_EXCP_DSI
;
490 env
->spr
[SPR_DAR
] = eaddr
;
491 if (need_prot
[rwx
] & ~pp_prot
) {
497 if (need_prot
[rwx
] & ~amr_prot
) {
500 env
->spr
[SPR_DSISR
] = dsisr
;
505 LOG_MMU("PTE access granted !\n");
507 /* 6. Update PTE referenced and changed bits if necessary */
509 new_pte1
= pte
.pte1
| HPTE64_R_R
; /* set referenced bit */
511 new_pte1
|= HPTE64_R_C
; /* set changed (dirty) bit */
513 /* Treat the page as read-only for now, so that a later write
514 * will pass through this function again to set the C bit */
518 if (new_pte1
!= pte
.pte1
) {
519 ppc_hash64_store_hpte1(env
, pte_offset
, new_pte1
);
522 /* 7. Determine the real address from the PTE */
524 raddr
= ppc_hash64_pte_raddr(slb
, pte
, eaddr
);
526 tlb_set_page(env
, eaddr
& TARGET_PAGE_MASK
, raddr
& TARGET_PAGE_MASK
,
527 prot
, mmu_idx
, TARGET_PAGE_SIZE
);
532 hwaddr
ppc_hash64_get_phys_page_debug(CPUPPCState
*env
, target_ulong addr
)
536 ppc_hash_pte64_t pte
;
539 /* In real mode the top 4 effective address bits are ignored */
540 return addr
& 0x0FFFFFFFFFFFFFFFULL
;
543 slb
= slb_lookup(env
, addr
);
548 pte_offset
= ppc_hash64_htab_lookup(env
, slb
, addr
, &pte
);
549 if (pte_offset
== -1) {
553 return ppc_hash64_pte_raddr(slb
, pte
, addr
) & TARGET_PAGE_MASK
;