4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
28 #include "disas/disas.h"
31 #include "qemu/bitops.h"
37 #define ENABLE_ARCH_4T arm_feature(env, ARM_FEATURE_V4T)
38 #define ENABLE_ARCH_5 arm_feature(env, ARM_FEATURE_V5)
39 /* currently all emulated v5 cores are also v5TE, so don't bother */
40 #define ENABLE_ARCH_5TE arm_feature(env, ARM_FEATURE_V5)
41 #define ENABLE_ARCH_5J 0
42 #define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
43 #define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
44 #define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
45 #define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
46 #define ENABLE_ARCH_8 arm_feature(env, ARM_FEATURE_V8)
48 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
50 #include "translate.h"
51 static uint32_t gen_opc_condexec_bits
[OPC_BUF_SIZE
];
53 #if defined(CONFIG_USER_ONLY)
56 #define IS_USER(s) (s->user)
60 /* We reuse the same 64-bit temporaries for efficiency. */
61 static TCGv_i64 cpu_V0
, cpu_V1
, cpu_M0
;
62 static TCGv_i32 cpu_R
[16];
63 static TCGv_i32 cpu_CF
, cpu_NF
, cpu_VF
, cpu_ZF
;
64 static TCGv_i64 cpu_exclusive_addr
;
65 static TCGv_i64 cpu_exclusive_val
;
66 #ifdef CONFIG_USER_ONLY
67 static TCGv_i64 cpu_exclusive_test
;
68 static TCGv_i32 cpu_exclusive_info
;
71 /* FIXME: These should be removed. */
72 static TCGv_i32 cpu_F0s
, cpu_F1s
;
73 static TCGv_i64 cpu_F0d
, cpu_F1d
;
75 #include "exec/gen-icount.h"
77 static const char *regnames
[] =
78 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
79 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
81 /* initialize TCG globals. */
82 void arm_translate_init(void)
86 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
88 for (i
= 0; i
< 16; i
++) {
89 cpu_R
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
90 offsetof(CPUARMState
, regs
[i
]),
93 cpu_CF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, CF
), "CF");
94 cpu_NF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, NF
), "NF");
95 cpu_VF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, VF
), "VF");
96 cpu_ZF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, ZF
), "ZF");
98 cpu_exclusive_addr
= tcg_global_mem_new_i64(TCG_AREG0
,
99 offsetof(CPUARMState
, exclusive_addr
), "exclusive_addr");
100 cpu_exclusive_val
= tcg_global_mem_new_i64(TCG_AREG0
,
101 offsetof(CPUARMState
, exclusive_val
), "exclusive_val");
102 #ifdef CONFIG_USER_ONLY
103 cpu_exclusive_test
= tcg_global_mem_new_i64(TCG_AREG0
,
104 offsetof(CPUARMState
, exclusive_test
), "exclusive_test");
105 cpu_exclusive_info
= tcg_global_mem_new_i32(TCG_AREG0
,
106 offsetof(CPUARMState
, exclusive_info
), "exclusive_info");
109 a64_translate_init();
112 static inline TCGv_i32
load_cpu_offset(int offset
)
114 TCGv_i32 tmp
= tcg_temp_new_i32();
115 tcg_gen_ld_i32(tmp
, cpu_env
, offset
);
119 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
121 static inline void store_cpu_offset(TCGv_i32 var
, int offset
)
123 tcg_gen_st_i32(var
, cpu_env
, offset
);
124 tcg_temp_free_i32(var
);
127 #define store_cpu_field(var, name) \
128 store_cpu_offset(var, offsetof(CPUARMState, name))
130 /* Set a variable to the value of a CPU register. */
131 static void load_reg_var(DisasContext
*s
, TCGv_i32 var
, int reg
)
135 /* normally, since we updated PC, we need only to add one insn */
137 addr
= (long)s
->pc
+ 2;
139 addr
= (long)s
->pc
+ 4;
140 tcg_gen_movi_i32(var
, addr
);
142 tcg_gen_mov_i32(var
, cpu_R
[reg
]);
146 /* Create a new temporary and set it to the value of a CPU register. */
147 static inline TCGv_i32
load_reg(DisasContext
*s
, int reg
)
149 TCGv_i32 tmp
= tcg_temp_new_i32();
150 load_reg_var(s
, tmp
, reg
);
154 /* Set a CPU register. The source must be a temporary and will be
156 static void store_reg(DisasContext
*s
, int reg
, TCGv_i32 var
)
159 tcg_gen_andi_i32(var
, var
, ~1);
160 s
->is_jmp
= DISAS_JUMP
;
162 tcg_gen_mov_i32(cpu_R
[reg
], var
);
163 tcg_temp_free_i32(var
);
166 /* Value extensions. */
167 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
168 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
169 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
170 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
172 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
173 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
176 static inline void gen_set_cpsr(TCGv_i32 var
, uint32_t mask
)
178 TCGv_i32 tmp_mask
= tcg_const_i32(mask
);
179 gen_helper_cpsr_write(cpu_env
, var
, tmp_mask
);
180 tcg_temp_free_i32(tmp_mask
);
182 /* Set NZCV flags from the high 4 bits of var. */
183 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
185 static void gen_exception(int excp
)
187 TCGv_i32 tmp
= tcg_temp_new_i32();
188 tcg_gen_movi_i32(tmp
, excp
);
189 gen_helper_exception(cpu_env
, tmp
);
190 tcg_temp_free_i32(tmp
);
193 static void gen_smul_dual(TCGv_i32 a
, TCGv_i32 b
)
195 TCGv_i32 tmp1
= tcg_temp_new_i32();
196 TCGv_i32 tmp2
= tcg_temp_new_i32();
197 tcg_gen_ext16s_i32(tmp1
, a
);
198 tcg_gen_ext16s_i32(tmp2
, b
);
199 tcg_gen_mul_i32(tmp1
, tmp1
, tmp2
);
200 tcg_temp_free_i32(tmp2
);
201 tcg_gen_sari_i32(a
, a
, 16);
202 tcg_gen_sari_i32(b
, b
, 16);
203 tcg_gen_mul_i32(b
, b
, a
);
204 tcg_gen_mov_i32(a
, tmp1
);
205 tcg_temp_free_i32(tmp1
);
208 /* Byteswap each halfword. */
209 static void gen_rev16(TCGv_i32 var
)
211 TCGv_i32 tmp
= tcg_temp_new_i32();
212 tcg_gen_shri_i32(tmp
, var
, 8);
213 tcg_gen_andi_i32(tmp
, tmp
, 0x00ff00ff);
214 tcg_gen_shli_i32(var
, var
, 8);
215 tcg_gen_andi_i32(var
, var
, 0xff00ff00);
216 tcg_gen_or_i32(var
, var
, tmp
);
217 tcg_temp_free_i32(tmp
);
220 /* Byteswap low halfword and sign extend. */
221 static void gen_revsh(TCGv_i32 var
)
223 tcg_gen_ext16u_i32(var
, var
);
224 tcg_gen_bswap16_i32(var
, var
);
225 tcg_gen_ext16s_i32(var
, var
);
228 /* Unsigned bitfield extract. */
229 static void gen_ubfx(TCGv_i32 var
, int shift
, uint32_t mask
)
232 tcg_gen_shri_i32(var
, var
, shift
);
233 tcg_gen_andi_i32(var
, var
, mask
);
236 /* Signed bitfield extract. */
237 static void gen_sbfx(TCGv_i32 var
, int shift
, int width
)
242 tcg_gen_sari_i32(var
, var
, shift
);
243 if (shift
+ width
< 32) {
244 signbit
= 1u << (width
- 1);
245 tcg_gen_andi_i32(var
, var
, (1u << width
) - 1);
246 tcg_gen_xori_i32(var
, var
, signbit
);
247 tcg_gen_subi_i32(var
, var
, signbit
);
251 /* Return (b << 32) + a. Mark inputs as dead */
252 static TCGv_i64
gen_addq_msw(TCGv_i64 a
, TCGv_i32 b
)
254 TCGv_i64 tmp64
= tcg_temp_new_i64();
256 tcg_gen_extu_i32_i64(tmp64
, b
);
257 tcg_temp_free_i32(b
);
258 tcg_gen_shli_i64(tmp64
, tmp64
, 32);
259 tcg_gen_add_i64(a
, tmp64
, a
);
261 tcg_temp_free_i64(tmp64
);
265 /* Return (b << 32) - a. Mark inputs as dead. */
266 static TCGv_i64
gen_subq_msw(TCGv_i64 a
, TCGv_i32 b
)
268 TCGv_i64 tmp64
= tcg_temp_new_i64();
270 tcg_gen_extu_i32_i64(tmp64
, b
);
271 tcg_temp_free_i32(b
);
272 tcg_gen_shli_i64(tmp64
, tmp64
, 32);
273 tcg_gen_sub_i64(a
, tmp64
, a
);
275 tcg_temp_free_i64(tmp64
);
279 /* 32x32->64 multiply. Marks inputs as dead. */
280 static TCGv_i64
gen_mulu_i64_i32(TCGv_i32 a
, TCGv_i32 b
)
282 TCGv_i32 lo
= tcg_temp_new_i32();
283 TCGv_i32 hi
= tcg_temp_new_i32();
286 tcg_gen_mulu2_i32(lo
, hi
, a
, b
);
287 tcg_temp_free_i32(a
);
288 tcg_temp_free_i32(b
);
290 ret
= tcg_temp_new_i64();
291 tcg_gen_concat_i32_i64(ret
, lo
, hi
);
292 tcg_temp_free_i32(lo
);
293 tcg_temp_free_i32(hi
);
298 static TCGv_i64
gen_muls_i64_i32(TCGv_i32 a
, TCGv_i32 b
)
300 TCGv_i32 lo
= tcg_temp_new_i32();
301 TCGv_i32 hi
= tcg_temp_new_i32();
304 tcg_gen_muls2_i32(lo
, hi
, a
, b
);
305 tcg_temp_free_i32(a
);
306 tcg_temp_free_i32(b
);
308 ret
= tcg_temp_new_i64();
309 tcg_gen_concat_i32_i64(ret
, lo
, hi
);
310 tcg_temp_free_i32(lo
);
311 tcg_temp_free_i32(hi
);
316 /* Swap low and high halfwords. */
317 static void gen_swap_half(TCGv_i32 var
)
319 TCGv_i32 tmp
= tcg_temp_new_i32();
320 tcg_gen_shri_i32(tmp
, var
, 16);
321 tcg_gen_shli_i32(var
, var
, 16);
322 tcg_gen_or_i32(var
, var
, tmp
);
323 tcg_temp_free_i32(tmp
);
326 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
327 tmp = (t0 ^ t1) & 0x8000;
330 t0 = (t0 + t1) ^ tmp;
333 static void gen_add16(TCGv_i32 t0
, TCGv_i32 t1
)
335 TCGv_i32 tmp
= tcg_temp_new_i32();
336 tcg_gen_xor_i32(tmp
, t0
, t1
);
337 tcg_gen_andi_i32(tmp
, tmp
, 0x8000);
338 tcg_gen_andi_i32(t0
, t0
, ~0x8000);
339 tcg_gen_andi_i32(t1
, t1
, ~0x8000);
340 tcg_gen_add_i32(t0
, t0
, t1
);
341 tcg_gen_xor_i32(t0
, t0
, tmp
);
342 tcg_temp_free_i32(tmp
);
343 tcg_temp_free_i32(t1
);
346 /* Set CF to the top bit of var. */
347 static void gen_set_CF_bit31(TCGv_i32 var
)
349 tcg_gen_shri_i32(cpu_CF
, var
, 31);
352 /* Set N and Z flags from var. */
353 static inline void gen_logic_CC(TCGv_i32 var
)
355 tcg_gen_mov_i32(cpu_NF
, var
);
356 tcg_gen_mov_i32(cpu_ZF
, var
);
360 static void gen_adc(TCGv_i32 t0
, TCGv_i32 t1
)
362 tcg_gen_add_i32(t0
, t0
, t1
);
363 tcg_gen_add_i32(t0
, t0
, cpu_CF
);
366 /* dest = T0 + T1 + CF. */
367 static void gen_add_carry(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
369 tcg_gen_add_i32(dest
, t0
, t1
);
370 tcg_gen_add_i32(dest
, dest
, cpu_CF
);
373 /* dest = T0 - T1 + CF - 1. */
374 static void gen_sub_carry(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
376 tcg_gen_sub_i32(dest
, t0
, t1
);
377 tcg_gen_add_i32(dest
, dest
, cpu_CF
);
378 tcg_gen_subi_i32(dest
, dest
, 1);
381 /* dest = T0 + T1. Compute C, N, V and Z flags */
382 static void gen_add_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
384 TCGv_i32 tmp
= tcg_temp_new_i32();
385 tcg_gen_movi_i32(tmp
, 0);
386 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0
, tmp
, t1
, tmp
);
387 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
388 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0
);
389 tcg_gen_xor_i32(tmp
, t0
, t1
);
390 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
391 tcg_temp_free_i32(tmp
);
392 tcg_gen_mov_i32(dest
, cpu_NF
);
395 /* dest = T0 + T1 + CF. Compute C, N, V and Z flags */
396 static void gen_adc_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
398 TCGv_i32 tmp
= tcg_temp_new_i32();
399 if (TCG_TARGET_HAS_add2_i32
) {
400 tcg_gen_movi_i32(tmp
, 0);
401 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0
, tmp
, cpu_CF
, tmp
);
402 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1
, tmp
);
404 TCGv_i64 q0
= tcg_temp_new_i64();
405 TCGv_i64 q1
= tcg_temp_new_i64();
406 tcg_gen_extu_i32_i64(q0
, t0
);
407 tcg_gen_extu_i32_i64(q1
, t1
);
408 tcg_gen_add_i64(q0
, q0
, q1
);
409 tcg_gen_extu_i32_i64(q1
, cpu_CF
);
410 tcg_gen_add_i64(q0
, q0
, q1
);
411 tcg_gen_extr_i64_i32(cpu_NF
, cpu_CF
, q0
);
412 tcg_temp_free_i64(q0
);
413 tcg_temp_free_i64(q1
);
415 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
416 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0
);
417 tcg_gen_xor_i32(tmp
, t0
, t1
);
418 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
419 tcg_temp_free_i32(tmp
);
420 tcg_gen_mov_i32(dest
, cpu_NF
);
423 /* dest = T0 - T1. Compute C, N, V and Z flags */
424 static void gen_sub_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
427 tcg_gen_sub_i32(cpu_NF
, t0
, t1
);
428 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
429 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0
, t1
);
430 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0
);
431 tmp
= tcg_temp_new_i32();
432 tcg_gen_xor_i32(tmp
, t0
, t1
);
433 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
434 tcg_temp_free_i32(tmp
);
435 tcg_gen_mov_i32(dest
, cpu_NF
);
438 /* dest = T0 + ~T1 + CF. Compute C, N, V and Z flags */
439 static void gen_sbc_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
441 TCGv_i32 tmp
= tcg_temp_new_i32();
442 tcg_gen_not_i32(tmp
, t1
);
443 gen_adc_CC(dest
, t0
, tmp
);
444 tcg_temp_free_i32(tmp
);
447 #define GEN_SHIFT(name) \
448 static void gen_##name(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) \
450 TCGv_i32 tmp1, tmp2, tmp3; \
451 tmp1 = tcg_temp_new_i32(); \
452 tcg_gen_andi_i32(tmp1, t1, 0xff); \
453 tmp2 = tcg_const_i32(0); \
454 tmp3 = tcg_const_i32(0x1f); \
455 tcg_gen_movcond_i32(TCG_COND_GTU, tmp2, tmp1, tmp3, tmp2, t0); \
456 tcg_temp_free_i32(tmp3); \
457 tcg_gen_andi_i32(tmp1, tmp1, 0x1f); \
458 tcg_gen_##name##_i32(dest, tmp2, tmp1); \
459 tcg_temp_free_i32(tmp2); \
460 tcg_temp_free_i32(tmp1); \
466 static void gen_sar(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
469 tmp1
= tcg_temp_new_i32();
470 tcg_gen_andi_i32(tmp1
, t1
, 0xff);
471 tmp2
= tcg_const_i32(0x1f);
472 tcg_gen_movcond_i32(TCG_COND_GTU
, tmp1
, tmp1
, tmp2
, tmp2
, tmp1
);
473 tcg_temp_free_i32(tmp2
);
474 tcg_gen_sar_i32(dest
, t0
, tmp1
);
475 tcg_temp_free_i32(tmp1
);
478 static void tcg_gen_abs_i32(TCGv_i32 dest
, TCGv_i32 src
)
480 TCGv_i32 c0
= tcg_const_i32(0);
481 TCGv_i32 tmp
= tcg_temp_new_i32();
482 tcg_gen_neg_i32(tmp
, src
);
483 tcg_gen_movcond_i32(TCG_COND_GT
, dest
, src
, c0
, src
, tmp
);
484 tcg_temp_free_i32(c0
);
485 tcg_temp_free_i32(tmp
);
488 static void shifter_out_im(TCGv_i32 var
, int shift
)
491 tcg_gen_andi_i32(cpu_CF
, var
, 1);
493 tcg_gen_shri_i32(cpu_CF
, var
, shift
);
495 tcg_gen_andi_i32(cpu_CF
, cpu_CF
, 1);
500 /* Shift by immediate. Includes special handling for shift == 0. */
501 static inline void gen_arm_shift_im(TCGv_i32 var
, int shiftop
,
502 int shift
, int flags
)
508 shifter_out_im(var
, 32 - shift
);
509 tcg_gen_shli_i32(var
, var
, shift
);
515 tcg_gen_shri_i32(cpu_CF
, var
, 31);
517 tcg_gen_movi_i32(var
, 0);
520 shifter_out_im(var
, shift
- 1);
521 tcg_gen_shri_i32(var
, var
, shift
);
528 shifter_out_im(var
, shift
- 1);
531 tcg_gen_sari_i32(var
, var
, shift
);
533 case 3: /* ROR/RRX */
536 shifter_out_im(var
, shift
- 1);
537 tcg_gen_rotri_i32(var
, var
, shift
); break;
539 TCGv_i32 tmp
= tcg_temp_new_i32();
540 tcg_gen_shli_i32(tmp
, cpu_CF
, 31);
542 shifter_out_im(var
, 0);
543 tcg_gen_shri_i32(var
, var
, 1);
544 tcg_gen_or_i32(var
, var
, tmp
);
545 tcg_temp_free_i32(tmp
);
550 static inline void gen_arm_shift_reg(TCGv_i32 var
, int shiftop
,
551 TCGv_i32 shift
, int flags
)
555 case 0: gen_helper_shl_cc(var
, cpu_env
, var
, shift
); break;
556 case 1: gen_helper_shr_cc(var
, cpu_env
, var
, shift
); break;
557 case 2: gen_helper_sar_cc(var
, cpu_env
, var
, shift
); break;
558 case 3: gen_helper_ror_cc(var
, cpu_env
, var
, shift
); break;
563 gen_shl(var
, var
, shift
);
566 gen_shr(var
, var
, shift
);
569 gen_sar(var
, var
, shift
);
571 case 3: tcg_gen_andi_i32(shift
, shift
, 0x1f);
572 tcg_gen_rotr_i32(var
, var
, shift
); break;
575 tcg_temp_free_i32(shift
);
578 #define PAS_OP(pfx) \
580 case 0: gen_pas_helper(glue(pfx,add16)); break; \
581 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
582 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
583 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
584 case 4: gen_pas_helper(glue(pfx,add8)); break; \
585 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
587 static void gen_arm_parallel_addsub(int op1
, int op2
, TCGv_i32 a
, TCGv_i32 b
)
592 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
594 tmp
= tcg_temp_new_ptr();
595 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUARMState
, GE
));
597 tcg_temp_free_ptr(tmp
);
600 tmp
= tcg_temp_new_ptr();
601 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUARMState
, GE
));
603 tcg_temp_free_ptr(tmp
);
605 #undef gen_pas_helper
606 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
619 #undef gen_pas_helper
624 /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
625 #define PAS_OP(pfx) \
627 case 0: gen_pas_helper(glue(pfx,add8)); break; \
628 case 1: gen_pas_helper(glue(pfx,add16)); break; \
629 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
630 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
631 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
632 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
634 static void gen_thumb2_parallel_addsub(int op1
, int op2
, TCGv_i32 a
, TCGv_i32 b
)
639 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
641 tmp
= tcg_temp_new_ptr();
642 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUARMState
, GE
));
644 tcg_temp_free_ptr(tmp
);
647 tmp
= tcg_temp_new_ptr();
648 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUARMState
, GE
));
650 tcg_temp_free_ptr(tmp
);
652 #undef gen_pas_helper
653 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
666 #undef gen_pas_helper
672 * generate a conditional branch based on ARM condition code cc.
673 * This is common between ARM and Aarch64 targets.
675 void arm_gen_test_cc(int cc
, int label
)
682 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_ZF
, 0, label
);
685 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_ZF
, 0, label
);
688 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_CF
, 0, label
);
691 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_CF
, 0, label
);
694 tcg_gen_brcondi_i32(TCG_COND_LT
, cpu_NF
, 0, label
);
697 tcg_gen_brcondi_i32(TCG_COND_GE
, cpu_NF
, 0, label
);
700 tcg_gen_brcondi_i32(TCG_COND_LT
, cpu_VF
, 0, label
);
703 tcg_gen_brcondi_i32(TCG_COND_GE
, cpu_VF
, 0, label
);
705 case 8: /* hi: C && !Z */
706 inv
= gen_new_label();
707 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_CF
, 0, inv
);
708 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_ZF
, 0, label
);
711 case 9: /* ls: !C || Z */
712 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_CF
, 0, label
);
713 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_ZF
, 0, label
);
715 case 10: /* ge: N == V -> N ^ V == 0 */
716 tmp
= tcg_temp_new_i32();
717 tcg_gen_xor_i32(tmp
, cpu_VF
, cpu_NF
);
718 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
719 tcg_temp_free_i32(tmp
);
721 case 11: /* lt: N != V -> N ^ V != 0 */
722 tmp
= tcg_temp_new_i32();
723 tcg_gen_xor_i32(tmp
, cpu_VF
, cpu_NF
);
724 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
725 tcg_temp_free_i32(tmp
);
727 case 12: /* gt: !Z && N == V */
728 inv
= gen_new_label();
729 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_ZF
, 0, inv
);
730 tmp
= tcg_temp_new_i32();
731 tcg_gen_xor_i32(tmp
, cpu_VF
, cpu_NF
);
732 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
733 tcg_temp_free_i32(tmp
);
736 case 13: /* le: Z || N != V */
737 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_ZF
, 0, label
);
738 tmp
= tcg_temp_new_i32();
739 tcg_gen_xor_i32(tmp
, cpu_VF
, cpu_NF
);
740 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
741 tcg_temp_free_i32(tmp
);
744 fprintf(stderr
, "Bad condition code 0x%x\n", cc
);
749 static const uint8_t table_logic_cc
[16] = {
768 /* Set PC and Thumb state from an immediate address. */
769 static inline void gen_bx_im(DisasContext
*s
, uint32_t addr
)
773 s
->is_jmp
= DISAS_UPDATE
;
774 if (s
->thumb
!= (addr
& 1)) {
775 tmp
= tcg_temp_new_i32();
776 tcg_gen_movi_i32(tmp
, addr
& 1);
777 tcg_gen_st_i32(tmp
, cpu_env
, offsetof(CPUARMState
, thumb
));
778 tcg_temp_free_i32(tmp
);
780 tcg_gen_movi_i32(cpu_R
[15], addr
& ~1);
783 /* Set PC and Thumb state from var. var is marked as dead. */
784 static inline void gen_bx(DisasContext
*s
, TCGv_i32 var
)
786 s
->is_jmp
= DISAS_UPDATE
;
787 tcg_gen_andi_i32(cpu_R
[15], var
, ~1);
788 tcg_gen_andi_i32(var
, var
, 1);
789 store_cpu_field(var
, thumb
);
792 /* Variant of store_reg which uses branch&exchange logic when storing
793 to r15 in ARM architecture v7 and above. The source must be a temporary
794 and will be marked as dead. */
795 static inline void store_reg_bx(CPUARMState
*env
, DisasContext
*s
,
796 int reg
, TCGv_i32 var
)
798 if (reg
== 15 && ENABLE_ARCH_7
) {
801 store_reg(s
, reg
, var
);
805 /* Variant of store_reg which uses branch&exchange logic when storing
806 * to r15 in ARM architecture v5T and above. This is used for storing
807 * the results of a LDR/LDM/POP into r15, and corresponds to the cases
808 * in the ARM ARM which use the LoadWritePC() pseudocode function. */
809 static inline void store_reg_from_load(CPUARMState
*env
, DisasContext
*s
,
810 int reg
, TCGv_i32 var
)
812 if (reg
== 15 && ENABLE_ARCH_5
) {
815 store_reg(s
, reg
, var
);
819 /* Abstractions of "generate code to do a guest load/store for
820 * AArch32", where a vaddr is always 32 bits (and is zero
821 * extended if we're a 64 bit core) and data is also
822 * 32 bits unless specifically doing a 64 bit access.
823 * These functions work like tcg_gen_qemu_{ld,st}* except
824 * that the address argument is TCGv_i32 rather than TCGv.
826 #if TARGET_LONG_BITS == 32
828 #define DO_GEN_LD(SUFF, OPC) \
829 static inline void gen_aa32_ld##SUFF(TCGv_i32 val, TCGv_i32 addr, int index) \
831 tcg_gen_qemu_ld_i32(val, addr, index, OPC); \
834 #define DO_GEN_ST(SUFF, OPC) \
835 static inline void gen_aa32_st##SUFF(TCGv_i32 val, TCGv_i32 addr, int index) \
837 tcg_gen_qemu_st_i32(val, addr, index, OPC); \
840 static inline void gen_aa32_ld64(TCGv_i64 val
, TCGv_i32 addr
, int index
)
842 tcg_gen_qemu_ld_i64(val
, addr
, index
, MO_TEQ
);
845 static inline void gen_aa32_st64(TCGv_i64 val
, TCGv_i32 addr
, int index
)
847 tcg_gen_qemu_st_i64(val
, addr
, index
, MO_TEQ
);
852 #define DO_GEN_LD(SUFF, OPC) \
853 static inline void gen_aa32_ld##SUFF(TCGv_i32 val, TCGv_i32 addr, int index) \
855 TCGv addr64 = tcg_temp_new(); \
856 tcg_gen_extu_i32_i64(addr64, addr); \
857 tcg_gen_qemu_ld_i32(val, addr64, index, OPC); \
858 tcg_temp_free(addr64); \
861 #define DO_GEN_ST(SUFF, OPC) \
862 static inline void gen_aa32_st##SUFF(TCGv_i32 val, TCGv_i32 addr, int index) \
864 TCGv addr64 = tcg_temp_new(); \
865 tcg_gen_extu_i32_i64(addr64, addr); \
866 tcg_gen_qemu_st_i32(val, addr64, index, OPC); \
867 tcg_temp_free(addr64); \
870 static inline void gen_aa32_ld64(TCGv_i64 val
, TCGv_i32 addr
, int index
)
872 TCGv addr64
= tcg_temp_new();
873 tcg_gen_extu_i32_i64(addr64
, addr
);
874 tcg_gen_qemu_ld_i64(val
, addr64
, index
, MO_TEQ
);
875 tcg_temp_free(addr64
);
878 static inline void gen_aa32_st64(TCGv_i64 val
, TCGv_i32 addr
, int index
)
880 TCGv addr64
= tcg_temp_new();
881 tcg_gen_extu_i32_i64(addr64
, addr
);
882 tcg_gen_qemu_st_i64(val
, addr64
, index
, MO_TEQ
);
883 tcg_temp_free(addr64
);
890 DO_GEN_LD(16s
, MO_TESW
)
891 DO_GEN_LD(16u, MO_TEUW
)
892 DO_GEN_LD(32u, MO_TEUL
)
894 DO_GEN_ST(16, MO_TEUW
)
895 DO_GEN_ST(32, MO_TEUL
)
897 static inline void gen_set_pc_im(DisasContext
*s
, target_ulong val
)
899 tcg_gen_movi_i32(cpu_R
[15], val
);
902 /* Force a TB lookup after an instruction that changes the CPU state. */
903 static inline void gen_lookup_tb(DisasContext
*s
)
905 tcg_gen_movi_i32(cpu_R
[15], s
->pc
& ~1);
906 s
->is_jmp
= DISAS_UPDATE
;
909 static inline void gen_add_data_offset(DisasContext
*s
, unsigned int insn
,
912 int val
, rm
, shift
, shiftop
;
915 if (!(insn
& (1 << 25))) {
918 if (!(insn
& (1 << 23)))
921 tcg_gen_addi_i32(var
, var
, val
);
925 shift
= (insn
>> 7) & 0x1f;
926 shiftop
= (insn
>> 5) & 3;
927 offset
= load_reg(s
, rm
);
928 gen_arm_shift_im(offset
, shiftop
, shift
, 0);
929 if (!(insn
& (1 << 23)))
930 tcg_gen_sub_i32(var
, var
, offset
);
932 tcg_gen_add_i32(var
, var
, offset
);
933 tcg_temp_free_i32(offset
);
937 static inline void gen_add_datah_offset(DisasContext
*s
, unsigned int insn
,
938 int extra
, TCGv_i32 var
)
943 if (insn
& (1 << 22)) {
945 val
= (insn
& 0xf) | ((insn
>> 4) & 0xf0);
946 if (!(insn
& (1 << 23)))
950 tcg_gen_addi_i32(var
, var
, val
);
954 tcg_gen_addi_i32(var
, var
, extra
);
956 offset
= load_reg(s
, rm
);
957 if (!(insn
& (1 << 23)))
958 tcg_gen_sub_i32(var
, var
, offset
);
960 tcg_gen_add_i32(var
, var
, offset
);
961 tcg_temp_free_i32(offset
);
965 static TCGv_ptr
get_fpstatus_ptr(int neon
)
967 TCGv_ptr statusptr
= tcg_temp_new_ptr();
970 offset
= offsetof(CPUARMState
, vfp
.standard_fp_status
);
972 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
974 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
978 #define VFP_OP2(name) \
979 static inline void gen_vfp_##name(int dp) \
981 TCGv_ptr fpst = get_fpstatus_ptr(0); \
983 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, fpst); \
985 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, fpst); \
987 tcg_temp_free_ptr(fpst); \
997 static inline void gen_vfp_F1_mul(int dp
)
999 /* Like gen_vfp_mul() but put result in F1 */
1000 TCGv_ptr fpst
= get_fpstatus_ptr(0);
1002 gen_helper_vfp_muld(cpu_F1d
, cpu_F0d
, cpu_F1d
, fpst
);
1004 gen_helper_vfp_muls(cpu_F1s
, cpu_F0s
, cpu_F1s
, fpst
);
1006 tcg_temp_free_ptr(fpst
);
1009 static inline void gen_vfp_F1_neg(int dp
)
1011 /* Like gen_vfp_neg() but put result in F1 */
1013 gen_helper_vfp_negd(cpu_F1d
, cpu_F0d
);
1015 gen_helper_vfp_negs(cpu_F1s
, cpu_F0s
);
1019 static inline void gen_vfp_abs(int dp
)
1022 gen_helper_vfp_absd(cpu_F0d
, cpu_F0d
);
1024 gen_helper_vfp_abss(cpu_F0s
, cpu_F0s
);
1027 static inline void gen_vfp_neg(int dp
)
1030 gen_helper_vfp_negd(cpu_F0d
, cpu_F0d
);
1032 gen_helper_vfp_negs(cpu_F0s
, cpu_F0s
);
1035 static inline void gen_vfp_sqrt(int dp
)
1038 gen_helper_vfp_sqrtd(cpu_F0d
, cpu_F0d
, cpu_env
);
1040 gen_helper_vfp_sqrts(cpu_F0s
, cpu_F0s
, cpu_env
);
1043 static inline void gen_vfp_cmp(int dp
)
1046 gen_helper_vfp_cmpd(cpu_F0d
, cpu_F1d
, cpu_env
);
1048 gen_helper_vfp_cmps(cpu_F0s
, cpu_F1s
, cpu_env
);
1051 static inline void gen_vfp_cmpe(int dp
)
1054 gen_helper_vfp_cmped(cpu_F0d
, cpu_F1d
, cpu_env
);
1056 gen_helper_vfp_cmpes(cpu_F0s
, cpu_F1s
, cpu_env
);
1059 static inline void gen_vfp_F1_ld0(int dp
)
1062 tcg_gen_movi_i64(cpu_F1d
, 0);
1064 tcg_gen_movi_i32(cpu_F1s
, 0);
1067 #define VFP_GEN_ITOF(name) \
1068 static inline void gen_vfp_##name(int dp, int neon) \
1070 TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
1072 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0s, statusptr); \
1074 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, statusptr); \
1076 tcg_temp_free_ptr(statusptr); \
1083 #define VFP_GEN_FTOI(name) \
1084 static inline void gen_vfp_##name(int dp, int neon) \
1086 TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
1088 gen_helper_vfp_##name##d(cpu_F0s, cpu_F0d, statusptr); \
1090 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, statusptr); \
1092 tcg_temp_free_ptr(statusptr); \
1101 #define VFP_GEN_FIX(name, round) \
1102 static inline void gen_vfp_##name(int dp, int shift, int neon) \
1104 TCGv_i32 tmp_shift = tcg_const_i32(shift); \
1105 TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
1107 gen_helper_vfp_##name##d##round(cpu_F0d, cpu_F0d, tmp_shift, \
1110 gen_helper_vfp_##name##s##round(cpu_F0s, cpu_F0s, tmp_shift, \
1113 tcg_temp_free_i32(tmp_shift); \
1114 tcg_temp_free_ptr(statusptr); \
1116 VFP_GEN_FIX(tosh
, _round_to_zero
)
1117 VFP_GEN_FIX(tosl
, _round_to_zero
)
1118 VFP_GEN_FIX(touh
, _round_to_zero
)
1119 VFP_GEN_FIX(toul
, _round_to_zero
)
1126 static inline void gen_vfp_ld(DisasContext
*s
, int dp
, TCGv_i32 addr
)
1129 gen_aa32_ld64(cpu_F0d
, addr
, IS_USER(s
));
1131 gen_aa32_ld32u(cpu_F0s
, addr
, IS_USER(s
));
1135 static inline void gen_vfp_st(DisasContext
*s
, int dp
, TCGv_i32 addr
)
1138 gen_aa32_st64(cpu_F0d
, addr
, IS_USER(s
));
1140 gen_aa32_st32(cpu_F0s
, addr
, IS_USER(s
));
1145 vfp_reg_offset (int dp
, int reg
)
1148 return offsetof(CPUARMState
, vfp
.regs
[reg
]);
1150 return offsetof(CPUARMState
, vfp
.regs
[reg
>> 1])
1151 + offsetof(CPU_DoubleU
, l
.upper
);
1153 return offsetof(CPUARMState
, vfp
.regs
[reg
>> 1])
1154 + offsetof(CPU_DoubleU
, l
.lower
);
1158 /* Return the offset of a 32-bit piece of a NEON register.
1159 zero is the least significant end of the register. */
1161 neon_reg_offset (int reg
, int n
)
1165 return vfp_reg_offset(0, sreg
);
1168 static TCGv_i32
neon_load_reg(int reg
, int pass
)
1170 TCGv_i32 tmp
= tcg_temp_new_i32();
1171 tcg_gen_ld_i32(tmp
, cpu_env
, neon_reg_offset(reg
, pass
));
1175 static void neon_store_reg(int reg
, int pass
, TCGv_i32 var
)
1177 tcg_gen_st_i32(var
, cpu_env
, neon_reg_offset(reg
, pass
));
1178 tcg_temp_free_i32(var
);
1181 static inline void neon_load_reg64(TCGv_i64 var
, int reg
)
1183 tcg_gen_ld_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1186 static inline void neon_store_reg64(TCGv_i64 var
, int reg
)
1188 tcg_gen_st_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1191 #define tcg_gen_ld_f32 tcg_gen_ld_i32
1192 #define tcg_gen_ld_f64 tcg_gen_ld_i64
1193 #define tcg_gen_st_f32 tcg_gen_st_i32
1194 #define tcg_gen_st_f64 tcg_gen_st_i64
1196 static inline void gen_mov_F0_vreg(int dp
, int reg
)
1199 tcg_gen_ld_f64(cpu_F0d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1201 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1204 static inline void gen_mov_F1_vreg(int dp
, int reg
)
1207 tcg_gen_ld_f64(cpu_F1d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1209 tcg_gen_ld_f32(cpu_F1s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1212 static inline void gen_mov_vreg_F0(int dp
, int reg
)
1215 tcg_gen_st_f64(cpu_F0d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1217 tcg_gen_st_f32(cpu_F0s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1220 #define ARM_CP_RW_BIT (1 << 20)
1222 static inline void iwmmxt_load_reg(TCGv_i64 var
, int reg
)
1224 tcg_gen_ld_i64(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.regs
[reg
]));
1227 static inline void iwmmxt_store_reg(TCGv_i64 var
, int reg
)
1229 tcg_gen_st_i64(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.regs
[reg
]));
1232 static inline TCGv_i32
iwmmxt_load_creg(int reg
)
1234 TCGv_i32 var
= tcg_temp_new_i32();
1235 tcg_gen_ld_i32(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.cregs
[reg
]));
1239 static inline void iwmmxt_store_creg(int reg
, TCGv_i32 var
)
1241 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.cregs
[reg
]));
1242 tcg_temp_free_i32(var
);
1245 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn
)
1247 iwmmxt_store_reg(cpu_M0
, rn
);
1250 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn
)
1252 iwmmxt_load_reg(cpu_M0
, rn
);
1255 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn
)
1257 iwmmxt_load_reg(cpu_V1
, rn
);
1258 tcg_gen_or_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1261 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn
)
1263 iwmmxt_load_reg(cpu_V1
, rn
);
1264 tcg_gen_and_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1267 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn
)
1269 iwmmxt_load_reg(cpu_V1
, rn
);
1270 tcg_gen_xor_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1273 #define IWMMXT_OP(name) \
1274 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1276 iwmmxt_load_reg(cpu_V1, rn); \
1277 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1280 #define IWMMXT_OP_ENV(name) \
1281 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1283 iwmmxt_load_reg(cpu_V1, rn); \
1284 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1287 #define IWMMXT_OP_ENV_SIZE(name) \
1288 IWMMXT_OP_ENV(name##b) \
1289 IWMMXT_OP_ENV(name##w) \
1290 IWMMXT_OP_ENV(name##l)
1292 #define IWMMXT_OP_ENV1(name) \
1293 static inline void gen_op_iwmmxt_##name##_M0(void) \
1295 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1309 IWMMXT_OP_ENV_SIZE(unpackl
)
1310 IWMMXT_OP_ENV_SIZE(unpackh
)
1312 IWMMXT_OP_ENV1(unpacklub
)
1313 IWMMXT_OP_ENV1(unpackluw
)
1314 IWMMXT_OP_ENV1(unpacklul
)
1315 IWMMXT_OP_ENV1(unpackhub
)
1316 IWMMXT_OP_ENV1(unpackhuw
)
1317 IWMMXT_OP_ENV1(unpackhul
)
1318 IWMMXT_OP_ENV1(unpacklsb
)
1319 IWMMXT_OP_ENV1(unpacklsw
)
1320 IWMMXT_OP_ENV1(unpacklsl
)
1321 IWMMXT_OP_ENV1(unpackhsb
)
1322 IWMMXT_OP_ENV1(unpackhsw
)
1323 IWMMXT_OP_ENV1(unpackhsl
)
1325 IWMMXT_OP_ENV_SIZE(cmpeq
)
1326 IWMMXT_OP_ENV_SIZE(cmpgtu
)
1327 IWMMXT_OP_ENV_SIZE(cmpgts
)
1329 IWMMXT_OP_ENV_SIZE(mins
)
1330 IWMMXT_OP_ENV_SIZE(minu
)
1331 IWMMXT_OP_ENV_SIZE(maxs
)
1332 IWMMXT_OP_ENV_SIZE(maxu
)
1334 IWMMXT_OP_ENV_SIZE(subn
)
1335 IWMMXT_OP_ENV_SIZE(addn
)
1336 IWMMXT_OP_ENV_SIZE(subu
)
1337 IWMMXT_OP_ENV_SIZE(addu
)
1338 IWMMXT_OP_ENV_SIZE(subs
)
1339 IWMMXT_OP_ENV_SIZE(adds
)
1341 IWMMXT_OP_ENV(avgb0
)
1342 IWMMXT_OP_ENV(avgb1
)
1343 IWMMXT_OP_ENV(avgw0
)
1344 IWMMXT_OP_ENV(avgw1
)
1348 IWMMXT_OP_ENV(packuw
)
1349 IWMMXT_OP_ENV(packul
)
1350 IWMMXT_OP_ENV(packuq
)
1351 IWMMXT_OP_ENV(packsw
)
1352 IWMMXT_OP_ENV(packsl
)
1353 IWMMXT_OP_ENV(packsq
)
1355 static void gen_op_iwmmxt_set_mup(void)
1358 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1359 tcg_gen_ori_i32(tmp
, tmp
, 2);
1360 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1363 static void gen_op_iwmmxt_set_cup(void)
1366 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1367 tcg_gen_ori_i32(tmp
, tmp
, 1);
1368 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1371 static void gen_op_iwmmxt_setpsr_nz(void)
1373 TCGv_i32 tmp
= tcg_temp_new_i32();
1374 gen_helper_iwmmxt_setpsr_nz(tmp
, cpu_M0
);
1375 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCASF
]);
1378 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn
)
1380 iwmmxt_load_reg(cpu_V1
, rn
);
1381 tcg_gen_ext32u_i64(cpu_V1
, cpu_V1
);
1382 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1385 static inline int gen_iwmmxt_address(DisasContext
*s
, uint32_t insn
,
1392 rd
= (insn
>> 16) & 0xf;
1393 tmp
= load_reg(s
, rd
);
1395 offset
= (insn
& 0xff) << ((insn
>> 7) & 2);
1396 if (insn
& (1 << 24)) {
1398 if (insn
& (1 << 23))
1399 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1401 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1402 tcg_gen_mov_i32(dest
, tmp
);
1403 if (insn
& (1 << 21))
1404 store_reg(s
, rd
, tmp
);
1406 tcg_temp_free_i32(tmp
);
1407 } else if (insn
& (1 << 21)) {
1409 tcg_gen_mov_i32(dest
, tmp
);
1410 if (insn
& (1 << 23))
1411 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1413 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1414 store_reg(s
, rd
, tmp
);
1415 } else if (!(insn
& (1 << 23)))
1420 static inline int gen_iwmmxt_shift(uint32_t insn
, uint32_t mask
, TCGv_i32 dest
)
1422 int rd
= (insn
>> 0) & 0xf;
1425 if (insn
& (1 << 8)) {
1426 if (rd
< ARM_IWMMXT_wCGR0
|| rd
> ARM_IWMMXT_wCGR3
) {
1429 tmp
= iwmmxt_load_creg(rd
);
1432 tmp
= tcg_temp_new_i32();
1433 iwmmxt_load_reg(cpu_V0
, rd
);
1434 tcg_gen_trunc_i64_i32(tmp
, cpu_V0
);
1436 tcg_gen_andi_i32(tmp
, tmp
, mask
);
1437 tcg_gen_mov_i32(dest
, tmp
);
1438 tcg_temp_free_i32(tmp
);
1442 /* Disassemble an iwMMXt instruction. Returns nonzero if an error occurred
1443 (ie. an undefined instruction). */
1444 static int disas_iwmmxt_insn(CPUARMState
*env
, DisasContext
*s
, uint32_t insn
)
1447 int rdhi
, rdlo
, rd0
, rd1
, i
;
1449 TCGv_i32 tmp
, tmp2
, tmp3
;
1451 if ((insn
& 0x0e000e00) == 0x0c000000) {
1452 if ((insn
& 0x0fe00ff0) == 0x0c400000) {
1454 rdlo
= (insn
>> 12) & 0xf;
1455 rdhi
= (insn
>> 16) & 0xf;
1456 if (insn
& ARM_CP_RW_BIT
) { /* TMRRC */
1457 iwmmxt_load_reg(cpu_V0
, wrd
);
1458 tcg_gen_trunc_i64_i32(cpu_R
[rdlo
], cpu_V0
);
1459 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
1460 tcg_gen_trunc_i64_i32(cpu_R
[rdhi
], cpu_V0
);
1461 } else { /* TMCRR */
1462 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
1463 iwmmxt_store_reg(cpu_V0
, wrd
);
1464 gen_op_iwmmxt_set_mup();
1469 wrd
= (insn
>> 12) & 0xf;
1470 addr
= tcg_temp_new_i32();
1471 if (gen_iwmmxt_address(s
, insn
, addr
)) {
1472 tcg_temp_free_i32(addr
);
1475 if (insn
& ARM_CP_RW_BIT
) {
1476 if ((insn
>> 28) == 0xf) { /* WLDRW wCx */
1477 tmp
= tcg_temp_new_i32();
1478 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
1479 iwmmxt_store_creg(wrd
, tmp
);
1482 if (insn
& (1 << 8)) {
1483 if (insn
& (1 << 22)) { /* WLDRD */
1484 gen_aa32_ld64(cpu_M0
, addr
, IS_USER(s
));
1486 } else { /* WLDRW wRd */
1487 tmp
= tcg_temp_new_i32();
1488 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
1491 tmp
= tcg_temp_new_i32();
1492 if (insn
& (1 << 22)) { /* WLDRH */
1493 gen_aa32_ld16u(tmp
, addr
, IS_USER(s
));
1494 } else { /* WLDRB */
1495 gen_aa32_ld8u(tmp
, addr
, IS_USER(s
));
1499 tcg_gen_extu_i32_i64(cpu_M0
, tmp
);
1500 tcg_temp_free_i32(tmp
);
1502 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1505 if ((insn
>> 28) == 0xf) { /* WSTRW wCx */
1506 tmp
= iwmmxt_load_creg(wrd
);
1507 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
1509 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1510 tmp
= tcg_temp_new_i32();
1511 if (insn
& (1 << 8)) {
1512 if (insn
& (1 << 22)) { /* WSTRD */
1513 gen_aa32_st64(cpu_M0
, addr
, IS_USER(s
));
1514 } else { /* WSTRW wRd */
1515 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1516 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
1519 if (insn
& (1 << 22)) { /* WSTRH */
1520 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1521 gen_aa32_st16(tmp
, addr
, IS_USER(s
));
1522 } else { /* WSTRB */
1523 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1524 gen_aa32_st8(tmp
, addr
, IS_USER(s
));
1528 tcg_temp_free_i32(tmp
);
1530 tcg_temp_free_i32(addr
);
1534 if ((insn
& 0x0f000000) != 0x0e000000)
1537 switch (((insn
>> 12) & 0xf00) | ((insn
>> 4) & 0xff)) {
1538 case 0x000: /* WOR */
1539 wrd
= (insn
>> 12) & 0xf;
1540 rd0
= (insn
>> 0) & 0xf;
1541 rd1
= (insn
>> 16) & 0xf;
1542 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1543 gen_op_iwmmxt_orq_M0_wRn(rd1
);
1544 gen_op_iwmmxt_setpsr_nz();
1545 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1546 gen_op_iwmmxt_set_mup();
1547 gen_op_iwmmxt_set_cup();
1549 case 0x011: /* TMCR */
1552 rd
= (insn
>> 12) & 0xf;
1553 wrd
= (insn
>> 16) & 0xf;
1555 case ARM_IWMMXT_wCID
:
1556 case ARM_IWMMXT_wCASF
:
1558 case ARM_IWMMXT_wCon
:
1559 gen_op_iwmmxt_set_cup();
1561 case ARM_IWMMXT_wCSSF
:
1562 tmp
= iwmmxt_load_creg(wrd
);
1563 tmp2
= load_reg(s
, rd
);
1564 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
1565 tcg_temp_free_i32(tmp2
);
1566 iwmmxt_store_creg(wrd
, tmp
);
1568 case ARM_IWMMXT_wCGR0
:
1569 case ARM_IWMMXT_wCGR1
:
1570 case ARM_IWMMXT_wCGR2
:
1571 case ARM_IWMMXT_wCGR3
:
1572 gen_op_iwmmxt_set_cup();
1573 tmp
= load_reg(s
, rd
);
1574 iwmmxt_store_creg(wrd
, tmp
);
1580 case 0x100: /* WXOR */
1581 wrd
= (insn
>> 12) & 0xf;
1582 rd0
= (insn
>> 0) & 0xf;
1583 rd1
= (insn
>> 16) & 0xf;
1584 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1585 gen_op_iwmmxt_xorq_M0_wRn(rd1
);
1586 gen_op_iwmmxt_setpsr_nz();
1587 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1588 gen_op_iwmmxt_set_mup();
1589 gen_op_iwmmxt_set_cup();
1591 case 0x111: /* TMRC */
1594 rd
= (insn
>> 12) & 0xf;
1595 wrd
= (insn
>> 16) & 0xf;
1596 tmp
= iwmmxt_load_creg(wrd
);
1597 store_reg(s
, rd
, tmp
);
1599 case 0x300: /* WANDN */
1600 wrd
= (insn
>> 12) & 0xf;
1601 rd0
= (insn
>> 0) & 0xf;
1602 rd1
= (insn
>> 16) & 0xf;
1603 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1604 tcg_gen_neg_i64(cpu_M0
, cpu_M0
);
1605 gen_op_iwmmxt_andq_M0_wRn(rd1
);
1606 gen_op_iwmmxt_setpsr_nz();
1607 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1608 gen_op_iwmmxt_set_mup();
1609 gen_op_iwmmxt_set_cup();
1611 case 0x200: /* WAND */
1612 wrd
= (insn
>> 12) & 0xf;
1613 rd0
= (insn
>> 0) & 0xf;
1614 rd1
= (insn
>> 16) & 0xf;
1615 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1616 gen_op_iwmmxt_andq_M0_wRn(rd1
);
1617 gen_op_iwmmxt_setpsr_nz();
1618 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1619 gen_op_iwmmxt_set_mup();
1620 gen_op_iwmmxt_set_cup();
1622 case 0x810: case 0xa10: /* WMADD */
1623 wrd
= (insn
>> 12) & 0xf;
1624 rd0
= (insn
>> 0) & 0xf;
1625 rd1
= (insn
>> 16) & 0xf;
1626 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1627 if (insn
& (1 << 21))
1628 gen_op_iwmmxt_maddsq_M0_wRn(rd1
);
1630 gen_op_iwmmxt_madduq_M0_wRn(rd1
);
1631 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1632 gen_op_iwmmxt_set_mup();
1634 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1635 wrd
= (insn
>> 12) & 0xf;
1636 rd0
= (insn
>> 16) & 0xf;
1637 rd1
= (insn
>> 0) & 0xf;
1638 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1639 switch ((insn
>> 22) & 3) {
1641 gen_op_iwmmxt_unpacklb_M0_wRn(rd1
);
1644 gen_op_iwmmxt_unpacklw_M0_wRn(rd1
);
1647 gen_op_iwmmxt_unpackll_M0_wRn(rd1
);
1652 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1653 gen_op_iwmmxt_set_mup();
1654 gen_op_iwmmxt_set_cup();
1656 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1657 wrd
= (insn
>> 12) & 0xf;
1658 rd0
= (insn
>> 16) & 0xf;
1659 rd1
= (insn
>> 0) & 0xf;
1660 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1661 switch ((insn
>> 22) & 3) {
1663 gen_op_iwmmxt_unpackhb_M0_wRn(rd1
);
1666 gen_op_iwmmxt_unpackhw_M0_wRn(rd1
);
1669 gen_op_iwmmxt_unpackhl_M0_wRn(rd1
);
1674 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1675 gen_op_iwmmxt_set_mup();
1676 gen_op_iwmmxt_set_cup();
1678 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1679 wrd
= (insn
>> 12) & 0xf;
1680 rd0
= (insn
>> 16) & 0xf;
1681 rd1
= (insn
>> 0) & 0xf;
1682 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1683 if (insn
& (1 << 22))
1684 gen_op_iwmmxt_sadw_M0_wRn(rd1
);
1686 gen_op_iwmmxt_sadb_M0_wRn(rd1
);
1687 if (!(insn
& (1 << 20)))
1688 gen_op_iwmmxt_addl_M0_wRn(wrd
);
1689 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1690 gen_op_iwmmxt_set_mup();
1692 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1693 wrd
= (insn
>> 12) & 0xf;
1694 rd0
= (insn
>> 16) & 0xf;
1695 rd1
= (insn
>> 0) & 0xf;
1696 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1697 if (insn
& (1 << 21)) {
1698 if (insn
& (1 << 20))
1699 gen_op_iwmmxt_mulshw_M0_wRn(rd1
);
1701 gen_op_iwmmxt_mulslw_M0_wRn(rd1
);
1703 if (insn
& (1 << 20))
1704 gen_op_iwmmxt_muluhw_M0_wRn(rd1
);
1706 gen_op_iwmmxt_mululw_M0_wRn(rd1
);
1708 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1709 gen_op_iwmmxt_set_mup();
1711 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1712 wrd
= (insn
>> 12) & 0xf;
1713 rd0
= (insn
>> 16) & 0xf;
1714 rd1
= (insn
>> 0) & 0xf;
1715 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1716 if (insn
& (1 << 21))
1717 gen_op_iwmmxt_macsw_M0_wRn(rd1
);
1719 gen_op_iwmmxt_macuw_M0_wRn(rd1
);
1720 if (!(insn
& (1 << 20))) {
1721 iwmmxt_load_reg(cpu_V1
, wrd
);
1722 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1724 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1725 gen_op_iwmmxt_set_mup();
1727 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1728 wrd
= (insn
>> 12) & 0xf;
1729 rd0
= (insn
>> 16) & 0xf;
1730 rd1
= (insn
>> 0) & 0xf;
1731 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1732 switch ((insn
>> 22) & 3) {
1734 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1
);
1737 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1
);
1740 gen_op_iwmmxt_cmpeql_M0_wRn(rd1
);
1745 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1746 gen_op_iwmmxt_set_mup();
1747 gen_op_iwmmxt_set_cup();
1749 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1750 wrd
= (insn
>> 12) & 0xf;
1751 rd0
= (insn
>> 16) & 0xf;
1752 rd1
= (insn
>> 0) & 0xf;
1753 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1754 if (insn
& (1 << 22)) {
1755 if (insn
& (1 << 20))
1756 gen_op_iwmmxt_avgw1_M0_wRn(rd1
);
1758 gen_op_iwmmxt_avgw0_M0_wRn(rd1
);
1760 if (insn
& (1 << 20))
1761 gen_op_iwmmxt_avgb1_M0_wRn(rd1
);
1763 gen_op_iwmmxt_avgb0_M0_wRn(rd1
);
1765 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1766 gen_op_iwmmxt_set_mup();
1767 gen_op_iwmmxt_set_cup();
1769 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1770 wrd
= (insn
>> 12) & 0xf;
1771 rd0
= (insn
>> 16) & 0xf;
1772 rd1
= (insn
>> 0) & 0xf;
1773 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1774 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCGR0
+ ((insn
>> 20) & 3));
1775 tcg_gen_andi_i32(tmp
, tmp
, 7);
1776 iwmmxt_load_reg(cpu_V1
, rd1
);
1777 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
1778 tcg_temp_free_i32(tmp
);
1779 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1780 gen_op_iwmmxt_set_mup();
1782 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
1783 if (((insn
>> 6) & 3) == 3)
1785 rd
= (insn
>> 12) & 0xf;
1786 wrd
= (insn
>> 16) & 0xf;
1787 tmp
= load_reg(s
, rd
);
1788 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1789 switch ((insn
>> 6) & 3) {
1791 tmp2
= tcg_const_i32(0xff);
1792 tmp3
= tcg_const_i32((insn
& 7) << 3);
1795 tmp2
= tcg_const_i32(0xffff);
1796 tmp3
= tcg_const_i32((insn
& 3) << 4);
1799 tmp2
= tcg_const_i32(0xffffffff);
1800 tmp3
= tcg_const_i32((insn
& 1) << 5);
1803 TCGV_UNUSED_I32(tmp2
);
1804 TCGV_UNUSED_I32(tmp3
);
1806 gen_helper_iwmmxt_insr(cpu_M0
, cpu_M0
, tmp
, tmp2
, tmp3
);
1807 tcg_temp_free_i32(tmp3
);
1808 tcg_temp_free_i32(tmp2
);
1809 tcg_temp_free_i32(tmp
);
1810 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1811 gen_op_iwmmxt_set_mup();
1813 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1814 rd
= (insn
>> 12) & 0xf;
1815 wrd
= (insn
>> 16) & 0xf;
1816 if (rd
== 15 || ((insn
>> 22) & 3) == 3)
1818 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1819 tmp
= tcg_temp_new_i32();
1820 switch ((insn
>> 22) & 3) {
1822 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 7) << 3);
1823 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1825 tcg_gen_ext8s_i32(tmp
, tmp
);
1827 tcg_gen_andi_i32(tmp
, tmp
, 0xff);
1831 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 3) << 4);
1832 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1834 tcg_gen_ext16s_i32(tmp
, tmp
);
1836 tcg_gen_andi_i32(tmp
, tmp
, 0xffff);
1840 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 1) << 5);
1841 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1844 store_reg(s
, rd
, tmp
);
1846 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
1847 if ((insn
& 0x000ff008) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
1849 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
1850 switch ((insn
>> 22) & 3) {
1852 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 7) << 2) + 0);
1855 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 3) << 3) + 4);
1858 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 1) << 4) + 12);
1861 tcg_gen_shli_i32(tmp
, tmp
, 28);
1863 tcg_temp_free_i32(tmp
);
1865 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
1866 if (((insn
>> 6) & 3) == 3)
1868 rd
= (insn
>> 12) & 0xf;
1869 wrd
= (insn
>> 16) & 0xf;
1870 tmp
= load_reg(s
, rd
);
1871 switch ((insn
>> 6) & 3) {
1873 gen_helper_iwmmxt_bcstb(cpu_M0
, tmp
);
1876 gen_helper_iwmmxt_bcstw(cpu_M0
, tmp
);
1879 gen_helper_iwmmxt_bcstl(cpu_M0
, tmp
);
1882 tcg_temp_free_i32(tmp
);
1883 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1884 gen_op_iwmmxt_set_mup();
1886 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
1887 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
1889 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
1890 tmp2
= tcg_temp_new_i32();
1891 tcg_gen_mov_i32(tmp2
, tmp
);
1892 switch ((insn
>> 22) & 3) {
1894 for (i
= 0; i
< 7; i
++) {
1895 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
1896 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1900 for (i
= 0; i
< 3; i
++) {
1901 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
1902 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1906 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
1907 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1911 tcg_temp_free_i32(tmp2
);
1912 tcg_temp_free_i32(tmp
);
1914 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1915 wrd
= (insn
>> 12) & 0xf;
1916 rd0
= (insn
>> 16) & 0xf;
1917 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1918 switch ((insn
>> 22) & 3) {
1920 gen_helper_iwmmxt_addcb(cpu_M0
, cpu_M0
);
1923 gen_helper_iwmmxt_addcw(cpu_M0
, cpu_M0
);
1926 gen_helper_iwmmxt_addcl(cpu_M0
, cpu_M0
);
1931 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1932 gen_op_iwmmxt_set_mup();
1934 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
1935 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
1937 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
1938 tmp2
= tcg_temp_new_i32();
1939 tcg_gen_mov_i32(tmp2
, tmp
);
1940 switch ((insn
>> 22) & 3) {
1942 for (i
= 0; i
< 7; i
++) {
1943 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
1944 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1948 for (i
= 0; i
< 3; i
++) {
1949 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
1950 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1954 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
1955 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1959 tcg_temp_free_i32(tmp2
);
1960 tcg_temp_free_i32(tmp
);
1962 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1963 rd
= (insn
>> 12) & 0xf;
1964 rd0
= (insn
>> 16) & 0xf;
1965 if ((insn
& 0xf) != 0 || ((insn
>> 22) & 3) == 3)
1967 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1968 tmp
= tcg_temp_new_i32();
1969 switch ((insn
>> 22) & 3) {
1971 gen_helper_iwmmxt_msbb(tmp
, cpu_M0
);
1974 gen_helper_iwmmxt_msbw(tmp
, cpu_M0
);
1977 gen_helper_iwmmxt_msbl(tmp
, cpu_M0
);
1980 store_reg(s
, rd
, tmp
);
1982 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1983 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1984 wrd
= (insn
>> 12) & 0xf;
1985 rd0
= (insn
>> 16) & 0xf;
1986 rd1
= (insn
>> 0) & 0xf;
1987 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1988 switch ((insn
>> 22) & 3) {
1990 if (insn
& (1 << 21))
1991 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1
);
1993 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1
);
1996 if (insn
& (1 << 21))
1997 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1
);
1999 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1
);
2002 if (insn
& (1 << 21))
2003 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1
);
2005 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1
);
2010 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2011 gen_op_iwmmxt_set_mup();
2012 gen_op_iwmmxt_set_cup();
2014 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
2015 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
2016 wrd
= (insn
>> 12) & 0xf;
2017 rd0
= (insn
>> 16) & 0xf;
2018 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2019 switch ((insn
>> 22) & 3) {
2021 if (insn
& (1 << 21))
2022 gen_op_iwmmxt_unpacklsb_M0();
2024 gen_op_iwmmxt_unpacklub_M0();
2027 if (insn
& (1 << 21))
2028 gen_op_iwmmxt_unpacklsw_M0();
2030 gen_op_iwmmxt_unpackluw_M0();
2033 if (insn
& (1 << 21))
2034 gen_op_iwmmxt_unpacklsl_M0();
2036 gen_op_iwmmxt_unpacklul_M0();
2041 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2042 gen_op_iwmmxt_set_mup();
2043 gen_op_iwmmxt_set_cup();
2045 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
2046 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
2047 wrd
= (insn
>> 12) & 0xf;
2048 rd0
= (insn
>> 16) & 0xf;
2049 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2050 switch ((insn
>> 22) & 3) {
2052 if (insn
& (1 << 21))
2053 gen_op_iwmmxt_unpackhsb_M0();
2055 gen_op_iwmmxt_unpackhub_M0();
2058 if (insn
& (1 << 21))
2059 gen_op_iwmmxt_unpackhsw_M0();
2061 gen_op_iwmmxt_unpackhuw_M0();
2064 if (insn
& (1 << 21))
2065 gen_op_iwmmxt_unpackhsl_M0();
2067 gen_op_iwmmxt_unpackhul_M0();
2072 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2073 gen_op_iwmmxt_set_mup();
2074 gen_op_iwmmxt_set_cup();
2076 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
2077 case 0x214: case 0x614: case 0xa14: case 0xe14:
2078 if (((insn
>> 22) & 3) == 0)
2080 wrd
= (insn
>> 12) & 0xf;
2081 rd0
= (insn
>> 16) & 0xf;
2082 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2083 tmp
= tcg_temp_new_i32();
2084 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2085 tcg_temp_free_i32(tmp
);
2088 switch ((insn
>> 22) & 3) {
2090 gen_helper_iwmmxt_srlw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2093 gen_helper_iwmmxt_srll(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2096 gen_helper_iwmmxt_srlq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2099 tcg_temp_free_i32(tmp
);
2100 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2101 gen_op_iwmmxt_set_mup();
2102 gen_op_iwmmxt_set_cup();
2104 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
2105 case 0x014: case 0x414: case 0x814: case 0xc14:
2106 if (((insn
>> 22) & 3) == 0)
2108 wrd
= (insn
>> 12) & 0xf;
2109 rd0
= (insn
>> 16) & 0xf;
2110 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2111 tmp
= tcg_temp_new_i32();
2112 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2113 tcg_temp_free_i32(tmp
);
2116 switch ((insn
>> 22) & 3) {
2118 gen_helper_iwmmxt_sraw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2121 gen_helper_iwmmxt_sral(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2124 gen_helper_iwmmxt_sraq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2127 tcg_temp_free_i32(tmp
);
2128 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2129 gen_op_iwmmxt_set_mup();
2130 gen_op_iwmmxt_set_cup();
2132 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2133 case 0x114: case 0x514: case 0x914: case 0xd14:
2134 if (((insn
>> 22) & 3) == 0)
2136 wrd
= (insn
>> 12) & 0xf;
2137 rd0
= (insn
>> 16) & 0xf;
2138 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2139 tmp
= tcg_temp_new_i32();
2140 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2141 tcg_temp_free_i32(tmp
);
2144 switch ((insn
>> 22) & 3) {
2146 gen_helper_iwmmxt_sllw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2149 gen_helper_iwmmxt_slll(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2152 gen_helper_iwmmxt_sllq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2155 tcg_temp_free_i32(tmp
);
2156 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2157 gen_op_iwmmxt_set_mup();
2158 gen_op_iwmmxt_set_cup();
2160 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2161 case 0x314: case 0x714: case 0xb14: case 0xf14:
2162 if (((insn
>> 22) & 3) == 0)
2164 wrd
= (insn
>> 12) & 0xf;
2165 rd0
= (insn
>> 16) & 0xf;
2166 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2167 tmp
= tcg_temp_new_i32();
2168 switch ((insn
>> 22) & 3) {
2170 if (gen_iwmmxt_shift(insn
, 0xf, tmp
)) {
2171 tcg_temp_free_i32(tmp
);
2174 gen_helper_iwmmxt_rorw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2177 if (gen_iwmmxt_shift(insn
, 0x1f, tmp
)) {
2178 tcg_temp_free_i32(tmp
);
2181 gen_helper_iwmmxt_rorl(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2184 if (gen_iwmmxt_shift(insn
, 0x3f, tmp
)) {
2185 tcg_temp_free_i32(tmp
);
2188 gen_helper_iwmmxt_rorq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2191 tcg_temp_free_i32(tmp
);
2192 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2193 gen_op_iwmmxt_set_mup();
2194 gen_op_iwmmxt_set_cup();
2196 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2197 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2198 wrd
= (insn
>> 12) & 0xf;
2199 rd0
= (insn
>> 16) & 0xf;
2200 rd1
= (insn
>> 0) & 0xf;
2201 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2202 switch ((insn
>> 22) & 3) {
2204 if (insn
& (1 << 21))
2205 gen_op_iwmmxt_minsb_M0_wRn(rd1
);
2207 gen_op_iwmmxt_minub_M0_wRn(rd1
);
2210 if (insn
& (1 << 21))
2211 gen_op_iwmmxt_minsw_M0_wRn(rd1
);
2213 gen_op_iwmmxt_minuw_M0_wRn(rd1
);
2216 if (insn
& (1 << 21))
2217 gen_op_iwmmxt_minsl_M0_wRn(rd1
);
2219 gen_op_iwmmxt_minul_M0_wRn(rd1
);
2224 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2225 gen_op_iwmmxt_set_mup();
2227 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2228 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2229 wrd
= (insn
>> 12) & 0xf;
2230 rd0
= (insn
>> 16) & 0xf;
2231 rd1
= (insn
>> 0) & 0xf;
2232 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2233 switch ((insn
>> 22) & 3) {
2235 if (insn
& (1 << 21))
2236 gen_op_iwmmxt_maxsb_M0_wRn(rd1
);
2238 gen_op_iwmmxt_maxub_M0_wRn(rd1
);
2241 if (insn
& (1 << 21))
2242 gen_op_iwmmxt_maxsw_M0_wRn(rd1
);
2244 gen_op_iwmmxt_maxuw_M0_wRn(rd1
);
2247 if (insn
& (1 << 21))
2248 gen_op_iwmmxt_maxsl_M0_wRn(rd1
);
2250 gen_op_iwmmxt_maxul_M0_wRn(rd1
);
2255 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2256 gen_op_iwmmxt_set_mup();
2258 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2259 case 0x402: case 0x502: case 0x602: case 0x702:
2260 wrd
= (insn
>> 12) & 0xf;
2261 rd0
= (insn
>> 16) & 0xf;
2262 rd1
= (insn
>> 0) & 0xf;
2263 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2264 tmp
= tcg_const_i32((insn
>> 20) & 3);
2265 iwmmxt_load_reg(cpu_V1
, rd1
);
2266 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
2267 tcg_temp_free_i32(tmp
);
2268 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2269 gen_op_iwmmxt_set_mup();
2271 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2272 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2273 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2274 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2275 wrd
= (insn
>> 12) & 0xf;
2276 rd0
= (insn
>> 16) & 0xf;
2277 rd1
= (insn
>> 0) & 0xf;
2278 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2279 switch ((insn
>> 20) & 0xf) {
2281 gen_op_iwmmxt_subnb_M0_wRn(rd1
);
2284 gen_op_iwmmxt_subub_M0_wRn(rd1
);
2287 gen_op_iwmmxt_subsb_M0_wRn(rd1
);
2290 gen_op_iwmmxt_subnw_M0_wRn(rd1
);
2293 gen_op_iwmmxt_subuw_M0_wRn(rd1
);
2296 gen_op_iwmmxt_subsw_M0_wRn(rd1
);
2299 gen_op_iwmmxt_subnl_M0_wRn(rd1
);
2302 gen_op_iwmmxt_subul_M0_wRn(rd1
);
2305 gen_op_iwmmxt_subsl_M0_wRn(rd1
);
2310 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2311 gen_op_iwmmxt_set_mup();
2312 gen_op_iwmmxt_set_cup();
2314 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2315 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2316 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2317 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2318 wrd
= (insn
>> 12) & 0xf;
2319 rd0
= (insn
>> 16) & 0xf;
2320 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2321 tmp
= tcg_const_i32(((insn
>> 16) & 0xf0) | (insn
& 0x0f));
2322 gen_helper_iwmmxt_shufh(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2323 tcg_temp_free_i32(tmp
);
2324 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2325 gen_op_iwmmxt_set_mup();
2326 gen_op_iwmmxt_set_cup();
2328 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2329 case 0x418: case 0x518: case 0x618: case 0x718:
2330 case 0x818: case 0x918: case 0xa18: case 0xb18:
2331 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2332 wrd
= (insn
>> 12) & 0xf;
2333 rd0
= (insn
>> 16) & 0xf;
2334 rd1
= (insn
>> 0) & 0xf;
2335 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2336 switch ((insn
>> 20) & 0xf) {
2338 gen_op_iwmmxt_addnb_M0_wRn(rd1
);
2341 gen_op_iwmmxt_addub_M0_wRn(rd1
);
2344 gen_op_iwmmxt_addsb_M0_wRn(rd1
);
2347 gen_op_iwmmxt_addnw_M0_wRn(rd1
);
2350 gen_op_iwmmxt_adduw_M0_wRn(rd1
);
2353 gen_op_iwmmxt_addsw_M0_wRn(rd1
);
2356 gen_op_iwmmxt_addnl_M0_wRn(rd1
);
2359 gen_op_iwmmxt_addul_M0_wRn(rd1
);
2362 gen_op_iwmmxt_addsl_M0_wRn(rd1
);
2367 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2368 gen_op_iwmmxt_set_mup();
2369 gen_op_iwmmxt_set_cup();
2371 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2372 case 0x408: case 0x508: case 0x608: case 0x708:
2373 case 0x808: case 0x908: case 0xa08: case 0xb08:
2374 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2375 if (!(insn
& (1 << 20)) || ((insn
>> 22) & 3) == 0)
2377 wrd
= (insn
>> 12) & 0xf;
2378 rd0
= (insn
>> 16) & 0xf;
2379 rd1
= (insn
>> 0) & 0xf;
2380 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2381 switch ((insn
>> 22) & 3) {
2383 if (insn
& (1 << 21))
2384 gen_op_iwmmxt_packsw_M0_wRn(rd1
);
2386 gen_op_iwmmxt_packuw_M0_wRn(rd1
);
2389 if (insn
& (1 << 21))
2390 gen_op_iwmmxt_packsl_M0_wRn(rd1
);
2392 gen_op_iwmmxt_packul_M0_wRn(rd1
);
2395 if (insn
& (1 << 21))
2396 gen_op_iwmmxt_packsq_M0_wRn(rd1
);
2398 gen_op_iwmmxt_packuq_M0_wRn(rd1
);
2401 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2402 gen_op_iwmmxt_set_mup();
2403 gen_op_iwmmxt_set_cup();
2405 case 0x201: case 0x203: case 0x205: case 0x207:
2406 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2407 case 0x211: case 0x213: case 0x215: case 0x217:
2408 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2409 wrd
= (insn
>> 5) & 0xf;
2410 rd0
= (insn
>> 12) & 0xf;
2411 rd1
= (insn
>> 0) & 0xf;
2412 if (rd0
== 0xf || rd1
== 0xf)
2414 gen_op_iwmmxt_movq_M0_wRn(wrd
);
2415 tmp
= load_reg(s
, rd0
);
2416 tmp2
= load_reg(s
, rd1
);
2417 switch ((insn
>> 16) & 0xf) {
2418 case 0x0: /* TMIA */
2419 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2421 case 0x8: /* TMIAPH */
2422 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2424 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2425 if (insn
& (1 << 16))
2426 tcg_gen_shri_i32(tmp
, tmp
, 16);
2427 if (insn
& (1 << 17))
2428 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2429 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2432 tcg_temp_free_i32(tmp2
);
2433 tcg_temp_free_i32(tmp
);
2436 tcg_temp_free_i32(tmp2
);
2437 tcg_temp_free_i32(tmp
);
2438 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2439 gen_op_iwmmxt_set_mup();
2448 /* Disassemble an XScale DSP instruction. Returns nonzero if an error occurred
2449 (ie. an undefined instruction). */
2450 static int disas_dsp_insn(CPUARMState
*env
, DisasContext
*s
, uint32_t insn
)
2452 int acc
, rd0
, rd1
, rdhi
, rdlo
;
2455 if ((insn
& 0x0ff00f10) == 0x0e200010) {
2456 /* Multiply with Internal Accumulate Format */
2457 rd0
= (insn
>> 12) & 0xf;
2459 acc
= (insn
>> 5) & 7;
2464 tmp
= load_reg(s
, rd0
);
2465 tmp2
= load_reg(s
, rd1
);
2466 switch ((insn
>> 16) & 0xf) {
2468 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2470 case 0x8: /* MIAPH */
2471 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2473 case 0xc: /* MIABB */
2474 case 0xd: /* MIABT */
2475 case 0xe: /* MIATB */
2476 case 0xf: /* MIATT */
2477 if (insn
& (1 << 16))
2478 tcg_gen_shri_i32(tmp
, tmp
, 16);
2479 if (insn
& (1 << 17))
2480 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2481 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2486 tcg_temp_free_i32(tmp2
);
2487 tcg_temp_free_i32(tmp
);
2489 gen_op_iwmmxt_movq_wRn_M0(acc
);
2493 if ((insn
& 0x0fe00ff8) == 0x0c400000) {
2494 /* Internal Accumulator Access Format */
2495 rdhi
= (insn
>> 16) & 0xf;
2496 rdlo
= (insn
>> 12) & 0xf;
2502 if (insn
& ARM_CP_RW_BIT
) { /* MRA */
2503 iwmmxt_load_reg(cpu_V0
, acc
);
2504 tcg_gen_trunc_i64_i32(cpu_R
[rdlo
], cpu_V0
);
2505 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
2506 tcg_gen_trunc_i64_i32(cpu_R
[rdhi
], cpu_V0
);
2507 tcg_gen_andi_i32(cpu_R
[rdhi
], cpu_R
[rdhi
], (1 << (40 - 32)) - 1);
2509 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
2510 iwmmxt_store_reg(cpu_V0
, acc
);
2518 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2519 #define VFP_SREG(insn, bigbit, smallbit) \
2520 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2521 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2522 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2523 reg = (((insn) >> (bigbit)) & 0x0f) \
2524 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2526 if (insn & (1 << (smallbit))) \
2528 reg = ((insn) >> (bigbit)) & 0x0f; \
2531 #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2532 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2533 #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2534 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2535 #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2536 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2538 /* Move between integer and VFP cores. */
2539 static TCGv_i32
gen_vfp_mrs(void)
2541 TCGv_i32 tmp
= tcg_temp_new_i32();
2542 tcg_gen_mov_i32(tmp
, cpu_F0s
);
2546 static void gen_vfp_msr(TCGv_i32 tmp
)
2548 tcg_gen_mov_i32(cpu_F0s
, tmp
);
2549 tcg_temp_free_i32(tmp
);
2552 static void gen_neon_dup_u8(TCGv_i32 var
, int shift
)
2554 TCGv_i32 tmp
= tcg_temp_new_i32();
2556 tcg_gen_shri_i32(var
, var
, shift
);
2557 tcg_gen_ext8u_i32(var
, var
);
2558 tcg_gen_shli_i32(tmp
, var
, 8);
2559 tcg_gen_or_i32(var
, var
, tmp
);
2560 tcg_gen_shli_i32(tmp
, var
, 16);
2561 tcg_gen_or_i32(var
, var
, tmp
);
2562 tcg_temp_free_i32(tmp
);
2565 static void gen_neon_dup_low16(TCGv_i32 var
)
2567 TCGv_i32 tmp
= tcg_temp_new_i32();
2568 tcg_gen_ext16u_i32(var
, var
);
2569 tcg_gen_shli_i32(tmp
, var
, 16);
2570 tcg_gen_or_i32(var
, var
, tmp
);
2571 tcg_temp_free_i32(tmp
);
2574 static void gen_neon_dup_high16(TCGv_i32 var
)
2576 TCGv_i32 tmp
= tcg_temp_new_i32();
2577 tcg_gen_andi_i32(var
, var
, 0xffff0000);
2578 tcg_gen_shri_i32(tmp
, var
, 16);
2579 tcg_gen_or_i32(var
, var
, tmp
);
2580 tcg_temp_free_i32(tmp
);
2583 static TCGv_i32
gen_load_and_replicate(DisasContext
*s
, TCGv_i32 addr
, int size
)
2585 /* Load a single Neon element and replicate into a 32 bit TCG reg */
2586 TCGv_i32 tmp
= tcg_temp_new_i32();
2589 gen_aa32_ld8u(tmp
, addr
, IS_USER(s
));
2590 gen_neon_dup_u8(tmp
, 0);
2593 gen_aa32_ld16u(tmp
, addr
, IS_USER(s
));
2594 gen_neon_dup_low16(tmp
);
2597 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
2599 default: /* Avoid compiler warnings. */
2605 static int handle_vsel(uint32_t insn
, uint32_t rd
, uint32_t rn
, uint32_t rm
,
2608 uint32_t cc
= extract32(insn
, 20, 2);
2611 TCGv_i64 frn
, frm
, dest
;
2612 TCGv_i64 tmp
, zero
, zf
, nf
, vf
;
2614 zero
= tcg_const_i64(0);
2616 frn
= tcg_temp_new_i64();
2617 frm
= tcg_temp_new_i64();
2618 dest
= tcg_temp_new_i64();
2620 zf
= tcg_temp_new_i64();
2621 nf
= tcg_temp_new_i64();
2622 vf
= tcg_temp_new_i64();
2624 tcg_gen_extu_i32_i64(zf
, cpu_ZF
);
2625 tcg_gen_ext_i32_i64(nf
, cpu_NF
);
2626 tcg_gen_ext_i32_i64(vf
, cpu_VF
);
2628 tcg_gen_ld_f64(frn
, cpu_env
, vfp_reg_offset(dp
, rn
));
2629 tcg_gen_ld_f64(frm
, cpu_env
, vfp_reg_offset(dp
, rm
));
2632 tcg_gen_movcond_i64(TCG_COND_EQ
, dest
, zf
, zero
,
2636 tcg_gen_movcond_i64(TCG_COND_LT
, dest
, vf
, zero
,
2639 case 2: /* ge: N == V -> N ^ V == 0 */
2640 tmp
= tcg_temp_new_i64();
2641 tcg_gen_xor_i64(tmp
, vf
, nf
);
2642 tcg_gen_movcond_i64(TCG_COND_GE
, dest
, tmp
, zero
,
2644 tcg_temp_free_i64(tmp
);
2646 case 3: /* gt: !Z && N == V */
2647 tcg_gen_movcond_i64(TCG_COND_NE
, dest
, zf
, zero
,
2649 tmp
= tcg_temp_new_i64();
2650 tcg_gen_xor_i64(tmp
, vf
, nf
);
2651 tcg_gen_movcond_i64(TCG_COND_GE
, dest
, tmp
, zero
,
2653 tcg_temp_free_i64(tmp
);
2656 tcg_gen_st_f64(dest
, cpu_env
, vfp_reg_offset(dp
, rd
));
2657 tcg_temp_free_i64(frn
);
2658 tcg_temp_free_i64(frm
);
2659 tcg_temp_free_i64(dest
);
2661 tcg_temp_free_i64(zf
);
2662 tcg_temp_free_i64(nf
);
2663 tcg_temp_free_i64(vf
);
2665 tcg_temp_free_i64(zero
);
2667 TCGv_i32 frn
, frm
, dest
;
2670 zero
= tcg_const_i32(0);
2672 frn
= tcg_temp_new_i32();
2673 frm
= tcg_temp_new_i32();
2674 dest
= tcg_temp_new_i32();
2675 tcg_gen_ld_f32(frn
, cpu_env
, vfp_reg_offset(dp
, rn
));
2676 tcg_gen_ld_f32(frm
, cpu_env
, vfp_reg_offset(dp
, rm
));
2679 tcg_gen_movcond_i32(TCG_COND_EQ
, dest
, cpu_ZF
, zero
,
2683 tcg_gen_movcond_i32(TCG_COND_LT
, dest
, cpu_VF
, zero
,
2686 case 2: /* ge: N == V -> N ^ V == 0 */
2687 tmp
= tcg_temp_new_i32();
2688 tcg_gen_xor_i32(tmp
, cpu_VF
, cpu_NF
);
2689 tcg_gen_movcond_i32(TCG_COND_GE
, dest
, tmp
, zero
,
2691 tcg_temp_free_i32(tmp
);
2693 case 3: /* gt: !Z && N == V */
2694 tcg_gen_movcond_i32(TCG_COND_NE
, dest
, cpu_ZF
, zero
,
2696 tmp
= tcg_temp_new_i32();
2697 tcg_gen_xor_i32(tmp
, cpu_VF
, cpu_NF
);
2698 tcg_gen_movcond_i32(TCG_COND_GE
, dest
, tmp
, zero
,
2700 tcg_temp_free_i32(tmp
);
2703 tcg_gen_st_f32(dest
, cpu_env
, vfp_reg_offset(dp
, rd
));
2704 tcg_temp_free_i32(frn
);
2705 tcg_temp_free_i32(frm
);
2706 tcg_temp_free_i32(dest
);
2708 tcg_temp_free_i32(zero
);
2714 static int handle_vminmaxnm(uint32_t insn
, uint32_t rd
, uint32_t rn
,
2715 uint32_t rm
, uint32_t dp
)
2717 uint32_t vmin
= extract32(insn
, 6, 1);
2718 TCGv_ptr fpst
= get_fpstatus_ptr(0);
2721 TCGv_i64 frn
, frm
, dest
;
2723 frn
= tcg_temp_new_i64();
2724 frm
= tcg_temp_new_i64();
2725 dest
= tcg_temp_new_i64();
2727 tcg_gen_ld_f64(frn
, cpu_env
, vfp_reg_offset(dp
, rn
));
2728 tcg_gen_ld_f64(frm
, cpu_env
, vfp_reg_offset(dp
, rm
));
2730 gen_helper_vfp_minnumd(dest
, frn
, frm
, fpst
);
2732 gen_helper_vfp_maxnumd(dest
, frn
, frm
, fpst
);
2734 tcg_gen_st_f64(dest
, cpu_env
, vfp_reg_offset(dp
, rd
));
2735 tcg_temp_free_i64(frn
);
2736 tcg_temp_free_i64(frm
);
2737 tcg_temp_free_i64(dest
);
2739 TCGv_i32 frn
, frm
, dest
;
2741 frn
= tcg_temp_new_i32();
2742 frm
= tcg_temp_new_i32();
2743 dest
= tcg_temp_new_i32();
2745 tcg_gen_ld_f32(frn
, cpu_env
, vfp_reg_offset(dp
, rn
));
2746 tcg_gen_ld_f32(frm
, cpu_env
, vfp_reg_offset(dp
, rm
));
2748 gen_helper_vfp_minnums(dest
, frn
, frm
, fpst
);
2750 gen_helper_vfp_maxnums(dest
, frn
, frm
, fpst
);
2752 tcg_gen_st_f32(dest
, cpu_env
, vfp_reg_offset(dp
, rd
));
2753 tcg_temp_free_i32(frn
);
2754 tcg_temp_free_i32(frm
);
2755 tcg_temp_free_i32(dest
);
2758 tcg_temp_free_ptr(fpst
);
2762 static int handle_vrint(uint32_t insn
, uint32_t rd
, uint32_t rm
, uint32_t dp
,
2765 TCGv_ptr fpst
= get_fpstatus_ptr(0);
2768 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rounding
));
2769 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
2774 tcg_op
= tcg_temp_new_i64();
2775 tcg_res
= tcg_temp_new_i64();
2776 tcg_gen_ld_f64(tcg_op
, cpu_env
, vfp_reg_offset(dp
, rm
));
2777 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
2778 tcg_gen_st_f64(tcg_res
, cpu_env
, vfp_reg_offset(dp
, rd
));
2779 tcg_temp_free_i64(tcg_op
);
2780 tcg_temp_free_i64(tcg_res
);
2784 tcg_op
= tcg_temp_new_i32();
2785 tcg_res
= tcg_temp_new_i32();
2786 tcg_gen_ld_f32(tcg_op
, cpu_env
, vfp_reg_offset(dp
, rm
));
2787 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
2788 tcg_gen_st_f32(tcg_res
, cpu_env
, vfp_reg_offset(dp
, rd
));
2789 tcg_temp_free_i32(tcg_op
);
2790 tcg_temp_free_i32(tcg_res
);
2793 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
2794 tcg_temp_free_i32(tcg_rmode
);
2796 tcg_temp_free_ptr(fpst
);
2800 static int handle_vcvt(uint32_t insn
, uint32_t rd
, uint32_t rm
, uint32_t dp
,
2803 bool is_signed
= extract32(insn
, 7, 1);
2804 TCGv_ptr fpst
= get_fpstatus_ptr(0);
2805 TCGv_i32 tcg_rmode
, tcg_shift
;
2807 tcg_shift
= tcg_const_i32(0);
2809 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rounding
));
2810 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
2813 TCGv_i64 tcg_double
, tcg_res
;
2815 /* Rd is encoded as a single precision register even when the source
2816 * is double precision.
2818 rd
= ((rd
<< 1) & 0x1e) | ((rd
>> 4) & 0x1);
2819 tcg_double
= tcg_temp_new_i64();
2820 tcg_res
= tcg_temp_new_i64();
2821 tcg_tmp
= tcg_temp_new_i32();
2822 tcg_gen_ld_f64(tcg_double
, cpu_env
, vfp_reg_offset(1, rm
));
2824 gen_helper_vfp_tosld(tcg_res
, tcg_double
, tcg_shift
, fpst
);
2826 gen_helper_vfp_tould(tcg_res
, tcg_double
, tcg_shift
, fpst
);
2828 tcg_gen_trunc_i64_i32(tcg_tmp
, tcg_res
);
2829 tcg_gen_st_f32(tcg_tmp
, cpu_env
, vfp_reg_offset(0, rd
));
2830 tcg_temp_free_i32(tcg_tmp
);
2831 tcg_temp_free_i64(tcg_res
);
2832 tcg_temp_free_i64(tcg_double
);
2834 TCGv_i32 tcg_single
, tcg_res
;
2835 tcg_single
= tcg_temp_new_i32();
2836 tcg_res
= tcg_temp_new_i32();
2837 tcg_gen_ld_f32(tcg_single
, cpu_env
, vfp_reg_offset(0, rm
));
2839 gen_helper_vfp_tosls(tcg_res
, tcg_single
, tcg_shift
, fpst
);
2841 gen_helper_vfp_touls(tcg_res
, tcg_single
, tcg_shift
, fpst
);
2843 tcg_gen_st_f32(tcg_res
, cpu_env
, vfp_reg_offset(0, rd
));
2844 tcg_temp_free_i32(tcg_res
);
2845 tcg_temp_free_i32(tcg_single
);
2848 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
2849 tcg_temp_free_i32(tcg_rmode
);
2851 tcg_temp_free_i32(tcg_shift
);
2853 tcg_temp_free_ptr(fpst
);
2858 /* Table for converting the most common AArch32 encoding of
2859 * rounding mode to arm_fprounding order (which matches the
2860 * common AArch64 order); see ARM ARM pseudocode FPDecodeRM().
2862 static const uint8_t fp_decode_rm
[] = {
2869 static int disas_vfp_v8_insn(CPUARMState
*env
, DisasContext
*s
, uint32_t insn
)
2871 uint32_t rd
, rn
, rm
, dp
= extract32(insn
, 8, 1);
2873 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
2878 VFP_DREG_D(rd
, insn
);
2879 VFP_DREG_N(rn
, insn
);
2880 VFP_DREG_M(rm
, insn
);
2882 rd
= VFP_SREG_D(insn
);
2883 rn
= VFP_SREG_N(insn
);
2884 rm
= VFP_SREG_M(insn
);
2887 if ((insn
& 0x0f800e50) == 0x0e000a00) {
2888 return handle_vsel(insn
, rd
, rn
, rm
, dp
);
2889 } else if ((insn
& 0x0fb00e10) == 0x0e800a00) {
2890 return handle_vminmaxnm(insn
, rd
, rn
, rm
, dp
);
2891 } else if ((insn
& 0x0fbc0ed0) == 0x0eb80a40) {
2892 /* VRINTA, VRINTN, VRINTP, VRINTM */
2893 int rounding
= fp_decode_rm
[extract32(insn
, 16, 2)];
2894 return handle_vrint(insn
, rd
, rm
, dp
, rounding
);
2895 } else if ((insn
& 0x0fbc0e50) == 0x0ebc0a40) {
2896 /* VCVTA, VCVTN, VCVTP, VCVTM */
2897 int rounding
= fp_decode_rm
[extract32(insn
, 16, 2)];
2898 return handle_vcvt(insn
, rd
, rm
, dp
, rounding
);
2903 /* Disassemble a VFP instruction. Returns nonzero if an error occurred
2904 (ie. an undefined instruction). */
2905 static int disas_vfp_insn(CPUARMState
* env
, DisasContext
*s
, uint32_t insn
)
2907 uint32_t rd
, rn
, rm
, op
, i
, n
, offset
, delta_d
, delta_m
, bank_mask
;
2913 if (!arm_feature(env
, ARM_FEATURE_VFP
))
2916 if (!s
->vfp_enabled
) {
2917 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
2918 if ((insn
& 0x0fe00fff) != 0x0ee00a10)
2920 rn
= (insn
>> 16) & 0xf;
2921 if (rn
!= ARM_VFP_FPSID
&& rn
!= ARM_VFP_FPEXC
2922 && rn
!= ARM_VFP_MVFR1
&& rn
!= ARM_VFP_MVFR0
)
2926 if (extract32(insn
, 28, 4) == 0xf) {
2927 /* Encodings with T=1 (Thumb) or unconditional (ARM):
2928 * only used in v8 and above.
2930 return disas_vfp_v8_insn(env
, s
, insn
);
2933 dp
= ((insn
& 0xf00) == 0xb00);
2934 switch ((insn
>> 24) & 0xf) {
2936 if (insn
& (1 << 4)) {
2937 /* single register transfer */
2938 rd
= (insn
>> 12) & 0xf;
2943 VFP_DREG_N(rn
, insn
);
2946 if (insn
& 0x00c00060
2947 && !arm_feature(env
, ARM_FEATURE_NEON
))
2950 pass
= (insn
>> 21) & 1;
2951 if (insn
& (1 << 22)) {
2953 offset
= ((insn
>> 5) & 3) * 8;
2954 } else if (insn
& (1 << 5)) {
2956 offset
= (insn
& (1 << 6)) ? 16 : 0;
2961 if (insn
& ARM_CP_RW_BIT
) {
2963 tmp
= neon_load_reg(rn
, pass
);
2967 tcg_gen_shri_i32(tmp
, tmp
, offset
);
2968 if (insn
& (1 << 23))
2974 if (insn
& (1 << 23)) {
2976 tcg_gen_shri_i32(tmp
, tmp
, 16);
2982 tcg_gen_sari_i32(tmp
, tmp
, 16);
2991 store_reg(s
, rd
, tmp
);
2994 tmp
= load_reg(s
, rd
);
2995 if (insn
& (1 << 23)) {
2998 gen_neon_dup_u8(tmp
, 0);
2999 } else if (size
== 1) {
3000 gen_neon_dup_low16(tmp
);
3002 for (n
= 0; n
<= pass
* 2; n
++) {
3003 tmp2
= tcg_temp_new_i32();
3004 tcg_gen_mov_i32(tmp2
, tmp
);
3005 neon_store_reg(rn
, n
, tmp2
);
3007 neon_store_reg(rn
, n
, tmp
);
3012 tmp2
= neon_load_reg(rn
, pass
);
3013 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, offset
, 8);
3014 tcg_temp_free_i32(tmp2
);
3017 tmp2
= neon_load_reg(rn
, pass
);
3018 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, offset
, 16);
3019 tcg_temp_free_i32(tmp2
);
3024 neon_store_reg(rn
, pass
, tmp
);
3028 if ((insn
& 0x6f) != 0x00)
3030 rn
= VFP_SREG_N(insn
);
3031 if (insn
& ARM_CP_RW_BIT
) {
3033 if (insn
& (1 << 21)) {
3034 /* system register */
3039 /* VFP2 allows access to FSID from userspace.
3040 VFP3 restricts all id registers to privileged
3043 && arm_feature(env
, ARM_FEATURE_VFP3
))
3045 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
3050 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
3052 case ARM_VFP_FPINST
:
3053 case ARM_VFP_FPINST2
:
3054 /* Not present in VFP3. */
3056 || arm_feature(env
, ARM_FEATURE_VFP3
))
3058 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
3062 tmp
= load_cpu_field(vfp
.xregs
[ARM_VFP_FPSCR
]);
3063 tcg_gen_andi_i32(tmp
, tmp
, 0xf0000000);
3065 tmp
= tcg_temp_new_i32();
3066 gen_helper_vfp_get_fpscr(tmp
, cpu_env
);
3072 || !arm_feature(env
, ARM_FEATURE_MVFR
))
3074 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
3080 gen_mov_F0_vreg(0, rn
);
3081 tmp
= gen_vfp_mrs();
3084 /* Set the 4 flag bits in the CPSR. */
3086 tcg_temp_free_i32(tmp
);
3088 store_reg(s
, rd
, tmp
);
3092 if (insn
& (1 << 21)) {
3094 /* system register */
3099 /* Writes are ignored. */
3102 tmp
= load_reg(s
, rd
);
3103 gen_helper_vfp_set_fpscr(cpu_env
, tmp
);
3104 tcg_temp_free_i32(tmp
);
3110 /* TODO: VFP subarchitecture support.
3111 * For now, keep the EN bit only */
3112 tmp
= load_reg(s
, rd
);
3113 tcg_gen_andi_i32(tmp
, tmp
, 1 << 30);
3114 store_cpu_field(tmp
, vfp
.xregs
[rn
]);
3117 case ARM_VFP_FPINST
:
3118 case ARM_VFP_FPINST2
:
3119 tmp
= load_reg(s
, rd
);
3120 store_cpu_field(tmp
, vfp
.xregs
[rn
]);
3126 tmp
= load_reg(s
, rd
);
3128 gen_mov_vreg_F0(0, rn
);
3133 /* data processing */
3134 /* The opcode is in bits 23, 21, 20 and 6. */
3135 op
= ((insn
>> 20) & 8) | ((insn
>> 19) & 6) | ((insn
>> 6) & 1);
3139 rn
= ((insn
>> 15) & 0x1e) | ((insn
>> 7) & 1);
3141 /* rn is register number */
3142 VFP_DREG_N(rn
, insn
);
3145 if (op
== 15 && (rn
== 15 || ((rn
& 0x1c) == 0x18) ||
3146 ((rn
& 0x1e) == 0x6))) {
3147 /* Integer or single/half precision destination. */
3148 rd
= VFP_SREG_D(insn
);
3150 VFP_DREG_D(rd
, insn
);
3153 (((rn
& 0x1c) == 0x10) || ((rn
& 0x14) == 0x14) ||
3154 ((rn
& 0x1e) == 0x4))) {
3155 /* VCVT from int or half precision is always from S reg
3156 * regardless of dp bit. VCVT with immediate frac_bits
3157 * has same format as SREG_M.
3159 rm
= VFP_SREG_M(insn
);
3161 VFP_DREG_M(rm
, insn
);
3164 rn
= VFP_SREG_N(insn
);
3165 if (op
== 15 && rn
== 15) {
3166 /* Double precision destination. */
3167 VFP_DREG_D(rd
, insn
);
3169 rd
= VFP_SREG_D(insn
);
3171 /* NB that we implicitly rely on the encoding for the frac_bits
3172 * in VCVT of fixed to float being the same as that of an SREG_M
3174 rm
= VFP_SREG_M(insn
);
3177 veclen
= s
->vec_len
;
3178 if (op
== 15 && rn
> 3)
3181 /* Shut up compiler warnings. */
3192 /* Figure out what type of vector operation this is. */
3193 if ((rd
& bank_mask
) == 0) {
3198 delta_d
= (s
->vec_stride
>> 1) + 1;
3200 delta_d
= s
->vec_stride
+ 1;
3202 if ((rm
& bank_mask
) == 0) {
3203 /* mixed scalar/vector */
3212 /* Load the initial operands. */
3217 /* Integer source */
3218 gen_mov_F0_vreg(0, rm
);
3223 gen_mov_F0_vreg(dp
, rd
);
3224 gen_mov_F1_vreg(dp
, rm
);
3228 /* Compare with zero */
3229 gen_mov_F0_vreg(dp
, rd
);
3240 /* Source and destination the same. */
3241 gen_mov_F0_vreg(dp
, rd
);
3247 /* VCVTB, VCVTT: only present with the halfprec extension
3248 * UNPREDICTABLE if bit 8 is set prior to ARMv8
3249 * (we choose to UNDEF)
3251 if ((dp
&& !arm_feature(env
, ARM_FEATURE_V8
)) ||
3252 !arm_feature(env
, ARM_FEATURE_VFP_FP16
)) {
3255 if (!extract32(rn
, 1, 1)) {
3256 /* Half precision source. */
3257 gen_mov_F0_vreg(0, rm
);
3260 /* Otherwise fall through */
3262 /* One source operand. */
3263 gen_mov_F0_vreg(dp
, rm
);
3267 /* Two source operands. */
3268 gen_mov_F0_vreg(dp
, rn
);
3269 gen_mov_F1_vreg(dp
, rm
);
3273 /* Perform the calculation. */
3275 case 0: /* VMLA: fd + (fn * fm) */
3276 /* Note that order of inputs to the add matters for NaNs */
3278 gen_mov_F0_vreg(dp
, rd
);
3281 case 1: /* VMLS: fd + -(fn * fm) */
3284 gen_mov_F0_vreg(dp
, rd
);
3287 case 2: /* VNMLS: -fd + (fn * fm) */
3288 /* Note that it isn't valid to replace (-A + B) with (B - A)
3289 * or similar plausible looking simplifications
3290 * because this will give wrong results for NaNs.
3293 gen_mov_F0_vreg(dp
, rd
);
3297 case 3: /* VNMLA: -fd + -(fn * fm) */
3300 gen_mov_F0_vreg(dp
, rd
);
3304 case 4: /* mul: fn * fm */
3307 case 5: /* nmul: -(fn * fm) */
3311 case 6: /* add: fn + fm */
3314 case 7: /* sub: fn - fm */
3317 case 8: /* div: fn / fm */
3320 case 10: /* VFNMA : fd = muladd(-fd, fn, fm) */
3321 case 11: /* VFNMS : fd = muladd(-fd, -fn, fm) */
3322 case 12: /* VFMA : fd = muladd( fd, fn, fm) */
3323 case 13: /* VFMS : fd = muladd( fd, -fn, fm) */
3324 /* These are fused multiply-add, and must be done as one
3325 * floating point operation with no rounding between the
3326 * multiplication and addition steps.
3327 * NB that doing the negations here as separate steps is
3328 * correct : an input NaN should come out with its sign bit
3329 * flipped if it is a negated-input.
3331 if (!arm_feature(env
, ARM_FEATURE_VFP4
)) {
3339 gen_helper_vfp_negd(cpu_F0d
, cpu_F0d
);
3341 frd
= tcg_temp_new_i64();
3342 tcg_gen_ld_f64(frd
, cpu_env
, vfp_reg_offset(dp
, rd
));
3345 gen_helper_vfp_negd(frd
, frd
);
3347 fpst
= get_fpstatus_ptr(0);
3348 gen_helper_vfp_muladdd(cpu_F0d
, cpu_F0d
,
3349 cpu_F1d
, frd
, fpst
);
3350 tcg_temp_free_ptr(fpst
);
3351 tcg_temp_free_i64(frd
);
3357 gen_helper_vfp_negs(cpu_F0s
, cpu_F0s
);
3359 frd
= tcg_temp_new_i32();
3360 tcg_gen_ld_f32(frd
, cpu_env
, vfp_reg_offset(dp
, rd
));
3362 gen_helper_vfp_negs(frd
, frd
);
3364 fpst
= get_fpstatus_ptr(0);
3365 gen_helper_vfp_muladds(cpu_F0s
, cpu_F0s
,
3366 cpu_F1s
, frd
, fpst
);
3367 tcg_temp_free_ptr(fpst
);
3368 tcg_temp_free_i32(frd
);
3371 case 14: /* fconst */
3372 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3375 n
= (insn
<< 12) & 0x80000000;
3376 i
= ((insn
>> 12) & 0x70) | (insn
& 0xf);
3383 tcg_gen_movi_i64(cpu_F0d
, ((uint64_t)n
) << 32);
3390 tcg_gen_movi_i32(cpu_F0s
, n
);
3393 case 15: /* extension space */
3407 case 4: /* vcvtb.f32.f16, vcvtb.f64.f16 */
3408 tmp
= gen_vfp_mrs();
3409 tcg_gen_ext16u_i32(tmp
, tmp
);
3411 gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d
, tmp
,
3414 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s
, tmp
,
3417 tcg_temp_free_i32(tmp
);
3419 case 5: /* vcvtt.f32.f16, vcvtt.f64.f16 */
3420 tmp
= gen_vfp_mrs();
3421 tcg_gen_shri_i32(tmp
, tmp
, 16);
3423 gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d
, tmp
,
3426 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s
, tmp
,
3429 tcg_temp_free_i32(tmp
);
3431 case 6: /* vcvtb.f16.f32, vcvtb.f16.f64 */
3432 tmp
= tcg_temp_new_i32();
3434 gen_helper_vfp_fcvt_f64_to_f16(tmp
, cpu_F0d
,
3437 gen_helper_vfp_fcvt_f32_to_f16(tmp
, cpu_F0s
,
3440 gen_mov_F0_vreg(0, rd
);
3441 tmp2
= gen_vfp_mrs();
3442 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff0000);
3443 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
3444 tcg_temp_free_i32(tmp2
);
3447 case 7: /* vcvtt.f16.f32, vcvtt.f16.f64 */
3448 tmp
= tcg_temp_new_i32();
3450 gen_helper_vfp_fcvt_f64_to_f16(tmp
, cpu_F0d
,
3453 gen_helper_vfp_fcvt_f32_to_f16(tmp
, cpu_F0s
,
3456 tcg_gen_shli_i32(tmp
, tmp
, 16);
3457 gen_mov_F0_vreg(0, rd
);
3458 tmp2
= gen_vfp_mrs();
3459 tcg_gen_ext16u_i32(tmp2
, tmp2
);
3460 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
3461 tcg_temp_free_i32(tmp2
);
3473 case 11: /* cmpez */
3477 case 12: /* vrintr */
3479 TCGv_ptr fpst
= get_fpstatus_ptr(0);
3481 gen_helper_rintd(cpu_F0d
, cpu_F0d
, fpst
);
3483 gen_helper_rints(cpu_F0s
, cpu_F0s
, fpst
);
3485 tcg_temp_free_ptr(fpst
);
3488 case 13: /* vrintz */
3490 TCGv_ptr fpst
= get_fpstatus_ptr(0);
3492 tcg_rmode
= tcg_const_i32(float_round_to_zero
);
3493 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
3495 gen_helper_rintd(cpu_F0d
, cpu_F0d
, fpst
);
3497 gen_helper_rints(cpu_F0s
, cpu_F0s
, fpst
);
3499 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
3500 tcg_temp_free_i32(tcg_rmode
);
3501 tcg_temp_free_ptr(fpst
);
3504 case 14: /* vrintx */
3506 TCGv_ptr fpst
= get_fpstatus_ptr(0);
3508 gen_helper_rintd_exact(cpu_F0d
, cpu_F0d
, fpst
);
3510 gen_helper_rints_exact(cpu_F0s
, cpu_F0s
, fpst
);
3512 tcg_temp_free_ptr(fpst
);
3515 case 15: /* single<->double conversion */
3517 gen_helper_vfp_fcvtsd(cpu_F0s
, cpu_F0d
, cpu_env
);
3519 gen_helper_vfp_fcvtds(cpu_F0d
, cpu_F0s
, cpu_env
);
3521 case 16: /* fuito */
3522 gen_vfp_uito(dp
, 0);
3524 case 17: /* fsito */
3525 gen_vfp_sito(dp
, 0);
3527 case 20: /* fshto */
3528 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3530 gen_vfp_shto(dp
, 16 - rm
, 0);
3532 case 21: /* fslto */
3533 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3535 gen_vfp_slto(dp
, 32 - rm
, 0);
3537 case 22: /* fuhto */
3538 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3540 gen_vfp_uhto(dp
, 16 - rm
, 0);
3542 case 23: /* fulto */
3543 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3545 gen_vfp_ulto(dp
, 32 - rm
, 0);
3547 case 24: /* ftoui */
3548 gen_vfp_toui(dp
, 0);
3550 case 25: /* ftouiz */
3551 gen_vfp_touiz(dp
, 0);
3553 case 26: /* ftosi */
3554 gen_vfp_tosi(dp
, 0);
3556 case 27: /* ftosiz */
3557 gen_vfp_tosiz(dp
, 0);
3559 case 28: /* ftosh */
3560 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3562 gen_vfp_tosh(dp
, 16 - rm
, 0);
3564 case 29: /* ftosl */
3565 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3567 gen_vfp_tosl(dp
, 32 - rm
, 0);
3569 case 30: /* ftouh */
3570 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3572 gen_vfp_touh(dp
, 16 - rm
, 0);
3574 case 31: /* ftoul */
3575 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3577 gen_vfp_toul(dp
, 32 - rm
, 0);
3579 default: /* undefined */
3583 default: /* undefined */
3587 /* Write back the result. */
3588 if (op
== 15 && (rn
>= 8 && rn
<= 11)) {
3589 /* Comparison, do nothing. */
3590 } else if (op
== 15 && dp
&& ((rn
& 0x1c) == 0x18 ||
3591 (rn
& 0x1e) == 0x6)) {
3592 /* VCVT double to int: always integer result.
3593 * VCVT double to half precision is always a single
3596 gen_mov_vreg_F0(0, rd
);
3597 } else if (op
== 15 && rn
== 15) {
3599 gen_mov_vreg_F0(!dp
, rd
);
3601 gen_mov_vreg_F0(dp
, rd
);
3604 /* break out of the loop if we have finished */
3608 if (op
== 15 && delta_m
== 0) {
3609 /* single source one-many */
3611 rd
= ((rd
+ delta_d
) & (bank_mask
- 1))
3613 gen_mov_vreg_F0(dp
, rd
);
3617 /* Setup the next operands. */
3619 rd
= ((rd
+ delta_d
) & (bank_mask
- 1))
3623 /* One source operand. */
3624 rm
= ((rm
+ delta_m
) & (bank_mask
- 1))
3626 gen_mov_F0_vreg(dp
, rm
);
3628 /* Two source operands. */
3629 rn
= ((rn
+ delta_d
) & (bank_mask
- 1))
3631 gen_mov_F0_vreg(dp
, rn
);
3633 rm
= ((rm
+ delta_m
) & (bank_mask
- 1))
3635 gen_mov_F1_vreg(dp
, rm
);
3643 if ((insn
& 0x03e00000) == 0x00400000) {
3644 /* two-register transfer */
3645 rn
= (insn
>> 16) & 0xf;
3646 rd
= (insn
>> 12) & 0xf;
3648 VFP_DREG_M(rm
, insn
);
3650 rm
= VFP_SREG_M(insn
);
3653 if (insn
& ARM_CP_RW_BIT
) {
3656 gen_mov_F0_vreg(0, rm
* 2);
3657 tmp
= gen_vfp_mrs();
3658 store_reg(s
, rd
, tmp
);
3659 gen_mov_F0_vreg(0, rm
* 2 + 1);
3660 tmp
= gen_vfp_mrs();
3661 store_reg(s
, rn
, tmp
);
3663 gen_mov_F0_vreg(0, rm
);
3664 tmp
= gen_vfp_mrs();
3665 store_reg(s
, rd
, tmp
);
3666 gen_mov_F0_vreg(0, rm
+ 1);
3667 tmp
= gen_vfp_mrs();
3668 store_reg(s
, rn
, tmp
);
3673 tmp
= load_reg(s
, rd
);
3675 gen_mov_vreg_F0(0, rm
* 2);
3676 tmp
= load_reg(s
, rn
);
3678 gen_mov_vreg_F0(0, rm
* 2 + 1);
3680 tmp
= load_reg(s
, rd
);
3682 gen_mov_vreg_F0(0, rm
);
3683 tmp
= load_reg(s
, rn
);
3685 gen_mov_vreg_F0(0, rm
+ 1);
3690 rn
= (insn
>> 16) & 0xf;
3692 VFP_DREG_D(rd
, insn
);
3694 rd
= VFP_SREG_D(insn
);
3695 if ((insn
& 0x01200000) == 0x01000000) {
3696 /* Single load/store */
3697 offset
= (insn
& 0xff) << 2;
3698 if ((insn
& (1 << 23)) == 0)
3700 if (s
->thumb
&& rn
== 15) {
3701 /* This is actually UNPREDICTABLE */
3702 addr
= tcg_temp_new_i32();
3703 tcg_gen_movi_i32(addr
, s
->pc
& ~2);
3705 addr
= load_reg(s
, rn
);
3707 tcg_gen_addi_i32(addr
, addr
, offset
);
3708 if (insn
& (1 << 20)) {
3709 gen_vfp_ld(s
, dp
, addr
);
3710 gen_mov_vreg_F0(dp
, rd
);
3712 gen_mov_F0_vreg(dp
, rd
);
3713 gen_vfp_st(s
, dp
, addr
);
3715 tcg_temp_free_i32(addr
);
3717 /* load/store multiple */
3718 int w
= insn
& (1 << 21);
3720 n
= (insn
>> 1) & 0x7f;
3724 if (w
&& !(((insn
>> 23) ^ (insn
>> 24)) & 1)) {
3725 /* P == U , W == 1 => UNDEF */
3728 if (n
== 0 || (rd
+ n
) > 32 || (dp
&& n
> 16)) {
3729 /* UNPREDICTABLE cases for bad immediates: we choose to
3730 * UNDEF to avoid generating huge numbers of TCG ops
3734 if (rn
== 15 && w
) {
3735 /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
3739 if (s
->thumb
&& rn
== 15) {
3740 /* This is actually UNPREDICTABLE */
3741 addr
= tcg_temp_new_i32();
3742 tcg_gen_movi_i32(addr
, s
->pc
& ~2);
3744 addr
= load_reg(s
, rn
);
3746 if (insn
& (1 << 24)) /* pre-decrement */
3747 tcg_gen_addi_i32(addr
, addr
, -((insn
& 0xff) << 2));
3753 for (i
= 0; i
< n
; i
++) {
3754 if (insn
& ARM_CP_RW_BIT
) {
3756 gen_vfp_ld(s
, dp
, addr
);
3757 gen_mov_vreg_F0(dp
, rd
+ i
);
3760 gen_mov_F0_vreg(dp
, rd
+ i
);
3761 gen_vfp_st(s
, dp
, addr
);
3763 tcg_gen_addi_i32(addr
, addr
, offset
);
3767 if (insn
& (1 << 24))
3768 offset
= -offset
* n
;
3769 else if (dp
&& (insn
& 1))
3775 tcg_gen_addi_i32(addr
, addr
, offset
);
3776 store_reg(s
, rn
, addr
);
3778 tcg_temp_free_i32(addr
);
3784 /* Should never happen. */
3790 static inline void gen_goto_tb(DisasContext
*s
, int n
, target_ulong dest
)
3792 TranslationBlock
*tb
;
3795 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
3797 gen_set_pc_im(s
, dest
);
3798 tcg_gen_exit_tb((uintptr_t)tb
+ n
);
3800 gen_set_pc_im(s
, dest
);
3805 static inline void gen_jmp (DisasContext
*s
, uint32_t dest
)
3807 if (unlikely(s
->singlestep_enabled
)) {
3808 /* An indirect jump so that we still trigger the debug exception. */
3813 gen_goto_tb(s
, 0, dest
);
3814 s
->is_jmp
= DISAS_TB_JUMP
;
3818 static inline void gen_mulxy(TCGv_i32 t0
, TCGv_i32 t1
, int x
, int y
)
3821 tcg_gen_sari_i32(t0
, t0
, 16);
3825 tcg_gen_sari_i32(t1
, t1
, 16);
3828 tcg_gen_mul_i32(t0
, t0
, t1
);
3831 /* Return the mask of PSR bits set by a MSR instruction. */
3832 static uint32_t msr_mask(CPUARMState
*env
, DisasContext
*s
, int flags
, int spsr
) {
3836 if (flags
& (1 << 0))
3838 if (flags
& (1 << 1))
3840 if (flags
& (1 << 2))
3842 if (flags
& (1 << 3))
3845 /* Mask out undefined bits. */
3846 mask
&= ~CPSR_RESERVED
;
3847 if (!arm_feature(env
, ARM_FEATURE_V4T
))
3849 if (!arm_feature(env
, ARM_FEATURE_V5
))
3850 mask
&= ~CPSR_Q
; /* V5TE in reality*/
3851 if (!arm_feature(env
, ARM_FEATURE_V6
))
3852 mask
&= ~(CPSR_E
| CPSR_GE
);
3853 if (!arm_feature(env
, ARM_FEATURE_THUMB2
))
3855 /* Mask out execution state bits. */
3858 /* Mask out privileged bits. */
3864 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3865 static int gen_set_psr(DisasContext
*s
, uint32_t mask
, int spsr
, TCGv_i32 t0
)
3869 /* ??? This is also undefined in system mode. */
3873 tmp
= load_cpu_field(spsr
);
3874 tcg_gen_andi_i32(tmp
, tmp
, ~mask
);
3875 tcg_gen_andi_i32(t0
, t0
, mask
);
3876 tcg_gen_or_i32(tmp
, tmp
, t0
);
3877 store_cpu_field(tmp
, spsr
);
3879 gen_set_cpsr(t0
, mask
);
3881 tcg_temp_free_i32(t0
);
3886 /* Returns nonzero if access to the PSR is not permitted. */
3887 static int gen_set_psr_im(DisasContext
*s
, uint32_t mask
, int spsr
, uint32_t val
)
3890 tmp
= tcg_temp_new_i32();
3891 tcg_gen_movi_i32(tmp
, val
);
3892 return gen_set_psr(s
, mask
, spsr
, tmp
);
3895 /* Generate an old-style exception return. Marks pc as dead. */
3896 static void gen_exception_return(DisasContext
*s
, TCGv_i32 pc
)
3899 store_reg(s
, 15, pc
);
3900 tmp
= load_cpu_field(spsr
);
3901 gen_set_cpsr(tmp
, 0xffffffff);
3902 tcg_temp_free_i32(tmp
);
3903 s
->is_jmp
= DISAS_UPDATE
;
3906 /* Generate a v6 exception return. Marks both values as dead. */
3907 static void gen_rfe(DisasContext
*s
, TCGv_i32 pc
, TCGv_i32 cpsr
)
3909 gen_set_cpsr(cpsr
, 0xffffffff);
3910 tcg_temp_free_i32(cpsr
);
3911 store_reg(s
, 15, pc
);
3912 s
->is_jmp
= DISAS_UPDATE
;
3916 gen_set_condexec (DisasContext
*s
)
3918 if (s
->condexec_mask
) {
3919 uint32_t val
= (s
->condexec_cond
<< 4) | (s
->condexec_mask
>> 1);
3920 TCGv_i32 tmp
= tcg_temp_new_i32();
3921 tcg_gen_movi_i32(tmp
, val
);
3922 store_cpu_field(tmp
, condexec_bits
);
3926 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
)
3928 gen_set_condexec(s
);
3929 gen_set_pc_im(s
, s
->pc
- offset
);
3930 gen_exception(excp
);
3931 s
->is_jmp
= DISAS_JUMP
;
3934 static void gen_nop_hint(DisasContext
*s
, int val
)
3938 gen_set_pc_im(s
, s
->pc
);
3939 s
->is_jmp
= DISAS_WFI
;
3944 /* TODO: Implement SEV, SEVL and WFE. May help SMP performance. */
3950 #define CPU_V001 cpu_V0, cpu_V0, cpu_V1
3952 static inline void gen_neon_add(int size
, TCGv_i32 t0
, TCGv_i32 t1
)
3955 case 0: gen_helper_neon_add_u8(t0
, t0
, t1
); break;
3956 case 1: gen_helper_neon_add_u16(t0
, t0
, t1
); break;
3957 case 2: tcg_gen_add_i32(t0
, t0
, t1
); break;
3962 static inline void gen_neon_rsb(int size
, TCGv_i32 t0
, TCGv_i32 t1
)
3965 case 0: gen_helper_neon_sub_u8(t0
, t1
, t0
); break;
3966 case 1: gen_helper_neon_sub_u16(t0
, t1
, t0
); break;
3967 case 2: tcg_gen_sub_i32(t0
, t1
, t0
); break;
3972 /* 32-bit pairwise ops end up the same as the elementwise versions. */
3973 #define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3974 #define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3975 #define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3976 #define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3978 #define GEN_NEON_INTEGER_OP_ENV(name) do { \
3979 switch ((size << 1) | u) { \
3981 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
3984 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
3987 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
3990 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
3993 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
3996 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
3998 default: return 1; \
4001 #define GEN_NEON_INTEGER_OP(name) do { \
4002 switch ((size << 1) | u) { \
4004 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
4007 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
4010 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
4013 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
4016 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
4019 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
4021 default: return 1; \
4024 static TCGv_i32
neon_load_scratch(int scratch
)
4026 TCGv_i32 tmp
= tcg_temp_new_i32();
4027 tcg_gen_ld_i32(tmp
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
4031 static void neon_store_scratch(int scratch
, TCGv_i32 var
)
4033 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
4034 tcg_temp_free_i32(var
);
4037 static inline TCGv_i32
neon_get_scalar(int size
, int reg
)
4041 tmp
= neon_load_reg(reg
& 7, reg
>> 4);
4043 gen_neon_dup_high16(tmp
);
4045 gen_neon_dup_low16(tmp
);
4048 tmp
= neon_load_reg(reg
& 15, reg
>> 4);
4053 static int gen_neon_unzip(int rd
, int rm
, int size
, int q
)
4056 if (!q
&& size
== 2) {
4059 tmp
= tcg_const_i32(rd
);
4060 tmp2
= tcg_const_i32(rm
);
4064 gen_helper_neon_qunzip8(cpu_env
, tmp
, tmp2
);
4067 gen_helper_neon_qunzip16(cpu_env
, tmp
, tmp2
);
4070 gen_helper_neon_qunzip32(cpu_env
, tmp
, tmp2
);
4078 gen_helper_neon_unzip8(cpu_env
, tmp
, tmp2
);
4081 gen_helper_neon_unzip16(cpu_env
, tmp
, tmp2
);
4087 tcg_temp_free_i32(tmp
);
4088 tcg_temp_free_i32(tmp2
);
4092 static int gen_neon_zip(int rd
, int rm
, int size
, int q
)
4095 if (!q
&& size
== 2) {
4098 tmp
= tcg_const_i32(rd
);
4099 tmp2
= tcg_const_i32(rm
);
4103 gen_helper_neon_qzip8(cpu_env
, tmp
, tmp2
);
4106 gen_helper_neon_qzip16(cpu_env
, tmp
, tmp2
);
4109 gen_helper_neon_qzip32(cpu_env
, tmp
, tmp2
);
4117 gen_helper_neon_zip8(cpu_env
, tmp
, tmp2
);
4120 gen_helper_neon_zip16(cpu_env
, tmp
, tmp2
);
4126 tcg_temp_free_i32(tmp
);
4127 tcg_temp_free_i32(tmp2
);
4131 static void gen_neon_trn_u8(TCGv_i32 t0
, TCGv_i32 t1
)
4135 rd
= tcg_temp_new_i32();
4136 tmp
= tcg_temp_new_i32();
4138 tcg_gen_shli_i32(rd
, t0
, 8);
4139 tcg_gen_andi_i32(rd
, rd
, 0xff00ff00);
4140 tcg_gen_andi_i32(tmp
, t1
, 0x00ff00ff);
4141 tcg_gen_or_i32(rd
, rd
, tmp
);
4143 tcg_gen_shri_i32(t1
, t1
, 8);
4144 tcg_gen_andi_i32(t1
, t1
, 0x00ff00ff);
4145 tcg_gen_andi_i32(tmp
, t0
, 0xff00ff00);
4146 tcg_gen_or_i32(t1
, t1
, tmp
);
4147 tcg_gen_mov_i32(t0
, rd
);
4149 tcg_temp_free_i32(tmp
);
4150 tcg_temp_free_i32(rd
);
4153 static void gen_neon_trn_u16(TCGv_i32 t0
, TCGv_i32 t1
)
4157 rd
= tcg_temp_new_i32();
4158 tmp
= tcg_temp_new_i32();
4160 tcg_gen_shli_i32(rd
, t0
, 16);
4161 tcg_gen_andi_i32(tmp
, t1
, 0xffff);
4162 tcg_gen_or_i32(rd
, rd
, tmp
);
4163 tcg_gen_shri_i32(t1
, t1
, 16);
4164 tcg_gen_andi_i32(tmp
, t0
, 0xffff0000);
4165 tcg_gen_or_i32(t1
, t1
, tmp
);
4166 tcg_gen_mov_i32(t0
, rd
);
4168 tcg_temp_free_i32(tmp
);
4169 tcg_temp_free_i32(rd
);
4177 } neon_ls_element_type
[11] = {
4191 /* Translate a NEON load/store element instruction. Return nonzero if the
4192 instruction is invalid. */
4193 static int disas_neon_ls_insn(CPUARMState
* env
, DisasContext
*s
, uint32_t insn
)
4212 if (!s
->vfp_enabled
)
4214 VFP_DREG_D(rd
, insn
);
4215 rn
= (insn
>> 16) & 0xf;
4217 load
= (insn
& (1 << 21)) != 0;
4218 if ((insn
& (1 << 23)) == 0) {
4219 /* Load store all elements. */
4220 op
= (insn
>> 8) & 0xf;
4221 size
= (insn
>> 6) & 3;
4224 /* Catch UNDEF cases for bad values of align field */
4227 if (((insn
>> 5) & 1) == 1) {
4232 if (((insn
>> 4) & 3) == 3) {
4239 nregs
= neon_ls_element_type
[op
].nregs
;
4240 interleave
= neon_ls_element_type
[op
].interleave
;
4241 spacing
= neon_ls_element_type
[op
].spacing
;
4242 if (size
== 3 && (interleave
| spacing
) != 1)
4244 addr
= tcg_temp_new_i32();
4245 load_reg_var(s
, addr
, rn
);
4246 stride
= (1 << size
) * interleave
;
4247 for (reg
= 0; reg
< nregs
; reg
++) {
4248 if (interleave
> 2 || (interleave
== 2 && nregs
== 2)) {
4249 load_reg_var(s
, addr
, rn
);
4250 tcg_gen_addi_i32(addr
, addr
, (1 << size
) * reg
);
4251 } else if (interleave
== 2 && nregs
== 4 && reg
== 2) {
4252 load_reg_var(s
, addr
, rn
);
4253 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
4256 tmp64
= tcg_temp_new_i64();
4258 gen_aa32_ld64(tmp64
, addr
, IS_USER(s
));
4259 neon_store_reg64(tmp64
, rd
);
4261 neon_load_reg64(tmp64
, rd
);
4262 gen_aa32_st64(tmp64
, addr
, IS_USER(s
));
4264 tcg_temp_free_i64(tmp64
);
4265 tcg_gen_addi_i32(addr
, addr
, stride
);
4267 for (pass
= 0; pass
< 2; pass
++) {
4270 tmp
= tcg_temp_new_i32();
4271 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
4272 neon_store_reg(rd
, pass
, tmp
);
4274 tmp
= neon_load_reg(rd
, pass
);
4275 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
4276 tcg_temp_free_i32(tmp
);
4278 tcg_gen_addi_i32(addr
, addr
, stride
);
4279 } else if (size
== 1) {
4281 tmp
= tcg_temp_new_i32();
4282 gen_aa32_ld16u(tmp
, addr
, IS_USER(s
));
4283 tcg_gen_addi_i32(addr
, addr
, stride
);
4284 tmp2
= tcg_temp_new_i32();
4285 gen_aa32_ld16u(tmp2
, addr
, IS_USER(s
));
4286 tcg_gen_addi_i32(addr
, addr
, stride
);
4287 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
4288 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
4289 tcg_temp_free_i32(tmp2
);
4290 neon_store_reg(rd
, pass
, tmp
);
4292 tmp
= neon_load_reg(rd
, pass
);
4293 tmp2
= tcg_temp_new_i32();
4294 tcg_gen_shri_i32(tmp2
, tmp
, 16);
4295 gen_aa32_st16(tmp
, addr
, IS_USER(s
));
4296 tcg_temp_free_i32(tmp
);
4297 tcg_gen_addi_i32(addr
, addr
, stride
);
4298 gen_aa32_st16(tmp2
, addr
, IS_USER(s
));
4299 tcg_temp_free_i32(tmp2
);
4300 tcg_gen_addi_i32(addr
, addr
, stride
);
4302 } else /* size == 0 */ {
4304 TCGV_UNUSED_I32(tmp2
);
4305 for (n
= 0; n
< 4; n
++) {
4306 tmp
= tcg_temp_new_i32();
4307 gen_aa32_ld8u(tmp
, addr
, IS_USER(s
));
4308 tcg_gen_addi_i32(addr
, addr
, stride
);
4312 tcg_gen_shli_i32(tmp
, tmp
, n
* 8);
4313 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
4314 tcg_temp_free_i32(tmp
);
4317 neon_store_reg(rd
, pass
, tmp2
);
4319 tmp2
= neon_load_reg(rd
, pass
);
4320 for (n
= 0; n
< 4; n
++) {
4321 tmp
= tcg_temp_new_i32();
4323 tcg_gen_mov_i32(tmp
, tmp2
);
4325 tcg_gen_shri_i32(tmp
, tmp2
, n
* 8);
4327 gen_aa32_st8(tmp
, addr
, IS_USER(s
));
4328 tcg_temp_free_i32(tmp
);
4329 tcg_gen_addi_i32(addr
, addr
, stride
);
4331 tcg_temp_free_i32(tmp2
);
4338 tcg_temp_free_i32(addr
);
4341 size
= (insn
>> 10) & 3;
4343 /* Load single element to all lanes. */
4344 int a
= (insn
>> 4) & 1;
4348 size
= (insn
>> 6) & 3;
4349 nregs
= ((insn
>> 8) & 3) + 1;
4352 if (nregs
!= 4 || a
== 0) {
4355 /* For VLD4 size==3 a == 1 means 32 bits at 16 byte alignment */
4358 if (nregs
== 1 && a
== 1 && size
== 0) {
4361 if (nregs
== 3 && a
== 1) {
4364 addr
= tcg_temp_new_i32();
4365 load_reg_var(s
, addr
, rn
);
4367 /* VLD1 to all lanes: bit 5 indicates how many Dregs to write */
4368 tmp
= gen_load_and_replicate(s
, addr
, size
);
4369 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 0));
4370 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 1));
4371 if (insn
& (1 << 5)) {
4372 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
+ 1, 0));
4373 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
+ 1, 1));
4375 tcg_temp_free_i32(tmp
);
4377 /* VLD2/3/4 to all lanes: bit 5 indicates register stride */
4378 stride
= (insn
& (1 << 5)) ? 2 : 1;
4379 for (reg
= 0; reg
< nregs
; reg
++) {
4380 tmp
= gen_load_and_replicate(s
, addr
, size
);
4381 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 0));
4382 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 1));
4383 tcg_temp_free_i32(tmp
);
4384 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
4388 tcg_temp_free_i32(addr
);
4389 stride
= (1 << size
) * nregs
;
4391 /* Single element. */
4392 int idx
= (insn
>> 4) & 0xf;
4393 pass
= (insn
>> 7) & 1;
4396 shift
= ((insn
>> 5) & 3) * 8;
4400 shift
= ((insn
>> 6) & 1) * 16;
4401 stride
= (insn
& (1 << 5)) ? 2 : 1;
4405 stride
= (insn
& (1 << 6)) ? 2 : 1;
4410 nregs
= ((insn
>> 8) & 3) + 1;
4411 /* Catch the UNDEF cases. This is unavoidably a bit messy. */
4414 if (((idx
& (1 << size
)) != 0) ||
4415 (size
== 2 && ((idx
& 3) == 1 || (idx
& 3) == 2))) {
4420 if ((idx
& 1) != 0) {
4425 if (size
== 2 && (idx
& 2) != 0) {
4430 if ((size
== 2) && ((idx
& 3) == 3)) {
4437 if ((rd
+ stride
* (nregs
- 1)) > 31) {
4438 /* Attempts to write off the end of the register file
4439 * are UNPREDICTABLE; we choose to UNDEF because otherwise
4440 * the neon_load_reg() would write off the end of the array.
4444 addr
= tcg_temp_new_i32();
4445 load_reg_var(s
, addr
, rn
);
4446 for (reg
= 0; reg
< nregs
; reg
++) {
4448 tmp
= tcg_temp_new_i32();
4451 gen_aa32_ld8u(tmp
, addr
, IS_USER(s
));
4454 gen_aa32_ld16u(tmp
, addr
, IS_USER(s
));
4457 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
4459 default: /* Avoid compiler warnings. */
4463 tmp2
= neon_load_reg(rd
, pass
);
4464 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
,
4465 shift
, size
? 16 : 8);
4466 tcg_temp_free_i32(tmp2
);
4468 neon_store_reg(rd
, pass
, tmp
);
4469 } else { /* Store */
4470 tmp
= neon_load_reg(rd
, pass
);
4472 tcg_gen_shri_i32(tmp
, tmp
, shift
);
4475 gen_aa32_st8(tmp
, addr
, IS_USER(s
));
4478 gen_aa32_st16(tmp
, addr
, IS_USER(s
));
4481 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
4484 tcg_temp_free_i32(tmp
);
4487 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
4489 tcg_temp_free_i32(addr
);
4490 stride
= nregs
* (1 << size
);
4496 base
= load_reg(s
, rn
);
4498 tcg_gen_addi_i32(base
, base
, stride
);
4501 index
= load_reg(s
, rm
);
4502 tcg_gen_add_i32(base
, base
, index
);
4503 tcg_temp_free_i32(index
);
4505 store_reg(s
, rn
, base
);
4510 /* Bitwise select. dest = c ? t : f. Clobbers T and F. */
4511 static void gen_neon_bsl(TCGv_i32 dest
, TCGv_i32 t
, TCGv_i32 f
, TCGv_i32 c
)
4513 tcg_gen_and_i32(t
, t
, c
);
4514 tcg_gen_andc_i32(f
, f
, c
);
4515 tcg_gen_or_i32(dest
, t
, f
);
4518 static inline void gen_neon_narrow(int size
, TCGv_i32 dest
, TCGv_i64 src
)
4521 case 0: gen_helper_neon_narrow_u8(dest
, src
); break;
4522 case 1: gen_helper_neon_narrow_u16(dest
, src
); break;
4523 case 2: tcg_gen_trunc_i64_i32(dest
, src
); break;
4528 static inline void gen_neon_narrow_sats(int size
, TCGv_i32 dest
, TCGv_i64 src
)
4531 case 0: gen_helper_neon_narrow_sat_s8(dest
, cpu_env
, src
); break;
4532 case 1: gen_helper_neon_narrow_sat_s16(dest
, cpu_env
, src
); break;
4533 case 2: gen_helper_neon_narrow_sat_s32(dest
, cpu_env
, src
); break;
4538 static inline void gen_neon_narrow_satu(int size
, TCGv_i32 dest
, TCGv_i64 src
)
4541 case 0: gen_helper_neon_narrow_sat_u8(dest
, cpu_env
, src
); break;
4542 case 1: gen_helper_neon_narrow_sat_u16(dest
, cpu_env
, src
); break;
4543 case 2: gen_helper_neon_narrow_sat_u32(dest
, cpu_env
, src
); break;
4548 static inline void gen_neon_unarrow_sats(int size
, TCGv_i32 dest
, TCGv_i64 src
)
4551 case 0: gen_helper_neon_unarrow_sat8(dest
, cpu_env
, src
); break;
4552 case 1: gen_helper_neon_unarrow_sat16(dest
, cpu_env
, src
); break;
4553 case 2: gen_helper_neon_unarrow_sat32(dest
, cpu_env
, src
); break;
4558 static inline void gen_neon_shift_narrow(int size
, TCGv_i32 var
, TCGv_i32 shift
,
4564 case 1: gen_helper_neon_rshl_u16(var
, var
, shift
); break;
4565 case 2: gen_helper_neon_rshl_u32(var
, var
, shift
); break;
4570 case 1: gen_helper_neon_rshl_s16(var
, var
, shift
); break;
4571 case 2: gen_helper_neon_rshl_s32(var
, var
, shift
); break;
4578 case 1: gen_helper_neon_shl_u16(var
, var
, shift
); break;
4579 case 2: gen_helper_neon_shl_u32(var
, var
, shift
); break;
4584 case 1: gen_helper_neon_shl_s16(var
, var
, shift
); break;
4585 case 2: gen_helper_neon_shl_s32(var
, var
, shift
); break;
4592 static inline void gen_neon_widen(TCGv_i64 dest
, TCGv_i32 src
, int size
, int u
)
4596 case 0: gen_helper_neon_widen_u8(dest
, src
); break;
4597 case 1: gen_helper_neon_widen_u16(dest
, src
); break;
4598 case 2: tcg_gen_extu_i32_i64(dest
, src
); break;
4603 case 0: gen_helper_neon_widen_s8(dest
, src
); break;
4604 case 1: gen_helper_neon_widen_s16(dest
, src
); break;
4605 case 2: tcg_gen_ext_i32_i64(dest
, src
); break;
4609 tcg_temp_free_i32(src
);
4612 static inline void gen_neon_addl(int size
)
4615 case 0: gen_helper_neon_addl_u16(CPU_V001
); break;
4616 case 1: gen_helper_neon_addl_u32(CPU_V001
); break;
4617 case 2: tcg_gen_add_i64(CPU_V001
); break;
4622 static inline void gen_neon_subl(int size
)
4625 case 0: gen_helper_neon_subl_u16(CPU_V001
); break;
4626 case 1: gen_helper_neon_subl_u32(CPU_V001
); break;
4627 case 2: tcg_gen_sub_i64(CPU_V001
); break;
4632 static inline void gen_neon_negl(TCGv_i64 var
, int size
)
4635 case 0: gen_helper_neon_negl_u16(var
, var
); break;
4636 case 1: gen_helper_neon_negl_u32(var
, var
); break;
4638 tcg_gen_neg_i64(var
, var
);
4644 static inline void gen_neon_addl_saturate(TCGv_i64 op0
, TCGv_i64 op1
, int size
)
4647 case 1: gen_helper_neon_addl_saturate_s32(op0
, cpu_env
, op0
, op1
); break;
4648 case 2: gen_helper_neon_addl_saturate_s64(op0
, cpu_env
, op0
, op1
); break;
4653 static inline void gen_neon_mull(TCGv_i64 dest
, TCGv_i32 a
, TCGv_i32 b
,
4658 switch ((size
<< 1) | u
) {
4659 case 0: gen_helper_neon_mull_s8(dest
, a
, b
); break;
4660 case 1: gen_helper_neon_mull_u8(dest
, a
, b
); break;
4661 case 2: gen_helper_neon_mull_s16(dest
, a
, b
); break;
4662 case 3: gen_helper_neon_mull_u16(dest
, a
, b
); break;
4664 tmp
= gen_muls_i64_i32(a
, b
);
4665 tcg_gen_mov_i64(dest
, tmp
);
4666 tcg_temp_free_i64(tmp
);
4669 tmp
= gen_mulu_i64_i32(a
, b
);
4670 tcg_gen_mov_i64(dest
, tmp
);
4671 tcg_temp_free_i64(tmp
);
4676 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
4677 Don't forget to clean them now. */
4679 tcg_temp_free_i32(a
);
4680 tcg_temp_free_i32(b
);
4684 static void gen_neon_narrow_op(int op
, int u
, int size
,
4685 TCGv_i32 dest
, TCGv_i64 src
)
4689 gen_neon_unarrow_sats(size
, dest
, src
);
4691 gen_neon_narrow(size
, dest
, src
);
4695 gen_neon_narrow_satu(size
, dest
, src
);
4697 gen_neon_narrow_sats(size
, dest
, src
);
4702 /* Symbolic constants for op fields for Neon 3-register same-length.
4703 * The values correspond to bits [11:8,4]; see the ARM ARM DDI0406B
4706 #define NEON_3R_VHADD 0
4707 #define NEON_3R_VQADD 1
4708 #define NEON_3R_VRHADD 2
4709 #define NEON_3R_LOGIC 3 /* VAND,VBIC,VORR,VMOV,VORN,VEOR,VBIF,VBIT,VBSL */
4710 #define NEON_3R_VHSUB 4
4711 #define NEON_3R_VQSUB 5
4712 #define NEON_3R_VCGT 6
4713 #define NEON_3R_VCGE 7
4714 #define NEON_3R_VSHL 8
4715 #define NEON_3R_VQSHL 9
4716 #define NEON_3R_VRSHL 10
4717 #define NEON_3R_VQRSHL 11
4718 #define NEON_3R_VMAX 12
4719 #define NEON_3R_VMIN 13
4720 #define NEON_3R_VABD 14
4721 #define NEON_3R_VABA 15
4722 #define NEON_3R_VADD_VSUB 16
4723 #define NEON_3R_VTST_VCEQ 17
4724 #define NEON_3R_VML 18 /* VMLA, VMLAL, VMLS, VMLSL */
4725 #define NEON_3R_VMUL 19
4726 #define NEON_3R_VPMAX 20
4727 #define NEON_3R_VPMIN 21
4728 #define NEON_3R_VQDMULH_VQRDMULH 22
4729 #define NEON_3R_VPADD 23
4730 #define NEON_3R_VFM 25 /* VFMA, VFMS : float fused multiply-add */
4731 #define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */
4732 #define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */
4733 #define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */
4734 #define NEON_3R_FLOAT_ACMP 29 /* float VACGE, VACGT, VACLE, VACLT */
4735 #define NEON_3R_FLOAT_MINMAX 30 /* float VMIN, VMAX */
4736 #define NEON_3R_FLOAT_MISC 31 /* float VRECPS, VRSQRTS, VMAXNM/MINNM */
4738 static const uint8_t neon_3r_sizes
[] = {
4739 [NEON_3R_VHADD
] = 0x7,
4740 [NEON_3R_VQADD
] = 0xf,
4741 [NEON_3R_VRHADD
] = 0x7,
4742 [NEON_3R_LOGIC
] = 0xf, /* size field encodes op type */
4743 [NEON_3R_VHSUB
] = 0x7,
4744 [NEON_3R_VQSUB
] = 0xf,
4745 [NEON_3R_VCGT
] = 0x7,
4746 [NEON_3R_VCGE
] = 0x7,
4747 [NEON_3R_VSHL
] = 0xf,
4748 [NEON_3R_VQSHL
] = 0xf,
4749 [NEON_3R_VRSHL
] = 0xf,
4750 [NEON_3R_VQRSHL
] = 0xf,
4751 [NEON_3R_VMAX
] = 0x7,
4752 [NEON_3R_VMIN
] = 0x7,
4753 [NEON_3R_VABD
] = 0x7,
4754 [NEON_3R_VABA
] = 0x7,
4755 [NEON_3R_VADD_VSUB
] = 0xf,
4756 [NEON_3R_VTST_VCEQ
] = 0x7,
4757 [NEON_3R_VML
] = 0x7,
4758 [NEON_3R_VMUL
] = 0x7,
4759 [NEON_3R_VPMAX
] = 0x7,
4760 [NEON_3R_VPMIN
] = 0x7,
4761 [NEON_3R_VQDMULH_VQRDMULH
] = 0x6,
4762 [NEON_3R_VPADD
] = 0x7,
4763 [NEON_3R_VFM
] = 0x5, /* size bit 1 encodes op */
4764 [NEON_3R_FLOAT_ARITH
] = 0x5, /* size bit 1 encodes op */
4765 [NEON_3R_FLOAT_MULTIPLY
] = 0x5, /* size bit 1 encodes op */
4766 [NEON_3R_FLOAT_CMP
] = 0x5, /* size bit 1 encodes op */
4767 [NEON_3R_FLOAT_ACMP
] = 0x5, /* size bit 1 encodes op */
4768 [NEON_3R_FLOAT_MINMAX
] = 0x5, /* size bit 1 encodes op */
4769 [NEON_3R_FLOAT_MISC
] = 0x5, /* size bit 1 encodes op */
4772 /* Symbolic constants for op fields for Neon 2-register miscellaneous.
4773 * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B
4776 #define NEON_2RM_VREV64 0
4777 #define NEON_2RM_VREV32 1
4778 #define NEON_2RM_VREV16 2
4779 #define NEON_2RM_VPADDL 4
4780 #define NEON_2RM_VPADDL_U 5
4781 #define NEON_2RM_AESE 6 /* Includes AESD */
4782 #define NEON_2RM_AESMC 7 /* Includes AESIMC */
4783 #define NEON_2RM_VCLS 8
4784 #define NEON_2RM_VCLZ 9
4785 #define NEON_2RM_VCNT 10
4786 #define NEON_2RM_VMVN 11
4787 #define NEON_2RM_VPADAL 12
4788 #define NEON_2RM_VPADAL_U 13
4789 #define NEON_2RM_VQABS 14
4790 #define NEON_2RM_VQNEG 15
4791 #define NEON_2RM_VCGT0 16
4792 #define NEON_2RM_VCGE0 17
4793 #define NEON_2RM_VCEQ0 18
4794 #define NEON_2RM_VCLE0 19
4795 #define NEON_2RM_VCLT0 20
4796 #define NEON_2RM_VABS 22
4797 #define NEON_2RM_VNEG 23
4798 #define NEON_2RM_VCGT0_F 24
4799 #define NEON_2RM_VCGE0_F 25
4800 #define NEON_2RM_VCEQ0_F 26
4801 #define NEON_2RM_VCLE0_F 27
4802 #define NEON_2RM_VCLT0_F 28
4803 #define NEON_2RM_VABS_F 30
4804 #define NEON_2RM_VNEG_F 31
4805 #define NEON_2RM_VSWP 32
4806 #define NEON_2RM_VTRN 33
4807 #define NEON_2RM_VUZP 34
4808 #define NEON_2RM_VZIP 35
4809 #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
4810 #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
4811 #define NEON_2RM_VSHLL 38
4812 #define NEON_2RM_VRINTN 40
4813 #define NEON_2RM_VRINTX 41
4814 #define NEON_2RM_VRINTA 42
4815 #define NEON_2RM_VRINTZ 43
4816 #define NEON_2RM_VCVT_F16_F32 44
4817 #define NEON_2RM_VRINTM 45
4818 #define NEON_2RM_VCVT_F32_F16 46
4819 #define NEON_2RM_VRINTP 47
4820 #define NEON_2RM_VCVTAU 48
4821 #define NEON_2RM_VCVTAS 49
4822 #define NEON_2RM_VCVTNU 50
4823 #define NEON_2RM_VCVTNS 51
4824 #define NEON_2RM_VCVTPU 52
4825 #define NEON_2RM_VCVTPS 53
4826 #define NEON_2RM_VCVTMU 54
4827 #define NEON_2RM_VCVTMS 55
4828 #define NEON_2RM_VRECPE 56
4829 #define NEON_2RM_VRSQRTE 57
4830 #define NEON_2RM_VRECPE_F 58
4831 #define NEON_2RM_VRSQRTE_F 59
4832 #define NEON_2RM_VCVT_FS 60
4833 #define NEON_2RM_VCVT_FU 61
4834 #define NEON_2RM_VCVT_SF 62
4835 #define NEON_2RM_VCVT_UF 63
4837 static int neon_2rm_is_float_op(int op
)
4839 /* Return true if this neon 2reg-misc op is float-to-float */
4840 return (op
== NEON_2RM_VABS_F
|| op
== NEON_2RM_VNEG_F
||
4841 (op
>= NEON_2RM_VRINTN
&& op
<= NEON_2RM_VRINTZ
) ||
4842 op
== NEON_2RM_VRINTM
||
4843 (op
>= NEON_2RM_VRINTP
&& op
<= NEON_2RM_VCVTMS
) ||
4844 op
>= NEON_2RM_VRECPE_F
);
4847 /* Each entry in this array has bit n set if the insn allows
4848 * size value n (otherwise it will UNDEF). Since unallocated
4849 * op values will have no bits set they always UNDEF.
4851 static const uint8_t neon_2rm_sizes
[] = {
4852 [NEON_2RM_VREV64
] = 0x7,
4853 [NEON_2RM_VREV32
] = 0x3,
4854 [NEON_2RM_VREV16
] = 0x1,
4855 [NEON_2RM_VPADDL
] = 0x7,
4856 [NEON_2RM_VPADDL_U
] = 0x7,
4857 [NEON_2RM_AESE
] = 0x1,
4858 [NEON_2RM_AESMC
] = 0x1,
4859 [NEON_2RM_VCLS
] = 0x7,
4860 [NEON_2RM_VCLZ
] = 0x7,
4861 [NEON_2RM_VCNT
] = 0x1,
4862 [NEON_2RM_VMVN
] = 0x1,
4863 [NEON_2RM_VPADAL
] = 0x7,
4864 [NEON_2RM_VPADAL_U
] = 0x7,
4865 [NEON_2RM_VQABS
] = 0x7,
4866 [NEON_2RM_VQNEG
] = 0x7,
4867 [NEON_2RM_VCGT0
] = 0x7,
4868 [NEON_2RM_VCGE0
] = 0x7,
4869 [NEON_2RM_VCEQ0
] = 0x7,
4870 [NEON_2RM_VCLE0
] = 0x7,
4871 [NEON_2RM_VCLT0
] = 0x7,
4872 [NEON_2RM_VABS
] = 0x7,
4873 [NEON_2RM_VNEG
] = 0x7,
4874 [NEON_2RM_VCGT0_F
] = 0x4,
4875 [NEON_2RM_VCGE0_F
] = 0x4,
4876 [NEON_2RM_VCEQ0_F
] = 0x4,
4877 [NEON_2RM_VCLE0_F
] = 0x4,
4878 [NEON_2RM_VCLT0_F
] = 0x4,
4879 [NEON_2RM_VABS_F
] = 0x4,
4880 [NEON_2RM_VNEG_F
] = 0x4,
4881 [NEON_2RM_VSWP
] = 0x1,
4882 [NEON_2RM_VTRN
] = 0x7,
4883 [NEON_2RM_VUZP
] = 0x7,
4884 [NEON_2RM_VZIP
] = 0x7,
4885 [NEON_2RM_VMOVN
] = 0x7,
4886 [NEON_2RM_VQMOVN
] = 0x7,
4887 [NEON_2RM_VSHLL
] = 0x7,
4888 [NEON_2RM_VRINTN
] = 0x4,
4889 [NEON_2RM_VRINTX
] = 0x4,
4890 [NEON_2RM_VRINTA
] = 0x4,
4891 [NEON_2RM_VRINTZ
] = 0x4,
4892 [NEON_2RM_VCVT_F16_F32
] = 0x2,
4893 [NEON_2RM_VRINTM
] = 0x4,
4894 [NEON_2RM_VCVT_F32_F16
] = 0x2,
4895 [NEON_2RM_VRINTP
] = 0x4,
4896 [NEON_2RM_VCVTAU
] = 0x4,
4897 [NEON_2RM_VCVTAS
] = 0x4,
4898 [NEON_2RM_VCVTNU
] = 0x4,
4899 [NEON_2RM_VCVTNS
] = 0x4,
4900 [NEON_2RM_VCVTPU
] = 0x4,
4901 [NEON_2RM_VCVTPS
] = 0x4,
4902 [NEON_2RM_VCVTMU
] = 0x4,
4903 [NEON_2RM_VCVTMS
] = 0x4,
4904 [NEON_2RM_VRECPE
] = 0x4,
4905 [NEON_2RM_VRSQRTE
] = 0x4,
4906 [NEON_2RM_VRECPE_F
] = 0x4,
4907 [NEON_2RM_VRSQRTE_F
] = 0x4,
4908 [NEON_2RM_VCVT_FS
] = 0x4,
4909 [NEON_2RM_VCVT_FU
] = 0x4,
4910 [NEON_2RM_VCVT_SF
] = 0x4,
4911 [NEON_2RM_VCVT_UF
] = 0x4,
4914 /* Translate a NEON data processing instruction. Return nonzero if the
4915 instruction is invalid.
4916 We process data in a mixture of 32-bit and 64-bit chunks.
4917 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
4919 static int disas_neon_data_insn(CPUARMState
* env
, DisasContext
*s
, uint32_t insn
)
4931 TCGv_i32 tmp
, tmp2
, tmp3
, tmp4
, tmp5
;
4934 if (!s
->vfp_enabled
)
4936 q
= (insn
& (1 << 6)) != 0;
4937 u
= (insn
>> 24) & 1;
4938 VFP_DREG_D(rd
, insn
);
4939 VFP_DREG_N(rn
, insn
);
4940 VFP_DREG_M(rm
, insn
);
4941 size
= (insn
>> 20) & 3;
4942 if ((insn
& (1 << 23)) == 0) {
4943 /* Three register same length. */
4944 op
= ((insn
>> 7) & 0x1e) | ((insn
>> 4) & 1);
4945 /* Catch invalid op and bad size combinations: UNDEF */
4946 if ((neon_3r_sizes
[op
] & (1 << size
)) == 0) {
4949 /* All insns of this form UNDEF for either this condition or the
4950 * superset of cases "Q==1"; we catch the latter later.
4952 if (q
&& ((rd
| rn
| rm
) & 1)) {
4955 if (size
== 3 && op
!= NEON_3R_LOGIC
) {
4956 /* 64-bit element instructions. */
4957 for (pass
= 0; pass
< (q
? 2 : 1); pass
++) {
4958 neon_load_reg64(cpu_V0
, rn
+ pass
);
4959 neon_load_reg64(cpu_V1
, rm
+ pass
);
4963 gen_helper_neon_qadd_u64(cpu_V0
, cpu_env
,
4966 gen_helper_neon_qadd_s64(cpu_V0
, cpu_env
,
4972 gen_helper_neon_qsub_u64(cpu_V0
, cpu_env
,
4975 gen_helper_neon_qsub_s64(cpu_V0
, cpu_env
,
4981 gen_helper_neon_shl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
4983 gen_helper_neon_shl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
4988 gen_helper_neon_qshl_u64(cpu_V0
, cpu_env
,
4991 gen_helper_neon_qshl_s64(cpu_V0
, cpu_env
,
4997 gen_helper_neon_rshl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
4999 gen_helper_neon_rshl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
5002 case NEON_3R_VQRSHL
:
5004 gen_helper_neon_qrshl_u64(cpu_V0
, cpu_env
,
5007 gen_helper_neon_qrshl_s64(cpu_V0
, cpu_env
,
5011 case NEON_3R_VADD_VSUB
:
5013 tcg_gen_sub_i64(CPU_V001
);
5015 tcg_gen_add_i64(CPU_V001
);
5021 neon_store_reg64(cpu_V0
, rd
+ pass
);
5030 case NEON_3R_VQRSHL
:
5033 /* Shift instruction operands are reversed. */
5048 case NEON_3R_FLOAT_ARITH
:
5049 pairwise
= (u
&& size
< 2); /* if VPADD (float) */
5051 case NEON_3R_FLOAT_MINMAX
:
5052 pairwise
= u
; /* if VPMIN/VPMAX (float) */
5054 case NEON_3R_FLOAT_CMP
:
5056 /* no encoding for U=0 C=1x */
5060 case NEON_3R_FLOAT_ACMP
:
5065 case NEON_3R_FLOAT_MISC
:
5066 /* VMAXNM/VMINNM in ARMv8 */
5067 if (u
&& !arm_feature(env
, ARM_FEATURE_V8
)) {
5072 if (u
&& (size
!= 0)) {
5073 /* UNDEF on invalid size for polynomial subcase */
5078 if (!arm_feature(env
, ARM_FEATURE_VFP4
) || u
) {
5086 if (pairwise
&& q
) {
5087 /* All the pairwise insns UNDEF if Q is set */
5091 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5096 tmp
= neon_load_reg(rn
, 0);
5097 tmp2
= neon_load_reg(rn
, 1);
5099 tmp
= neon_load_reg(rm
, 0);
5100 tmp2
= neon_load_reg(rm
, 1);
5104 tmp
= neon_load_reg(rn
, pass
);
5105 tmp2
= neon_load_reg(rm
, pass
);
5109 GEN_NEON_INTEGER_OP(hadd
);
5112 GEN_NEON_INTEGER_OP_ENV(qadd
);
5114 case NEON_3R_VRHADD
:
5115 GEN_NEON_INTEGER_OP(rhadd
);
5117 case NEON_3R_LOGIC
: /* Logic ops. */
5118 switch ((u
<< 2) | size
) {
5120 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
5123 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
5126 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
5129 tcg_gen_orc_i32(tmp
, tmp
, tmp2
);
5132 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
5135 tmp3
= neon_load_reg(rd
, pass
);
5136 gen_neon_bsl(tmp
, tmp
, tmp2
, tmp3
);
5137 tcg_temp_free_i32(tmp3
);
5140 tmp3
= neon_load_reg(rd
, pass
);
5141 gen_neon_bsl(tmp
, tmp
, tmp3
, tmp2
);
5142 tcg_temp_free_i32(tmp3
);
5145 tmp3
= neon_load_reg(rd
, pass
);
5146 gen_neon_bsl(tmp
, tmp3
, tmp
, tmp2
);
5147 tcg_temp_free_i32(tmp3
);
5152 GEN_NEON_INTEGER_OP(hsub
);
5155 GEN_NEON_INTEGER_OP_ENV(qsub
);
5158 GEN_NEON_INTEGER_OP(cgt
);
5161 GEN_NEON_INTEGER_OP(cge
);
5164 GEN_NEON_INTEGER_OP(shl
);
5167 GEN_NEON_INTEGER_OP_ENV(qshl
);
5170 GEN_NEON_INTEGER_OP(rshl
);
5172 case NEON_3R_VQRSHL
:
5173 GEN_NEON_INTEGER_OP_ENV(qrshl
);
5176 GEN_NEON_INTEGER_OP(max
);
5179 GEN_NEON_INTEGER_OP(min
);
5182 GEN_NEON_INTEGER_OP(abd
);
5185 GEN_NEON_INTEGER_OP(abd
);
5186 tcg_temp_free_i32(tmp2
);
5187 tmp2
= neon_load_reg(rd
, pass
);
5188 gen_neon_add(size
, tmp
, tmp2
);
5190 case NEON_3R_VADD_VSUB
:
5191 if (!u
) { /* VADD */
5192 gen_neon_add(size
, tmp
, tmp2
);
5195 case 0: gen_helper_neon_sub_u8(tmp
, tmp
, tmp2
); break;
5196 case 1: gen_helper_neon_sub_u16(tmp
, tmp
, tmp2
); break;
5197 case 2: tcg_gen_sub_i32(tmp
, tmp
, tmp2
); break;
5202 case NEON_3R_VTST_VCEQ
:
5203 if (!u
) { /* VTST */
5205 case 0: gen_helper_neon_tst_u8(tmp
, tmp
, tmp2
); break;
5206 case 1: gen_helper_neon_tst_u16(tmp
, tmp
, tmp2
); break;
5207 case 2: gen_helper_neon_tst_u32(tmp
, tmp
, tmp2
); break;
5212 case 0: gen_helper_neon_ceq_u8(tmp
, tmp
, tmp2
); break;
5213 case 1: gen_helper_neon_ceq_u16(tmp
, tmp
, tmp2
); break;
5214 case 2: gen_helper_neon_ceq_u32(tmp
, tmp
, tmp2
); break;
5219 case NEON_3R_VML
: /* VMLA, VMLAL, VMLS,VMLSL */
5221 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
5222 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
5223 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
5226 tcg_temp_free_i32(tmp2
);
5227 tmp2
= neon_load_reg(rd
, pass
);
5229 gen_neon_rsb(size
, tmp
, tmp2
);
5231 gen_neon_add(size
, tmp
, tmp2
);
5235 if (u
) { /* polynomial */
5236 gen_helper_neon_mul_p8(tmp
, tmp
, tmp2
);
5237 } else { /* Integer */
5239 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
5240 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
5241 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
5247 GEN_NEON_INTEGER_OP(pmax
);
5250 GEN_NEON_INTEGER_OP(pmin
);
5252 case NEON_3R_VQDMULH_VQRDMULH
: /* Multiply high. */
5253 if (!u
) { /* VQDMULH */
5256 gen_helper_neon_qdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
5259 gen_helper_neon_qdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
5263 } else { /* VQRDMULH */
5266 gen_helper_neon_qrdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
5269 gen_helper_neon_qrdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
5277 case 0: gen_helper_neon_padd_u8(tmp
, tmp
, tmp2
); break;
5278 case 1: gen_helper_neon_padd_u16(tmp
, tmp
, tmp2
); break;
5279 case 2: tcg_gen_add_i32(tmp
, tmp
, tmp2
); break;
5283 case NEON_3R_FLOAT_ARITH
: /* Floating point arithmetic. */
5285 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5286 switch ((u
<< 2) | size
) {
5289 gen_helper_vfp_adds(tmp
, tmp
, tmp2
, fpstatus
);
5292 gen_helper_vfp_subs(tmp
, tmp
, tmp2
, fpstatus
);
5295 gen_helper_neon_abd_f32(tmp
, tmp
, tmp2
, fpstatus
);
5300 tcg_temp_free_ptr(fpstatus
);
5303 case NEON_3R_FLOAT_MULTIPLY
:
5305 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5306 gen_helper_vfp_muls(tmp
, tmp
, tmp2
, fpstatus
);
5308 tcg_temp_free_i32(tmp2
);
5309 tmp2
= neon_load_reg(rd
, pass
);
5311 gen_helper_vfp_adds(tmp
, tmp
, tmp2
, fpstatus
);
5313 gen_helper_vfp_subs(tmp
, tmp2
, tmp
, fpstatus
);
5316 tcg_temp_free_ptr(fpstatus
);
5319 case NEON_3R_FLOAT_CMP
:
5321 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5323 gen_helper_neon_ceq_f32(tmp
, tmp
, tmp2
, fpstatus
);
5326 gen_helper_neon_cge_f32(tmp
, tmp
, tmp2
, fpstatus
);
5328 gen_helper_neon_cgt_f32(tmp
, tmp
, tmp2
, fpstatus
);
5331 tcg_temp_free_ptr(fpstatus
);
5334 case NEON_3R_FLOAT_ACMP
:
5336 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5338 gen_helper_neon_acge_f32(tmp
, tmp
, tmp2
, fpstatus
);
5340 gen_helper_neon_acgt_f32(tmp
, tmp
, tmp2
, fpstatus
);
5342 tcg_temp_free_ptr(fpstatus
);
5345 case NEON_3R_FLOAT_MINMAX
:
5347 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5349 gen_helper_vfp_maxs(tmp
, tmp
, tmp2
, fpstatus
);
5351 gen_helper_vfp_mins(tmp
, tmp
, tmp2
, fpstatus
);
5353 tcg_temp_free_ptr(fpstatus
);
5356 case NEON_3R_FLOAT_MISC
:
5359 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5361 gen_helper_vfp_maxnums(tmp
, tmp
, tmp2
, fpstatus
);
5363 gen_helper_vfp_minnums(tmp
, tmp
, tmp2
, fpstatus
);
5365 tcg_temp_free_ptr(fpstatus
);
5368 gen_helper_recps_f32(tmp
, tmp
, tmp2
, cpu_env
);
5370 gen_helper_rsqrts_f32(tmp
, tmp
, tmp2
, cpu_env
);
5376 /* VFMA, VFMS: fused multiply-add */
5377 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5378 TCGv_i32 tmp3
= neon_load_reg(rd
, pass
);
5381 gen_helper_vfp_negs(tmp
, tmp
);
5383 gen_helper_vfp_muladds(tmp
, tmp
, tmp2
, tmp3
, fpstatus
);
5384 tcg_temp_free_i32(tmp3
);
5385 tcg_temp_free_ptr(fpstatus
);
5391 tcg_temp_free_i32(tmp2
);
5393 /* Save the result. For elementwise operations we can put it
5394 straight into the destination register. For pairwise operations
5395 we have to be careful to avoid clobbering the source operands. */
5396 if (pairwise
&& rd
== rm
) {
5397 neon_store_scratch(pass
, tmp
);
5399 neon_store_reg(rd
, pass
, tmp
);
5403 if (pairwise
&& rd
== rm
) {
5404 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5405 tmp
= neon_load_scratch(pass
);
5406 neon_store_reg(rd
, pass
, tmp
);
5409 /* End of 3 register same size operations. */
5410 } else if (insn
& (1 << 4)) {
5411 if ((insn
& 0x00380080) != 0) {
5412 /* Two registers and shift. */
5413 op
= (insn
>> 8) & 0xf;
5414 if (insn
& (1 << 7)) {
5422 while ((insn
& (1 << (size
+ 19))) == 0)
5425 shift
= (insn
>> 16) & ((1 << (3 + size
)) - 1);
5426 /* To avoid excessive duplication of ops we implement shift
5427 by immediate using the variable shift operations. */
5429 /* Shift by immediate:
5430 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
5431 if (q
&& ((rd
| rm
) & 1)) {
5434 if (!u
&& (op
== 4 || op
== 6)) {
5437 /* Right shifts are encoded as N - shift, where N is the
5438 element size in bits. */
5440 shift
= shift
- (1 << (size
+ 3));
5448 imm
= (uint8_t) shift
;
5453 imm
= (uint16_t) shift
;
5464 for (pass
= 0; pass
< count
; pass
++) {
5466 neon_load_reg64(cpu_V0
, rm
+ pass
);
5467 tcg_gen_movi_i64(cpu_V1
, imm
);
5472 gen_helper_neon_shl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
5474 gen_helper_neon_shl_s64(cpu_V0
, cpu_V0
, cpu_V1
);
5479 gen_helper_neon_rshl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
5481 gen_helper_neon_rshl_s64(cpu_V0
, cpu_V0
, cpu_V1
);
5484 case 5: /* VSHL, VSLI */
5485 gen_helper_neon_shl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
5487 case 6: /* VQSHLU */
5488 gen_helper_neon_qshlu_s64(cpu_V0
, cpu_env
,
5493 gen_helper_neon_qshl_u64(cpu_V0
, cpu_env
,
5496 gen_helper_neon_qshl_s64(cpu_V0
, cpu_env
,
5501 if (op
== 1 || op
== 3) {
5503 neon_load_reg64(cpu_V1
, rd
+ pass
);
5504 tcg_gen_add_i64(cpu_V0
, cpu_V0
, cpu_V1
);
5505 } else if (op
== 4 || (op
== 5 && u
)) {
5507 neon_load_reg64(cpu_V1
, rd
+ pass
);
5509 if (shift
< -63 || shift
> 63) {
5513 mask
= 0xffffffffffffffffull
>> -shift
;
5515 mask
= 0xffffffffffffffffull
<< shift
;
5518 tcg_gen_andi_i64(cpu_V1
, cpu_V1
, ~mask
);
5519 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
5521 neon_store_reg64(cpu_V0
, rd
+ pass
);
5522 } else { /* size < 3 */
5523 /* Operands in T0 and T1. */
5524 tmp
= neon_load_reg(rm
, pass
);
5525 tmp2
= tcg_temp_new_i32();
5526 tcg_gen_movi_i32(tmp2
, imm
);
5530 GEN_NEON_INTEGER_OP(shl
);
5534 GEN_NEON_INTEGER_OP(rshl
);
5537 case 5: /* VSHL, VSLI */
5539 case 0: gen_helper_neon_shl_u8(tmp
, tmp
, tmp2
); break;
5540 case 1: gen_helper_neon_shl_u16(tmp
, tmp
, tmp2
); break;
5541 case 2: gen_helper_neon_shl_u32(tmp
, tmp
, tmp2
); break;
5545 case 6: /* VQSHLU */
5548 gen_helper_neon_qshlu_s8(tmp
, cpu_env
,
5552 gen_helper_neon_qshlu_s16(tmp
, cpu_env
,
5556 gen_helper_neon_qshlu_s32(tmp
, cpu_env
,
5564 GEN_NEON_INTEGER_OP_ENV(qshl
);
5567 tcg_temp_free_i32(tmp2
);
5569 if (op
== 1 || op
== 3) {
5571 tmp2
= neon_load_reg(rd
, pass
);
5572 gen_neon_add(size
, tmp
, tmp2
);
5573 tcg_temp_free_i32(tmp2
);
5574 } else if (op
== 4 || (op
== 5 && u
)) {
5579 mask
= 0xff >> -shift
;
5581 mask
= (uint8_t)(0xff << shift
);
5587 mask
= 0xffff >> -shift
;
5589 mask
= (uint16_t)(0xffff << shift
);
5593 if (shift
< -31 || shift
> 31) {
5597 mask
= 0xffffffffu
>> -shift
;
5599 mask
= 0xffffffffu
<< shift
;
5605 tmp2
= neon_load_reg(rd
, pass
);
5606 tcg_gen_andi_i32(tmp
, tmp
, mask
);
5607 tcg_gen_andi_i32(tmp2
, tmp2
, ~mask
);
5608 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
5609 tcg_temp_free_i32(tmp2
);
5611 neon_store_reg(rd
, pass
, tmp
);
5614 } else if (op
< 10) {
5615 /* Shift by immediate and narrow:
5616 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
5617 int input_unsigned
= (op
== 8) ? !u
: u
;
5621 shift
= shift
- (1 << (size
+ 3));
5624 tmp64
= tcg_const_i64(shift
);
5625 neon_load_reg64(cpu_V0
, rm
);
5626 neon_load_reg64(cpu_V1
, rm
+ 1);
5627 for (pass
= 0; pass
< 2; pass
++) {
5635 if (input_unsigned
) {
5636 gen_helper_neon_rshl_u64(cpu_V0
, in
, tmp64
);
5638 gen_helper_neon_rshl_s64(cpu_V0
, in
, tmp64
);
5641 if (input_unsigned
) {
5642 gen_helper_neon_shl_u64(cpu_V0
, in
, tmp64
);
5644 gen_helper_neon_shl_s64(cpu_V0
, in
, tmp64
);
5647 tmp
= tcg_temp_new_i32();
5648 gen_neon_narrow_op(op
== 8, u
, size
- 1, tmp
, cpu_V0
);
5649 neon_store_reg(rd
, pass
, tmp
);
5651 tcg_temp_free_i64(tmp64
);
5654 imm
= (uint16_t)shift
;
5658 imm
= (uint32_t)shift
;
5660 tmp2
= tcg_const_i32(imm
);
5661 tmp4
= neon_load_reg(rm
+ 1, 0);
5662 tmp5
= neon_load_reg(rm
+ 1, 1);
5663 for (pass
= 0; pass
< 2; pass
++) {
5665 tmp
= neon_load_reg(rm
, 0);
5669 gen_neon_shift_narrow(size
, tmp
, tmp2
, q
,
5672 tmp3
= neon_load_reg(rm
, 1);
5676 gen_neon_shift_narrow(size
, tmp3
, tmp2
, q
,
5678 tcg_gen_concat_i32_i64(cpu_V0
, tmp
, tmp3
);
5679 tcg_temp_free_i32(tmp
);
5680 tcg_temp_free_i32(tmp3
);
5681 tmp
= tcg_temp_new_i32();
5682 gen_neon_narrow_op(op
== 8, u
, size
- 1, tmp
, cpu_V0
);
5683 neon_store_reg(rd
, pass
, tmp
);
5685 tcg_temp_free_i32(tmp2
);
5687 } else if (op
== 10) {
5689 if (q
|| (rd
& 1)) {
5692 tmp
= neon_load_reg(rm
, 0);
5693 tmp2
= neon_load_reg(rm
, 1);
5694 for (pass
= 0; pass
< 2; pass
++) {
5698 gen_neon_widen(cpu_V0
, tmp
, size
, u
);
5701 /* The shift is less than the width of the source
5702 type, so we can just shift the whole register. */
5703 tcg_gen_shli_i64(cpu_V0
, cpu_V0
, shift
);
5704 /* Widen the result of shift: we need to clear
5705 * the potential overflow bits resulting from
5706 * left bits of the narrow input appearing as
5707 * right bits of left the neighbour narrow
5709 if (size
< 2 || !u
) {
5712 imm
= (0xffu
>> (8 - shift
));
5714 } else if (size
== 1) {
5715 imm
= 0xffff >> (16 - shift
);
5718 imm
= 0xffffffff >> (32 - shift
);
5721 imm64
= imm
| (((uint64_t)imm
) << 32);
5725 tcg_gen_andi_i64(cpu_V0
, cpu_V0
, ~imm64
);
5728 neon_store_reg64(cpu_V0
, rd
+ pass
);
5730 } else if (op
>= 14) {
5731 /* VCVT fixed-point. */
5732 if (!(insn
& (1 << 21)) || (q
&& ((rd
| rm
) & 1))) {
5735 /* We have already masked out the must-be-1 top bit of imm6,
5736 * hence this 32-shift where the ARM ARM has 64-imm6.
5739 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5740 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, pass
));
5743 gen_vfp_ulto(0, shift
, 1);
5745 gen_vfp_slto(0, shift
, 1);
5748 gen_vfp_toul(0, shift
, 1);
5750 gen_vfp_tosl(0, shift
, 1);
5752 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, pass
));
5757 } else { /* (insn & 0x00380080) == 0 */
5759 if (q
&& (rd
& 1)) {
5763 op
= (insn
>> 8) & 0xf;
5764 /* One register and immediate. */
5765 imm
= (u
<< 7) | ((insn
>> 12) & 0x70) | (insn
& 0xf);
5766 invert
= (insn
& (1 << 5)) != 0;
5767 /* Note that op = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
5768 * We choose to not special-case this and will behave as if a
5769 * valid constant encoding of 0 had been given.
5788 imm
= (imm
<< 8) | (imm
<< 24);
5791 imm
= (imm
<< 8) | 0xff;
5794 imm
= (imm
<< 16) | 0xffff;
5797 imm
|= (imm
<< 8) | (imm
<< 16) | (imm
<< 24);
5805 imm
= ((imm
& 0x80) << 24) | ((imm
& 0x3f) << 19)
5806 | ((imm
& 0x40) ? (0x1f << 25) : (1 << 30));
5812 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5813 if (op
& 1 && op
< 12) {
5814 tmp
= neon_load_reg(rd
, pass
);
5816 /* The immediate value has already been inverted, so
5818 tcg_gen_andi_i32(tmp
, tmp
, imm
);
5820 tcg_gen_ori_i32(tmp
, tmp
, imm
);
5824 tmp
= tcg_temp_new_i32();
5825 if (op
== 14 && invert
) {
5829 for (n
= 0; n
< 4; n
++) {
5830 if (imm
& (1 << (n
+ (pass
& 1) * 4)))
5831 val
|= 0xff << (n
* 8);
5833 tcg_gen_movi_i32(tmp
, val
);
5835 tcg_gen_movi_i32(tmp
, imm
);
5838 neon_store_reg(rd
, pass
, tmp
);
5841 } else { /* (insn & 0x00800010 == 0x00800000) */
5843 op
= (insn
>> 8) & 0xf;
5844 if ((insn
& (1 << 6)) == 0) {
5845 /* Three registers of different lengths. */
5849 /* undefreq: bit 0 : UNDEF if size != 0
5850 * bit 1 : UNDEF if size == 0
5851 * bit 2 : UNDEF if U == 1
5852 * Note that [1:0] set implies 'always UNDEF'
5855 /* prewiden, src1_wide, src2_wide, undefreq */
5856 static const int neon_3reg_wide
[16][4] = {
5857 {1, 0, 0, 0}, /* VADDL */
5858 {1, 1, 0, 0}, /* VADDW */
5859 {1, 0, 0, 0}, /* VSUBL */
5860 {1, 1, 0, 0}, /* VSUBW */
5861 {0, 1, 1, 0}, /* VADDHN */
5862 {0, 0, 0, 0}, /* VABAL */
5863 {0, 1, 1, 0}, /* VSUBHN */
5864 {0, 0, 0, 0}, /* VABDL */
5865 {0, 0, 0, 0}, /* VMLAL */
5866 {0, 0, 0, 6}, /* VQDMLAL */
5867 {0, 0, 0, 0}, /* VMLSL */
5868 {0, 0, 0, 6}, /* VQDMLSL */
5869 {0, 0, 0, 0}, /* Integer VMULL */
5870 {0, 0, 0, 2}, /* VQDMULL */
5871 {0, 0, 0, 5}, /* Polynomial VMULL */
5872 {0, 0, 0, 3}, /* Reserved: always UNDEF */
5875 prewiden
= neon_3reg_wide
[op
][0];
5876 src1_wide
= neon_3reg_wide
[op
][1];
5877 src2_wide
= neon_3reg_wide
[op
][2];
5878 undefreq
= neon_3reg_wide
[op
][3];
5880 if (((undefreq
& 1) && (size
!= 0)) ||
5881 ((undefreq
& 2) && (size
== 0)) ||
5882 ((undefreq
& 4) && u
)) {
5885 if ((src1_wide
&& (rn
& 1)) ||
5886 (src2_wide
&& (rm
& 1)) ||
5887 (!src2_wide
&& (rd
& 1))) {
5891 /* Avoid overlapping operands. Wide source operands are
5892 always aligned so will never overlap with wide
5893 destinations in problematic ways. */
5894 if (rd
== rm
&& !src2_wide
) {
5895 tmp
= neon_load_reg(rm
, 1);
5896 neon_store_scratch(2, tmp
);
5897 } else if (rd
== rn
&& !src1_wide
) {
5898 tmp
= neon_load_reg(rn
, 1);
5899 neon_store_scratch(2, tmp
);
5901 TCGV_UNUSED_I32(tmp3
);
5902 for (pass
= 0; pass
< 2; pass
++) {
5904 neon_load_reg64(cpu_V0
, rn
+ pass
);
5905 TCGV_UNUSED_I32(tmp
);
5907 if (pass
== 1 && rd
== rn
) {
5908 tmp
= neon_load_scratch(2);
5910 tmp
= neon_load_reg(rn
, pass
);
5913 gen_neon_widen(cpu_V0
, tmp
, size
, u
);
5917 neon_load_reg64(cpu_V1
, rm
+ pass
);
5918 TCGV_UNUSED_I32(tmp2
);
5920 if (pass
== 1 && rd
== rm
) {
5921 tmp2
= neon_load_scratch(2);
5923 tmp2
= neon_load_reg(rm
, pass
);
5926 gen_neon_widen(cpu_V1
, tmp2
, size
, u
);
5930 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
5931 gen_neon_addl(size
);
5933 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
5934 gen_neon_subl(size
);
5936 case 5: case 7: /* VABAL, VABDL */
5937 switch ((size
<< 1) | u
) {
5939 gen_helper_neon_abdl_s16(cpu_V0
, tmp
, tmp2
);
5942 gen_helper_neon_abdl_u16(cpu_V0
, tmp
, tmp2
);
5945 gen_helper_neon_abdl_s32(cpu_V0
, tmp
, tmp2
);
5948 gen_helper_neon_abdl_u32(cpu_V0
, tmp
, tmp2
);
5951 gen_helper_neon_abdl_s64(cpu_V0
, tmp
, tmp2
);
5954 gen_helper_neon_abdl_u64(cpu_V0
, tmp
, tmp2
);
5958 tcg_temp_free_i32(tmp2
);
5959 tcg_temp_free_i32(tmp
);
5961 case 8: case 9: case 10: case 11: case 12: case 13:
5962 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
5963 gen_neon_mull(cpu_V0
, tmp
, tmp2
, size
, u
);
5965 case 14: /* Polynomial VMULL */
5966 gen_helper_neon_mull_p8(cpu_V0
, tmp
, tmp2
);
5967 tcg_temp_free_i32(tmp2
);
5968 tcg_temp_free_i32(tmp
);
5970 default: /* 15 is RESERVED: caught earlier */
5975 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5976 neon_store_reg64(cpu_V0
, rd
+ pass
);
5977 } else if (op
== 5 || (op
>= 8 && op
<= 11)) {
5979 neon_load_reg64(cpu_V1
, rd
+ pass
);
5981 case 10: /* VMLSL */
5982 gen_neon_negl(cpu_V0
, size
);
5984 case 5: case 8: /* VABAL, VMLAL */
5985 gen_neon_addl(size
);
5987 case 9: case 11: /* VQDMLAL, VQDMLSL */
5988 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5990 gen_neon_negl(cpu_V0
, size
);
5992 gen_neon_addl_saturate(cpu_V0
, cpu_V1
, size
);
5997 neon_store_reg64(cpu_V0
, rd
+ pass
);
5998 } else if (op
== 4 || op
== 6) {
5999 /* Narrowing operation. */
6000 tmp
= tcg_temp_new_i32();
6004 gen_helper_neon_narrow_high_u8(tmp
, cpu_V0
);
6007 gen_helper_neon_narrow_high_u16(tmp
, cpu_V0
);
6010 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
6011 tcg_gen_trunc_i64_i32(tmp
, cpu_V0
);
6018 gen_helper_neon_narrow_round_high_u8(tmp
, cpu_V0
);
6021 gen_helper_neon_narrow_round_high_u16(tmp
, cpu_V0
);
6024 tcg_gen_addi_i64(cpu_V0
, cpu_V0
, 1u << 31);
6025 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
6026 tcg_gen_trunc_i64_i32(tmp
, cpu_V0
);
6034 neon_store_reg(rd
, 0, tmp3
);
6035 neon_store_reg(rd
, 1, tmp
);
6038 /* Write back the result. */
6039 neon_store_reg64(cpu_V0
, rd
+ pass
);
6043 /* Two registers and a scalar. NB that for ops of this form
6044 * the ARM ARM labels bit 24 as Q, but it is in our variable
6051 case 1: /* Float VMLA scalar */
6052 case 5: /* Floating point VMLS scalar */
6053 case 9: /* Floating point VMUL scalar */
6058 case 0: /* Integer VMLA scalar */
6059 case 4: /* Integer VMLS scalar */
6060 case 8: /* Integer VMUL scalar */
6061 case 12: /* VQDMULH scalar */
6062 case 13: /* VQRDMULH scalar */
6063 if (u
&& ((rd
| rn
) & 1)) {
6066 tmp
= neon_get_scalar(size
, rm
);
6067 neon_store_scratch(0, tmp
);
6068 for (pass
= 0; pass
< (u
? 4 : 2); pass
++) {
6069 tmp
= neon_load_scratch(0);
6070 tmp2
= neon_load_reg(rn
, pass
);
6073 gen_helper_neon_qdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
6075 gen_helper_neon_qdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
6077 } else if (op
== 13) {
6079 gen_helper_neon_qrdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
6081 gen_helper_neon_qrdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
6083 } else if (op
& 1) {
6084 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6085 gen_helper_vfp_muls(tmp
, tmp
, tmp2
, fpstatus
);
6086 tcg_temp_free_ptr(fpstatus
);
6089 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
6090 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
6091 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
6095 tcg_temp_free_i32(tmp2
);
6098 tmp2
= neon_load_reg(rd
, pass
);
6101 gen_neon_add(size
, tmp
, tmp2
);
6105 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6106 gen_helper_vfp_adds(tmp
, tmp
, tmp2
, fpstatus
);
6107 tcg_temp_free_ptr(fpstatus
);
6111 gen_neon_rsb(size
, tmp
, tmp2
);
6115 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6116 gen_helper_vfp_subs(tmp
, tmp2
, tmp
, fpstatus
);
6117 tcg_temp_free_ptr(fpstatus
);
6123 tcg_temp_free_i32(tmp2
);
6125 neon_store_reg(rd
, pass
, tmp
);
6128 case 3: /* VQDMLAL scalar */
6129 case 7: /* VQDMLSL scalar */
6130 case 11: /* VQDMULL scalar */
6135 case 2: /* VMLAL sclar */
6136 case 6: /* VMLSL scalar */
6137 case 10: /* VMULL scalar */
6141 tmp2
= neon_get_scalar(size
, rm
);
6142 /* We need a copy of tmp2 because gen_neon_mull
6143 * deletes it during pass 0. */
6144 tmp4
= tcg_temp_new_i32();
6145 tcg_gen_mov_i32(tmp4
, tmp2
);
6146 tmp3
= neon_load_reg(rn
, 1);
6148 for (pass
= 0; pass
< 2; pass
++) {
6150 tmp
= neon_load_reg(rn
, 0);
6155 gen_neon_mull(cpu_V0
, tmp
, tmp2
, size
, u
);
6157 neon_load_reg64(cpu_V1
, rd
+ pass
);
6161 gen_neon_negl(cpu_V0
, size
);
6164 gen_neon_addl(size
);
6167 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
6169 gen_neon_negl(cpu_V0
, size
);
6171 gen_neon_addl_saturate(cpu_V0
, cpu_V1
, size
);
6177 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
6182 neon_store_reg64(cpu_V0
, rd
+ pass
);
6187 default: /* 14 and 15 are RESERVED */
6191 } else { /* size == 3 */
6194 imm
= (insn
>> 8) & 0xf;
6199 if (q
&& ((rd
| rn
| rm
) & 1)) {
6204 neon_load_reg64(cpu_V0
, rn
);
6206 neon_load_reg64(cpu_V1
, rn
+ 1);
6208 } else if (imm
== 8) {
6209 neon_load_reg64(cpu_V0
, rn
+ 1);
6211 neon_load_reg64(cpu_V1
, rm
);
6214 tmp64
= tcg_temp_new_i64();
6216 neon_load_reg64(cpu_V0
, rn
);
6217 neon_load_reg64(tmp64
, rn
+ 1);
6219 neon_load_reg64(cpu_V0
, rn
+ 1);
6220 neon_load_reg64(tmp64
, rm
);
6222 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, (imm
& 7) * 8);
6223 tcg_gen_shli_i64(cpu_V1
, tmp64
, 64 - ((imm
& 7) * 8));
6224 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
6226 neon_load_reg64(cpu_V1
, rm
);
6228 neon_load_reg64(cpu_V1
, rm
+ 1);
6231 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
6232 tcg_gen_shri_i64(tmp64
, tmp64
, imm
* 8);
6233 tcg_gen_or_i64(cpu_V1
, cpu_V1
, tmp64
);
6234 tcg_temp_free_i64(tmp64
);
6237 neon_load_reg64(cpu_V0
, rn
);
6238 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, imm
* 8);
6239 neon_load_reg64(cpu_V1
, rm
);
6240 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
6241 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
6243 neon_store_reg64(cpu_V0
, rd
);
6245 neon_store_reg64(cpu_V1
, rd
+ 1);
6247 } else if ((insn
& (1 << 11)) == 0) {
6248 /* Two register misc. */
6249 op
= ((insn
>> 12) & 0x30) | ((insn
>> 7) & 0xf);
6250 size
= (insn
>> 18) & 3;
6251 /* UNDEF for unknown op values and bad op-size combinations */
6252 if ((neon_2rm_sizes
[op
] & (1 << size
)) == 0) {
6255 if ((op
!= NEON_2RM_VMOVN
&& op
!= NEON_2RM_VQMOVN
) &&
6256 q
&& ((rm
| rd
) & 1)) {
6260 case NEON_2RM_VREV64
:
6261 for (pass
= 0; pass
< (q
? 2 : 1); pass
++) {
6262 tmp
= neon_load_reg(rm
, pass
* 2);
6263 tmp2
= neon_load_reg(rm
, pass
* 2 + 1);
6265 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
6266 case 1: gen_swap_half(tmp
); break;
6267 case 2: /* no-op */ break;
6270 neon_store_reg(rd
, pass
* 2 + 1, tmp
);
6272 neon_store_reg(rd
, pass
* 2, tmp2
);
6275 case 0: tcg_gen_bswap32_i32(tmp2
, tmp2
); break;
6276 case 1: gen_swap_half(tmp2
); break;
6279 neon_store_reg(rd
, pass
* 2, tmp2
);
6283 case NEON_2RM_VPADDL
: case NEON_2RM_VPADDL_U
:
6284 case NEON_2RM_VPADAL
: case NEON_2RM_VPADAL_U
:
6285 for (pass
= 0; pass
< q
+ 1; pass
++) {
6286 tmp
= neon_load_reg(rm
, pass
* 2);
6287 gen_neon_widen(cpu_V0
, tmp
, size
, op
& 1);
6288 tmp
= neon_load_reg(rm
, pass
* 2 + 1);
6289 gen_neon_widen(cpu_V1
, tmp
, size
, op
& 1);
6291 case 0: gen_helper_neon_paddl_u16(CPU_V001
); break;
6292 case 1: gen_helper_neon_paddl_u32(CPU_V001
); break;
6293 case 2: tcg_gen_add_i64(CPU_V001
); break;
6296 if (op
>= NEON_2RM_VPADAL
) {
6298 neon_load_reg64(cpu_V1
, rd
+ pass
);
6299 gen_neon_addl(size
);
6301 neon_store_reg64(cpu_V0
, rd
+ pass
);
6307 for (n
= 0; n
< (q
? 4 : 2); n
+= 2) {
6308 tmp
= neon_load_reg(rm
, n
);
6309 tmp2
= neon_load_reg(rd
, n
+ 1);
6310 neon_store_reg(rm
, n
, tmp2
);
6311 neon_store_reg(rd
, n
+ 1, tmp
);
6318 if (gen_neon_unzip(rd
, rm
, size
, q
)) {
6323 if (gen_neon_zip(rd
, rm
, size
, q
)) {
6327 case NEON_2RM_VMOVN
: case NEON_2RM_VQMOVN
:
6328 /* also VQMOVUN; op field and mnemonics don't line up */
6332 TCGV_UNUSED_I32(tmp2
);
6333 for (pass
= 0; pass
< 2; pass
++) {
6334 neon_load_reg64(cpu_V0
, rm
+ pass
);
6335 tmp
= tcg_temp_new_i32();
6336 gen_neon_narrow_op(op
== NEON_2RM_VMOVN
, q
, size
,
6341 neon_store_reg(rd
, 0, tmp2
);
6342 neon_store_reg(rd
, 1, tmp
);
6346 case NEON_2RM_VSHLL
:
6347 if (q
|| (rd
& 1)) {
6350 tmp
= neon_load_reg(rm
, 0);
6351 tmp2
= neon_load_reg(rm
, 1);
6352 for (pass
= 0; pass
< 2; pass
++) {
6355 gen_neon_widen(cpu_V0
, tmp
, size
, 1);
6356 tcg_gen_shli_i64(cpu_V0
, cpu_V0
, 8 << size
);
6357 neon_store_reg64(cpu_V0
, rd
+ pass
);
6360 case NEON_2RM_VCVT_F16_F32
:
6361 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
) ||
6365 tmp
= tcg_temp_new_i32();
6366 tmp2
= tcg_temp_new_i32();
6367 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 0));
6368 gen_helper_neon_fcvt_f32_to_f16(tmp
, cpu_F0s
, cpu_env
);
6369 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 1));
6370 gen_helper_neon_fcvt_f32_to_f16(tmp2
, cpu_F0s
, cpu_env
);
6371 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
6372 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
6373 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 2));
6374 gen_helper_neon_fcvt_f32_to_f16(tmp
, cpu_F0s
, cpu_env
);
6375 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 3));
6376 neon_store_reg(rd
, 0, tmp2
);
6377 tmp2
= tcg_temp_new_i32();
6378 gen_helper_neon_fcvt_f32_to_f16(tmp2
, cpu_F0s
, cpu_env
);
6379 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
6380 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
6381 neon_store_reg(rd
, 1, tmp2
);
6382 tcg_temp_free_i32(tmp
);
6384 case NEON_2RM_VCVT_F32_F16
:
6385 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
) ||
6389 tmp3
= tcg_temp_new_i32();
6390 tmp
= neon_load_reg(rm
, 0);
6391 tmp2
= neon_load_reg(rm
, 1);
6392 tcg_gen_ext16u_i32(tmp3
, tmp
);
6393 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
6394 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 0));
6395 tcg_gen_shri_i32(tmp3
, tmp
, 16);
6396 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
6397 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 1));
6398 tcg_temp_free_i32(tmp
);
6399 tcg_gen_ext16u_i32(tmp3
, tmp2
);
6400 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
6401 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 2));
6402 tcg_gen_shri_i32(tmp3
, tmp2
, 16);
6403 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
6404 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 3));
6405 tcg_temp_free_i32(tmp2
);
6406 tcg_temp_free_i32(tmp3
);
6408 case NEON_2RM_AESE
: case NEON_2RM_AESMC
:
6409 if (!arm_feature(env
, ARM_FEATURE_V8_AES
)
6410 || ((rm
| rd
) & 1)) {
6413 tmp
= tcg_const_i32(rd
);
6414 tmp2
= tcg_const_i32(rm
);
6416 /* Bit 6 is the lowest opcode bit; it distinguishes between
6417 * encryption (AESE/AESMC) and decryption (AESD/AESIMC)
6419 tmp3
= tcg_const_i32(extract32(insn
, 6, 1));
6421 if (op
== NEON_2RM_AESE
) {
6422 gen_helper_crypto_aese(cpu_env
, tmp
, tmp2
, tmp3
);
6424 gen_helper_crypto_aesmc(cpu_env
, tmp
, tmp2
, tmp3
);
6426 tcg_temp_free_i32(tmp
);
6427 tcg_temp_free_i32(tmp2
);
6428 tcg_temp_free_i32(tmp3
);
6432 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
6433 if (neon_2rm_is_float_op(op
)) {
6434 tcg_gen_ld_f32(cpu_F0s
, cpu_env
,
6435 neon_reg_offset(rm
, pass
));
6436 TCGV_UNUSED_I32(tmp
);
6438 tmp
= neon_load_reg(rm
, pass
);
6441 case NEON_2RM_VREV32
:
6443 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
6444 case 1: gen_swap_half(tmp
); break;
6448 case NEON_2RM_VREV16
:
6453 case 0: gen_helper_neon_cls_s8(tmp
, tmp
); break;
6454 case 1: gen_helper_neon_cls_s16(tmp
, tmp
); break;
6455 case 2: gen_helper_neon_cls_s32(tmp
, tmp
); break;
6461 case 0: gen_helper_neon_clz_u8(tmp
, tmp
); break;
6462 case 1: gen_helper_neon_clz_u16(tmp
, tmp
); break;
6463 case 2: gen_helper_clz(tmp
, tmp
); break;
6468 gen_helper_neon_cnt_u8(tmp
, tmp
);
6471 tcg_gen_not_i32(tmp
, tmp
);
6473 case NEON_2RM_VQABS
:
6476 gen_helper_neon_qabs_s8(tmp
, cpu_env
, tmp
);
6479 gen_helper_neon_qabs_s16(tmp
, cpu_env
, tmp
);
6482 gen_helper_neon_qabs_s32(tmp
, cpu_env
, tmp
);
6487 case NEON_2RM_VQNEG
:
6490 gen_helper_neon_qneg_s8(tmp
, cpu_env
, tmp
);
6493 gen_helper_neon_qneg_s16(tmp
, cpu_env
, tmp
);
6496 gen_helper_neon_qneg_s32(tmp
, cpu_env
, tmp
);
6501 case NEON_2RM_VCGT0
: case NEON_2RM_VCLE0
:
6502 tmp2
= tcg_const_i32(0);
6504 case 0: gen_helper_neon_cgt_s8(tmp
, tmp
, tmp2
); break;
6505 case 1: gen_helper_neon_cgt_s16(tmp
, tmp
, tmp2
); break;
6506 case 2: gen_helper_neon_cgt_s32(tmp
, tmp
, tmp2
); break;
6509 tcg_temp_free_i32(tmp2
);
6510 if (op
== NEON_2RM_VCLE0
) {
6511 tcg_gen_not_i32(tmp
, tmp
);
6514 case NEON_2RM_VCGE0
: case NEON_2RM_VCLT0
:
6515 tmp2
= tcg_const_i32(0);
6517 case 0: gen_helper_neon_cge_s8(tmp
, tmp
, tmp2
); break;
6518 case 1: gen_helper_neon_cge_s16(tmp
, tmp
, tmp2
); break;
6519 case 2: gen_helper_neon_cge_s32(tmp
, tmp
, tmp2
); break;
6522 tcg_temp_free_i32(tmp2
);
6523 if (op
== NEON_2RM_VCLT0
) {
6524 tcg_gen_not_i32(tmp
, tmp
);
6527 case NEON_2RM_VCEQ0
:
6528 tmp2
= tcg_const_i32(0);
6530 case 0: gen_helper_neon_ceq_u8(tmp
, tmp
, tmp2
); break;
6531 case 1: gen_helper_neon_ceq_u16(tmp
, tmp
, tmp2
); break;
6532 case 2: gen_helper_neon_ceq_u32(tmp
, tmp
, tmp2
); break;
6535 tcg_temp_free_i32(tmp2
);
6539 case 0: gen_helper_neon_abs_s8(tmp
, tmp
); break;
6540 case 1: gen_helper_neon_abs_s16(tmp
, tmp
); break;
6541 case 2: tcg_gen_abs_i32(tmp
, tmp
); break;
6546 tmp2
= tcg_const_i32(0);
6547 gen_neon_rsb(size
, tmp
, tmp2
);
6548 tcg_temp_free_i32(tmp2
);
6550 case NEON_2RM_VCGT0_F
:
6552 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6553 tmp2
= tcg_const_i32(0);
6554 gen_helper_neon_cgt_f32(tmp
, tmp
, tmp2
, fpstatus
);
6555 tcg_temp_free_i32(tmp2
);
6556 tcg_temp_free_ptr(fpstatus
);
6559 case NEON_2RM_VCGE0_F
:
6561 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6562 tmp2
= tcg_const_i32(0);
6563 gen_helper_neon_cge_f32(tmp
, tmp
, tmp2
, fpstatus
);
6564 tcg_temp_free_i32(tmp2
);
6565 tcg_temp_free_ptr(fpstatus
);
6568 case NEON_2RM_VCEQ0_F
:
6570 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6571 tmp2
= tcg_const_i32(0);
6572 gen_helper_neon_ceq_f32(tmp
, tmp
, tmp2
, fpstatus
);
6573 tcg_temp_free_i32(tmp2
);
6574 tcg_temp_free_ptr(fpstatus
);
6577 case NEON_2RM_VCLE0_F
:
6579 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6580 tmp2
= tcg_const_i32(0);
6581 gen_helper_neon_cge_f32(tmp
, tmp2
, tmp
, fpstatus
);
6582 tcg_temp_free_i32(tmp2
);
6583 tcg_temp_free_ptr(fpstatus
);
6586 case NEON_2RM_VCLT0_F
:
6588 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6589 tmp2
= tcg_const_i32(0);
6590 gen_helper_neon_cgt_f32(tmp
, tmp2
, tmp
, fpstatus
);
6591 tcg_temp_free_i32(tmp2
);
6592 tcg_temp_free_ptr(fpstatus
);
6595 case NEON_2RM_VABS_F
:
6598 case NEON_2RM_VNEG_F
:
6602 tmp2
= neon_load_reg(rd
, pass
);
6603 neon_store_reg(rm
, pass
, tmp2
);
6606 tmp2
= neon_load_reg(rd
, pass
);
6608 case 0: gen_neon_trn_u8(tmp
, tmp2
); break;
6609 case 1: gen_neon_trn_u16(tmp
, tmp2
); break;
6612 neon_store_reg(rm
, pass
, tmp2
);
6614 case NEON_2RM_VRINTN
:
6615 case NEON_2RM_VRINTA
:
6616 case NEON_2RM_VRINTM
:
6617 case NEON_2RM_VRINTP
:
6618 case NEON_2RM_VRINTZ
:
6621 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6624 if (op
== NEON_2RM_VRINTZ
) {
6625 rmode
= FPROUNDING_ZERO
;
6627 rmode
= fp_decode_rm
[((op
& 0x6) >> 1) ^ 1];
6630 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6631 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
6633 gen_helper_rints(cpu_F0s
, cpu_F0s
, fpstatus
);
6634 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
6636 tcg_temp_free_ptr(fpstatus
);
6637 tcg_temp_free_i32(tcg_rmode
);
6640 case NEON_2RM_VRINTX
:
6642 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6643 gen_helper_rints_exact(cpu_F0s
, cpu_F0s
, fpstatus
);
6644 tcg_temp_free_ptr(fpstatus
);
6647 case NEON_2RM_VCVTAU
:
6648 case NEON_2RM_VCVTAS
:
6649 case NEON_2RM_VCVTNU
:
6650 case NEON_2RM_VCVTNS
:
6651 case NEON_2RM_VCVTPU
:
6652 case NEON_2RM_VCVTPS
:
6653 case NEON_2RM_VCVTMU
:
6654 case NEON_2RM_VCVTMS
:
6656 bool is_signed
= !extract32(insn
, 7, 1);
6657 TCGv_ptr fpst
= get_fpstatus_ptr(1);
6658 TCGv_i32 tcg_rmode
, tcg_shift
;
6659 int rmode
= fp_decode_rm
[extract32(insn
, 8, 2)];
6661 tcg_shift
= tcg_const_i32(0);
6662 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6663 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
6667 gen_helper_vfp_tosls(cpu_F0s
, cpu_F0s
,
6670 gen_helper_vfp_touls(cpu_F0s
, cpu_F0s
,
6674 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
6676 tcg_temp_free_i32(tcg_rmode
);
6677 tcg_temp_free_i32(tcg_shift
);
6678 tcg_temp_free_ptr(fpst
);
6681 case NEON_2RM_VRECPE
:
6682 gen_helper_recpe_u32(tmp
, tmp
, cpu_env
);
6684 case NEON_2RM_VRSQRTE
:
6685 gen_helper_rsqrte_u32(tmp
, tmp
, cpu_env
);
6687 case NEON_2RM_VRECPE_F
:
6688 gen_helper_recpe_f32(cpu_F0s
, cpu_F0s
, cpu_env
);
6690 case NEON_2RM_VRSQRTE_F
:
6691 gen_helper_rsqrte_f32(cpu_F0s
, cpu_F0s
, cpu_env
);
6693 case NEON_2RM_VCVT_FS
: /* VCVT.F32.S32 */
6696 case NEON_2RM_VCVT_FU
: /* VCVT.F32.U32 */
6699 case NEON_2RM_VCVT_SF
: /* VCVT.S32.F32 */
6700 gen_vfp_tosiz(0, 1);
6702 case NEON_2RM_VCVT_UF
: /* VCVT.U32.F32 */
6703 gen_vfp_touiz(0, 1);
6706 /* Reserved op values were caught by the
6707 * neon_2rm_sizes[] check earlier.
6711 if (neon_2rm_is_float_op(op
)) {
6712 tcg_gen_st_f32(cpu_F0s
, cpu_env
,
6713 neon_reg_offset(rd
, pass
));
6715 neon_store_reg(rd
, pass
, tmp
);
6720 } else if ((insn
& (1 << 10)) == 0) {
6722 int n
= ((insn
>> 8) & 3) + 1;
6723 if ((rn
+ n
) > 32) {
6724 /* This is UNPREDICTABLE; we choose to UNDEF to avoid the
6725 * helper function running off the end of the register file.
6730 if (insn
& (1 << 6)) {
6731 tmp
= neon_load_reg(rd
, 0);
6733 tmp
= tcg_temp_new_i32();
6734 tcg_gen_movi_i32(tmp
, 0);
6736 tmp2
= neon_load_reg(rm
, 0);
6737 tmp4
= tcg_const_i32(rn
);
6738 tmp5
= tcg_const_i32(n
);
6739 gen_helper_neon_tbl(tmp2
, cpu_env
, tmp2
, tmp
, tmp4
, tmp5
);
6740 tcg_temp_free_i32(tmp
);
6741 if (insn
& (1 << 6)) {
6742 tmp
= neon_load_reg(rd
, 1);
6744 tmp
= tcg_temp_new_i32();
6745 tcg_gen_movi_i32(tmp
, 0);
6747 tmp3
= neon_load_reg(rm
, 1);
6748 gen_helper_neon_tbl(tmp3
, cpu_env
, tmp3
, tmp
, tmp4
, tmp5
);
6749 tcg_temp_free_i32(tmp5
);
6750 tcg_temp_free_i32(tmp4
);
6751 neon_store_reg(rd
, 0, tmp2
);
6752 neon_store_reg(rd
, 1, tmp3
);
6753 tcg_temp_free_i32(tmp
);
6754 } else if ((insn
& 0x380) == 0) {
6756 if ((insn
& (7 << 16)) == 0 || (q
&& (rd
& 1))) {
6759 if (insn
& (1 << 19)) {
6760 tmp
= neon_load_reg(rm
, 1);
6762 tmp
= neon_load_reg(rm
, 0);
6764 if (insn
& (1 << 16)) {
6765 gen_neon_dup_u8(tmp
, ((insn
>> 17) & 3) * 8);
6766 } else if (insn
& (1 << 17)) {
6767 if ((insn
>> 18) & 1)
6768 gen_neon_dup_high16(tmp
);
6770 gen_neon_dup_low16(tmp
);
6772 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
6773 tmp2
= tcg_temp_new_i32();
6774 tcg_gen_mov_i32(tmp2
, tmp
);
6775 neon_store_reg(rd
, pass
, tmp2
);
6777 tcg_temp_free_i32(tmp
);
6786 static int disas_coproc_insn(CPUARMState
* env
, DisasContext
*s
, uint32_t insn
)
6788 int cpnum
, is64
, crn
, crm
, opc1
, opc2
, isread
, rt
, rt2
;
6789 const ARMCPRegInfo
*ri
;
6791 cpnum
= (insn
>> 8) & 0xf;
6792 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
6793 && ((env
->cp15
.c15_cpar
^ 0x3fff) & (1 << cpnum
)))
6796 /* First check for coprocessor space used for actual instructions */
6800 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
6801 return disas_iwmmxt_insn(env
, s
, insn
);
6802 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
6803 return disas_dsp_insn(env
, s
, insn
);
6810 /* Otherwise treat as a generic register access */
6811 is64
= (insn
& (1 << 25)) == 0;
6812 if (!is64
&& ((insn
& (1 << 4)) == 0)) {
6820 opc1
= (insn
>> 4) & 0xf;
6822 rt2
= (insn
>> 16) & 0xf;
6824 crn
= (insn
>> 16) & 0xf;
6825 opc1
= (insn
>> 21) & 7;
6826 opc2
= (insn
>> 5) & 7;
6829 isread
= (insn
>> 20) & 1;
6830 rt
= (insn
>> 12) & 0xf;
6832 ri
= get_arm_cp_reginfo(s
->cp_regs
,
6833 ENCODE_CP_REG(cpnum
, is64
, crn
, crm
, opc1
, opc2
));
6835 /* Check access permissions */
6836 if (!cp_access_ok(s
->current_pl
, ri
, isread
)) {
6841 /* Emit code to perform further access permissions checks at
6842 * runtime; this may result in an exception.
6845 gen_set_pc_im(s
, s
->pc
);
6846 tmpptr
= tcg_const_ptr(ri
);
6847 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
);
6848 tcg_temp_free_ptr(tmpptr
);
6851 /* Handle special cases first */
6852 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
6859 gen_set_pc_im(s
, s
->pc
);
6860 s
->is_jmp
= DISAS_WFI
;
6866 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
6875 if (ri
->type
& ARM_CP_CONST
) {
6876 tmp64
= tcg_const_i64(ri
->resetvalue
);
6877 } else if (ri
->readfn
) {
6879 tmp64
= tcg_temp_new_i64();
6880 tmpptr
= tcg_const_ptr(ri
);
6881 gen_helper_get_cp_reg64(tmp64
, cpu_env
, tmpptr
);
6882 tcg_temp_free_ptr(tmpptr
);
6884 tmp64
= tcg_temp_new_i64();
6885 tcg_gen_ld_i64(tmp64
, cpu_env
, ri
->fieldoffset
);
6887 tmp
= tcg_temp_new_i32();
6888 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
6889 store_reg(s
, rt
, tmp
);
6890 tcg_gen_shri_i64(tmp64
, tmp64
, 32);
6891 tmp
= tcg_temp_new_i32();
6892 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
6893 tcg_temp_free_i64(tmp64
);
6894 store_reg(s
, rt2
, tmp
);
6897 if (ri
->type
& ARM_CP_CONST
) {
6898 tmp
= tcg_const_i32(ri
->resetvalue
);
6899 } else if (ri
->readfn
) {
6901 tmp
= tcg_temp_new_i32();
6902 tmpptr
= tcg_const_ptr(ri
);
6903 gen_helper_get_cp_reg(tmp
, cpu_env
, tmpptr
);
6904 tcg_temp_free_ptr(tmpptr
);
6906 tmp
= load_cpu_offset(ri
->fieldoffset
);
6909 /* Destination register of r15 for 32 bit loads sets
6910 * the condition codes from the high 4 bits of the value
6913 tcg_temp_free_i32(tmp
);
6915 store_reg(s
, rt
, tmp
);
6920 if (ri
->type
& ARM_CP_CONST
) {
6921 /* If not forbidden by access permissions, treat as WI */
6926 TCGv_i32 tmplo
, tmphi
;
6927 TCGv_i64 tmp64
= tcg_temp_new_i64();
6928 tmplo
= load_reg(s
, rt
);
6929 tmphi
= load_reg(s
, rt2
);
6930 tcg_gen_concat_i32_i64(tmp64
, tmplo
, tmphi
);
6931 tcg_temp_free_i32(tmplo
);
6932 tcg_temp_free_i32(tmphi
);
6934 TCGv_ptr tmpptr
= tcg_const_ptr(ri
);
6935 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tmp64
);
6936 tcg_temp_free_ptr(tmpptr
);
6938 tcg_gen_st_i64(tmp64
, cpu_env
, ri
->fieldoffset
);
6940 tcg_temp_free_i64(tmp64
);
6945 tmp
= load_reg(s
, rt
);
6946 tmpptr
= tcg_const_ptr(ri
);
6947 gen_helper_set_cp_reg(cpu_env
, tmpptr
, tmp
);
6948 tcg_temp_free_ptr(tmpptr
);
6949 tcg_temp_free_i32(tmp
);
6951 TCGv_i32 tmp
= load_reg(s
, rt
);
6952 store_cpu_offset(tmp
, ri
->fieldoffset
);
6957 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
6958 /* I/O operations must end the TB here (whether read or write) */
6961 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
6962 /* We default to ending the TB on a coprocessor register write,
6963 * but allow this to be suppressed by the register definition
6964 * (usually only necessary to work around guest bugs).
6972 /* Unknown register; this might be a guest error or a QEMU
6973 * unimplemented feature.
6976 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch32 "
6977 "64 bit system register cp:%d opc1: %d crm:%d\n",
6978 isread
? "read" : "write", cpnum
, opc1
, crm
);
6980 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch32 "
6981 "system register cp:%d opc1:%d crn:%d crm:%d opc2:%d\n",
6982 isread
? "read" : "write", cpnum
, opc1
, crn
, crm
, opc2
);
6989 /* Store a 64-bit value to a register pair. Clobbers val. */
6990 static void gen_storeq_reg(DisasContext
*s
, int rlow
, int rhigh
, TCGv_i64 val
)
6993 tmp
= tcg_temp_new_i32();
6994 tcg_gen_trunc_i64_i32(tmp
, val
);
6995 store_reg(s
, rlow
, tmp
);
6996 tmp
= tcg_temp_new_i32();
6997 tcg_gen_shri_i64(val
, val
, 32);
6998 tcg_gen_trunc_i64_i32(tmp
, val
);
6999 store_reg(s
, rhigh
, tmp
);
7002 /* load a 32-bit value from a register and perform a 64-bit accumulate. */
7003 static void gen_addq_lo(DisasContext
*s
, TCGv_i64 val
, int rlow
)
7008 /* Load value and extend to 64 bits. */
7009 tmp
= tcg_temp_new_i64();
7010 tmp2
= load_reg(s
, rlow
);
7011 tcg_gen_extu_i32_i64(tmp
, tmp2
);
7012 tcg_temp_free_i32(tmp2
);
7013 tcg_gen_add_i64(val
, val
, tmp
);
7014 tcg_temp_free_i64(tmp
);
7017 /* load and add a 64-bit value from a register pair. */
7018 static void gen_addq(DisasContext
*s
, TCGv_i64 val
, int rlow
, int rhigh
)
7024 /* Load 64-bit value rd:rn. */
7025 tmpl
= load_reg(s
, rlow
);
7026 tmph
= load_reg(s
, rhigh
);
7027 tmp
= tcg_temp_new_i64();
7028 tcg_gen_concat_i32_i64(tmp
, tmpl
, tmph
);
7029 tcg_temp_free_i32(tmpl
);
7030 tcg_temp_free_i32(tmph
);
7031 tcg_gen_add_i64(val
, val
, tmp
);
7032 tcg_temp_free_i64(tmp
);
7035 /* Set N and Z flags from hi|lo. */
7036 static void gen_logicq_cc(TCGv_i32 lo
, TCGv_i32 hi
)
7038 tcg_gen_mov_i32(cpu_NF
, hi
);
7039 tcg_gen_or_i32(cpu_ZF
, lo
, hi
);
7042 /* Load/Store exclusive instructions are implemented by remembering
7043 the value/address loaded, and seeing if these are the same
7044 when the store is performed. This should be sufficient to implement
7045 the architecturally mandated semantics, and avoids having to monitor
7048 In system emulation mode only one CPU will be running at once, so
7049 this sequence is effectively atomic. In user emulation mode we
7050 throw an exception and handle the atomic operation elsewhere. */
7051 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
7052 TCGv_i32 addr
, int size
)
7054 TCGv_i32 tmp
= tcg_temp_new_i32();
7058 gen_aa32_ld8u(tmp
, addr
, IS_USER(s
));
7061 gen_aa32_ld16u(tmp
, addr
, IS_USER(s
));
7065 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
7072 TCGv_i32 tmp2
= tcg_temp_new_i32();
7073 TCGv_i32 tmp3
= tcg_temp_new_i32();
7075 tcg_gen_addi_i32(tmp2
, addr
, 4);
7076 gen_aa32_ld32u(tmp3
, tmp2
, IS_USER(s
));
7077 tcg_temp_free_i32(tmp2
);
7078 tcg_gen_concat_i32_i64(cpu_exclusive_val
, tmp
, tmp3
);
7079 store_reg(s
, rt2
, tmp3
);
7081 tcg_gen_extu_i32_i64(cpu_exclusive_val
, tmp
);
7084 store_reg(s
, rt
, tmp
);
7085 tcg_gen_extu_i32_i64(cpu_exclusive_addr
, addr
);
7088 static void gen_clrex(DisasContext
*s
)
7090 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
7093 #ifdef CONFIG_USER_ONLY
7094 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
7095 TCGv_i32 addr
, int size
)
7097 tcg_gen_extu_i32_i64(cpu_exclusive_test
, addr
);
7098 tcg_gen_movi_i32(cpu_exclusive_info
,
7099 size
| (rd
<< 4) | (rt
<< 8) | (rt2
<< 12));
7100 gen_exception_insn(s
, 4, EXCP_STREX
);
7103 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
7104 TCGv_i32 addr
, int size
)
7107 TCGv_i64 val64
, extaddr
;
7111 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
7117 fail_label
= gen_new_label();
7118 done_label
= gen_new_label();
7119 extaddr
= tcg_temp_new_i64();
7120 tcg_gen_extu_i32_i64(extaddr
, addr
);
7121 tcg_gen_brcond_i64(TCG_COND_NE
, extaddr
, cpu_exclusive_addr
, fail_label
);
7122 tcg_temp_free_i64(extaddr
);
7124 tmp
= tcg_temp_new_i32();
7127 gen_aa32_ld8u(tmp
, addr
, IS_USER(s
));
7130 gen_aa32_ld16u(tmp
, addr
, IS_USER(s
));
7134 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
7140 val64
= tcg_temp_new_i64();
7142 TCGv_i32 tmp2
= tcg_temp_new_i32();
7143 TCGv_i32 tmp3
= tcg_temp_new_i32();
7144 tcg_gen_addi_i32(tmp2
, addr
, 4);
7145 gen_aa32_ld32u(tmp3
, tmp2
, IS_USER(s
));
7146 tcg_temp_free_i32(tmp2
);
7147 tcg_gen_concat_i32_i64(val64
, tmp
, tmp3
);
7148 tcg_temp_free_i32(tmp3
);
7150 tcg_gen_extu_i32_i64(val64
, tmp
);
7152 tcg_temp_free_i32(tmp
);
7154 tcg_gen_brcond_i64(TCG_COND_NE
, val64
, cpu_exclusive_val
, fail_label
);
7155 tcg_temp_free_i64(val64
);
7157 tmp
= load_reg(s
, rt
);
7160 gen_aa32_st8(tmp
, addr
, IS_USER(s
));
7163 gen_aa32_st16(tmp
, addr
, IS_USER(s
));
7167 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
7172 tcg_temp_free_i32(tmp
);
7174 tcg_gen_addi_i32(addr
, addr
, 4);
7175 tmp
= load_reg(s
, rt2
);
7176 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
7177 tcg_temp_free_i32(tmp
);
7179 tcg_gen_movi_i32(cpu_R
[rd
], 0);
7180 tcg_gen_br(done_label
);
7181 gen_set_label(fail_label
);
7182 tcg_gen_movi_i32(cpu_R
[rd
], 1);
7183 gen_set_label(done_label
);
7184 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
7191 * @mode: mode field from insn (which stack to store to)
7192 * @amode: addressing mode (DA/IA/DB/IB), encoded as per P,U bits in ARM insn
7193 * @writeback: true if writeback bit set
7195 * Generate code for the SRS (Store Return State) insn.
7197 static void gen_srs(DisasContext
*s
,
7198 uint32_t mode
, uint32_t amode
, bool writeback
)
7201 TCGv_i32 addr
= tcg_temp_new_i32();
7202 TCGv_i32 tmp
= tcg_const_i32(mode
);
7203 gen_helper_get_r13_banked(addr
, cpu_env
, tmp
);
7204 tcg_temp_free_i32(tmp
);
7221 tcg_gen_addi_i32(addr
, addr
, offset
);
7222 tmp
= load_reg(s
, 14);
7223 gen_aa32_st32(tmp
, addr
, 0);
7224 tcg_temp_free_i32(tmp
);
7225 tmp
= load_cpu_field(spsr
);
7226 tcg_gen_addi_i32(addr
, addr
, 4);
7227 gen_aa32_st32(tmp
, addr
, 0);
7228 tcg_temp_free_i32(tmp
);
7246 tcg_gen_addi_i32(addr
, addr
, offset
);
7247 tmp
= tcg_const_i32(mode
);
7248 gen_helper_set_r13_banked(cpu_env
, tmp
, addr
);
7249 tcg_temp_free_i32(tmp
);
7251 tcg_temp_free_i32(addr
);
7254 static void disas_arm_insn(CPUARMState
* env
, DisasContext
*s
)
7256 unsigned int cond
, insn
, val
, op1
, i
, shift
, rm
, rs
, rn
, rd
, sh
;
7263 insn
= arm_ldl_code(env
, s
->pc
, s
->bswap_code
);
7266 /* M variants do not implement ARM mode. */
7271 /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
7272 * choose to UNDEF. In ARMv5 and above the space is used
7273 * for miscellaneous unconditional instructions.
7277 /* Unconditional instructions. */
7278 if (((insn
>> 25) & 7) == 1) {
7279 /* NEON Data processing. */
7280 if (!arm_feature(env
, ARM_FEATURE_NEON
))
7283 if (disas_neon_data_insn(env
, s
, insn
))
7287 if ((insn
& 0x0f100000) == 0x04000000) {
7288 /* NEON load/store. */
7289 if (!arm_feature(env
, ARM_FEATURE_NEON
))
7292 if (disas_neon_ls_insn(env
, s
, insn
))
7296 if ((insn
& 0x0f000e10) == 0x0e000a00) {
7298 if (disas_vfp_insn(env
, s
, insn
)) {
7303 if (((insn
& 0x0f30f000) == 0x0510f000) ||
7304 ((insn
& 0x0f30f010) == 0x0710f000)) {
7305 if ((insn
& (1 << 22)) == 0) {
7307 if (!arm_feature(env
, ARM_FEATURE_V7MP
)) {
7311 /* Otherwise PLD; v5TE+ */
7315 if (((insn
& 0x0f70f000) == 0x0450f000) ||
7316 ((insn
& 0x0f70f010) == 0x0650f000)) {
7318 return; /* PLI; V7 */
7320 if (((insn
& 0x0f700000) == 0x04100000) ||
7321 ((insn
& 0x0f700010) == 0x06100000)) {
7322 if (!arm_feature(env
, ARM_FEATURE_V7MP
)) {
7325 return; /* v7MP: Unallocated memory hint: must NOP */
7328 if ((insn
& 0x0ffffdff) == 0x01010000) {
7331 if (((insn
>> 9) & 1) != s
->bswap_code
) {
7332 /* Dynamic endianness switching not implemented. */
7333 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented setend\n");
7337 } else if ((insn
& 0x0fffff00) == 0x057ff000) {
7338 switch ((insn
>> 4) & 0xf) {
7347 /* We don't emulate caches so these are a no-op. */
7352 } else if ((insn
& 0x0e5fffe0) == 0x084d0500) {
7358 gen_srs(s
, (insn
& 0x1f), (insn
>> 23) & 3, insn
& (1 << 21));
7360 } else if ((insn
& 0x0e50ffe0) == 0x08100a00) {
7366 rn
= (insn
>> 16) & 0xf;
7367 addr
= load_reg(s
, rn
);
7368 i
= (insn
>> 23) & 3;
7370 case 0: offset
= -4; break; /* DA */
7371 case 1: offset
= 0; break; /* IA */
7372 case 2: offset
= -8; break; /* DB */
7373 case 3: offset
= 4; break; /* IB */
7377 tcg_gen_addi_i32(addr
, addr
, offset
);
7378 /* Load PC into tmp and CPSR into tmp2. */
7379 tmp
= tcg_temp_new_i32();
7380 gen_aa32_ld32u(tmp
, addr
, 0);
7381 tcg_gen_addi_i32(addr
, addr
, 4);
7382 tmp2
= tcg_temp_new_i32();
7383 gen_aa32_ld32u(tmp2
, addr
, 0);
7384 if (insn
& (1 << 21)) {
7385 /* Base writeback. */
7387 case 0: offset
= -8; break;
7388 case 1: offset
= 4; break;
7389 case 2: offset
= -4; break;
7390 case 3: offset
= 0; break;
7394 tcg_gen_addi_i32(addr
, addr
, offset
);
7395 store_reg(s
, rn
, addr
);
7397 tcg_temp_free_i32(addr
);
7399 gen_rfe(s
, tmp
, tmp2
);
7401 } else if ((insn
& 0x0e000000) == 0x0a000000) {
7402 /* branch link and change to thumb (blx <offset>) */
7405 val
= (uint32_t)s
->pc
;
7406 tmp
= tcg_temp_new_i32();
7407 tcg_gen_movi_i32(tmp
, val
);
7408 store_reg(s
, 14, tmp
);
7409 /* Sign-extend the 24-bit offset */
7410 offset
= (((int32_t)insn
) << 8) >> 8;
7411 /* offset * 4 + bit24 * 2 + (thumb bit) */
7412 val
+= (offset
<< 2) | ((insn
>> 23) & 2) | 1;
7413 /* pipeline offset */
7415 /* protected by ARCH(5); above, near the start of uncond block */
7418 } else if ((insn
& 0x0e000f00) == 0x0c000100) {
7419 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
7420 /* iWMMXt register transfer. */
7421 if (env
->cp15
.c15_cpar
& (1 << 1))
7422 if (!disas_iwmmxt_insn(env
, s
, insn
))
7425 } else if ((insn
& 0x0fe00000) == 0x0c400000) {
7426 /* Coprocessor double register transfer. */
7428 } else if ((insn
& 0x0f000010) == 0x0e000010) {
7429 /* Additional coprocessor register transfer. */
7430 } else if ((insn
& 0x0ff10020) == 0x01000000) {
7433 /* cps (privileged) */
7437 if (insn
& (1 << 19)) {
7438 if (insn
& (1 << 8))
7440 if (insn
& (1 << 7))
7442 if (insn
& (1 << 6))
7444 if (insn
& (1 << 18))
7447 if (insn
& (1 << 17)) {
7449 val
|= (insn
& 0x1f);
7452 gen_set_psr_im(s
, mask
, 0, val
);
7459 /* if not always execute, we generate a conditional jump to
7461 s
->condlabel
= gen_new_label();
7462 arm_gen_test_cc(cond
^ 1, s
->condlabel
);
7465 if ((insn
& 0x0f900000) == 0x03000000) {
7466 if ((insn
& (1 << 21)) == 0) {
7468 rd
= (insn
>> 12) & 0xf;
7469 val
= ((insn
>> 4) & 0xf000) | (insn
& 0xfff);
7470 if ((insn
& (1 << 22)) == 0) {
7472 tmp
= tcg_temp_new_i32();
7473 tcg_gen_movi_i32(tmp
, val
);
7476 tmp
= load_reg(s
, rd
);
7477 tcg_gen_ext16u_i32(tmp
, tmp
);
7478 tcg_gen_ori_i32(tmp
, tmp
, val
<< 16);
7480 store_reg(s
, rd
, tmp
);
7482 if (((insn
>> 12) & 0xf) != 0xf)
7484 if (((insn
>> 16) & 0xf) == 0) {
7485 gen_nop_hint(s
, insn
& 0xff);
7487 /* CPSR = immediate */
7489 shift
= ((insn
>> 8) & 0xf) * 2;
7491 val
= (val
>> shift
) | (val
<< (32 - shift
));
7492 i
= ((insn
& (1 << 22)) != 0);
7493 if (gen_set_psr_im(s
, msr_mask(env
, s
, (insn
>> 16) & 0xf, i
), i
, val
))
7497 } else if ((insn
& 0x0f900000) == 0x01000000
7498 && (insn
& 0x00000090) != 0x00000090) {
7499 /* miscellaneous instructions */
7500 op1
= (insn
>> 21) & 3;
7501 sh
= (insn
>> 4) & 0xf;
7504 case 0x0: /* move program status register */
7507 tmp
= load_reg(s
, rm
);
7508 i
= ((op1
& 2) != 0);
7509 if (gen_set_psr(s
, msr_mask(env
, s
, (insn
>> 16) & 0xf, i
), i
, tmp
))
7513 rd
= (insn
>> 12) & 0xf;
7517 tmp
= load_cpu_field(spsr
);
7519 tmp
= tcg_temp_new_i32();
7520 gen_helper_cpsr_read(tmp
, cpu_env
);
7522 store_reg(s
, rd
, tmp
);
7527 /* branch/exchange thumb (bx). */
7529 tmp
= load_reg(s
, rm
);
7531 } else if (op1
== 3) {
7534 rd
= (insn
>> 12) & 0xf;
7535 tmp
= load_reg(s
, rm
);
7536 gen_helper_clz(tmp
, tmp
);
7537 store_reg(s
, rd
, tmp
);
7545 /* Trivial implementation equivalent to bx. */
7546 tmp
= load_reg(s
, rm
);
7557 /* branch link/exchange thumb (blx) */
7558 tmp
= load_reg(s
, rm
);
7559 tmp2
= tcg_temp_new_i32();
7560 tcg_gen_movi_i32(tmp2
, s
->pc
);
7561 store_reg(s
, 14, tmp2
);
7567 uint32_t c
= extract32(insn
, 8, 4);
7569 /* Check this CPU supports ARMv8 CRC instructions.
7570 * op1 == 3 is UNPREDICTABLE but handle as UNDEFINED.
7571 * Bits 8, 10 and 11 should be zero.
7573 if (!arm_feature(env
, ARM_FEATURE_CRC
) || op1
== 0x3 ||
7578 rn
= extract32(insn
, 16, 4);
7579 rd
= extract32(insn
, 12, 4);
7581 tmp
= load_reg(s
, rn
);
7582 tmp2
= load_reg(s
, rm
);
7583 tmp3
= tcg_const_i32(1 << op1
);
7585 gen_helper_crc32c(tmp
, tmp
, tmp2
, tmp3
);
7587 gen_helper_crc32(tmp
, tmp
, tmp2
, tmp3
);
7589 tcg_temp_free_i32(tmp2
);
7590 tcg_temp_free_i32(tmp3
);
7591 store_reg(s
, rd
, tmp
);
7594 case 0x5: /* saturating add/subtract */
7596 rd
= (insn
>> 12) & 0xf;
7597 rn
= (insn
>> 16) & 0xf;
7598 tmp
= load_reg(s
, rm
);
7599 tmp2
= load_reg(s
, rn
);
7601 gen_helper_double_saturate(tmp2
, cpu_env
, tmp2
);
7603 gen_helper_sub_saturate(tmp
, cpu_env
, tmp
, tmp2
);
7605 gen_helper_add_saturate(tmp
, cpu_env
, tmp
, tmp2
);
7606 tcg_temp_free_i32(tmp2
);
7607 store_reg(s
, rd
, tmp
);
7610 /* SMC instruction (op1 == 3)
7611 and undefined instructions (op1 == 0 || op1 == 2)
7618 gen_exception_insn(s
, 4, EXCP_BKPT
);
7620 case 0x8: /* signed multiply */
7625 rs
= (insn
>> 8) & 0xf;
7626 rn
= (insn
>> 12) & 0xf;
7627 rd
= (insn
>> 16) & 0xf;
7629 /* (32 * 16) >> 16 */
7630 tmp
= load_reg(s
, rm
);
7631 tmp2
= load_reg(s
, rs
);
7633 tcg_gen_sari_i32(tmp2
, tmp2
, 16);
7636 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
7637 tcg_gen_shri_i64(tmp64
, tmp64
, 16);
7638 tmp
= tcg_temp_new_i32();
7639 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
7640 tcg_temp_free_i64(tmp64
);
7641 if ((sh
& 2) == 0) {
7642 tmp2
= load_reg(s
, rn
);
7643 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
7644 tcg_temp_free_i32(tmp2
);
7646 store_reg(s
, rd
, tmp
);
7649 tmp
= load_reg(s
, rm
);
7650 tmp2
= load_reg(s
, rs
);
7651 gen_mulxy(tmp
, tmp2
, sh
& 2, sh
& 4);
7652 tcg_temp_free_i32(tmp2
);
7654 tmp64
= tcg_temp_new_i64();
7655 tcg_gen_ext_i32_i64(tmp64
, tmp
);
7656 tcg_temp_free_i32(tmp
);
7657 gen_addq(s
, tmp64
, rn
, rd
);
7658 gen_storeq_reg(s
, rn
, rd
, tmp64
);
7659 tcg_temp_free_i64(tmp64
);
7662 tmp2
= load_reg(s
, rn
);
7663 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
7664 tcg_temp_free_i32(tmp2
);
7666 store_reg(s
, rd
, tmp
);
7673 } else if (((insn
& 0x0e000000) == 0 &&
7674 (insn
& 0x00000090) != 0x90) ||
7675 ((insn
& 0x0e000000) == (1 << 25))) {
7676 int set_cc
, logic_cc
, shiftop
;
7678 op1
= (insn
>> 21) & 0xf;
7679 set_cc
= (insn
>> 20) & 1;
7680 logic_cc
= table_logic_cc
[op1
] & set_cc
;
7682 /* data processing instruction */
7683 if (insn
& (1 << 25)) {
7684 /* immediate operand */
7686 shift
= ((insn
>> 8) & 0xf) * 2;
7688 val
= (val
>> shift
) | (val
<< (32 - shift
));
7690 tmp2
= tcg_temp_new_i32();
7691 tcg_gen_movi_i32(tmp2
, val
);
7692 if (logic_cc
&& shift
) {
7693 gen_set_CF_bit31(tmp2
);
7698 tmp2
= load_reg(s
, rm
);
7699 shiftop
= (insn
>> 5) & 3;
7700 if (!(insn
& (1 << 4))) {
7701 shift
= (insn
>> 7) & 0x1f;
7702 gen_arm_shift_im(tmp2
, shiftop
, shift
, logic_cc
);
7704 rs
= (insn
>> 8) & 0xf;
7705 tmp
= load_reg(s
, rs
);
7706 gen_arm_shift_reg(tmp2
, shiftop
, tmp
, logic_cc
);
7709 if (op1
!= 0x0f && op1
!= 0x0d) {
7710 rn
= (insn
>> 16) & 0xf;
7711 tmp
= load_reg(s
, rn
);
7713 TCGV_UNUSED_I32(tmp
);
7715 rd
= (insn
>> 12) & 0xf;
7718 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
7722 store_reg_bx(env
, s
, rd
, tmp
);
7725 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
7729 store_reg_bx(env
, s
, rd
, tmp
);
7732 if (set_cc
&& rd
== 15) {
7733 /* SUBS r15, ... is used for exception return. */
7737 gen_sub_CC(tmp
, tmp
, tmp2
);
7738 gen_exception_return(s
, tmp
);
7741 gen_sub_CC(tmp
, tmp
, tmp2
);
7743 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
7745 store_reg_bx(env
, s
, rd
, tmp
);
7750 gen_sub_CC(tmp
, tmp2
, tmp
);
7752 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
7754 store_reg_bx(env
, s
, rd
, tmp
);
7758 gen_add_CC(tmp
, tmp
, tmp2
);
7760 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7762 store_reg_bx(env
, s
, rd
, tmp
);
7766 gen_adc_CC(tmp
, tmp
, tmp2
);
7768 gen_add_carry(tmp
, tmp
, tmp2
);
7770 store_reg_bx(env
, s
, rd
, tmp
);
7774 gen_sbc_CC(tmp
, tmp
, tmp2
);
7776 gen_sub_carry(tmp
, tmp
, tmp2
);
7778 store_reg_bx(env
, s
, rd
, tmp
);
7782 gen_sbc_CC(tmp
, tmp2
, tmp
);
7784 gen_sub_carry(tmp
, tmp2
, tmp
);
7786 store_reg_bx(env
, s
, rd
, tmp
);
7790 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
7793 tcg_temp_free_i32(tmp
);
7797 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
7800 tcg_temp_free_i32(tmp
);
7804 gen_sub_CC(tmp
, tmp
, tmp2
);
7806 tcg_temp_free_i32(tmp
);
7810 gen_add_CC(tmp
, tmp
, tmp2
);
7812 tcg_temp_free_i32(tmp
);
7815 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
7819 store_reg_bx(env
, s
, rd
, tmp
);
7822 if (logic_cc
&& rd
== 15) {
7823 /* MOVS r15, ... is used for exception return. */
7827 gen_exception_return(s
, tmp2
);
7832 store_reg_bx(env
, s
, rd
, tmp2
);
7836 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
7840 store_reg_bx(env
, s
, rd
, tmp
);
7844 tcg_gen_not_i32(tmp2
, tmp2
);
7848 store_reg_bx(env
, s
, rd
, tmp2
);
7851 if (op1
!= 0x0f && op1
!= 0x0d) {
7852 tcg_temp_free_i32(tmp2
);
7855 /* other instructions */
7856 op1
= (insn
>> 24) & 0xf;
7860 /* multiplies, extra load/stores */
7861 sh
= (insn
>> 5) & 3;
7864 rd
= (insn
>> 16) & 0xf;
7865 rn
= (insn
>> 12) & 0xf;
7866 rs
= (insn
>> 8) & 0xf;
7868 op1
= (insn
>> 20) & 0xf;
7870 case 0: case 1: case 2: case 3: case 6:
7872 tmp
= load_reg(s
, rs
);
7873 tmp2
= load_reg(s
, rm
);
7874 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
7875 tcg_temp_free_i32(tmp2
);
7876 if (insn
& (1 << 22)) {
7877 /* Subtract (mls) */
7879 tmp2
= load_reg(s
, rn
);
7880 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
7881 tcg_temp_free_i32(tmp2
);
7882 } else if (insn
& (1 << 21)) {
7884 tmp2
= load_reg(s
, rn
);
7885 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7886 tcg_temp_free_i32(tmp2
);
7888 if (insn
& (1 << 20))
7890 store_reg(s
, rd
, tmp
);
7893 /* 64 bit mul double accumulate (UMAAL) */
7895 tmp
= load_reg(s
, rs
);
7896 tmp2
= load_reg(s
, rm
);
7897 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
7898 gen_addq_lo(s
, tmp64
, rn
);
7899 gen_addq_lo(s
, tmp64
, rd
);
7900 gen_storeq_reg(s
, rn
, rd
, tmp64
);
7901 tcg_temp_free_i64(tmp64
);
7903 case 8: case 9: case 10: case 11:
7904 case 12: case 13: case 14: case 15:
7905 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
7906 tmp
= load_reg(s
, rs
);
7907 tmp2
= load_reg(s
, rm
);
7908 if (insn
& (1 << 22)) {
7909 tcg_gen_muls2_i32(tmp
, tmp2
, tmp
, tmp2
);
7911 tcg_gen_mulu2_i32(tmp
, tmp2
, tmp
, tmp2
);
7913 if (insn
& (1 << 21)) { /* mult accumulate */
7914 TCGv_i32 al
= load_reg(s
, rn
);
7915 TCGv_i32 ah
= load_reg(s
, rd
);
7916 tcg_gen_add2_i32(tmp
, tmp2
, tmp
, tmp2
, al
, ah
);
7917 tcg_temp_free_i32(al
);
7918 tcg_temp_free_i32(ah
);
7920 if (insn
& (1 << 20)) {
7921 gen_logicq_cc(tmp
, tmp2
);
7923 store_reg(s
, rn
, tmp
);
7924 store_reg(s
, rd
, tmp2
);
7930 rn
= (insn
>> 16) & 0xf;
7931 rd
= (insn
>> 12) & 0xf;
7932 if (insn
& (1 << 23)) {
7933 /* load/store exclusive */
7934 int op2
= (insn
>> 8) & 3;
7935 op1
= (insn
>> 21) & 0x3;
7938 case 0: /* lda/stl */
7944 case 1: /* reserved */
7946 case 2: /* ldaex/stlex */
7949 case 3: /* ldrex/strex */
7958 addr
= tcg_temp_local_new_i32();
7959 load_reg_var(s
, addr
, rn
);
7961 /* Since the emulation does not have barriers,
7962 the acquire/release semantics need no special
7965 if (insn
& (1 << 20)) {
7966 tmp
= tcg_temp_new_i32();
7969 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
7972 gen_aa32_ld8u(tmp
, addr
, IS_USER(s
));
7975 gen_aa32_ld16u(tmp
, addr
, IS_USER(s
));
7980 store_reg(s
, rd
, tmp
);
7983 tmp
= load_reg(s
, rm
);
7986 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
7989 gen_aa32_st8(tmp
, addr
, IS_USER(s
));
7992 gen_aa32_st16(tmp
, addr
, IS_USER(s
));
7997 tcg_temp_free_i32(tmp
);
7999 } else if (insn
& (1 << 20)) {
8002 gen_load_exclusive(s
, rd
, 15, addr
, 2);
8004 case 1: /* ldrexd */
8005 gen_load_exclusive(s
, rd
, rd
+ 1, addr
, 3);
8007 case 2: /* ldrexb */
8008 gen_load_exclusive(s
, rd
, 15, addr
, 0);
8010 case 3: /* ldrexh */
8011 gen_load_exclusive(s
, rd
, 15, addr
, 1);
8020 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 2);
8022 case 1: /* strexd */
8023 gen_store_exclusive(s
, rd
, rm
, rm
+ 1, addr
, 3);
8025 case 2: /* strexb */
8026 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 0);
8028 case 3: /* strexh */
8029 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 1);
8035 tcg_temp_free_i32(addr
);
8037 /* SWP instruction */
8040 /* ??? This is not really atomic. However we know
8041 we never have multiple CPUs running in parallel,
8042 so it is good enough. */
8043 addr
= load_reg(s
, rn
);
8044 tmp
= load_reg(s
, rm
);
8045 tmp2
= tcg_temp_new_i32();
8046 if (insn
& (1 << 22)) {
8047 gen_aa32_ld8u(tmp2
, addr
, IS_USER(s
));
8048 gen_aa32_st8(tmp
, addr
, IS_USER(s
));
8050 gen_aa32_ld32u(tmp2
, addr
, IS_USER(s
));
8051 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
8053 tcg_temp_free_i32(tmp
);
8054 tcg_temp_free_i32(addr
);
8055 store_reg(s
, rd
, tmp2
);
8061 /* Misc load/store */
8062 rn
= (insn
>> 16) & 0xf;
8063 rd
= (insn
>> 12) & 0xf;
8064 addr
= load_reg(s
, rn
);
8065 if (insn
& (1 << 24))
8066 gen_add_datah_offset(s
, insn
, 0, addr
);
8068 if (insn
& (1 << 20)) {
8070 tmp
= tcg_temp_new_i32();
8073 gen_aa32_ld16u(tmp
, addr
, IS_USER(s
));
8076 gen_aa32_ld8s(tmp
, addr
, IS_USER(s
));
8080 gen_aa32_ld16s(tmp
, addr
, IS_USER(s
));
8084 } else if (sh
& 2) {
8089 tmp
= load_reg(s
, rd
);
8090 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
8091 tcg_temp_free_i32(tmp
);
8092 tcg_gen_addi_i32(addr
, addr
, 4);
8093 tmp
= load_reg(s
, rd
+ 1);
8094 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
8095 tcg_temp_free_i32(tmp
);
8099 tmp
= tcg_temp_new_i32();
8100 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
8101 store_reg(s
, rd
, tmp
);
8102 tcg_gen_addi_i32(addr
, addr
, 4);
8103 tmp
= tcg_temp_new_i32();
8104 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
8108 address_offset
= -4;
8111 tmp
= load_reg(s
, rd
);
8112 gen_aa32_st16(tmp
, addr
, IS_USER(s
));
8113 tcg_temp_free_i32(tmp
);
8116 /* Perform base writeback before the loaded value to
8117 ensure correct behavior with overlapping index registers.
8118 ldrd with base writeback is is undefined if the
8119 destination and index registers overlap. */
8120 if (!(insn
& (1 << 24))) {
8121 gen_add_datah_offset(s
, insn
, address_offset
, addr
);
8122 store_reg(s
, rn
, addr
);
8123 } else if (insn
& (1 << 21)) {
8125 tcg_gen_addi_i32(addr
, addr
, address_offset
);
8126 store_reg(s
, rn
, addr
);
8128 tcg_temp_free_i32(addr
);
8131 /* Complete the load. */
8132 store_reg(s
, rd
, tmp
);
8141 if (insn
& (1 << 4)) {
8143 /* Armv6 Media instructions. */
8145 rn
= (insn
>> 16) & 0xf;
8146 rd
= (insn
>> 12) & 0xf;
8147 rs
= (insn
>> 8) & 0xf;
8148 switch ((insn
>> 23) & 3) {
8149 case 0: /* Parallel add/subtract. */
8150 op1
= (insn
>> 20) & 7;
8151 tmp
= load_reg(s
, rn
);
8152 tmp2
= load_reg(s
, rm
);
8153 sh
= (insn
>> 5) & 7;
8154 if ((op1
& 3) == 0 || sh
== 5 || sh
== 6)
8156 gen_arm_parallel_addsub(op1
, sh
, tmp
, tmp2
);
8157 tcg_temp_free_i32(tmp2
);
8158 store_reg(s
, rd
, tmp
);
8161 if ((insn
& 0x00700020) == 0) {
8162 /* Halfword pack. */
8163 tmp
= load_reg(s
, rn
);
8164 tmp2
= load_reg(s
, rm
);
8165 shift
= (insn
>> 7) & 0x1f;
8166 if (insn
& (1 << 6)) {
8170 tcg_gen_sari_i32(tmp2
, tmp2
, shift
);
8171 tcg_gen_andi_i32(tmp
, tmp
, 0xffff0000);
8172 tcg_gen_ext16u_i32(tmp2
, tmp2
);
8176 tcg_gen_shli_i32(tmp2
, tmp2
, shift
);
8177 tcg_gen_ext16u_i32(tmp
, tmp
);
8178 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff0000);
8180 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
8181 tcg_temp_free_i32(tmp2
);
8182 store_reg(s
, rd
, tmp
);
8183 } else if ((insn
& 0x00200020) == 0x00200000) {
8185 tmp
= load_reg(s
, rm
);
8186 shift
= (insn
>> 7) & 0x1f;
8187 if (insn
& (1 << 6)) {
8190 tcg_gen_sari_i32(tmp
, tmp
, shift
);
8192 tcg_gen_shli_i32(tmp
, tmp
, shift
);
8194 sh
= (insn
>> 16) & 0x1f;
8195 tmp2
= tcg_const_i32(sh
);
8196 if (insn
& (1 << 22))
8197 gen_helper_usat(tmp
, cpu_env
, tmp
, tmp2
);
8199 gen_helper_ssat(tmp
, cpu_env
, tmp
, tmp2
);
8200 tcg_temp_free_i32(tmp2
);
8201 store_reg(s
, rd
, tmp
);
8202 } else if ((insn
& 0x00300fe0) == 0x00200f20) {
8204 tmp
= load_reg(s
, rm
);
8205 sh
= (insn
>> 16) & 0x1f;
8206 tmp2
= tcg_const_i32(sh
);
8207 if (insn
& (1 << 22))
8208 gen_helper_usat16(tmp
, cpu_env
, tmp
, tmp2
);
8210 gen_helper_ssat16(tmp
, cpu_env
, tmp
, tmp2
);
8211 tcg_temp_free_i32(tmp2
);
8212 store_reg(s
, rd
, tmp
);
8213 } else if ((insn
& 0x00700fe0) == 0x00000fa0) {
8215 tmp
= load_reg(s
, rn
);
8216 tmp2
= load_reg(s
, rm
);
8217 tmp3
= tcg_temp_new_i32();
8218 tcg_gen_ld_i32(tmp3
, cpu_env
, offsetof(CPUARMState
, GE
));
8219 gen_helper_sel_flags(tmp
, tmp3
, tmp
, tmp2
);
8220 tcg_temp_free_i32(tmp3
);
8221 tcg_temp_free_i32(tmp2
);
8222 store_reg(s
, rd
, tmp
);
8223 } else if ((insn
& 0x000003e0) == 0x00000060) {
8224 tmp
= load_reg(s
, rm
);
8225 shift
= (insn
>> 10) & 3;
8226 /* ??? In many cases it's not necessary to do a
8227 rotate, a shift is sufficient. */
8229 tcg_gen_rotri_i32(tmp
, tmp
, shift
* 8);
8230 op1
= (insn
>> 20) & 7;
8232 case 0: gen_sxtb16(tmp
); break;
8233 case 2: gen_sxtb(tmp
); break;
8234 case 3: gen_sxth(tmp
); break;
8235 case 4: gen_uxtb16(tmp
); break;
8236 case 6: gen_uxtb(tmp
); break;
8237 case 7: gen_uxth(tmp
); break;
8238 default: goto illegal_op
;
8241 tmp2
= load_reg(s
, rn
);
8242 if ((op1
& 3) == 0) {
8243 gen_add16(tmp
, tmp2
);
8245 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8246 tcg_temp_free_i32(tmp2
);
8249 store_reg(s
, rd
, tmp
);
8250 } else if ((insn
& 0x003f0f60) == 0x003f0f20) {
8252 tmp
= load_reg(s
, rm
);
8253 if (insn
& (1 << 22)) {
8254 if (insn
& (1 << 7)) {
8258 gen_helper_rbit(tmp
, tmp
);
8261 if (insn
& (1 << 7))
8264 tcg_gen_bswap32_i32(tmp
, tmp
);
8266 store_reg(s
, rd
, tmp
);
8271 case 2: /* Multiplies (Type 3). */
8272 switch ((insn
>> 20) & 0x7) {
8274 if (((insn
>> 6) ^ (insn
>> 7)) & 1) {
8275 /* op2 not 00x or 11x : UNDEF */
8278 /* Signed multiply most significant [accumulate].
8279 (SMMUL, SMMLA, SMMLS) */
8280 tmp
= load_reg(s
, rm
);
8281 tmp2
= load_reg(s
, rs
);
8282 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
8285 tmp
= load_reg(s
, rd
);
8286 if (insn
& (1 << 6)) {
8287 tmp64
= gen_subq_msw(tmp64
, tmp
);
8289 tmp64
= gen_addq_msw(tmp64
, tmp
);
8292 if (insn
& (1 << 5)) {
8293 tcg_gen_addi_i64(tmp64
, tmp64
, 0x80000000u
);
8295 tcg_gen_shri_i64(tmp64
, tmp64
, 32);
8296 tmp
= tcg_temp_new_i32();
8297 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
8298 tcg_temp_free_i64(tmp64
);
8299 store_reg(s
, rn
, tmp
);
8303 /* SMLAD, SMUAD, SMLSD, SMUSD, SMLALD, SMLSLD */
8304 if (insn
& (1 << 7)) {
8307 tmp
= load_reg(s
, rm
);
8308 tmp2
= load_reg(s
, rs
);
8309 if (insn
& (1 << 5))
8310 gen_swap_half(tmp2
);
8311 gen_smul_dual(tmp
, tmp2
);
8312 if (insn
& (1 << 6)) {
8313 /* This subtraction cannot overflow. */
8314 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
8316 /* This addition cannot overflow 32 bits;
8317 * however it may overflow considered as a signed
8318 * operation, in which case we must set the Q flag.
8320 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
8322 tcg_temp_free_i32(tmp2
);
8323 if (insn
& (1 << 22)) {
8324 /* smlald, smlsld */
8325 tmp64
= tcg_temp_new_i64();
8326 tcg_gen_ext_i32_i64(tmp64
, tmp
);
8327 tcg_temp_free_i32(tmp
);
8328 gen_addq(s
, tmp64
, rd
, rn
);
8329 gen_storeq_reg(s
, rd
, rn
, tmp64
);
8330 tcg_temp_free_i64(tmp64
);
8332 /* smuad, smusd, smlad, smlsd */
8335 tmp2
= load_reg(s
, rd
);
8336 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
8337 tcg_temp_free_i32(tmp2
);
8339 store_reg(s
, rn
, tmp
);
8345 if (!arm_feature(env
, ARM_FEATURE_ARM_DIV
)) {
8348 if (((insn
>> 5) & 7) || (rd
!= 15)) {
8351 tmp
= load_reg(s
, rm
);
8352 tmp2
= load_reg(s
, rs
);
8353 if (insn
& (1 << 21)) {
8354 gen_helper_udiv(tmp
, tmp
, tmp2
);
8356 gen_helper_sdiv(tmp
, tmp
, tmp2
);
8358 tcg_temp_free_i32(tmp2
);
8359 store_reg(s
, rn
, tmp
);
8366 op1
= ((insn
>> 17) & 0x38) | ((insn
>> 5) & 7);
8368 case 0: /* Unsigned sum of absolute differences. */
8370 tmp
= load_reg(s
, rm
);
8371 tmp2
= load_reg(s
, rs
);
8372 gen_helper_usad8(tmp
, tmp
, tmp2
);
8373 tcg_temp_free_i32(tmp2
);
8375 tmp2
= load_reg(s
, rd
);
8376 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8377 tcg_temp_free_i32(tmp2
);
8379 store_reg(s
, rn
, tmp
);
8381 case 0x20: case 0x24: case 0x28: case 0x2c:
8382 /* Bitfield insert/clear. */
8384 shift
= (insn
>> 7) & 0x1f;
8385 i
= (insn
>> 16) & 0x1f;
8388 tmp
= tcg_temp_new_i32();
8389 tcg_gen_movi_i32(tmp
, 0);
8391 tmp
= load_reg(s
, rm
);
8394 tmp2
= load_reg(s
, rd
);
8395 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, shift
, i
);
8396 tcg_temp_free_i32(tmp2
);
8398 store_reg(s
, rd
, tmp
);
8400 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
8401 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
8403 tmp
= load_reg(s
, rm
);
8404 shift
= (insn
>> 7) & 0x1f;
8405 i
= ((insn
>> 16) & 0x1f) + 1;
8410 gen_ubfx(tmp
, shift
, (1u << i
) - 1);
8412 gen_sbfx(tmp
, shift
, i
);
8415 store_reg(s
, rd
, tmp
);
8425 /* Check for undefined extension instructions
8426 * per the ARM Bible IE:
8427 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
8429 sh
= (0xf << 20) | (0xf << 4);
8430 if (op1
== 0x7 && ((insn
& sh
) == sh
))
8434 /* load/store byte/word */
8435 rn
= (insn
>> 16) & 0xf;
8436 rd
= (insn
>> 12) & 0xf;
8437 tmp2
= load_reg(s
, rn
);
8438 i
= (IS_USER(s
) || (insn
& 0x01200000) == 0x00200000);
8439 if (insn
& (1 << 24))
8440 gen_add_data_offset(s
, insn
, tmp2
);
8441 if (insn
& (1 << 20)) {
8443 tmp
= tcg_temp_new_i32();
8444 if (insn
& (1 << 22)) {
8445 gen_aa32_ld8u(tmp
, tmp2
, i
);
8447 gen_aa32_ld32u(tmp
, tmp2
, i
);
8451 tmp
= load_reg(s
, rd
);
8452 if (insn
& (1 << 22)) {
8453 gen_aa32_st8(tmp
, tmp2
, i
);
8455 gen_aa32_st32(tmp
, tmp2
, i
);
8457 tcg_temp_free_i32(tmp
);
8459 if (!(insn
& (1 << 24))) {
8460 gen_add_data_offset(s
, insn
, tmp2
);
8461 store_reg(s
, rn
, tmp2
);
8462 } else if (insn
& (1 << 21)) {
8463 store_reg(s
, rn
, tmp2
);
8465 tcg_temp_free_i32(tmp2
);
8467 if (insn
& (1 << 20)) {
8468 /* Complete the load. */
8469 store_reg_from_load(env
, s
, rd
, tmp
);
8475 int j
, n
, user
, loaded_base
;
8476 TCGv_i32 loaded_var
;
8477 /* load/store multiple words */
8478 /* XXX: store correct base if write back */
8480 if (insn
& (1 << 22)) {
8482 goto illegal_op
; /* only usable in supervisor mode */
8484 if ((insn
& (1 << 15)) == 0)
8487 rn
= (insn
>> 16) & 0xf;
8488 addr
= load_reg(s
, rn
);
8490 /* compute total size */
8492 TCGV_UNUSED_I32(loaded_var
);
8495 if (insn
& (1 << i
))
8498 /* XXX: test invalid n == 0 case ? */
8499 if (insn
& (1 << 23)) {
8500 if (insn
& (1 << 24)) {
8502 tcg_gen_addi_i32(addr
, addr
, 4);
8504 /* post increment */
8507 if (insn
& (1 << 24)) {
8509 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
8511 /* post decrement */
8513 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
8518 if (insn
& (1 << i
)) {
8519 if (insn
& (1 << 20)) {
8521 tmp
= tcg_temp_new_i32();
8522 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
8524 tmp2
= tcg_const_i32(i
);
8525 gen_helper_set_user_reg(cpu_env
, tmp2
, tmp
);
8526 tcg_temp_free_i32(tmp2
);
8527 tcg_temp_free_i32(tmp
);
8528 } else if (i
== rn
) {
8532 store_reg_from_load(env
, s
, i
, tmp
);
8537 /* special case: r15 = PC + 8 */
8538 val
= (long)s
->pc
+ 4;
8539 tmp
= tcg_temp_new_i32();
8540 tcg_gen_movi_i32(tmp
, val
);
8542 tmp
= tcg_temp_new_i32();
8543 tmp2
= tcg_const_i32(i
);
8544 gen_helper_get_user_reg(tmp
, cpu_env
, tmp2
);
8545 tcg_temp_free_i32(tmp2
);
8547 tmp
= load_reg(s
, i
);
8549 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
8550 tcg_temp_free_i32(tmp
);
8553 /* no need to add after the last transfer */
8555 tcg_gen_addi_i32(addr
, addr
, 4);
8558 if (insn
& (1 << 21)) {
8560 if (insn
& (1 << 23)) {
8561 if (insn
& (1 << 24)) {
8564 /* post increment */
8565 tcg_gen_addi_i32(addr
, addr
, 4);
8568 if (insn
& (1 << 24)) {
8571 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
8573 /* post decrement */
8574 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
8577 store_reg(s
, rn
, addr
);
8579 tcg_temp_free_i32(addr
);
8582 store_reg(s
, rn
, loaded_var
);
8584 if ((insn
& (1 << 22)) && !user
) {
8585 /* Restore CPSR from SPSR. */
8586 tmp
= load_cpu_field(spsr
);
8587 gen_set_cpsr(tmp
, 0xffffffff);
8588 tcg_temp_free_i32(tmp
);
8589 s
->is_jmp
= DISAS_UPDATE
;
8598 /* branch (and link) */
8599 val
= (int32_t)s
->pc
;
8600 if (insn
& (1 << 24)) {
8601 tmp
= tcg_temp_new_i32();
8602 tcg_gen_movi_i32(tmp
, val
);
8603 store_reg(s
, 14, tmp
);
8605 offset
= sextract32(insn
<< 2, 0, 26);
8613 if (((insn
>> 8) & 0xe) == 10) {
8615 if (disas_vfp_insn(env
, s
, insn
)) {
8618 } else if (disas_coproc_insn(env
, s
, insn
)) {
8625 gen_set_pc_im(s
, s
->pc
);
8626 s
->is_jmp
= DISAS_SWI
;
8630 gen_exception_insn(s
, 4, EXCP_UDEF
);
8636 /* Return true if this is a Thumb-2 logical op. */
8638 thumb2_logic_op(int op
)
8643 /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
8644 then set condition code flags based on the result of the operation.
8645 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
8646 to the high bit of T1.
8647 Returns zero if the opcode is valid. */
8650 gen_thumb2_data_op(DisasContext
*s
, int op
, int conds
, uint32_t shifter_out
,
8651 TCGv_i32 t0
, TCGv_i32 t1
)
8658 tcg_gen_and_i32(t0
, t0
, t1
);
8662 tcg_gen_andc_i32(t0
, t0
, t1
);
8666 tcg_gen_or_i32(t0
, t0
, t1
);
8670 tcg_gen_orc_i32(t0
, t0
, t1
);
8674 tcg_gen_xor_i32(t0
, t0
, t1
);
8679 gen_add_CC(t0
, t0
, t1
);
8681 tcg_gen_add_i32(t0
, t0
, t1
);
8685 gen_adc_CC(t0
, t0
, t1
);
8691 gen_sbc_CC(t0
, t0
, t1
);
8693 gen_sub_carry(t0
, t0
, t1
);
8698 gen_sub_CC(t0
, t0
, t1
);
8700 tcg_gen_sub_i32(t0
, t0
, t1
);
8704 gen_sub_CC(t0
, t1
, t0
);
8706 tcg_gen_sub_i32(t0
, t1
, t0
);
8708 default: /* 5, 6, 7, 9, 12, 15. */
8714 gen_set_CF_bit31(t1
);
8719 /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
8721 static int disas_thumb2_insn(CPUARMState
*env
, DisasContext
*s
, uint16_t insn_hw1
)
8723 uint32_t insn
, imm
, shift
, offset
;
8724 uint32_t rd
, rn
, rm
, rs
;
8735 if (!(arm_feature(env
, ARM_FEATURE_THUMB2
)
8736 || arm_feature (env
, ARM_FEATURE_M
))) {
8737 /* Thumb-1 cores may need to treat bl and blx as a pair of
8738 16-bit instructions to get correct prefetch abort behavior. */
8740 if ((insn
& (1 << 12)) == 0) {
8742 /* Second half of blx. */
8743 offset
= ((insn
& 0x7ff) << 1);
8744 tmp
= load_reg(s
, 14);
8745 tcg_gen_addi_i32(tmp
, tmp
, offset
);
8746 tcg_gen_andi_i32(tmp
, tmp
, 0xfffffffc);
8748 tmp2
= tcg_temp_new_i32();
8749 tcg_gen_movi_i32(tmp2
, s
->pc
| 1);
8750 store_reg(s
, 14, tmp2
);
8754 if (insn
& (1 << 11)) {
8755 /* Second half of bl. */
8756 offset
= ((insn
& 0x7ff) << 1) | 1;
8757 tmp
= load_reg(s
, 14);
8758 tcg_gen_addi_i32(tmp
, tmp
, offset
);
8760 tmp2
= tcg_temp_new_i32();
8761 tcg_gen_movi_i32(tmp2
, s
->pc
| 1);
8762 store_reg(s
, 14, tmp2
);
8766 if ((s
->pc
& ~TARGET_PAGE_MASK
) == 0) {
8767 /* Instruction spans a page boundary. Implement it as two
8768 16-bit instructions in case the second half causes an
8770 offset
= ((int32_t)insn
<< 21) >> 9;
8771 tcg_gen_movi_i32(cpu_R
[14], s
->pc
+ 2 + offset
);
8774 /* Fall through to 32-bit decode. */
8777 insn
= arm_lduw_code(env
, s
->pc
, s
->bswap_code
);
8779 insn
|= (uint32_t)insn_hw1
<< 16;
8781 if ((insn
& 0xf800e800) != 0xf000e800) {
8785 rn
= (insn
>> 16) & 0xf;
8786 rs
= (insn
>> 12) & 0xf;
8787 rd
= (insn
>> 8) & 0xf;
8789 switch ((insn
>> 25) & 0xf) {
8790 case 0: case 1: case 2: case 3:
8791 /* 16-bit instructions. Should never happen. */
8794 if (insn
& (1 << 22)) {
8795 /* Other load/store, table branch. */
8796 if (insn
& 0x01200000) {
8797 /* Load/store doubleword. */
8799 addr
= tcg_temp_new_i32();
8800 tcg_gen_movi_i32(addr
, s
->pc
& ~3);
8802 addr
= load_reg(s
, rn
);
8804 offset
= (insn
& 0xff) * 4;
8805 if ((insn
& (1 << 23)) == 0)
8807 if (insn
& (1 << 24)) {
8808 tcg_gen_addi_i32(addr
, addr
, offset
);
8811 if (insn
& (1 << 20)) {
8813 tmp
= tcg_temp_new_i32();
8814 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
8815 store_reg(s
, rs
, tmp
);
8816 tcg_gen_addi_i32(addr
, addr
, 4);
8817 tmp
= tcg_temp_new_i32();
8818 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
8819 store_reg(s
, rd
, tmp
);
8822 tmp
= load_reg(s
, rs
);
8823 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
8824 tcg_temp_free_i32(tmp
);
8825 tcg_gen_addi_i32(addr
, addr
, 4);
8826 tmp
= load_reg(s
, rd
);
8827 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
8828 tcg_temp_free_i32(tmp
);
8830 if (insn
& (1 << 21)) {
8831 /* Base writeback. */
8834 tcg_gen_addi_i32(addr
, addr
, offset
- 4);
8835 store_reg(s
, rn
, addr
);
8837 tcg_temp_free_i32(addr
);
8839 } else if ((insn
& (1 << 23)) == 0) {
8840 /* Load/store exclusive word. */
8841 addr
= tcg_temp_local_new_i32();
8842 load_reg_var(s
, addr
, rn
);
8843 tcg_gen_addi_i32(addr
, addr
, (insn
& 0xff) << 2);
8844 if (insn
& (1 << 20)) {
8845 gen_load_exclusive(s
, rs
, 15, addr
, 2);
8847 gen_store_exclusive(s
, rd
, rs
, 15, addr
, 2);
8849 tcg_temp_free_i32(addr
);
8850 } else if ((insn
& (7 << 5)) == 0) {
8853 addr
= tcg_temp_new_i32();
8854 tcg_gen_movi_i32(addr
, s
->pc
);
8856 addr
= load_reg(s
, rn
);
8858 tmp
= load_reg(s
, rm
);
8859 tcg_gen_add_i32(addr
, addr
, tmp
);
8860 if (insn
& (1 << 4)) {
8862 tcg_gen_add_i32(addr
, addr
, tmp
);
8863 tcg_temp_free_i32(tmp
);
8864 tmp
= tcg_temp_new_i32();
8865 gen_aa32_ld16u(tmp
, addr
, IS_USER(s
));
8867 tcg_temp_free_i32(tmp
);
8868 tmp
= tcg_temp_new_i32();
8869 gen_aa32_ld8u(tmp
, addr
, IS_USER(s
));
8871 tcg_temp_free_i32(addr
);
8872 tcg_gen_shli_i32(tmp
, tmp
, 1);
8873 tcg_gen_addi_i32(tmp
, tmp
, s
->pc
);
8874 store_reg(s
, 15, tmp
);
8876 int op2
= (insn
>> 6) & 0x3;
8877 op
= (insn
>> 4) & 0x3;
8882 /* Load/store exclusive byte/halfword/doubleword */
8889 /* Load-acquire/store-release */
8895 /* Load-acquire/store-release exclusive */
8899 addr
= tcg_temp_local_new_i32();
8900 load_reg_var(s
, addr
, rn
);
8902 if (insn
& (1 << 20)) {
8903 tmp
= tcg_temp_new_i32();
8906 gen_aa32_ld8u(tmp
, addr
, IS_USER(s
));
8909 gen_aa32_ld16u(tmp
, addr
, IS_USER(s
));
8912 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
8917 store_reg(s
, rs
, tmp
);
8919 tmp
= load_reg(s
, rs
);
8922 gen_aa32_st8(tmp
, addr
, IS_USER(s
));
8925 gen_aa32_st16(tmp
, addr
, IS_USER(s
));
8928 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
8933 tcg_temp_free_i32(tmp
);
8935 } else if (insn
& (1 << 20)) {
8936 gen_load_exclusive(s
, rs
, rd
, addr
, op
);
8938 gen_store_exclusive(s
, rm
, rs
, rd
, addr
, op
);
8940 tcg_temp_free_i32(addr
);
8943 /* Load/store multiple, RFE, SRS. */
8944 if (((insn
>> 23) & 1) == ((insn
>> 24) & 1)) {
8945 /* RFE, SRS: not available in user mode or on M profile */
8946 if (IS_USER(s
) || IS_M(env
)) {
8949 if (insn
& (1 << 20)) {
8951 addr
= load_reg(s
, rn
);
8952 if ((insn
& (1 << 24)) == 0)
8953 tcg_gen_addi_i32(addr
, addr
, -8);
8954 /* Load PC into tmp and CPSR into tmp2. */
8955 tmp
= tcg_temp_new_i32();
8956 gen_aa32_ld32u(tmp
, addr
, 0);
8957 tcg_gen_addi_i32(addr
, addr
, 4);
8958 tmp2
= tcg_temp_new_i32();
8959 gen_aa32_ld32u(tmp2
, addr
, 0);
8960 if (insn
& (1 << 21)) {
8961 /* Base writeback. */
8962 if (insn
& (1 << 24)) {
8963 tcg_gen_addi_i32(addr
, addr
, 4);
8965 tcg_gen_addi_i32(addr
, addr
, -4);
8967 store_reg(s
, rn
, addr
);
8969 tcg_temp_free_i32(addr
);
8971 gen_rfe(s
, tmp
, tmp2
);
8974 gen_srs(s
, (insn
& 0x1f), (insn
& (1 << 24)) ? 1 : 2,
8978 int i
, loaded_base
= 0;
8979 TCGv_i32 loaded_var
;
8980 /* Load/store multiple. */
8981 addr
= load_reg(s
, rn
);
8983 for (i
= 0; i
< 16; i
++) {
8984 if (insn
& (1 << i
))
8987 if (insn
& (1 << 24)) {
8988 tcg_gen_addi_i32(addr
, addr
, -offset
);
8991 TCGV_UNUSED_I32(loaded_var
);
8992 for (i
= 0; i
< 16; i
++) {
8993 if ((insn
& (1 << i
)) == 0)
8995 if (insn
& (1 << 20)) {
8997 tmp
= tcg_temp_new_i32();
8998 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
9001 } else if (i
== rn
) {
9005 store_reg(s
, i
, tmp
);
9009 tmp
= load_reg(s
, i
);
9010 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
9011 tcg_temp_free_i32(tmp
);
9013 tcg_gen_addi_i32(addr
, addr
, 4);
9016 store_reg(s
, rn
, loaded_var
);
9018 if (insn
& (1 << 21)) {
9019 /* Base register writeback. */
9020 if (insn
& (1 << 24)) {
9021 tcg_gen_addi_i32(addr
, addr
, -offset
);
9023 /* Fault if writeback register is in register list. */
9024 if (insn
& (1 << rn
))
9026 store_reg(s
, rn
, addr
);
9028 tcg_temp_free_i32(addr
);
9035 op
= (insn
>> 21) & 0xf;
9037 /* Halfword pack. */
9038 tmp
= load_reg(s
, rn
);
9039 tmp2
= load_reg(s
, rm
);
9040 shift
= ((insn
>> 10) & 0x1c) | ((insn
>> 6) & 0x3);
9041 if (insn
& (1 << 5)) {
9045 tcg_gen_sari_i32(tmp2
, tmp2
, shift
);
9046 tcg_gen_andi_i32(tmp
, tmp
, 0xffff0000);
9047 tcg_gen_ext16u_i32(tmp2
, tmp2
);
9051 tcg_gen_shli_i32(tmp2
, tmp2
, shift
);
9052 tcg_gen_ext16u_i32(tmp
, tmp
);
9053 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff0000);
9055 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
9056 tcg_temp_free_i32(tmp2
);
9057 store_reg(s
, rd
, tmp
);
9059 /* Data processing register constant shift. */
9061 tmp
= tcg_temp_new_i32();
9062 tcg_gen_movi_i32(tmp
, 0);
9064 tmp
= load_reg(s
, rn
);
9066 tmp2
= load_reg(s
, rm
);
9068 shiftop
= (insn
>> 4) & 3;
9069 shift
= ((insn
>> 6) & 3) | ((insn
>> 10) & 0x1c);
9070 conds
= (insn
& (1 << 20)) != 0;
9071 logic_cc
= (conds
&& thumb2_logic_op(op
));
9072 gen_arm_shift_im(tmp2
, shiftop
, shift
, logic_cc
);
9073 if (gen_thumb2_data_op(s
, op
, conds
, 0, tmp
, tmp2
))
9075 tcg_temp_free_i32(tmp2
);
9077 store_reg(s
, rd
, tmp
);
9079 tcg_temp_free_i32(tmp
);
9083 case 13: /* Misc data processing. */
9084 op
= ((insn
>> 22) & 6) | ((insn
>> 7) & 1);
9085 if (op
< 4 && (insn
& 0xf000) != 0xf000)
9088 case 0: /* Register controlled shift. */
9089 tmp
= load_reg(s
, rn
);
9090 tmp2
= load_reg(s
, rm
);
9091 if ((insn
& 0x70) != 0)
9093 op
= (insn
>> 21) & 3;
9094 logic_cc
= (insn
& (1 << 20)) != 0;
9095 gen_arm_shift_reg(tmp
, op
, tmp2
, logic_cc
);
9098 store_reg_bx(env
, s
, rd
, tmp
);
9100 case 1: /* Sign/zero extend. */
9101 tmp
= load_reg(s
, rm
);
9102 shift
= (insn
>> 4) & 3;
9103 /* ??? In many cases it's not necessary to do a
9104 rotate, a shift is sufficient. */
9106 tcg_gen_rotri_i32(tmp
, tmp
, shift
* 8);
9107 op
= (insn
>> 20) & 7;
9109 case 0: gen_sxth(tmp
); break;
9110 case 1: gen_uxth(tmp
); break;
9111 case 2: gen_sxtb16(tmp
); break;
9112 case 3: gen_uxtb16(tmp
); break;
9113 case 4: gen_sxtb(tmp
); break;
9114 case 5: gen_uxtb(tmp
); break;
9115 default: goto illegal_op
;
9118 tmp2
= load_reg(s
, rn
);
9119 if ((op
>> 1) == 1) {
9120 gen_add16(tmp
, tmp2
);
9122 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
9123 tcg_temp_free_i32(tmp2
);
9126 store_reg(s
, rd
, tmp
);
9128 case 2: /* SIMD add/subtract. */
9129 op
= (insn
>> 20) & 7;
9130 shift
= (insn
>> 4) & 7;
9131 if ((op
& 3) == 3 || (shift
& 3) == 3)
9133 tmp
= load_reg(s
, rn
);
9134 tmp2
= load_reg(s
, rm
);
9135 gen_thumb2_parallel_addsub(op
, shift
, tmp
, tmp2
);
9136 tcg_temp_free_i32(tmp2
);
9137 store_reg(s
, rd
, tmp
);
9139 case 3: /* Other data processing. */
9140 op
= ((insn
>> 17) & 0x38) | ((insn
>> 4) & 7);
9142 /* Saturating add/subtract. */
9143 tmp
= load_reg(s
, rn
);
9144 tmp2
= load_reg(s
, rm
);
9146 gen_helper_double_saturate(tmp
, cpu_env
, tmp
);
9148 gen_helper_sub_saturate(tmp
, cpu_env
, tmp2
, tmp
);
9150 gen_helper_add_saturate(tmp
, cpu_env
, tmp
, tmp2
);
9151 tcg_temp_free_i32(tmp2
);
9153 tmp
= load_reg(s
, rn
);
9155 case 0x0a: /* rbit */
9156 gen_helper_rbit(tmp
, tmp
);
9158 case 0x08: /* rev */
9159 tcg_gen_bswap32_i32(tmp
, tmp
);
9161 case 0x09: /* rev16 */
9164 case 0x0b: /* revsh */
9167 case 0x10: /* sel */
9168 tmp2
= load_reg(s
, rm
);
9169 tmp3
= tcg_temp_new_i32();
9170 tcg_gen_ld_i32(tmp3
, cpu_env
, offsetof(CPUARMState
, GE
));
9171 gen_helper_sel_flags(tmp
, tmp3
, tmp
, tmp2
);
9172 tcg_temp_free_i32(tmp3
);
9173 tcg_temp_free_i32(tmp2
);
9175 case 0x18: /* clz */
9176 gen_helper_clz(tmp
, tmp
);
9186 uint32_t sz
= op
& 0x3;
9187 uint32_t c
= op
& 0x8;
9189 if (!arm_feature(env
, ARM_FEATURE_CRC
)) {
9193 tmp2
= load_reg(s
, rm
);
9194 tmp3
= tcg_const_i32(1 << sz
);
9196 gen_helper_crc32c(tmp
, tmp
, tmp2
, tmp3
);
9198 gen_helper_crc32(tmp
, tmp
, tmp2
, tmp3
);
9200 tcg_temp_free_i32(tmp2
);
9201 tcg_temp_free_i32(tmp3
);
9208 store_reg(s
, rd
, tmp
);
9210 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
9211 op
= (insn
>> 4) & 0xf;
9212 tmp
= load_reg(s
, rn
);
9213 tmp2
= load_reg(s
, rm
);
9214 switch ((insn
>> 20) & 7) {
9215 case 0: /* 32 x 32 -> 32 */
9216 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
9217 tcg_temp_free_i32(tmp2
);
9219 tmp2
= load_reg(s
, rs
);
9221 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
9223 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
9224 tcg_temp_free_i32(tmp2
);
9227 case 1: /* 16 x 16 -> 32 */
9228 gen_mulxy(tmp
, tmp2
, op
& 2, op
& 1);
9229 tcg_temp_free_i32(tmp2
);
9231 tmp2
= load_reg(s
, rs
);
9232 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
9233 tcg_temp_free_i32(tmp2
);
9236 case 2: /* Dual multiply add. */
9237 case 4: /* Dual multiply subtract. */
9239 gen_swap_half(tmp2
);
9240 gen_smul_dual(tmp
, tmp2
);
9241 if (insn
& (1 << 22)) {
9242 /* This subtraction cannot overflow. */
9243 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
9245 /* This addition cannot overflow 32 bits;
9246 * however it may overflow considered as a signed
9247 * operation, in which case we must set the Q flag.
9249 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
9251 tcg_temp_free_i32(tmp2
);
9254 tmp2
= load_reg(s
, rs
);
9255 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
9256 tcg_temp_free_i32(tmp2
);
9259 case 3: /* 32 * 16 -> 32msb */
9261 tcg_gen_sari_i32(tmp2
, tmp2
, 16);
9264 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
9265 tcg_gen_shri_i64(tmp64
, tmp64
, 16);
9266 tmp
= tcg_temp_new_i32();
9267 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
9268 tcg_temp_free_i64(tmp64
);
9271 tmp2
= load_reg(s
, rs
);
9272 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
9273 tcg_temp_free_i32(tmp2
);
9276 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
9277 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
9279 tmp
= load_reg(s
, rs
);
9280 if (insn
& (1 << 20)) {
9281 tmp64
= gen_addq_msw(tmp64
, tmp
);
9283 tmp64
= gen_subq_msw(tmp64
, tmp
);
9286 if (insn
& (1 << 4)) {
9287 tcg_gen_addi_i64(tmp64
, tmp64
, 0x80000000u
);
9289 tcg_gen_shri_i64(tmp64
, tmp64
, 32);
9290 tmp
= tcg_temp_new_i32();
9291 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
9292 tcg_temp_free_i64(tmp64
);
9294 case 7: /* Unsigned sum of absolute differences. */
9295 gen_helper_usad8(tmp
, tmp
, tmp2
);
9296 tcg_temp_free_i32(tmp2
);
9298 tmp2
= load_reg(s
, rs
);
9299 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
9300 tcg_temp_free_i32(tmp2
);
9304 store_reg(s
, rd
, tmp
);
9306 case 6: case 7: /* 64-bit multiply, Divide. */
9307 op
= ((insn
>> 4) & 0xf) | ((insn
>> 16) & 0x70);
9308 tmp
= load_reg(s
, rn
);
9309 tmp2
= load_reg(s
, rm
);
9310 if ((op
& 0x50) == 0x10) {
9312 if (!arm_feature(env
, ARM_FEATURE_THUMB_DIV
)) {
9316 gen_helper_udiv(tmp
, tmp
, tmp2
);
9318 gen_helper_sdiv(tmp
, tmp
, tmp2
);
9319 tcg_temp_free_i32(tmp2
);
9320 store_reg(s
, rd
, tmp
);
9321 } else if ((op
& 0xe) == 0xc) {
9322 /* Dual multiply accumulate long. */
9324 gen_swap_half(tmp2
);
9325 gen_smul_dual(tmp
, tmp2
);
9327 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
9329 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
9331 tcg_temp_free_i32(tmp2
);
9333 tmp64
= tcg_temp_new_i64();
9334 tcg_gen_ext_i32_i64(tmp64
, tmp
);
9335 tcg_temp_free_i32(tmp
);
9336 gen_addq(s
, tmp64
, rs
, rd
);
9337 gen_storeq_reg(s
, rs
, rd
, tmp64
);
9338 tcg_temp_free_i64(tmp64
);
9341 /* Unsigned 64-bit multiply */
9342 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
9346 gen_mulxy(tmp
, tmp2
, op
& 2, op
& 1);
9347 tcg_temp_free_i32(tmp2
);
9348 tmp64
= tcg_temp_new_i64();
9349 tcg_gen_ext_i32_i64(tmp64
, tmp
);
9350 tcg_temp_free_i32(tmp
);
9352 /* Signed 64-bit multiply */
9353 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
9358 gen_addq_lo(s
, tmp64
, rs
);
9359 gen_addq_lo(s
, tmp64
, rd
);
9360 } else if (op
& 0x40) {
9361 /* 64-bit accumulate. */
9362 gen_addq(s
, tmp64
, rs
, rd
);
9364 gen_storeq_reg(s
, rs
, rd
, tmp64
);
9365 tcg_temp_free_i64(tmp64
);
9370 case 6: case 7: case 14: case 15:
9372 if (((insn
>> 24) & 3) == 3) {
9373 /* Translate into the equivalent ARM encoding. */
9374 insn
= (insn
& 0xe2ffffff) | ((insn
& (1 << 28)) >> 4) | (1 << 28);
9375 if (disas_neon_data_insn(env
, s
, insn
))
9377 } else if (((insn
>> 8) & 0xe) == 10) {
9378 if (disas_vfp_insn(env
, s
, insn
)) {
9382 if (insn
& (1 << 28))
9384 if (disas_coproc_insn (env
, s
, insn
))
9388 case 8: case 9: case 10: case 11:
9389 if (insn
& (1 << 15)) {
9390 /* Branches, misc control. */
9391 if (insn
& 0x5000) {
9392 /* Unconditional branch. */
9393 /* signextend(hw1[10:0]) -> offset[:12]. */
9394 offset
= ((int32_t)insn
<< 5) >> 9 & ~(int32_t)0xfff;
9395 /* hw1[10:0] -> offset[11:1]. */
9396 offset
|= (insn
& 0x7ff) << 1;
9397 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
9398 offset[24:22] already have the same value because of the
9399 sign extension above. */
9400 offset
^= ((~insn
) & (1 << 13)) << 10;
9401 offset
^= ((~insn
) & (1 << 11)) << 11;
9403 if (insn
& (1 << 14)) {
9404 /* Branch and link. */
9405 tcg_gen_movi_i32(cpu_R
[14], s
->pc
| 1);
9409 if (insn
& (1 << 12)) {
9414 offset
&= ~(uint32_t)2;
9415 /* thumb2 bx, no need to check */
9416 gen_bx_im(s
, offset
);
9418 } else if (((insn
>> 23) & 7) == 7) {
9420 if (insn
& (1 << 13))
9423 if (insn
& (1 << 26)) {
9424 /* Secure monitor call (v6Z) */
9425 qemu_log_mask(LOG_UNIMP
,
9426 "arm: unimplemented secure monitor call\n");
9427 goto illegal_op
; /* not implemented. */
9429 op
= (insn
>> 20) & 7;
9431 case 0: /* msr cpsr. */
9433 tmp
= load_reg(s
, rn
);
9434 addr
= tcg_const_i32(insn
& 0xff);
9435 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
9436 tcg_temp_free_i32(addr
);
9437 tcg_temp_free_i32(tmp
);
9442 case 1: /* msr spsr. */
9445 tmp
= load_reg(s
, rn
);
9447 msr_mask(env
, s
, (insn
>> 8) & 0xf, op
== 1),
9451 case 2: /* cps, nop-hint. */
9452 if (((insn
>> 8) & 7) == 0) {
9453 gen_nop_hint(s
, insn
& 0xff);
9455 /* Implemented as NOP in user mode. */
9460 if (insn
& (1 << 10)) {
9461 if (insn
& (1 << 7))
9463 if (insn
& (1 << 6))
9465 if (insn
& (1 << 5))
9467 if (insn
& (1 << 9))
9468 imm
= CPSR_A
| CPSR_I
| CPSR_F
;
9470 if (insn
& (1 << 8)) {
9472 imm
|= (insn
& 0x1f);
9475 gen_set_psr_im(s
, offset
, 0, imm
);
9478 case 3: /* Special control operations. */
9480 op
= (insn
>> 4) & 0xf;
9488 /* These execute as NOPs. */
9495 /* Trivial implementation equivalent to bx. */
9496 tmp
= load_reg(s
, rn
);
9499 case 5: /* Exception return. */
9503 if (rn
!= 14 || rd
!= 15) {
9506 tmp
= load_reg(s
, rn
);
9507 tcg_gen_subi_i32(tmp
, tmp
, insn
& 0xff);
9508 gen_exception_return(s
, tmp
);
9510 case 6: /* mrs cpsr. */
9511 tmp
= tcg_temp_new_i32();
9513 addr
= tcg_const_i32(insn
& 0xff);
9514 gen_helper_v7m_mrs(tmp
, cpu_env
, addr
);
9515 tcg_temp_free_i32(addr
);
9517 gen_helper_cpsr_read(tmp
, cpu_env
);
9519 store_reg(s
, rd
, tmp
);
9521 case 7: /* mrs spsr. */
9522 /* Not accessible in user mode. */
9523 if (IS_USER(s
) || IS_M(env
))
9525 tmp
= load_cpu_field(spsr
);
9526 store_reg(s
, rd
, tmp
);
9531 /* Conditional branch. */
9532 op
= (insn
>> 22) & 0xf;
9533 /* Generate a conditional jump to next instruction. */
9534 s
->condlabel
= gen_new_label();
9535 arm_gen_test_cc(op
^ 1, s
->condlabel
);
9538 /* offset[11:1] = insn[10:0] */
9539 offset
= (insn
& 0x7ff) << 1;
9540 /* offset[17:12] = insn[21:16]. */
9541 offset
|= (insn
& 0x003f0000) >> 4;
9542 /* offset[31:20] = insn[26]. */
9543 offset
|= ((int32_t)((insn
<< 5) & 0x80000000)) >> 11;
9544 /* offset[18] = insn[13]. */
9545 offset
|= (insn
& (1 << 13)) << 5;
9546 /* offset[19] = insn[11]. */
9547 offset
|= (insn
& (1 << 11)) << 8;
9549 /* jump to the offset */
9550 gen_jmp(s
, s
->pc
+ offset
);
9553 /* Data processing immediate. */
9554 if (insn
& (1 << 25)) {
9555 if (insn
& (1 << 24)) {
9556 if (insn
& (1 << 20))
9558 /* Bitfield/Saturate. */
9559 op
= (insn
>> 21) & 7;
9561 shift
= ((insn
>> 6) & 3) | ((insn
>> 10) & 0x1c);
9563 tmp
= tcg_temp_new_i32();
9564 tcg_gen_movi_i32(tmp
, 0);
9566 tmp
= load_reg(s
, rn
);
9569 case 2: /* Signed bitfield extract. */
9571 if (shift
+ imm
> 32)
9574 gen_sbfx(tmp
, shift
, imm
);
9576 case 6: /* Unsigned bitfield extract. */
9578 if (shift
+ imm
> 32)
9581 gen_ubfx(tmp
, shift
, (1u << imm
) - 1);
9583 case 3: /* Bitfield insert/clear. */
9586 imm
= imm
+ 1 - shift
;
9588 tmp2
= load_reg(s
, rd
);
9589 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, shift
, imm
);
9590 tcg_temp_free_i32(tmp2
);
9595 default: /* Saturate. */
9598 tcg_gen_sari_i32(tmp
, tmp
, shift
);
9600 tcg_gen_shli_i32(tmp
, tmp
, shift
);
9602 tmp2
= tcg_const_i32(imm
);
9605 if ((op
& 1) && shift
== 0)
9606 gen_helper_usat16(tmp
, cpu_env
, tmp
, tmp2
);
9608 gen_helper_usat(tmp
, cpu_env
, tmp
, tmp2
);
9611 if ((op
& 1) && shift
== 0)
9612 gen_helper_ssat16(tmp
, cpu_env
, tmp
, tmp2
);
9614 gen_helper_ssat(tmp
, cpu_env
, tmp
, tmp2
);
9616 tcg_temp_free_i32(tmp2
);
9619 store_reg(s
, rd
, tmp
);
9621 imm
= ((insn
& 0x04000000) >> 15)
9622 | ((insn
& 0x7000) >> 4) | (insn
& 0xff);
9623 if (insn
& (1 << 22)) {
9624 /* 16-bit immediate. */
9625 imm
|= (insn
>> 4) & 0xf000;
9626 if (insn
& (1 << 23)) {
9628 tmp
= load_reg(s
, rd
);
9629 tcg_gen_ext16u_i32(tmp
, tmp
);
9630 tcg_gen_ori_i32(tmp
, tmp
, imm
<< 16);
9633 tmp
= tcg_temp_new_i32();
9634 tcg_gen_movi_i32(tmp
, imm
);
9637 /* Add/sub 12-bit immediate. */
9639 offset
= s
->pc
& ~(uint32_t)3;
9640 if (insn
& (1 << 23))
9644 tmp
= tcg_temp_new_i32();
9645 tcg_gen_movi_i32(tmp
, offset
);
9647 tmp
= load_reg(s
, rn
);
9648 if (insn
& (1 << 23))
9649 tcg_gen_subi_i32(tmp
, tmp
, imm
);
9651 tcg_gen_addi_i32(tmp
, tmp
, imm
);
9654 store_reg(s
, rd
, tmp
);
9657 int shifter_out
= 0;
9658 /* modified 12-bit immediate. */
9659 shift
= ((insn
& 0x04000000) >> 23) | ((insn
& 0x7000) >> 12);
9660 imm
= (insn
& 0xff);
9663 /* Nothing to do. */
9665 case 1: /* 00XY00XY */
9668 case 2: /* XY00XY00 */
9672 case 3: /* XYXYXYXY */
9676 default: /* Rotated constant. */
9677 shift
= (shift
<< 1) | (imm
>> 7);
9679 imm
= imm
<< (32 - shift
);
9683 tmp2
= tcg_temp_new_i32();
9684 tcg_gen_movi_i32(tmp2
, imm
);
9685 rn
= (insn
>> 16) & 0xf;
9687 tmp
= tcg_temp_new_i32();
9688 tcg_gen_movi_i32(tmp
, 0);
9690 tmp
= load_reg(s
, rn
);
9692 op
= (insn
>> 21) & 0xf;
9693 if (gen_thumb2_data_op(s
, op
, (insn
& (1 << 20)) != 0,
9694 shifter_out
, tmp
, tmp2
))
9696 tcg_temp_free_i32(tmp2
);
9697 rd
= (insn
>> 8) & 0xf;
9699 store_reg(s
, rd
, tmp
);
9701 tcg_temp_free_i32(tmp
);
9706 case 12: /* Load/store single data item. */
9711 if ((insn
& 0x01100000) == 0x01000000) {
9712 if (disas_neon_ls_insn(env
, s
, insn
))
9716 op
= ((insn
>> 21) & 3) | ((insn
>> 22) & 4);
9718 if (!(insn
& (1 << 20))) {
9722 /* Byte or halfword load space with dest == r15 : memory hints.
9723 * Catch them early so we don't emit pointless addressing code.
9724 * This space is a mix of:
9725 * PLD/PLDW/PLI, which we implement as NOPs (note that unlike
9726 * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP
9728 * unallocated hints, which must be treated as NOPs
9729 * UNPREDICTABLE space, which we NOP or UNDEF depending on
9730 * which is easiest for the decoding logic
9731 * Some space which must UNDEF
9733 int op1
= (insn
>> 23) & 3;
9734 int op2
= (insn
>> 6) & 0x3f;
9739 /* UNPREDICTABLE, unallocated hint or
9740 * PLD/PLDW/PLI (literal)
9745 return 0; /* PLD/PLDW/PLI or unallocated hint */
9747 if ((op2
== 0) || ((op2
& 0x3c) == 0x30)) {
9748 return 0; /* PLD/PLDW/PLI or unallocated hint */
9750 /* UNDEF space, or an UNPREDICTABLE */
9756 addr
= tcg_temp_new_i32();
9758 /* s->pc has already been incremented by 4. */
9759 imm
= s
->pc
& 0xfffffffc;
9760 if (insn
& (1 << 23))
9761 imm
+= insn
& 0xfff;
9763 imm
-= insn
& 0xfff;
9764 tcg_gen_movi_i32(addr
, imm
);
9766 addr
= load_reg(s
, rn
);
9767 if (insn
& (1 << 23)) {
9768 /* Positive offset. */
9770 tcg_gen_addi_i32(addr
, addr
, imm
);
9773 switch ((insn
>> 8) & 0xf) {
9774 case 0x0: /* Shifted Register. */
9775 shift
= (insn
>> 4) & 0xf;
9777 tcg_temp_free_i32(addr
);
9780 tmp
= load_reg(s
, rm
);
9782 tcg_gen_shli_i32(tmp
, tmp
, shift
);
9783 tcg_gen_add_i32(addr
, addr
, tmp
);
9784 tcg_temp_free_i32(tmp
);
9786 case 0xc: /* Negative offset. */
9787 tcg_gen_addi_i32(addr
, addr
, -imm
);
9789 case 0xe: /* User privilege. */
9790 tcg_gen_addi_i32(addr
, addr
, imm
);
9793 case 0x9: /* Post-decrement. */
9796 case 0xb: /* Post-increment. */
9800 case 0xd: /* Pre-decrement. */
9803 case 0xf: /* Pre-increment. */
9804 tcg_gen_addi_i32(addr
, addr
, imm
);
9808 tcg_temp_free_i32(addr
);
9813 if (insn
& (1 << 20)) {
9815 tmp
= tcg_temp_new_i32();
9818 gen_aa32_ld8u(tmp
, addr
, user
);
9821 gen_aa32_ld8s(tmp
, addr
, user
);
9824 gen_aa32_ld16u(tmp
, addr
, user
);
9827 gen_aa32_ld16s(tmp
, addr
, user
);
9830 gen_aa32_ld32u(tmp
, addr
, user
);
9833 tcg_temp_free_i32(tmp
);
9834 tcg_temp_free_i32(addr
);
9840 store_reg(s
, rs
, tmp
);
9844 tmp
= load_reg(s
, rs
);
9847 gen_aa32_st8(tmp
, addr
, user
);
9850 gen_aa32_st16(tmp
, addr
, user
);
9853 gen_aa32_st32(tmp
, addr
, user
);
9856 tcg_temp_free_i32(tmp
);
9857 tcg_temp_free_i32(addr
);
9860 tcg_temp_free_i32(tmp
);
9863 tcg_gen_addi_i32(addr
, addr
, imm
);
9865 store_reg(s
, rn
, addr
);
9867 tcg_temp_free_i32(addr
);
9879 static void disas_thumb_insn(CPUARMState
*env
, DisasContext
*s
)
9881 uint32_t val
, insn
, op
, rm
, rn
, rd
, shift
, cond
;
9888 if (s
->condexec_mask
) {
9889 cond
= s
->condexec_cond
;
9890 if (cond
!= 0x0e) { /* Skip conditional when condition is AL. */
9891 s
->condlabel
= gen_new_label();
9892 arm_gen_test_cc(cond
^ 1, s
->condlabel
);
9897 insn
= arm_lduw_code(env
, s
->pc
, s
->bswap_code
);
9900 switch (insn
>> 12) {
9904 op
= (insn
>> 11) & 3;
9907 rn
= (insn
>> 3) & 7;
9908 tmp
= load_reg(s
, rn
);
9909 if (insn
& (1 << 10)) {
9911 tmp2
= tcg_temp_new_i32();
9912 tcg_gen_movi_i32(tmp2
, (insn
>> 6) & 7);
9915 rm
= (insn
>> 6) & 7;
9916 tmp2
= load_reg(s
, rm
);
9918 if (insn
& (1 << 9)) {
9919 if (s
->condexec_mask
)
9920 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
9922 gen_sub_CC(tmp
, tmp
, tmp2
);
9924 if (s
->condexec_mask
)
9925 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
9927 gen_add_CC(tmp
, tmp
, tmp2
);
9929 tcg_temp_free_i32(tmp2
);
9930 store_reg(s
, rd
, tmp
);
9932 /* shift immediate */
9933 rm
= (insn
>> 3) & 7;
9934 shift
= (insn
>> 6) & 0x1f;
9935 tmp
= load_reg(s
, rm
);
9936 gen_arm_shift_im(tmp
, op
, shift
, s
->condexec_mask
== 0);
9937 if (!s
->condexec_mask
)
9939 store_reg(s
, rd
, tmp
);
9943 /* arithmetic large immediate */
9944 op
= (insn
>> 11) & 3;
9945 rd
= (insn
>> 8) & 0x7;
9946 if (op
== 0) { /* mov */
9947 tmp
= tcg_temp_new_i32();
9948 tcg_gen_movi_i32(tmp
, insn
& 0xff);
9949 if (!s
->condexec_mask
)
9951 store_reg(s
, rd
, tmp
);
9953 tmp
= load_reg(s
, rd
);
9954 tmp2
= tcg_temp_new_i32();
9955 tcg_gen_movi_i32(tmp2
, insn
& 0xff);
9958 gen_sub_CC(tmp
, tmp
, tmp2
);
9959 tcg_temp_free_i32(tmp
);
9960 tcg_temp_free_i32(tmp2
);
9963 if (s
->condexec_mask
)
9964 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
9966 gen_add_CC(tmp
, tmp
, tmp2
);
9967 tcg_temp_free_i32(tmp2
);
9968 store_reg(s
, rd
, tmp
);
9971 if (s
->condexec_mask
)
9972 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
9974 gen_sub_CC(tmp
, tmp
, tmp2
);
9975 tcg_temp_free_i32(tmp2
);
9976 store_reg(s
, rd
, tmp
);
9982 if (insn
& (1 << 11)) {
9983 rd
= (insn
>> 8) & 7;
9984 /* load pc-relative. Bit 1 of PC is ignored. */
9985 val
= s
->pc
+ 2 + ((insn
& 0xff) * 4);
9986 val
&= ~(uint32_t)2;
9987 addr
= tcg_temp_new_i32();
9988 tcg_gen_movi_i32(addr
, val
);
9989 tmp
= tcg_temp_new_i32();
9990 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
9991 tcg_temp_free_i32(addr
);
9992 store_reg(s
, rd
, tmp
);
9995 if (insn
& (1 << 10)) {
9996 /* data processing extended or blx */
9997 rd
= (insn
& 7) | ((insn
>> 4) & 8);
9998 rm
= (insn
>> 3) & 0xf;
9999 op
= (insn
>> 8) & 3;
10002 tmp
= load_reg(s
, rd
);
10003 tmp2
= load_reg(s
, rm
);
10004 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
10005 tcg_temp_free_i32(tmp2
);
10006 store_reg(s
, rd
, tmp
);
10009 tmp
= load_reg(s
, rd
);
10010 tmp2
= load_reg(s
, rm
);
10011 gen_sub_CC(tmp
, tmp
, tmp2
);
10012 tcg_temp_free_i32(tmp2
);
10013 tcg_temp_free_i32(tmp
);
10015 case 2: /* mov/cpy */
10016 tmp
= load_reg(s
, rm
);
10017 store_reg(s
, rd
, tmp
);
10019 case 3:/* branch [and link] exchange thumb register */
10020 tmp
= load_reg(s
, rm
);
10021 if (insn
& (1 << 7)) {
10023 val
= (uint32_t)s
->pc
| 1;
10024 tmp2
= tcg_temp_new_i32();
10025 tcg_gen_movi_i32(tmp2
, val
);
10026 store_reg(s
, 14, tmp2
);
10028 /* already thumb, no need to check */
10035 /* data processing register */
10037 rm
= (insn
>> 3) & 7;
10038 op
= (insn
>> 6) & 0xf;
10039 if (op
== 2 || op
== 3 || op
== 4 || op
== 7) {
10040 /* the shift/rotate ops want the operands backwards */
10049 if (op
== 9) { /* neg */
10050 tmp
= tcg_temp_new_i32();
10051 tcg_gen_movi_i32(tmp
, 0);
10052 } else if (op
!= 0xf) { /* mvn doesn't read its first operand */
10053 tmp
= load_reg(s
, rd
);
10055 TCGV_UNUSED_I32(tmp
);
10058 tmp2
= load_reg(s
, rm
);
10060 case 0x0: /* and */
10061 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
10062 if (!s
->condexec_mask
)
10065 case 0x1: /* eor */
10066 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
10067 if (!s
->condexec_mask
)
10070 case 0x2: /* lsl */
10071 if (s
->condexec_mask
) {
10072 gen_shl(tmp2
, tmp2
, tmp
);
10074 gen_helper_shl_cc(tmp2
, cpu_env
, tmp2
, tmp
);
10075 gen_logic_CC(tmp2
);
10078 case 0x3: /* lsr */
10079 if (s
->condexec_mask
) {
10080 gen_shr(tmp2
, tmp2
, tmp
);
10082 gen_helper_shr_cc(tmp2
, cpu_env
, tmp2
, tmp
);
10083 gen_logic_CC(tmp2
);
10086 case 0x4: /* asr */
10087 if (s
->condexec_mask
) {
10088 gen_sar(tmp2
, tmp2
, tmp
);
10090 gen_helper_sar_cc(tmp2
, cpu_env
, tmp2
, tmp
);
10091 gen_logic_CC(tmp2
);
10094 case 0x5: /* adc */
10095 if (s
->condexec_mask
) {
10096 gen_adc(tmp
, tmp2
);
10098 gen_adc_CC(tmp
, tmp
, tmp2
);
10101 case 0x6: /* sbc */
10102 if (s
->condexec_mask
) {
10103 gen_sub_carry(tmp
, tmp
, tmp2
);
10105 gen_sbc_CC(tmp
, tmp
, tmp2
);
10108 case 0x7: /* ror */
10109 if (s
->condexec_mask
) {
10110 tcg_gen_andi_i32(tmp
, tmp
, 0x1f);
10111 tcg_gen_rotr_i32(tmp2
, tmp2
, tmp
);
10113 gen_helper_ror_cc(tmp2
, cpu_env
, tmp2
, tmp
);
10114 gen_logic_CC(tmp2
);
10117 case 0x8: /* tst */
10118 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
10122 case 0x9: /* neg */
10123 if (s
->condexec_mask
)
10124 tcg_gen_neg_i32(tmp
, tmp2
);
10126 gen_sub_CC(tmp
, tmp
, tmp2
);
10128 case 0xa: /* cmp */
10129 gen_sub_CC(tmp
, tmp
, tmp2
);
10132 case 0xb: /* cmn */
10133 gen_add_CC(tmp
, tmp
, tmp2
);
10136 case 0xc: /* orr */
10137 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
10138 if (!s
->condexec_mask
)
10141 case 0xd: /* mul */
10142 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
10143 if (!s
->condexec_mask
)
10146 case 0xe: /* bic */
10147 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
10148 if (!s
->condexec_mask
)
10151 case 0xf: /* mvn */
10152 tcg_gen_not_i32(tmp2
, tmp2
);
10153 if (!s
->condexec_mask
)
10154 gen_logic_CC(tmp2
);
10161 store_reg(s
, rm
, tmp2
);
10163 tcg_temp_free_i32(tmp
);
10165 store_reg(s
, rd
, tmp
);
10166 tcg_temp_free_i32(tmp2
);
10169 tcg_temp_free_i32(tmp
);
10170 tcg_temp_free_i32(tmp2
);
10175 /* load/store register offset. */
10177 rn
= (insn
>> 3) & 7;
10178 rm
= (insn
>> 6) & 7;
10179 op
= (insn
>> 9) & 7;
10180 addr
= load_reg(s
, rn
);
10181 tmp
= load_reg(s
, rm
);
10182 tcg_gen_add_i32(addr
, addr
, tmp
);
10183 tcg_temp_free_i32(tmp
);
10185 if (op
< 3) { /* store */
10186 tmp
= load_reg(s
, rd
);
10188 tmp
= tcg_temp_new_i32();
10193 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
10196 gen_aa32_st16(tmp
, addr
, IS_USER(s
));
10199 gen_aa32_st8(tmp
, addr
, IS_USER(s
));
10201 case 3: /* ldrsb */
10202 gen_aa32_ld8s(tmp
, addr
, IS_USER(s
));
10205 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
10208 gen_aa32_ld16u(tmp
, addr
, IS_USER(s
));
10211 gen_aa32_ld8u(tmp
, addr
, IS_USER(s
));
10213 case 7: /* ldrsh */
10214 gen_aa32_ld16s(tmp
, addr
, IS_USER(s
));
10217 if (op
>= 3) { /* load */
10218 store_reg(s
, rd
, tmp
);
10220 tcg_temp_free_i32(tmp
);
10222 tcg_temp_free_i32(addr
);
10226 /* load/store word immediate offset */
10228 rn
= (insn
>> 3) & 7;
10229 addr
= load_reg(s
, rn
);
10230 val
= (insn
>> 4) & 0x7c;
10231 tcg_gen_addi_i32(addr
, addr
, val
);
10233 if (insn
& (1 << 11)) {
10235 tmp
= tcg_temp_new_i32();
10236 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
10237 store_reg(s
, rd
, tmp
);
10240 tmp
= load_reg(s
, rd
);
10241 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
10242 tcg_temp_free_i32(tmp
);
10244 tcg_temp_free_i32(addr
);
10248 /* load/store byte immediate offset */
10250 rn
= (insn
>> 3) & 7;
10251 addr
= load_reg(s
, rn
);
10252 val
= (insn
>> 6) & 0x1f;
10253 tcg_gen_addi_i32(addr
, addr
, val
);
10255 if (insn
& (1 << 11)) {
10257 tmp
= tcg_temp_new_i32();
10258 gen_aa32_ld8u(tmp
, addr
, IS_USER(s
));
10259 store_reg(s
, rd
, tmp
);
10262 tmp
= load_reg(s
, rd
);
10263 gen_aa32_st8(tmp
, addr
, IS_USER(s
));
10264 tcg_temp_free_i32(tmp
);
10266 tcg_temp_free_i32(addr
);
10270 /* load/store halfword immediate offset */
10272 rn
= (insn
>> 3) & 7;
10273 addr
= load_reg(s
, rn
);
10274 val
= (insn
>> 5) & 0x3e;
10275 tcg_gen_addi_i32(addr
, addr
, val
);
10277 if (insn
& (1 << 11)) {
10279 tmp
= tcg_temp_new_i32();
10280 gen_aa32_ld16u(tmp
, addr
, IS_USER(s
));
10281 store_reg(s
, rd
, tmp
);
10284 tmp
= load_reg(s
, rd
);
10285 gen_aa32_st16(tmp
, addr
, IS_USER(s
));
10286 tcg_temp_free_i32(tmp
);
10288 tcg_temp_free_i32(addr
);
10292 /* load/store from stack */
10293 rd
= (insn
>> 8) & 7;
10294 addr
= load_reg(s
, 13);
10295 val
= (insn
& 0xff) * 4;
10296 tcg_gen_addi_i32(addr
, addr
, val
);
10298 if (insn
& (1 << 11)) {
10300 tmp
= tcg_temp_new_i32();
10301 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
10302 store_reg(s
, rd
, tmp
);
10305 tmp
= load_reg(s
, rd
);
10306 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
10307 tcg_temp_free_i32(tmp
);
10309 tcg_temp_free_i32(addr
);
10313 /* add to high reg */
10314 rd
= (insn
>> 8) & 7;
10315 if (insn
& (1 << 11)) {
10317 tmp
= load_reg(s
, 13);
10319 /* PC. bit 1 is ignored. */
10320 tmp
= tcg_temp_new_i32();
10321 tcg_gen_movi_i32(tmp
, (s
->pc
+ 2) & ~(uint32_t)2);
10323 val
= (insn
& 0xff) * 4;
10324 tcg_gen_addi_i32(tmp
, tmp
, val
);
10325 store_reg(s
, rd
, tmp
);
10330 op
= (insn
>> 8) & 0xf;
10333 /* adjust stack pointer */
10334 tmp
= load_reg(s
, 13);
10335 val
= (insn
& 0x7f) * 4;
10336 if (insn
& (1 << 7))
10337 val
= -(int32_t)val
;
10338 tcg_gen_addi_i32(tmp
, tmp
, val
);
10339 store_reg(s
, 13, tmp
);
10342 case 2: /* sign/zero extend. */
10345 rm
= (insn
>> 3) & 7;
10346 tmp
= load_reg(s
, rm
);
10347 switch ((insn
>> 6) & 3) {
10348 case 0: gen_sxth(tmp
); break;
10349 case 1: gen_sxtb(tmp
); break;
10350 case 2: gen_uxth(tmp
); break;
10351 case 3: gen_uxtb(tmp
); break;
10353 store_reg(s
, rd
, tmp
);
10355 case 4: case 5: case 0xc: case 0xd:
10357 addr
= load_reg(s
, 13);
10358 if (insn
& (1 << 8))
10362 for (i
= 0; i
< 8; i
++) {
10363 if (insn
& (1 << i
))
10366 if ((insn
& (1 << 11)) == 0) {
10367 tcg_gen_addi_i32(addr
, addr
, -offset
);
10369 for (i
= 0; i
< 8; i
++) {
10370 if (insn
& (1 << i
)) {
10371 if (insn
& (1 << 11)) {
10373 tmp
= tcg_temp_new_i32();
10374 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
10375 store_reg(s
, i
, tmp
);
10378 tmp
= load_reg(s
, i
);
10379 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
10380 tcg_temp_free_i32(tmp
);
10382 /* advance to the next address. */
10383 tcg_gen_addi_i32(addr
, addr
, 4);
10386 TCGV_UNUSED_I32(tmp
);
10387 if (insn
& (1 << 8)) {
10388 if (insn
& (1 << 11)) {
10390 tmp
= tcg_temp_new_i32();
10391 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
10392 /* don't set the pc until the rest of the instruction
10396 tmp
= load_reg(s
, 14);
10397 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
10398 tcg_temp_free_i32(tmp
);
10400 tcg_gen_addi_i32(addr
, addr
, 4);
10402 if ((insn
& (1 << 11)) == 0) {
10403 tcg_gen_addi_i32(addr
, addr
, -offset
);
10405 /* write back the new stack pointer */
10406 store_reg(s
, 13, addr
);
10407 /* set the new PC value */
10408 if ((insn
& 0x0900) == 0x0900) {
10409 store_reg_from_load(env
, s
, 15, tmp
);
10413 case 1: case 3: case 9: case 11: /* czb */
10415 tmp
= load_reg(s
, rm
);
10416 s
->condlabel
= gen_new_label();
10418 if (insn
& (1 << 11))
10419 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, s
->condlabel
);
10421 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, s
->condlabel
);
10422 tcg_temp_free_i32(tmp
);
10423 offset
= ((insn
& 0xf8) >> 2) | (insn
& 0x200) >> 3;
10424 val
= (uint32_t)s
->pc
+ 2;
10429 case 15: /* IT, nop-hint. */
10430 if ((insn
& 0xf) == 0) {
10431 gen_nop_hint(s
, (insn
>> 4) & 0xf);
10435 s
->condexec_cond
= (insn
>> 4) & 0xe;
10436 s
->condexec_mask
= insn
& 0x1f;
10437 /* No actual code generated for this insn, just setup state. */
10440 case 0xe: /* bkpt */
10442 gen_exception_insn(s
, 2, EXCP_BKPT
);
10445 case 0xa: /* rev */
10447 rn
= (insn
>> 3) & 0x7;
10449 tmp
= load_reg(s
, rn
);
10450 switch ((insn
>> 6) & 3) {
10451 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
10452 case 1: gen_rev16(tmp
); break;
10453 case 3: gen_revsh(tmp
); break;
10454 default: goto illegal_op
;
10456 store_reg(s
, rd
, tmp
);
10460 switch ((insn
>> 5) & 7) {
10464 if (((insn
>> 3) & 1) != s
->bswap_code
) {
10465 /* Dynamic endianness switching not implemented. */
10466 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented setend\n");
10477 tmp
= tcg_const_i32((insn
& (1 << 4)) != 0);
10480 addr
= tcg_const_i32(19);
10481 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
10482 tcg_temp_free_i32(addr
);
10486 addr
= tcg_const_i32(16);
10487 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
10488 tcg_temp_free_i32(addr
);
10490 tcg_temp_free_i32(tmp
);
10493 if (insn
& (1 << 4)) {
10494 shift
= CPSR_A
| CPSR_I
| CPSR_F
;
10498 gen_set_psr_im(s
, ((insn
& 7) << 6), 0, shift
);
10513 /* load/store multiple */
10514 TCGv_i32 loaded_var
;
10515 TCGV_UNUSED_I32(loaded_var
);
10516 rn
= (insn
>> 8) & 0x7;
10517 addr
= load_reg(s
, rn
);
10518 for (i
= 0; i
< 8; i
++) {
10519 if (insn
& (1 << i
)) {
10520 if (insn
& (1 << 11)) {
10522 tmp
= tcg_temp_new_i32();
10523 gen_aa32_ld32u(tmp
, addr
, IS_USER(s
));
10527 store_reg(s
, i
, tmp
);
10531 tmp
= load_reg(s
, i
);
10532 gen_aa32_st32(tmp
, addr
, IS_USER(s
));
10533 tcg_temp_free_i32(tmp
);
10535 /* advance to the next address */
10536 tcg_gen_addi_i32(addr
, addr
, 4);
10539 if ((insn
& (1 << rn
)) == 0) {
10540 /* base reg not in list: base register writeback */
10541 store_reg(s
, rn
, addr
);
10543 /* base reg in list: if load, complete it now */
10544 if (insn
& (1 << 11)) {
10545 store_reg(s
, rn
, loaded_var
);
10547 tcg_temp_free_i32(addr
);
10552 /* conditional branch or swi */
10553 cond
= (insn
>> 8) & 0xf;
10559 gen_set_pc_im(s
, s
->pc
);
10560 s
->is_jmp
= DISAS_SWI
;
10563 /* generate a conditional jump to next instruction */
10564 s
->condlabel
= gen_new_label();
10565 arm_gen_test_cc(cond
^ 1, s
->condlabel
);
10568 /* jump to the offset */
10569 val
= (uint32_t)s
->pc
+ 2;
10570 offset
= ((int32_t)insn
<< 24) >> 24;
10571 val
+= offset
<< 1;
10576 if (insn
& (1 << 11)) {
10577 if (disas_thumb2_insn(env
, s
, insn
))
10581 /* unconditional branch */
10582 val
= (uint32_t)s
->pc
;
10583 offset
= ((int32_t)insn
<< 21) >> 21;
10584 val
+= (offset
<< 1) + 2;
10589 if (disas_thumb2_insn(env
, s
, insn
))
10595 gen_exception_insn(s
, 4, EXCP_UDEF
);
10599 gen_exception_insn(s
, 2, EXCP_UDEF
);
10602 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
10603 basic block 'tb'. If search_pc is TRUE, also generate PC
10604 information for each intermediate instruction. */
10605 static inline void gen_intermediate_code_internal(ARMCPU
*cpu
,
10606 TranslationBlock
*tb
,
10609 CPUState
*cs
= CPU(cpu
);
10610 CPUARMState
*env
= &cpu
->env
;
10611 DisasContext dc1
, *dc
= &dc1
;
10613 uint16_t *gen_opc_end
;
10615 target_ulong pc_start
;
10616 target_ulong next_page_start
;
10620 /* generate intermediate code */
10622 /* The A64 decoder has its own top level loop, because it doesn't need
10623 * the A32/T32 complexity to do with conditional execution/IT blocks/etc.
10625 if (ARM_TBFLAG_AARCH64_STATE(tb
->flags
)) {
10626 gen_intermediate_code_internal_a64(cpu
, tb
, search_pc
);
10634 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
10636 dc
->is_jmp
= DISAS_NEXT
;
10638 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
10642 dc
->thumb
= ARM_TBFLAG_THUMB(tb
->flags
);
10643 dc
->bswap_code
= ARM_TBFLAG_BSWAP_CODE(tb
->flags
);
10644 dc
->condexec_mask
= (ARM_TBFLAG_CONDEXEC(tb
->flags
) & 0xf) << 1;
10645 dc
->condexec_cond
= ARM_TBFLAG_CONDEXEC(tb
->flags
) >> 4;
10646 #if !defined(CONFIG_USER_ONLY)
10647 dc
->user
= (ARM_TBFLAG_PRIV(tb
->flags
) == 0);
10649 dc
->vfp_enabled
= ARM_TBFLAG_VFPEN(tb
->flags
);
10650 dc
->vec_len
= ARM_TBFLAG_VECLEN(tb
->flags
);
10651 dc
->vec_stride
= ARM_TBFLAG_VECSTRIDE(tb
->flags
);
10652 dc
->cp_regs
= cpu
->cp_regs
;
10653 dc
->current_pl
= arm_current_pl(env
);
10655 cpu_F0s
= tcg_temp_new_i32();
10656 cpu_F1s
= tcg_temp_new_i32();
10657 cpu_F0d
= tcg_temp_new_i64();
10658 cpu_F1d
= tcg_temp_new_i64();
10661 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
10662 cpu_M0
= tcg_temp_new_i64();
10663 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
10666 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
10667 if (max_insns
== 0)
10668 max_insns
= CF_COUNT_MASK
;
10672 tcg_clear_temp_count();
10674 /* A note on handling of the condexec (IT) bits:
10676 * We want to avoid the overhead of having to write the updated condexec
10677 * bits back to the CPUARMState for every instruction in an IT block. So:
10678 * (1) if the condexec bits are not already zero then we write
10679 * zero back into the CPUARMState now. This avoids complications trying
10680 * to do it at the end of the block. (For example if we don't do this
10681 * it's hard to identify whether we can safely skip writing condexec
10682 * at the end of the TB, which we definitely want to do for the case
10683 * where a TB doesn't do anything with the IT state at all.)
10684 * (2) if we are going to leave the TB then we call gen_set_condexec()
10685 * which will write the correct value into CPUARMState if zero is wrong.
10686 * This is done both for leaving the TB at the end, and for leaving
10687 * it because of an exception we know will happen, which is done in
10688 * gen_exception_insn(). The latter is necessary because we need to
10689 * leave the TB with the PC/IT state just prior to execution of the
10690 * instruction which caused the exception.
10691 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
10692 * then the CPUARMState will be wrong and we need to reset it.
10693 * This is handled in the same way as restoration of the
10694 * PC in these situations: we will be called again with search_pc=1
10695 * and generate a mapping of the condexec bits for each PC in
10696 * gen_opc_condexec_bits[]. restore_state_to_opc() then uses
10697 * this to restore the condexec bits.
10699 * Note that there are no instructions which can read the condexec
10700 * bits, and none which can write non-static values to them, so
10701 * we don't need to care about whether CPUARMState is correct in the
10705 /* Reset the conditional execution bits immediately. This avoids
10706 complications trying to do it at the end of the block. */
10707 if (dc
->condexec_mask
|| dc
->condexec_cond
)
10709 TCGv_i32 tmp
= tcg_temp_new_i32();
10710 tcg_gen_movi_i32(tmp
, 0);
10711 store_cpu_field(tmp
, condexec_bits
);
10714 #ifdef CONFIG_USER_ONLY
10715 /* Intercept jump to the magic kernel page. */
10716 if (dc
->pc
>= 0xffff0000) {
10717 /* We always get here via a jump, so know we are not in a
10718 conditional execution block. */
10719 gen_exception(EXCP_KERNEL_TRAP
);
10720 dc
->is_jmp
= DISAS_UPDATE
;
10724 if (dc
->pc
>= 0xfffffff0 && IS_M(env
)) {
10725 /* We always get here via a jump, so know we are not in a
10726 conditional execution block. */
10727 gen_exception(EXCP_EXCEPTION_EXIT
);
10728 dc
->is_jmp
= DISAS_UPDATE
;
10733 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
10734 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
10735 if (bp
->pc
== dc
->pc
) {
10736 gen_exception_insn(dc
, 0, EXCP_DEBUG
);
10737 /* Advance PC so that clearing the breakpoint will
10738 invalidate this TB. */
10740 goto done_generating
;
10745 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
10749 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
10751 tcg_ctx
.gen_opc_pc
[lj
] = dc
->pc
;
10752 gen_opc_condexec_bits
[lj
] = (dc
->condexec_cond
<< 4) | (dc
->condexec_mask
>> 1);
10753 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
10754 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
10757 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
10760 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
10761 tcg_gen_debug_insn_start(dc
->pc
);
10765 disas_thumb_insn(env
, dc
);
10766 if (dc
->condexec_mask
) {
10767 dc
->condexec_cond
= (dc
->condexec_cond
& 0xe)
10768 | ((dc
->condexec_mask
>> 4) & 1);
10769 dc
->condexec_mask
= (dc
->condexec_mask
<< 1) & 0x1f;
10770 if (dc
->condexec_mask
== 0) {
10771 dc
->condexec_cond
= 0;
10775 disas_arm_insn(env
, dc
);
10778 if (dc
->condjmp
&& !dc
->is_jmp
) {
10779 gen_set_label(dc
->condlabel
);
10783 if (tcg_check_temp_count()) {
10784 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
10788 /* Translation stops when a conditional branch is encountered.
10789 * Otherwise the subsequent code could get translated several times.
10790 * Also stop translation when a page boundary is reached. This
10791 * ensures prefetch aborts occur at the right place. */
10793 } while (!dc
->is_jmp
&& tcg_ctx
.gen_opc_ptr
< gen_opc_end
&&
10794 !cs
->singlestep_enabled
&&
10796 dc
->pc
< next_page_start
&&
10797 num_insns
< max_insns
);
10799 if (tb
->cflags
& CF_LAST_IO
) {
10801 /* FIXME: This can theoretically happen with self-modifying
10803 cpu_abort(env
, "IO on conditional branch instruction");
10808 /* At this stage dc->condjmp will only be set when the skipped
10809 instruction was a conditional branch or trap, and the PC has
10810 already been written. */
10811 if (unlikely(cs
->singlestep_enabled
)) {
10812 /* Make sure the pc is updated, and raise a debug exception. */
10814 gen_set_condexec(dc
);
10815 if (dc
->is_jmp
== DISAS_SWI
) {
10816 gen_exception(EXCP_SWI
);
10818 gen_exception(EXCP_DEBUG
);
10820 gen_set_label(dc
->condlabel
);
10822 if (dc
->condjmp
|| !dc
->is_jmp
) {
10823 gen_set_pc_im(dc
, dc
->pc
);
10826 gen_set_condexec(dc
);
10827 if (dc
->is_jmp
== DISAS_SWI
&& !dc
->condjmp
) {
10828 gen_exception(EXCP_SWI
);
10830 /* FIXME: Single stepping a WFI insn will not halt
10832 gen_exception(EXCP_DEBUG
);
10835 /* While branches must always occur at the end of an IT block,
10836 there are a few other things that can cause us to terminate
10837 the TB in the middle of an IT block:
10838 - Exception generating instructions (bkpt, swi, undefined).
10840 - Hardware watchpoints.
10841 Hardware breakpoints have already been handled and skip this code.
10843 gen_set_condexec(dc
);
10844 switch(dc
->is_jmp
) {
10846 gen_goto_tb(dc
, 1, dc
->pc
);
10851 /* indicate that the hash table must be used to find the next TB */
10852 tcg_gen_exit_tb(0);
10854 case DISAS_TB_JUMP
:
10855 /* nothing more to generate */
10858 gen_helper_wfi(cpu_env
);
10861 gen_exception(EXCP_SWI
);
10865 gen_set_label(dc
->condlabel
);
10866 gen_set_condexec(dc
);
10867 gen_goto_tb(dc
, 1, dc
->pc
);
10873 gen_tb_end(tb
, num_insns
);
10874 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
10877 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
10878 qemu_log("----------------\n");
10879 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
10880 log_target_disas(env
, pc_start
, dc
->pc
- pc_start
,
10881 dc
->thumb
| (dc
->bswap_code
<< 1));
10886 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
10889 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
10891 tb
->size
= dc
->pc
- pc_start
;
10892 tb
->icount
= num_insns
;
10896 void gen_intermediate_code(CPUARMState
*env
, TranslationBlock
*tb
)
10898 gen_intermediate_code_internal(arm_env_get_cpu(env
), tb
, false);
10901 void gen_intermediate_code_pc(CPUARMState
*env
, TranslationBlock
*tb
)
10903 gen_intermediate_code_internal(arm_env_get_cpu(env
), tb
, true);
10906 static const char *cpu_mode_names
[16] = {
10907 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
10908 "???", "???", "???", "und", "???", "???", "???", "sys"
10911 void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
10914 ARMCPU
*cpu
= ARM_CPU(cs
);
10915 CPUARMState
*env
= &cpu
->env
;
10919 for(i
=0;i
<16;i
++) {
10920 cpu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
10922 cpu_fprintf(f
, "\n");
10924 cpu_fprintf(f
, " ");
10926 psr
= cpsr_read(env
);
10927 cpu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%d\n",
10929 psr
& (1 << 31) ? 'N' : '-',
10930 psr
& (1 << 30) ? 'Z' : '-',
10931 psr
& (1 << 29) ? 'C' : '-',
10932 psr
& (1 << 28) ? 'V' : '-',
10933 psr
& CPSR_T
? 'T' : 'A',
10934 cpu_mode_names
[psr
& 0xf], (psr
& 0x10) ? 32 : 26);
10936 if (flags
& CPU_DUMP_FPU
) {
10937 int numvfpregs
= 0;
10938 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
10941 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
10944 for (i
= 0; i
< numvfpregs
; i
++) {
10945 uint64_t v
= float64_val(env
->vfp
.regs
[i
]);
10946 cpu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
10947 i
* 2, (uint32_t)v
,
10948 i
* 2 + 1, (uint32_t)(v
>> 32),
10951 cpu_fprintf(f
, "FPSCR: %08x\n", (int)env
->vfp
.xregs
[ARM_VFP_FPSCR
]);
10955 void restore_state_to_opc(CPUARMState
*env
, TranslationBlock
*tb
, int pc_pos
)
10958 env
->pc
= tcg_ctx
.gen_opc_pc
[pc_pos
];
10959 env
->condexec_bits
= 0;
10961 env
->regs
[15] = tcg_ctx
.gen_opc_pc
[pc_pos
];
10962 env
->condexec_bits
= gen_opc_condexec_bits
[pc_pos
];