2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 * o Isochronous transfers
22 * o Allocate bandwidth in frames properly
23 * o Disable timers when nothing needs to be done, or remove timer usage
25 * o BIOS work to boot from USB storage
28 #include "qemu/osdep.h"
30 #include "qemu/timer.h"
32 #include "hw/pci/pci.h"
33 #include "hw/sysbus.h"
34 #include "hw/qdev-dma.h"
37 /* This causes frames to occur 1000x slower */
38 //#define OHCI_TIME_WARP 1
40 /* Number of Downstream Ports on the root hub. */
42 #define OHCI_MAX_PORTS 15
44 static int64_t usb_frame_time
;
45 static int64_t usb_bit_time
;
47 typedef struct OHCIPort
{
64 /* Control partition */
69 /* memory pointer partition */
71 uint32_t ctrl_head
, ctrl_cur
;
72 uint32_t bulk_head
, bulk_cur
;
77 /* Frame counter partition */
82 uint16_t frame_number
;
87 /* Root Hub partition */
88 uint32_t rhdesc_a
, rhdesc_b
;
90 OHCIPort rhport
[OHCI_MAX_PORTS
];
92 /* PXA27x Non-OHCI events */
98 /* SM501 local memory offset */
99 dma_addr_t localmem_base
;
101 /* Active packets. */
103 USBPacket usb_packet
;
104 uint8_t usb_buf
[8192];
110 /* Host Controller Communications Area */
116 #define HCCA_WRITEBACK_OFFSET offsetof(struct ohci_hcca, frame)
117 #define HCCA_WRITEBACK_SIZE 8 /* frame, pad, done */
119 #define ED_WBACK_OFFSET offsetof(struct ohci_ed, head)
120 #define ED_WBACK_SIZE 4
122 static void ohci_bus_stop(OHCIState
*ohci
);
123 static void ohci_async_cancel_device(OHCIState
*ohci
, USBDevice
*dev
);
125 /* Bitfields for the first word of an Endpoint Desciptor. */
126 #define OHCI_ED_FA_SHIFT 0
127 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
128 #define OHCI_ED_EN_SHIFT 7
129 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
130 #define OHCI_ED_D_SHIFT 11
131 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
132 #define OHCI_ED_S (1<<13)
133 #define OHCI_ED_K (1<<14)
134 #define OHCI_ED_F (1<<15)
135 #define OHCI_ED_MPS_SHIFT 16
136 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT)
138 /* Flags in the head field of an Endpoint Desciptor. */
142 /* Bitfields for the first word of a Transfer Desciptor. */
143 #define OHCI_TD_R (1<<18)
144 #define OHCI_TD_DP_SHIFT 19
145 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
146 #define OHCI_TD_DI_SHIFT 21
147 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
148 #define OHCI_TD_T0 (1<<24)
149 #define OHCI_TD_T1 (1<<25)
150 #define OHCI_TD_EC_SHIFT 26
151 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
152 #define OHCI_TD_CC_SHIFT 28
153 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
155 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */
156 /* CC & DI - same as in the General Transfer Desciptor */
157 #define OHCI_TD_SF_SHIFT 0
158 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT)
159 #define OHCI_TD_FC_SHIFT 24
160 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT)
162 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
163 #define OHCI_TD_PSW_CC_SHIFT 12
164 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT)
165 #define OHCI_TD_PSW_SIZE_SHIFT 0
166 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
168 #define OHCI_PAGE_MASK 0xfffff000
169 #define OHCI_OFFSET_MASK 0xfff
171 #define OHCI_DPTR_MASK 0xfffffff0
173 #define OHCI_BM(val, field) \
174 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
176 #define OHCI_SET_BM(val, field, newval) do { \
177 val &= ~OHCI_##field##_MASK; \
178 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
181 /* endpoint descriptor */
189 /* General transfer descriptor */
197 /* Isochronous transfer descriptor */
206 #define USB_HZ 12000000
208 /* OHCI Local stuff */
209 #define OHCI_CTL_CBSR ((1<<0)|(1<<1))
210 #define OHCI_CTL_PLE (1<<2)
211 #define OHCI_CTL_IE (1<<3)
212 #define OHCI_CTL_CLE (1<<4)
213 #define OHCI_CTL_BLE (1<<5)
214 #define OHCI_CTL_HCFS ((1<<6)|(1<<7))
215 #define OHCI_USB_RESET 0x00
216 #define OHCI_USB_RESUME 0x40
217 #define OHCI_USB_OPERATIONAL 0x80
218 #define OHCI_USB_SUSPEND 0xc0
219 #define OHCI_CTL_IR (1<<8)
220 #define OHCI_CTL_RWC (1<<9)
221 #define OHCI_CTL_RWE (1<<10)
223 #define OHCI_STATUS_HCR (1<<0)
224 #define OHCI_STATUS_CLF (1<<1)
225 #define OHCI_STATUS_BLF (1<<2)
226 #define OHCI_STATUS_OCR (1<<3)
227 #define OHCI_STATUS_SOC ((1<<6)|(1<<7))
229 #define OHCI_INTR_SO (1U<<0) /* Scheduling overrun */
230 #define OHCI_INTR_WD (1U<<1) /* HcDoneHead writeback */
231 #define OHCI_INTR_SF (1U<<2) /* Start of frame */
232 #define OHCI_INTR_RD (1U<<3) /* Resume detect */
233 #define OHCI_INTR_UE (1U<<4) /* Unrecoverable error */
234 #define OHCI_INTR_FNO (1U<<5) /* Frame number overflow */
235 #define OHCI_INTR_RHSC (1U<<6) /* Root hub status change */
236 #define OHCI_INTR_OC (1U<<30) /* Ownership change */
237 #define OHCI_INTR_MIE (1U<<31) /* Master Interrupt Enable */
239 #define OHCI_HCCA_SIZE 0x100
240 #define OHCI_HCCA_MASK 0xffffff00
242 #define OHCI_EDPTR_MASK 0xfffffff0
244 #define OHCI_FMI_FI 0x00003fff
245 #define OHCI_FMI_FSMPS 0xffff0000
246 #define OHCI_FMI_FIT 0x80000000
248 #define OHCI_FR_RT (1U<<31)
250 #define OHCI_LS_THRESH 0x628
252 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
253 #define OHCI_RHA_PSM (1<<8)
254 #define OHCI_RHA_NPS (1<<9)
255 #define OHCI_RHA_DT (1<<10)
256 #define OHCI_RHA_OCPM (1<<11)
257 #define OHCI_RHA_NOCP (1<<12)
258 #define OHCI_RHA_POTPGT_MASK 0xff000000
260 #define OHCI_RHS_LPS (1U<<0)
261 #define OHCI_RHS_OCI (1U<<1)
262 #define OHCI_RHS_DRWE (1U<<15)
263 #define OHCI_RHS_LPSC (1U<<16)
264 #define OHCI_RHS_OCIC (1U<<17)
265 #define OHCI_RHS_CRWE (1U<<31)
267 #define OHCI_PORT_CCS (1<<0)
268 #define OHCI_PORT_PES (1<<1)
269 #define OHCI_PORT_PSS (1<<2)
270 #define OHCI_PORT_POCI (1<<3)
271 #define OHCI_PORT_PRS (1<<4)
272 #define OHCI_PORT_PPS (1<<8)
273 #define OHCI_PORT_LSDA (1<<9)
274 #define OHCI_PORT_CSC (1<<16)
275 #define OHCI_PORT_PESC (1<<17)
276 #define OHCI_PORT_PSSC (1<<18)
277 #define OHCI_PORT_OCIC (1<<19)
278 #define OHCI_PORT_PRSC (1<<20)
279 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
280 |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
282 #define OHCI_TD_DIR_SETUP 0x0
283 #define OHCI_TD_DIR_OUT 0x1
284 #define OHCI_TD_DIR_IN 0x2
285 #define OHCI_TD_DIR_RESERVED 0x3
287 #define OHCI_CC_NOERROR 0x0
288 #define OHCI_CC_CRC 0x1
289 #define OHCI_CC_BITSTUFFING 0x2
290 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
291 #define OHCI_CC_STALL 0x4
292 #define OHCI_CC_DEVICENOTRESPONDING 0x5
293 #define OHCI_CC_PIDCHECKFAILURE 0x6
294 #define OHCI_CC_UNDEXPETEDPID 0x7
295 #define OHCI_CC_DATAOVERRUN 0x8
296 #define OHCI_CC_DATAUNDERRUN 0x9
297 #define OHCI_CC_BUFFEROVERRUN 0xc
298 #define OHCI_CC_BUFFERUNDERRUN 0xd
300 #define OHCI_HRESET_FSBIR (1 << 0)
302 static void ohci_die(OHCIState
*ohci
);
304 /* Update IRQ levels */
305 static inline void ohci_intr_update(OHCIState
*ohci
)
309 if ((ohci
->intr
& OHCI_INTR_MIE
) &&
310 (ohci
->intr_status
& ohci
->intr
))
313 qemu_set_irq(ohci
->irq
, level
);
316 /* Set an interrupt */
317 static inline void ohci_set_interrupt(OHCIState
*ohci
, uint32_t intr
)
319 ohci
->intr_status
|= intr
;
320 ohci_intr_update(ohci
);
323 /* Attach or detach a device on a root hub port. */
324 static void ohci_attach(USBPort
*port1
)
326 OHCIState
*s
= port1
->opaque
;
327 OHCIPort
*port
= &s
->rhport
[port1
->index
];
328 uint32_t old_state
= port
->ctrl
;
330 /* set connect status */
331 port
->ctrl
|= OHCI_PORT_CCS
| OHCI_PORT_CSC
;
334 if (port
->port
.dev
->speed
== USB_SPEED_LOW
) {
335 port
->ctrl
|= OHCI_PORT_LSDA
;
337 port
->ctrl
&= ~OHCI_PORT_LSDA
;
340 /* notify of remote-wakeup */
341 if ((s
->ctl
& OHCI_CTL_HCFS
) == OHCI_USB_SUSPEND
) {
342 ohci_set_interrupt(s
, OHCI_INTR_RD
);
345 trace_usb_ohci_port_attach(port1
->index
);
347 if (old_state
!= port
->ctrl
) {
348 ohci_set_interrupt(s
, OHCI_INTR_RHSC
);
352 static void ohci_detach(USBPort
*port1
)
354 OHCIState
*s
= port1
->opaque
;
355 OHCIPort
*port
= &s
->rhport
[port1
->index
];
356 uint32_t old_state
= port
->ctrl
;
358 ohci_async_cancel_device(s
, port1
->dev
);
360 /* set connect status */
361 if (port
->ctrl
& OHCI_PORT_CCS
) {
362 port
->ctrl
&= ~OHCI_PORT_CCS
;
363 port
->ctrl
|= OHCI_PORT_CSC
;
366 if (port
->ctrl
& OHCI_PORT_PES
) {
367 port
->ctrl
&= ~OHCI_PORT_PES
;
368 port
->ctrl
|= OHCI_PORT_PESC
;
370 trace_usb_ohci_port_detach(port1
->index
);
372 if (old_state
!= port
->ctrl
) {
373 ohci_set_interrupt(s
, OHCI_INTR_RHSC
);
377 static void ohci_wakeup(USBPort
*port1
)
379 OHCIState
*s
= port1
->opaque
;
380 OHCIPort
*port
= &s
->rhport
[port1
->index
];
382 if (port
->ctrl
& OHCI_PORT_PSS
) {
383 trace_usb_ohci_port_wakeup(port1
->index
);
384 port
->ctrl
|= OHCI_PORT_PSSC
;
385 port
->ctrl
&= ~OHCI_PORT_PSS
;
386 intr
= OHCI_INTR_RHSC
;
388 /* Note that the controller can be suspended even if this port is not */
389 if ((s
->ctl
& OHCI_CTL_HCFS
) == OHCI_USB_SUSPEND
) {
390 trace_usb_ohci_remote_wakeup(s
->name
);
391 /* This is the one state transition the controller can do by itself */
392 s
->ctl
&= ~OHCI_CTL_HCFS
;
393 s
->ctl
|= OHCI_USB_RESUME
;
394 /* In suspend mode only ResumeDetected is possible, not RHSC:
395 * see the OHCI spec 5.1.2.3.
399 ohci_set_interrupt(s
, intr
);
402 static void ohci_child_detach(USBPort
*port1
, USBDevice
*child
)
404 OHCIState
*s
= port1
->opaque
;
406 ohci_async_cancel_device(s
, child
);
409 static USBDevice
*ohci_find_device(OHCIState
*ohci
, uint8_t addr
)
414 for (i
= 0; i
< ohci
->num_ports
; i
++) {
415 if ((ohci
->rhport
[i
].ctrl
& OHCI_PORT_PES
) == 0) {
418 dev
= usb_find_device(&ohci
->rhport
[i
].port
, addr
);
426 static void ohci_stop_endpoints(OHCIState
*ohci
)
431 for (i
= 0; i
< ohci
->num_ports
; i
++) {
432 dev
= ohci
->rhport
[i
].port
.dev
;
433 if (dev
&& dev
->attached
) {
434 usb_device_ep_stopped(dev
, &dev
->ep_ctl
);
435 for (j
= 0; j
< USB_MAX_ENDPOINTS
; j
++) {
436 usb_device_ep_stopped(dev
, &dev
->ep_in
[j
]);
437 usb_device_ep_stopped(dev
, &dev
->ep_out
[j
]);
443 static void ohci_roothub_reset(OHCIState
*ohci
)
449 ohci
->rhdesc_a
= OHCI_RHA_NPS
| ohci
->num_ports
;
450 ohci
->rhdesc_b
= 0x0; /* Impl. specific */
453 for (i
= 0; i
< ohci
->num_ports
; i
++) {
454 port
= &ohci
->rhport
[i
];
456 if (port
->port
.dev
&& port
->port
.dev
->attached
) {
457 usb_port_reset(&port
->port
);
460 if (ohci
->async_td
) {
461 usb_cancel_packet(&ohci
->usb_packet
);
464 ohci_stop_endpoints(ohci
);
467 /* Reset the controller */
468 static void ohci_soft_reset(OHCIState
*ohci
)
470 trace_usb_ohci_reset(ohci
->name
);
473 ohci
->ctl
= (ohci
->ctl
& OHCI_CTL_IR
) | OHCI_USB_SUSPEND
;
476 ohci
->intr_status
= 0;
477 ohci
->intr
= OHCI_INTR_MIE
;
480 ohci
->ctrl_head
= ohci
->ctrl_cur
= 0;
481 ohci
->bulk_head
= ohci
->bulk_cur
= 0;
484 ohci
->done_count
= 7;
486 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
487 * I took the value linux sets ...
489 ohci
->fsmps
= 0x2778;
493 ohci
->frame_number
= 0;
495 ohci
->lst
= OHCI_LS_THRESH
;
498 static void ohci_hard_reset(OHCIState
*ohci
)
500 ohci_soft_reset(ohci
);
502 ohci_roothub_reset(ohci
);
505 /* Get an array of dwords from main memory */
506 static inline int get_dwords(OHCIState
*ohci
,
507 dma_addr_t addr
, uint32_t *buf
, int num
)
511 addr
+= ohci
->localmem_base
;
513 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
514 if (dma_memory_read(ohci
->as
, addr
, buf
, sizeof(*buf
))) {
517 *buf
= le32_to_cpu(*buf
);
523 /* Put an array of dwords in to main memory */
524 static inline int put_dwords(OHCIState
*ohci
,
525 dma_addr_t addr
, uint32_t *buf
, int num
)
529 addr
+= ohci
->localmem_base
;
531 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
532 uint32_t tmp
= cpu_to_le32(*buf
);
533 if (dma_memory_write(ohci
->as
, addr
, &tmp
, sizeof(tmp
))) {
541 /* Get an array of words from main memory */
542 static inline int get_words(OHCIState
*ohci
,
543 dma_addr_t addr
, uint16_t *buf
, int num
)
547 addr
+= ohci
->localmem_base
;
549 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
550 if (dma_memory_read(ohci
->as
, addr
, buf
, sizeof(*buf
))) {
553 *buf
= le16_to_cpu(*buf
);
559 /* Put an array of words in to main memory */
560 static inline int put_words(OHCIState
*ohci
,
561 dma_addr_t addr
, uint16_t *buf
, int num
)
565 addr
+= ohci
->localmem_base
;
567 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
568 uint16_t tmp
= cpu_to_le16(*buf
);
569 if (dma_memory_write(ohci
->as
, addr
, &tmp
, sizeof(tmp
))) {
577 static inline int ohci_read_ed(OHCIState
*ohci
,
578 dma_addr_t addr
, struct ohci_ed
*ed
)
580 return get_dwords(ohci
, addr
, (uint32_t *)ed
, sizeof(*ed
) >> 2);
583 static inline int ohci_read_td(OHCIState
*ohci
,
584 dma_addr_t addr
, struct ohci_td
*td
)
586 return get_dwords(ohci
, addr
, (uint32_t *)td
, sizeof(*td
) >> 2);
589 static inline int ohci_read_iso_td(OHCIState
*ohci
,
590 dma_addr_t addr
, struct ohci_iso_td
*td
)
592 return get_dwords(ohci
, addr
, (uint32_t *)td
, 4) ||
593 get_words(ohci
, addr
+ 16, td
->offset
, 8);
596 static inline int ohci_read_hcca(OHCIState
*ohci
,
597 dma_addr_t addr
, struct ohci_hcca
*hcca
)
599 return dma_memory_read(ohci
->as
, addr
+ ohci
->localmem_base
,
600 hcca
, sizeof(*hcca
));
603 static inline int ohci_put_ed(OHCIState
*ohci
,
604 dma_addr_t addr
, struct ohci_ed
*ed
)
606 /* ed->tail is under control of the HCD.
607 * Since just ed->head is changed by HC, just write back this
610 return put_dwords(ohci
, addr
+ ED_WBACK_OFFSET
,
611 (uint32_t *)((char *)ed
+ ED_WBACK_OFFSET
),
615 static inline int ohci_put_td(OHCIState
*ohci
,
616 dma_addr_t addr
, struct ohci_td
*td
)
618 return put_dwords(ohci
, addr
, (uint32_t *)td
, sizeof(*td
) >> 2);
621 static inline int ohci_put_iso_td(OHCIState
*ohci
,
622 dma_addr_t addr
, struct ohci_iso_td
*td
)
624 return put_dwords(ohci
, addr
, (uint32_t *)td
, 4) ||
625 put_words(ohci
, addr
+ 16, td
->offset
, 8);
628 static inline int ohci_put_hcca(OHCIState
*ohci
,
629 dma_addr_t addr
, struct ohci_hcca
*hcca
)
631 return dma_memory_write(ohci
->as
,
632 addr
+ ohci
->localmem_base
+ HCCA_WRITEBACK_OFFSET
,
633 (char *)hcca
+ HCCA_WRITEBACK_OFFSET
,
634 HCCA_WRITEBACK_SIZE
);
637 /* Read/Write the contents of a TD from/to main memory. */
638 static int ohci_copy_td(OHCIState
*ohci
, struct ohci_td
*td
,
639 uint8_t *buf
, int len
, DMADirection dir
)
644 n
= 0x1000 - (ptr
& 0xfff);
648 if (dma_memory_rw(ohci
->as
, ptr
+ ohci
->localmem_base
, buf
, n
, dir
)) {
654 ptr
= td
->be
& ~0xfffu
;
656 if (dma_memory_rw(ohci
->as
, ptr
+ ohci
->localmem_base
, buf
,
663 /* Read/Write the contents of an ISO TD from/to main memory. */
664 static int ohci_copy_iso_td(OHCIState
*ohci
,
665 uint32_t start_addr
, uint32_t end_addr
,
666 uint8_t *buf
, int len
, DMADirection dir
)
671 n
= 0x1000 - (ptr
& 0xfff);
675 if (dma_memory_rw(ohci
->as
, ptr
+ ohci
->localmem_base
, buf
, n
, dir
)) {
681 ptr
= end_addr
& ~0xfffu
;
683 if (dma_memory_rw(ohci
->as
, ptr
+ ohci
->localmem_base
, buf
,
690 static void ohci_process_lists(OHCIState
*ohci
, int completion
);
692 static void ohci_async_complete_packet(USBPort
*port
, USBPacket
*packet
)
694 OHCIState
*ohci
= container_of(packet
, OHCIState
, usb_packet
);
696 trace_usb_ohci_async_complete();
697 ohci
->async_complete
= true;
698 ohci_process_lists(ohci
, 1);
701 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
703 static int ohci_service_iso_td(OHCIState
*ohci
, struct ohci_ed
*ed
,
708 const char *str
= NULL
;
714 struct ohci_iso_td iso_td
;
716 uint16_t starting_frame
;
717 int16_t relative_frame_number
;
719 uint32_t start_offset
, next_offset
, end_offset
= 0;
720 uint32_t start_addr
, end_addr
;
722 addr
= ed
->head
& OHCI_DPTR_MASK
;
724 if (ohci_read_iso_td(ohci
, addr
, &iso_td
)) {
725 trace_usb_ohci_iso_td_read_failed(addr
);
730 starting_frame
= OHCI_BM(iso_td
.flags
, TD_SF
);
731 frame_count
= OHCI_BM(iso_td
.flags
, TD_FC
);
732 relative_frame_number
= USUB(ohci
->frame_number
, starting_frame
);
734 trace_usb_ohci_iso_td_head(
735 ed
->head
& OHCI_DPTR_MASK
, ed
->tail
& OHCI_DPTR_MASK
,
736 iso_td
.flags
, iso_td
.bp
, iso_td
.next
, iso_td
.be
,
737 ohci
->frame_number
, starting_frame
,
738 frame_count
, relative_frame_number
);
739 trace_usb_ohci_iso_td_head_offset(
740 iso_td
.offset
[0], iso_td
.offset
[1],
741 iso_td
.offset
[2], iso_td
.offset
[3],
742 iso_td
.offset
[4], iso_td
.offset
[5],
743 iso_td
.offset
[6], iso_td
.offset
[7]);
745 if (relative_frame_number
< 0) {
746 trace_usb_ohci_iso_td_relative_frame_number_neg(relative_frame_number
);
748 } else if (relative_frame_number
> frame_count
) {
749 /* ISO TD expired - retire the TD to the Done Queue and continue with
750 the next ISO TD of the same ED */
751 trace_usb_ohci_iso_td_relative_frame_number_big(relative_frame_number
,
753 OHCI_SET_BM(iso_td
.flags
, TD_CC
, OHCI_CC_DATAOVERRUN
);
754 ed
->head
&= ~OHCI_DPTR_MASK
;
755 ed
->head
|= (iso_td
.next
& OHCI_DPTR_MASK
);
756 iso_td
.next
= ohci
->done
;
758 i
= OHCI_BM(iso_td
.flags
, TD_DI
);
759 if (i
< ohci
->done_count
)
760 ohci
->done_count
= i
;
761 if (ohci_put_iso_td(ohci
, addr
, &iso_td
)) {
768 dir
= OHCI_BM(ed
->flags
, ED_D
);
774 case OHCI_TD_DIR_OUT
:
778 case OHCI_TD_DIR_SETUP
:
780 pid
= USB_TOKEN_SETUP
;
783 trace_usb_ohci_iso_td_bad_direction(dir
);
787 if (!iso_td
.bp
|| !iso_td
.be
) {
788 trace_usb_ohci_iso_td_bad_bp_be(iso_td
.bp
, iso_td
.be
);
792 start_offset
= iso_td
.offset
[relative_frame_number
];
793 next_offset
= iso_td
.offset
[relative_frame_number
+ 1];
795 if (!(OHCI_BM(start_offset
, TD_PSW_CC
) & 0xe) ||
796 ((relative_frame_number
< frame_count
) &&
797 !(OHCI_BM(next_offset
, TD_PSW_CC
) & 0xe))) {
798 trace_usb_ohci_iso_td_bad_cc_not_accessed(start_offset
, next_offset
);
802 if ((relative_frame_number
< frame_count
) && (start_offset
> next_offset
)) {
803 trace_usb_ohci_iso_td_bad_cc_overrun(start_offset
, next_offset
);
807 if ((start_offset
& 0x1000) == 0) {
808 start_addr
= (iso_td
.bp
& OHCI_PAGE_MASK
) |
809 (start_offset
& OHCI_OFFSET_MASK
);
811 start_addr
= (iso_td
.be
& OHCI_PAGE_MASK
) |
812 (start_offset
& OHCI_OFFSET_MASK
);
815 if (relative_frame_number
< frame_count
) {
816 end_offset
= next_offset
- 1;
817 if ((end_offset
& 0x1000) == 0) {
818 end_addr
= (iso_td
.bp
& OHCI_PAGE_MASK
) |
819 (end_offset
& OHCI_OFFSET_MASK
);
821 end_addr
= (iso_td
.be
& OHCI_PAGE_MASK
) |
822 (end_offset
& OHCI_OFFSET_MASK
);
825 /* Last packet in the ISO TD */
826 end_addr
= iso_td
.be
;
829 if ((start_addr
& OHCI_PAGE_MASK
) != (end_addr
& OHCI_PAGE_MASK
)) {
830 len
= (end_addr
& OHCI_OFFSET_MASK
) + 0x1001
831 - (start_addr
& OHCI_OFFSET_MASK
);
833 len
= end_addr
- start_addr
+ 1;
836 if (len
&& dir
!= OHCI_TD_DIR_IN
) {
837 if (ohci_copy_iso_td(ohci
, start_addr
, end_addr
, ohci
->usb_buf
, len
,
838 DMA_DIRECTION_TO_DEVICE
)) {
845 bool int_req
= relative_frame_number
== frame_count
&&
846 OHCI_BM(iso_td
.flags
, TD_DI
) == 0;
847 dev
= ohci_find_device(ohci
, OHCI_BM(ed
->flags
, ED_FA
));
848 ep
= usb_ep_get(dev
, pid
, OHCI_BM(ed
->flags
, ED_EN
));
849 usb_packet_setup(&ohci
->usb_packet
, pid
, ep
, 0, addr
, false, int_req
);
850 usb_packet_addbuf(&ohci
->usb_packet
, ohci
->usb_buf
, len
);
851 usb_handle_packet(dev
, &ohci
->usb_packet
);
852 if (ohci
->usb_packet
.status
== USB_RET_ASYNC
) {
853 usb_device_flush_ep_queue(dev
, ep
);
857 if (ohci
->usb_packet
.status
== USB_RET_SUCCESS
) {
858 ret
= ohci
->usb_packet
.actual_length
;
860 ret
= ohci
->usb_packet
.status
;
863 trace_usb_ohci_iso_td_so(start_offset
, end_offset
, start_addr
, end_addr
,
867 if (dir
== OHCI_TD_DIR_IN
&& ret
>= 0 && ret
<= len
) {
868 /* IN transfer succeeded */
869 if (ohci_copy_iso_td(ohci
, start_addr
, end_addr
, ohci
->usb_buf
, ret
,
870 DMA_DIRECTION_FROM_DEVICE
)) {
874 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
876 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
, ret
);
877 } else if (dir
== OHCI_TD_DIR_OUT
&& ret
== len
) {
878 /* OUT transfer succeeded */
879 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
881 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
, 0);
883 if (ret
> (ssize_t
) len
) {
884 trace_usb_ohci_iso_td_data_overrun(ret
, len
);
885 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
886 OHCI_CC_DATAOVERRUN
);
887 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
,
889 } else if (ret
>= 0) {
890 trace_usb_ohci_iso_td_data_underrun(ret
);
891 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
892 OHCI_CC_DATAUNDERRUN
);
895 case USB_RET_IOERROR
:
897 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
898 OHCI_CC_DEVICENOTRESPONDING
);
899 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
,
904 trace_usb_ohci_iso_td_nak(ret
);
905 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
907 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
,
911 trace_usb_ohci_iso_td_bad_response(ret
);
912 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
913 OHCI_CC_UNDEXPETEDPID
);
919 if (relative_frame_number
== frame_count
) {
920 /* Last data packet of ISO TD - retire the TD to the Done Queue */
921 OHCI_SET_BM(iso_td
.flags
, TD_CC
, OHCI_CC_NOERROR
);
922 ed
->head
&= ~OHCI_DPTR_MASK
;
923 ed
->head
|= (iso_td
.next
& OHCI_DPTR_MASK
);
924 iso_td
.next
= ohci
->done
;
926 i
= OHCI_BM(iso_td
.flags
, TD_DI
);
927 if (i
< ohci
->done_count
)
928 ohci
->done_count
= i
;
930 if (ohci_put_iso_td(ohci
, addr
, &iso_td
)) {
936 #ifdef trace_event_get_state
937 static void ohci_td_pkt(const char *msg
, const uint8_t *buf
, size_t len
)
939 bool print16
= !!trace_event_get_state(TRACE_USB_OHCI_TD_PKT_SHORT
);
940 bool printall
= !!trace_event_get_state(TRACE_USB_OHCI_TD_PKT_FULL
);
941 const int width
= 16;
943 char tmp
[3 * width
+ 1];
946 if (!printall
&& !print16
) {
951 if (i
&& (!(i
% width
) || (i
== len
))) {
953 trace_usb_ohci_td_pkt_short(msg
, tmp
);
956 trace_usb_ohci_td_pkt_full(msg
, tmp
);
964 p
+= sprintf(p
, " %.2x", buf
[i
]);
968 static void ohci_td_pkt(const char *msg
, const uint8_t *buf
, size_t len
)
973 /* Service a transport descriptor.
974 Returns nonzero to terminate processing of this endpoint. */
976 static int ohci_service_td(OHCIState
*ohci
, struct ohci_ed
*ed
)
979 size_t len
= 0, pktlen
= 0;
980 const char *str
= NULL
;
991 addr
= ed
->head
& OHCI_DPTR_MASK
;
992 /* See if this TD has already been submitted to the device. */
993 completion
= (addr
== ohci
->async_td
);
994 if (completion
&& !ohci
->async_complete
) {
995 trace_usb_ohci_td_skip_async();
998 if (ohci_read_td(ohci
, addr
, &td
)) {
999 trace_usb_ohci_td_read_error(addr
);
1004 dir
= OHCI_BM(ed
->flags
, ED_D
);
1006 case OHCI_TD_DIR_OUT
:
1007 case OHCI_TD_DIR_IN
:
1011 dir
= OHCI_BM(td
.flags
, TD_DP
);
1016 case OHCI_TD_DIR_IN
:
1020 case OHCI_TD_DIR_OUT
:
1022 pid
= USB_TOKEN_OUT
;
1024 case OHCI_TD_DIR_SETUP
:
1026 pid
= USB_TOKEN_SETUP
;
1029 trace_usb_ohci_td_bad_direction(dir
);
1032 if (td
.cbp
&& td
.be
) {
1033 if ((td
.cbp
& 0xfffff000) != (td
.be
& 0xfffff000)) {
1034 len
= (td
.be
& 0xfff) + 0x1001 - (td
.cbp
& 0xfff);
1036 len
= (td
.be
- td
.cbp
) + 1;
1040 if (len
&& dir
!= OHCI_TD_DIR_IN
) {
1041 /* The endpoint may not allow us to transfer it all now */
1042 pktlen
= (ed
->flags
& OHCI_ED_MPS_MASK
) >> OHCI_ED_MPS_SHIFT
;
1047 if (ohci_copy_td(ohci
, &td
, ohci
->usb_buf
, pktlen
,
1048 DMA_DIRECTION_TO_DEVICE
)) {
1055 flag_r
= (td
.flags
& OHCI_TD_R
) != 0;
1056 trace_usb_ohci_td_pkt_hdr(addr
, (int64_t)pktlen
, (int64_t)len
, str
,
1057 flag_r
, td
.cbp
, td
.be
);
1058 ohci_td_pkt("OUT", ohci
->usb_buf
, pktlen
);
1062 ohci
->async_complete
= false;
1064 if (ohci
->async_td
) {
1065 /* ??? The hardware should allow one active packet per
1066 endpoint. We only allow one active packet per controller.
1067 This should be sufficient as long as devices respond in a
1070 trace_usb_ohci_td_too_many_pending();
1073 dev
= ohci_find_device(ohci
, OHCI_BM(ed
->flags
, ED_FA
));
1074 ep
= usb_ep_get(dev
, pid
, OHCI_BM(ed
->flags
, ED_EN
));
1075 usb_packet_setup(&ohci
->usb_packet
, pid
, ep
, 0, addr
, !flag_r
,
1076 OHCI_BM(td
.flags
, TD_DI
) == 0);
1077 usb_packet_addbuf(&ohci
->usb_packet
, ohci
->usb_buf
, pktlen
);
1078 usb_handle_packet(dev
, &ohci
->usb_packet
);
1079 trace_usb_ohci_td_packet_status(ohci
->usb_packet
.status
);
1081 if (ohci
->usb_packet
.status
== USB_RET_ASYNC
) {
1082 usb_device_flush_ep_queue(dev
, ep
);
1083 ohci
->async_td
= addr
;
1087 if (ohci
->usb_packet
.status
== USB_RET_SUCCESS
) {
1088 ret
= ohci
->usb_packet
.actual_length
;
1090 ret
= ohci
->usb_packet
.status
;
1094 if (dir
== OHCI_TD_DIR_IN
) {
1095 if (ohci_copy_td(ohci
, &td
, ohci
->usb_buf
, ret
,
1096 DMA_DIRECTION_FROM_DEVICE
)) {
1099 ohci_td_pkt("IN", ohci
->usb_buf
, pktlen
);
1106 if (ret
== pktlen
|| (dir
== OHCI_TD_DIR_IN
&& ret
>= 0 && flag_r
)) {
1107 /* Transmission succeeded. */
1111 if ((td
.cbp
& 0xfff) + ret
> 0xfff) {
1112 td
.cbp
= (td
.be
& ~0xfff) + ((td
.cbp
+ ret
) & 0xfff);
1117 td
.flags
|= OHCI_TD_T1
;
1118 td
.flags
^= OHCI_TD_T0
;
1119 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_NOERROR
);
1120 OHCI_SET_BM(td
.flags
, TD_EC
, 0);
1122 if ((dir
!= OHCI_TD_DIR_IN
) && (ret
!= len
)) {
1123 /* Partial packet transfer: TD not ready to retire yet */
1124 goto exit_no_retire
;
1127 /* Setting ED_C is part of the TD retirement process */
1128 ed
->head
&= ~OHCI_ED_C
;
1129 if (td
.flags
& OHCI_TD_T0
)
1130 ed
->head
|= OHCI_ED_C
;
1133 trace_usb_ohci_td_underrun();
1134 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DATAUNDERRUN
);
1137 case USB_RET_IOERROR
:
1139 trace_usb_ohci_td_dev_error();
1140 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DEVICENOTRESPONDING
);
1143 trace_usb_ohci_td_nak();
1146 trace_usb_ohci_td_stall();
1147 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_STALL
);
1149 case USB_RET_BABBLE
:
1150 trace_usb_ohci_td_babble();
1151 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DATAOVERRUN
);
1154 trace_usb_ohci_td_bad_device_response(ret
);
1155 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_UNDEXPETEDPID
);
1156 OHCI_SET_BM(td
.flags
, TD_EC
, 3);
1160 ed
->head
|= OHCI_ED_H
;
1163 /* Retire this TD */
1164 ed
->head
&= ~OHCI_DPTR_MASK
;
1165 ed
->head
|= td
.next
& OHCI_DPTR_MASK
;
1166 td
.next
= ohci
->done
;
1168 i
= OHCI_BM(td
.flags
, TD_DI
);
1169 if (i
< ohci
->done_count
)
1170 ohci
->done_count
= i
;
1172 if (ohci_put_td(ohci
, addr
, &td
)) {
1176 return OHCI_BM(td
.flags
, TD_CC
) != OHCI_CC_NOERROR
;
1179 /* Service an endpoint list. Returns nonzero if active TD were found. */
1180 static int ohci_service_ed_list(OHCIState
*ohci
, uint32_t head
, int completion
)
1192 for (cur
= head
; cur
; cur
= next_ed
) {
1193 if (ohci_read_ed(ohci
, cur
, &ed
)) {
1194 trace_usb_ohci_ed_read_error(cur
);
1199 next_ed
= ed
.next
& OHCI_DPTR_MASK
;
1201 if ((ed
.head
& OHCI_ED_H
) || (ed
.flags
& OHCI_ED_K
)) {
1203 /* Cancel pending packets for ED that have been paused. */
1204 addr
= ed
.head
& OHCI_DPTR_MASK
;
1205 if (ohci
->async_td
&& addr
== ohci
->async_td
) {
1206 usb_cancel_packet(&ohci
->usb_packet
);
1208 usb_device_ep_stopped(ohci
->usb_packet
.ep
->dev
,
1209 ohci
->usb_packet
.ep
);
1214 while ((ed
.head
& OHCI_DPTR_MASK
) != ed
.tail
) {
1215 trace_usb_ohci_ed_pkt(cur
, (ed
.head
& OHCI_ED_H
) != 0,
1216 (ed
.head
& OHCI_ED_C
) != 0, ed
.head
& OHCI_DPTR_MASK
,
1217 ed
.tail
& OHCI_DPTR_MASK
, ed
.next
& OHCI_DPTR_MASK
);
1218 trace_usb_ohci_ed_pkt_flags(
1219 OHCI_BM(ed
.flags
, ED_FA
), OHCI_BM(ed
.flags
, ED_EN
),
1220 OHCI_BM(ed
.flags
, ED_D
), (ed
.flags
& OHCI_ED_S
)!= 0,
1221 (ed
.flags
& OHCI_ED_K
) != 0, (ed
.flags
& OHCI_ED_F
) != 0,
1222 OHCI_BM(ed
.flags
, ED_MPS
));
1226 if ((ed
.flags
& OHCI_ED_F
) == 0) {
1227 if (ohci_service_td(ohci
, &ed
))
1230 /* Handle isochronous endpoints */
1231 if (ohci_service_iso_td(ohci
, &ed
, completion
))
1236 if (ohci_put_ed(ohci
, cur
, &ed
)) {
1245 /* set a timer for EOF */
1246 static void ohci_eof_timer(OHCIState
*ohci
)
1248 ohci
->sof_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1249 timer_mod(ohci
->eof_timer
, ohci
->sof_time
+ usb_frame_time
);
1251 /* Set a timer for EOF and generate a SOF event */
1252 static void ohci_sof(OHCIState
*ohci
)
1254 ohci_eof_timer(ohci
);
1255 ohci_set_interrupt(ohci
, OHCI_INTR_SF
);
1258 /* Process Control and Bulk lists. */
1259 static void ohci_process_lists(OHCIState
*ohci
, int completion
)
1261 if ((ohci
->ctl
& OHCI_CTL_CLE
) && (ohci
->status
& OHCI_STATUS_CLF
)) {
1262 if (ohci
->ctrl_cur
&& ohci
->ctrl_cur
!= ohci
->ctrl_head
) {
1263 trace_usb_ohci_process_lists(ohci
->ctrl_head
, ohci
->ctrl_cur
);
1265 if (!ohci_service_ed_list(ohci
, ohci
->ctrl_head
, completion
)) {
1267 ohci
->status
&= ~OHCI_STATUS_CLF
;
1271 if ((ohci
->ctl
& OHCI_CTL_BLE
) && (ohci
->status
& OHCI_STATUS_BLF
)) {
1272 if (!ohci_service_ed_list(ohci
, ohci
->bulk_head
, completion
)) {
1274 ohci
->status
&= ~OHCI_STATUS_BLF
;
1279 /* Do frame processing on frame boundary */
1280 static void ohci_frame_boundary(void *opaque
)
1282 OHCIState
*ohci
= opaque
;
1283 struct ohci_hcca hcca
;
1285 if (ohci_read_hcca(ohci
, ohci
->hcca
, &hcca
)) {
1286 trace_usb_ohci_hcca_read_error(ohci
->hcca
);
1291 /* Process all the lists at the end of the frame */
1292 if (ohci
->ctl
& OHCI_CTL_PLE
) {
1295 n
= ohci
->frame_number
& 0x1f;
1296 ohci_service_ed_list(ohci
, le32_to_cpu(hcca
.intr
[n
]), 0);
1299 /* Cancel all pending packets if either of the lists has been disabled. */
1300 if (ohci
->old_ctl
& (~ohci
->ctl
) & (OHCI_CTL_BLE
| OHCI_CTL_CLE
)) {
1301 if (ohci
->async_td
) {
1302 usb_cancel_packet(&ohci
->usb_packet
);
1305 ohci_stop_endpoints(ohci
);
1307 ohci
->old_ctl
= ohci
->ctl
;
1308 ohci_process_lists(ohci
, 0);
1310 /* Stop if UnrecoverableError happened or ohci_sof will crash */
1311 if (ohci
->intr_status
& OHCI_INTR_UE
) {
1315 /* Frame boundary, so do EOF stuf here */
1316 ohci
->frt
= ohci
->fit
;
1318 /* Increment frame number and take care of endianness. */
1319 ohci
->frame_number
= (ohci
->frame_number
+ 1) & 0xffff;
1320 hcca
.frame
= cpu_to_le16(ohci
->frame_number
);
1322 if (ohci
->done_count
== 0 && !(ohci
->intr_status
& OHCI_INTR_WD
)) {
1325 if (ohci
->intr
& ohci
->intr_status
)
1327 hcca
.done
= cpu_to_le32(ohci
->done
);
1329 ohci
->done_count
= 7;
1330 ohci_set_interrupt(ohci
, OHCI_INTR_WD
);
1333 if (ohci
->done_count
!= 7 && ohci
->done_count
!= 0)
1336 /* Do SOF stuff here */
1339 /* Writeback HCCA */
1340 if (ohci_put_hcca(ohci
, ohci
->hcca
, &hcca
)) {
1345 /* Start sending SOF tokens across the USB bus, lists are processed in
1348 static int ohci_bus_start(OHCIState
*ohci
)
1350 trace_usb_ohci_start(ohci
->name
);
1352 /* Delay the first SOF event by one frame time as
1353 * linux driver is not ready to receive it and
1354 * can meet some race conditions
1357 ohci_eof_timer(ohci
);
1362 /* Stop sending SOF tokens on the bus */
1363 static void ohci_bus_stop(OHCIState
*ohci
)
1365 trace_usb_ohci_stop(ohci
->name
);
1366 timer_del(ohci
->eof_timer
);
1369 /* Sets a flag in a port status register but only set it if the port is
1370 * connected, if not set ConnectStatusChange flag. If flag is enabled
1373 static int ohci_port_set_if_connected(OHCIState
*ohci
, int i
, uint32_t val
)
1377 /* writing a 0 has no effect */
1381 /* If CurrentConnectStatus is cleared we set
1382 * ConnectStatusChange
1384 if (!(ohci
->rhport
[i
].ctrl
& OHCI_PORT_CCS
)) {
1385 ohci
->rhport
[i
].ctrl
|= OHCI_PORT_CSC
;
1386 if (ohci
->rhstatus
& OHCI_RHS_DRWE
) {
1387 /* TODO: CSC is a wakeup event */
1392 if (ohci
->rhport
[i
].ctrl
& val
)
1396 ohci
->rhport
[i
].ctrl
|= val
;
1401 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1402 static void ohci_set_frame_interval(OHCIState
*ohci
, uint16_t val
)
1406 if (val
!= ohci
->fi
) {
1407 trace_usb_ohci_set_frame_interval(ohci
->name
, ohci
->fi
, ohci
->fi
);
1413 static void ohci_port_power(OHCIState
*ohci
, int i
, int p
)
1416 ohci
->rhport
[i
].ctrl
|= OHCI_PORT_PPS
;
1418 ohci
->rhport
[i
].ctrl
&= ~(OHCI_PORT_PPS
|
1425 /* Set HcControlRegister */
1426 static void ohci_set_ctl(OHCIState
*ohci
, uint32_t val
)
1431 old_state
= ohci
->ctl
& OHCI_CTL_HCFS
;
1433 new_state
= ohci
->ctl
& OHCI_CTL_HCFS
;
1435 /* no state change */
1436 if (old_state
== new_state
)
1439 trace_usb_ohci_set_ctl(ohci
->name
, new_state
);
1440 switch (new_state
) {
1441 case OHCI_USB_OPERATIONAL
:
1442 ohci_bus_start(ohci
);
1444 case OHCI_USB_SUSPEND
:
1445 ohci_bus_stop(ohci
);
1446 /* clear pending SF otherwise linux driver loops in ohci_irq() */
1447 ohci
->intr_status
&= ~OHCI_INTR_SF
;
1448 ohci_intr_update(ohci
);
1450 case OHCI_USB_RESUME
:
1451 trace_usb_ohci_resume(ohci
->name
);
1453 case OHCI_USB_RESET
:
1454 ohci_roothub_reset(ohci
);
1459 static uint32_t ohci_get_frame_remaining(OHCIState
*ohci
)
1464 if ((ohci
->ctl
& OHCI_CTL_HCFS
) != OHCI_USB_OPERATIONAL
)
1465 return (ohci
->frt
<< 31);
1467 /* Being in USB operational state guarnatees sof_time was
1470 tks
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) - ohci
->sof_time
;
1472 /* avoid muldiv if possible */
1473 if (tks
>= usb_frame_time
)
1474 return (ohci
->frt
<< 31);
1476 tks
= muldiv64(1, tks
, usb_bit_time
);
1477 fr
= (uint16_t)(ohci
->fi
- tks
);
1479 return (ohci
->frt
<< 31) | fr
;
1483 /* Set root hub status */
1484 static void ohci_set_hub_status(OHCIState
*ohci
, uint32_t val
)
1488 old_state
= ohci
->rhstatus
;
1490 /* write 1 to clear OCIC */
1491 if (val
& OHCI_RHS_OCIC
)
1492 ohci
->rhstatus
&= ~OHCI_RHS_OCIC
;
1494 if (val
& OHCI_RHS_LPS
) {
1497 for (i
= 0; i
< ohci
->num_ports
; i
++)
1498 ohci_port_power(ohci
, i
, 0);
1499 trace_usb_ohci_hub_power_down();
1502 if (val
& OHCI_RHS_LPSC
) {
1505 for (i
= 0; i
< ohci
->num_ports
; i
++)
1506 ohci_port_power(ohci
, i
, 1);
1507 trace_usb_ohci_hub_power_up();
1510 if (val
& OHCI_RHS_DRWE
)
1511 ohci
->rhstatus
|= OHCI_RHS_DRWE
;
1513 if (val
& OHCI_RHS_CRWE
)
1514 ohci
->rhstatus
&= ~OHCI_RHS_DRWE
;
1516 if (old_state
!= ohci
->rhstatus
)
1517 ohci_set_interrupt(ohci
, OHCI_INTR_RHSC
);
1520 /* Set root hub port status */
1521 static void ohci_port_set_status(OHCIState
*ohci
, int portnum
, uint32_t val
)
1526 port
= &ohci
->rhport
[portnum
];
1527 old_state
= port
->ctrl
;
1529 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1530 if (val
& OHCI_PORT_WTC
)
1531 port
->ctrl
&= ~(val
& OHCI_PORT_WTC
);
1533 if (val
& OHCI_PORT_CCS
)
1534 port
->ctrl
&= ~OHCI_PORT_PES
;
1536 ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PES
);
1538 if (ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PSS
)) {
1539 trace_usb_ohci_port_suspend(portnum
);
1542 if (ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PRS
)) {
1543 trace_usb_ohci_port_reset(portnum
);
1544 usb_device_reset(port
->port
.dev
);
1545 port
->ctrl
&= ~OHCI_PORT_PRS
;
1546 /* ??? Should this also set OHCI_PORT_PESC. */
1547 port
->ctrl
|= OHCI_PORT_PES
| OHCI_PORT_PRSC
;
1550 /* Invert order here to ensure in ambiguous case, device is
1553 if (val
& OHCI_PORT_LSDA
)
1554 ohci_port_power(ohci
, portnum
, 0);
1555 if (val
& OHCI_PORT_PPS
)
1556 ohci_port_power(ohci
, portnum
, 1);
1558 if (old_state
!= port
->ctrl
)
1559 ohci_set_interrupt(ohci
, OHCI_INTR_RHSC
);
1562 static uint64_t ohci_mem_read(void *opaque
,
1566 OHCIState
*ohci
= opaque
;
1569 /* Only aligned reads are allowed on OHCI */
1571 trace_usb_ohci_mem_read_unaligned(addr
);
1573 } else if (addr
>= 0x54 && addr
< 0x54 + ohci
->num_ports
* 4) {
1574 /* HcRhPortStatus */
1575 retval
= ohci
->rhport
[(addr
- 0x54) >> 2].ctrl
| OHCI_PORT_PPS
;
1577 switch (addr
>> 2) {
1578 case 0: /* HcRevision */
1582 case 1: /* HcControl */
1586 case 2: /* HcCommandStatus */
1587 retval
= ohci
->status
;
1590 case 3: /* HcInterruptStatus */
1591 retval
= ohci
->intr_status
;
1594 case 4: /* HcInterruptEnable */
1595 case 5: /* HcInterruptDisable */
1596 retval
= ohci
->intr
;
1599 case 6: /* HcHCCA */
1600 retval
= ohci
->hcca
;
1603 case 7: /* HcPeriodCurrentED */
1604 retval
= ohci
->per_cur
;
1607 case 8: /* HcControlHeadED */
1608 retval
= ohci
->ctrl_head
;
1611 case 9: /* HcControlCurrentED */
1612 retval
= ohci
->ctrl_cur
;
1615 case 10: /* HcBulkHeadED */
1616 retval
= ohci
->bulk_head
;
1619 case 11: /* HcBulkCurrentED */
1620 retval
= ohci
->bulk_cur
;
1623 case 12: /* HcDoneHead */
1624 retval
= ohci
->done
;
1627 case 13: /* HcFmInterretval */
1628 retval
= (ohci
->fit
<< 31) | (ohci
->fsmps
<< 16) | (ohci
->fi
);
1631 case 14: /* HcFmRemaining */
1632 retval
= ohci_get_frame_remaining(ohci
);
1635 case 15: /* HcFmNumber */
1636 retval
= ohci
->frame_number
;
1639 case 16: /* HcPeriodicStart */
1640 retval
= ohci
->pstart
;
1643 case 17: /* HcLSThreshold */
1647 case 18: /* HcRhDescriptorA */
1648 retval
= ohci
->rhdesc_a
;
1651 case 19: /* HcRhDescriptorB */
1652 retval
= ohci
->rhdesc_b
;
1655 case 20: /* HcRhStatus */
1656 retval
= ohci
->rhstatus
;
1659 /* PXA27x specific registers */
1660 case 24: /* HcStatus */
1661 retval
= ohci
->hstatus
& ohci
->hmask
;
1664 case 25: /* HcHReset */
1665 retval
= ohci
->hreset
;
1668 case 26: /* HcHInterruptEnable */
1669 retval
= ohci
->hmask
;
1672 case 27: /* HcHInterruptTest */
1673 retval
= ohci
->htest
;
1677 trace_usb_ohci_mem_read_bad_offset(addr
);
1678 retval
= 0xffffffff;
1685 static void ohci_mem_write(void *opaque
,
1690 OHCIState
*ohci
= opaque
;
1692 /* Only aligned reads are allowed on OHCI */
1694 trace_usb_ohci_mem_write_unaligned(addr
);
1698 if (addr
>= 0x54 && addr
< 0x54 + ohci
->num_ports
* 4) {
1699 /* HcRhPortStatus */
1700 ohci_port_set_status(ohci
, (addr
- 0x54) >> 2, val
);
1704 switch (addr
>> 2) {
1705 case 1: /* HcControl */
1706 ohci_set_ctl(ohci
, val
);
1709 case 2: /* HcCommandStatus */
1710 /* SOC is read-only */
1711 val
= (val
& ~OHCI_STATUS_SOC
);
1713 /* Bits written as '0' remain unchanged in the register */
1714 ohci
->status
|= val
;
1716 if (ohci
->status
& OHCI_STATUS_HCR
)
1717 ohci_soft_reset(ohci
);
1720 case 3: /* HcInterruptStatus */
1721 ohci
->intr_status
&= ~val
;
1722 ohci_intr_update(ohci
);
1725 case 4: /* HcInterruptEnable */
1727 ohci_intr_update(ohci
);
1730 case 5: /* HcInterruptDisable */
1732 ohci_intr_update(ohci
);
1735 case 6: /* HcHCCA */
1736 ohci
->hcca
= val
& OHCI_HCCA_MASK
;
1739 case 7: /* HcPeriodCurrentED */
1740 /* Ignore writes to this read-only register, Linux does them */
1743 case 8: /* HcControlHeadED */
1744 ohci
->ctrl_head
= val
& OHCI_EDPTR_MASK
;
1747 case 9: /* HcControlCurrentED */
1748 ohci
->ctrl_cur
= val
& OHCI_EDPTR_MASK
;
1751 case 10: /* HcBulkHeadED */
1752 ohci
->bulk_head
= val
& OHCI_EDPTR_MASK
;
1755 case 11: /* HcBulkCurrentED */
1756 ohci
->bulk_cur
= val
& OHCI_EDPTR_MASK
;
1759 case 13: /* HcFmInterval */
1760 ohci
->fsmps
= (val
& OHCI_FMI_FSMPS
) >> 16;
1761 ohci
->fit
= (val
& OHCI_FMI_FIT
) >> 31;
1762 ohci_set_frame_interval(ohci
, val
);
1765 case 15: /* HcFmNumber */
1768 case 16: /* HcPeriodicStart */
1769 ohci
->pstart
= val
& 0xffff;
1772 case 17: /* HcLSThreshold */
1773 ohci
->lst
= val
& 0xffff;
1776 case 18: /* HcRhDescriptorA */
1777 ohci
->rhdesc_a
&= ~OHCI_RHA_RW_MASK
;
1778 ohci
->rhdesc_a
|= val
& OHCI_RHA_RW_MASK
;
1781 case 19: /* HcRhDescriptorB */
1784 case 20: /* HcRhStatus */
1785 ohci_set_hub_status(ohci
, val
);
1788 /* PXA27x specific registers */
1789 case 24: /* HcStatus */
1790 ohci
->hstatus
&= ~(val
& ohci
->hmask
);
1793 case 25: /* HcHReset */
1794 ohci
->hreset
= val
& ~OHCI_HRESET_FSBIR
;
1795 if (val
& OHCI_HRESET_FSBIR
)
1796 ohci_hard_reset(ohci
);
1799 case 26: /* HcHInterruptEnable */
1803 case 27: /* HcHInterruptTest */
1808 trace_usb_ohci_mem_write_bad_offset(addr
);
1813 static void ohci_async_cancel_device(OHCIState
*ohci
, USBDevice
*dev
)
1815 if (ohci
->async_td
&&
1816 usb_packet_is_inflight(&ohci
->usb_packet
) &&
1817 ohci
->usb_packet
.ep
->dev
== dev
) {
1818 usb_cancel_packet(&ohci
->usb_packet
);
1823 static const MemoryRegionOps ohci_mem_ops
= {
1824 .read
= ohci_mem_read
,
1825 .write
= ohci_mem_write
,
1826 .endianness
= DEVICE_LITTLE_ENDIAN
,
1829 static USBPortOps ohci_port_ops
= {
1830 .attach
= ohci_attach
,
1831 .detach
= ohci_detach
,
1832 .child_detach
= ohci_child_detach
,
1833 .wakeup
= ohci_wakeup
,
1834 .complete
= ohci_async_complete_packet
,
1837 static USBBusOps ohci_bus_ops
= {
1840 static void usb_ohci_init(OHCIState
*ohci
, DeviceState
*dev
,
1841 int num_ports
, dma_addr_t localmem_base
,
1842 char *masterbus
, uint32_t firstport
,
1843 AddressSpace
*as
, Error
**errp
)
1850 if (usb_frame_time
== 0) {
1851 #ifdef OHCI_TIME_WARP
1852 usb_frame_time
= get_ticks_per_sec();
1853 usb_bit_time
= muldiv64(1, get_ticks_per_sec(), USB_HZ
/1000);
1855 usb_frame_time
= muldiv64(1, get_ticks_per_sec(), 1000);
1856 if (get_ticks_per_sec() >= USB_HZ
) {
1857 usb_bit_time
= muldiv64(1, get_ticks_per_sec(), USB_HZ
);
1862 trace_usb_ohci_init_time(usb_frame_time
, usb_bit_time
);
1865 ohci
->num_ports
= num_ports
;
1867 USBPort
*ports
[OHCI_MAX_PORTS
];
1868 for(i
= 0; i
< num_ports
; i
++) {
1869 ports
[i
] = &ohci
->rhport
[i
].port
;
1871 usb_register_companion(masterbus
, ports
, num_ports
,
1872 firstport
, ohci
, &ohci_port_ops
,
1873 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
,
1876 error_propagate(errp
, err
);
1880 usb_bus_new(&ohci
->bus
, sizeof(ohci
->bus
), &ohci_bus_ops
, dev
);
1881 for (i
= 0; i
< num_ports
; i
++) {
1882 usb_register_port(&ohci
->bus
, &ohci
->rhport
[i
].port
,
1883 ohci
, i
, &ohci_port_ops
,
1884 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
);
1888 memory_region_init_io(&ohci
->mem
, OBJECT(dev
), &ohci_mem_ops
,
1890 ohci
->localmem_base
= localmem_base
;
1892 ohci
->name
= object_get_typename(OBJECT(dev
));
1893 usb_packet_init(&ohci
->usb_packet
);
1897 ohci
->eof_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
1898 ohci_frame_boundary
, ohci
);
1901 #define TYPE_PCI_OHCI "pci-ohci"
1902 #define PCI_OHCI(obj) OBJECT_CHECK(OHCIPCIState, (obj), TYPE_PCI_OHCI)
1906 PCIDevice parent_obj
;
1915 /** A typical O/EHCI will stop operating, set itself into error state
1916 * (which can be queried by MMIO) and will set PERR in its config
1917 * space to signal that it got an error
1919 static void ohci_die(OHCIState
*ohci
)
1921 OHCIPCIState
*dev
= container_of(ohci
, OHCIPCIState
, state
);
1923 trace_usb_ohci_die();
1925 ohci_set_interrupt(ohci
, OHCI_INTR_UE
);
1926 ohci_bus_stop(ohci
);
1927 pci_set_word(dev
->parent_obj
.config
+ PCI_STATUS
,
1928 PCI_STATUS_DETECTED_PARITY
);
1931 static void usb_ohci_realize_pci(PCIDevice
*dev
, Error
**errp
)
1934 OHCIPCIState
*ohci
= PCI_OHCI(dev
);
1936 dev
->config
[PCI_CLASS_PROG
] = 0x10; /* OHCI */
1937 dev
->config
[PCI_INTERRUPT_PIN
] = 0x01; /* interrupt pin A */
1939 usb_ohci_init(&ohci
->state
, DEVICE(dev
), ohci
->num_ports
, 0,
1940 ohci
->masterbus
, ohci
->firstport
,
1941 pci_get_address_space(dev
), &err
);
1943 error_propagate(errp
, err
);
1947 ohci
->state
.irq
= pci_allocate_irq(dev
);
1948 pci_register_bar(dev
, 0, 0, &ohci
->state
.mem
);
1951 static void usb_ohci_exit(PCIDevice
*dev
)
1953 OHCIPCIState
*ohci
= PCI_OHCI(dev
);
1954 OHCIState
*s
= &ohci
->state
;
1956 trace_usb_ohci_exit(s
->name
);
1960 usb_cancel_packet(&s
->usb_packet
);
1963 ohci_stop_endpoints(s
);
1965 if (!ohci
->masterbus
) {
1966 usb_bus_release(&s
->bus
);
1969 timer_del(s
->eof_timer
);
1970 timer_free(s
->eof_timer
);
1973 static void usb_ohci_reset_pci(DeviceState
*d
)
1975 PCIDevice
*dev
= PCI_DEVICE(d
);
1976 OHCIPCIState
*ohci
= PCI_OHCI(dev
);
1977 OHCIState
*s
= &ohci
->state
;
1982 #define TYPE_SYSBUS_OHCI "sysbus-ohci"
1983 #define SYSBUS_OHCI(obj) OBJECT_CHECK(OHCISysBusState, (obj), TYPE_SYSBUS_OHCI)
1987 SysBusDevice parent_obj
;
1992 dma_addr_t dma_offset
;
1995 static void ohci_realize_pxa(DeviceState
*dev
, Error
**errp
)
1997 OHCISysBusState
*s
= SYSBUS_OHCI(dev
);
1998 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
2000 /* Cannot fail as we pass NULL for masterbus */
2001 usb_ohci_init(&s
->ohci
, dev
, s
->num_ports
, s
->dma_offset
, NULL
, 0,
2002 &address_space_memory
, &error_abort
);
2003 sysbus_init_irq(sbd
, &s
->ohci
.irq
);
2004 sysbus_init_mmio(sbd
, &s
->ohci
.mem
);
2007 static void usb_ohci_reset_sysbus(DeviceState
*dev
)
2009 OHCISysBusState
*s
= SYSBUS_OHCI(dev
);
2010 OHCIState
*ohci
= &s
->ohci
;
2012 ohci_hard_reset(ohci
);
2015 static Property ohci_pci_properties
[] = {
2016 DEFINE_PROP_STRING("masterbus", OHCIPCIState
, masterbus
),
2017 DEFINE_PROP_UINT32("num-ports", OHCIPCIState
, num_ports
, 3),
2018 DEFINE_PROP_UINT32("firstport", OHCIPCIState
, firstport
, 0),
2019 DEFINE_PROP_END_OF_LIST(),
2022 static const VMStateDescription vmstate_ohci_state_port
= {
2023 .name
= "ohci-core/port",
2025 .minimum_version_id
= 1,
2026 .fields
= (VMStateField
[]) {
2027 VMSTATE_UINT32(ctrl
, OHCIPort
),
2028 VMSTATE_END_OF_LIST()
2032 static bool ohci_eof_timer_needed(void *opaque
)
2034 OHCIState
*ohci
= opaque
;
2036 return timer_pending(ohci
->eof_timer
);
2039 static const VMStateDescription vmstate_ohci_eof_timer
= {
2040 .name
= "ohci-core/eof-timer",
2042 .minimum_version_id
= 1,
2043 .needed
= ohci_eof_timer_needed
,
2044 .fields
= (VMStateField
[]) {
2045 VMSTATE_TIMER_PTR(eof_timer
, OHCIState
),
2046 VMSTATE_END_OF_LIST()
2050 static const VMStateDescription vmstate_ohci_state
= {
2051 .name
= "ohci-core",
2053 .minimum_version_id
= 1,
2054 .fields
= (VMStateField
[]) {
2055 VMSTATE_INT64(sof_time
, OHCIState
),
2056 VMSTATE_UINT32(ctl
, OHCIState
),
2057 VMSTATE_UINT32(status
, OHCIState
),
2058 VMSTATE_UINT32(intr_status
, OHCIState
),
2059 VMSTATE_UINT32(intr
, OHCIState
),
2060 VMSTATE_UINT32(hcca
, OHCIState
),
2061 VMSTATE_UINT32(ctrl_head
, OHCIState
),
2062 VMSTATE_UINT32(ctrl_cur
, OHCIState
),
2063 VMSTATE_UINT32(bulk_head
, OHCIState
),
2064 VMSTATE_UINT32(bulk_cur
, OHCIState
),
2065 VMSTATE_UINT32(per_cur
, OHCIState
),
2066 VMSTATE_UINT32(done
, OHCIState
),
2067 VMSTATE_INT32(done_count
, OHCIState
),
2068 VMSTATE_UINT16(fsmps
, OHCIState
),
2069 VMSTATE_UINT8(fit
, OHCIState
),
2070 VMSTATE_UINT16(fi
, OHCIState
),
2071 VMSTATE_UINT8(frt
, OHCIState
),
2072 VMSTATE_UINT16(frame_number
, OHCIState
),
2073 VMSTATE_UINT16(padding
, OHCIState
),
2074 VMSTATE_UINT32(pstart
, OHCIState
),
2075 VMSTATE_UINT32(lst
, OHCIState
),
2076 VMSTATE_UINT32(rhdesc_a
, OHCIState
),
2077 VMSTATE_UINT32(rhdesc_b
, OHCIState
),
2078 VMSTATE_UINT32(rhstatus
, OHCIState
),
2079 VMSTATE_STRUCT_ARRAY(rhport
, OHCIState
, OHCI_MAX_PORTS
, 0,
2080 vmstate_ohci_state_port
, OHCIPort
),
2081 VMSTATE_UINT32(hstatus
, OHCIState
),
2082 VMSTATE_UINT32(hmask
, OHCIState
),
2083 VMSTATE_UINT32(hreset
, OHCIState
),
2084 VMSTATE_UINT32(htest
, OHCIState
),
2085 VMSTATE_UINT32(old_ctl
, OHCIState
),
2086 VMSTATE_UINT8_ARRAY(usb_buf
, OHCIState
, 8192),
2087 VMSTATE_UINT32(async_td
, OHCIState
),
2088 VMSTATE_BOOL(async_complete
, OHCIState
),
2089 VMSTATE_END_OF_LIST()
2091 .subsections
= (const VMStateDescription
*[]) {
2092 &vmstate_ohci_eof_timer
,
2097 static const VMStateDescription vmstate_ohci
= {
2100 .minimum_version_id
= 1,
2101 .fields
= (VMStateField
[]) {
2102 VMSTATE_PCI_DEVICE(parent_obj
, OHCIPCIState
),
2103 VMSTATE_STRUCT(state
, OHCIPCIState
, 1, vmstate_ohci_state
, OHCIState
),
2104 VMSTATE_END_OF_LIST()
2108 static void ohci_pci_class_init(ObjectClass
*klass
, void *data
)
2110 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2111 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2113 k
->realize
= usb_ohci_realize_pci
;
2114 k
->exit
= usb_ohci_exit
;
2115 k
->vendor_id
= PCI_VENDOR_ID_APPLE
;
2116 k
->device_id
= PCI_DEVICE_ID_APPLE_IPID_USB
;
2117 k
->class_id
= PCI_CLASS_SERIAL_USB
;
2118 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
2119 dc
->desc
= "Apple USB Controller";
2120 dc
->props
= ohci_pci_properties
;
2121 dc
->hotpluggable
= false;
2122 dc
->vmsd
= &vmstate_ohci
;
2123 dc
->reset
= usb_ohci_reset_pci
;
2126 static const TypeInfo ohci_pci_info
= {
2127 .name
= TYPE_PCI_OHCI
,
2128 .parent
= TYPE_PCI_DEVICE
,
2129 .instance_size
= sizeof(OHCIPCIState
),
2130 .class_init
= ohci_pci_class_init
,
2133 static Property ohci_sysbus_properties
[] = {
2134 DEFINE_PROP_UINT32("num-ports", OHCISysBusState
, num_ports
, 3),
2135 DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState
, dma_offset
, 3),
2136 DEFINE_PROP_END_OF_LIST(),
2139 static void ohci_sysbus_class_init(ObjectClass
*klass
, void *data
)
2141 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2143 dc
->realize
= ohci_realize_pxa
;
2144 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
2145 dc
->desc
= "OHCI USB Controller";
2146 dc
->props
= ohci_sysbus_properties
;
2147 dc
->reset
= usb_ohci_reset_sysbus
;
2150 static const TypeInfo ohci_sysbus_info
= {
2151 .name
= TYPE_SYSBUS_OHCI
,
2152 .parent
= TYPE_SYS_BUS_DEVICE
,
2153 .instance_size
= sizeof(OHCISysBusState
),
2154 .class_init
= ohci_sysbus_class_init
,
2157 static void ohci_register_types(void)
2159 type_register_static(&ohci_pci_info
);
2160 type_register_static(&ohci_sysbus_info
);
2163 type_init(ohci_register_types
)