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ivshmem-server: Don't overload POSIX shmem and file name
[qemu/ar7.git] / target-ppc / translate_init.c
blobfb206aff29ad30d5e3d0c6f0c79d2a2baa66c778
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "disas/bfd.h"
23 #include "exec/gdbstub.h"
24 #include <sysemu/kvm.h>
25 #include "kvm_ppc.h"
26 #include "sysemu/arch_init.h"
27 #include "sysemu/cpus.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qapi/visitor.h"
33 #include "hw/qdev-properties.h"
34
35 //#define PPC_DUMP_CPU
36 //#define PPC_DEBUG_SPR
37 //#define PPC_DUMP_SPR_ACCESSES
38 /* #define USE_APPLE_GDB */
39
40 /* For user-mode emulation, we don't emulate any IRQ controller */
41 #if defined(CONFIG_USER_ONLY)
42 #define PPC_IRQ_INIT_FN(name) \
43 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
44 { \
45 }
46 #else
47 #define PPC_IRQ_INIT_FN(name) \
48 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
49 #endif
50
51 PPC_IRQ_INIT_FN(40x);
52 PPC_IRQ_INIT_FN(6xx);
53 PPC_IRQ_INIT_FN(970);
54 PPC_IRQ_INIT_FN(POWER7);
55 PPC_IRQ_INIT_FN(e500);
56
57 /* Generic callbacks:
58 * do nothing but store/retrieve spr value
59 */
60 static void spr_load_dump_spr(int sprn)
61 {
62 #ifdef PPC_DUMP_SPR_ACCESSES
63 TCGv_i32 t0 = tcg_const_i32(sprn);
64 gen_helper_load_dump_spr(cpu_env, t0);
65 tcg_temp_free_i32(t0);
66 #endif
67 }
68
69 static void spr_read_generic (DisasContext *ctx, int gprn, int sprn)
70 {
71 gen_load_spr(cpu_gpr[gprn], sprn);
72 spr_load_dump_spr(sprn);
73 }
74
75 static void spr_store_dump_spr(int sprn)
76 {
77 #ifdef PPC_DUMP_SPR_ACCESSES
78 TCGv_i32 t0 = tcg_const_i32(sprn);
79 gen_helper_store_dump_spr(cpu_env, t0);
80 tcg_temp_free_i32(t0);
81 #endif
82 }
83
84 static void spr_write_generic (DisasContext *ctx, int sprn, int gprn)
85 {
86 gen_store_spr(sprn, cpu_gpr[gprn]);
87 spr_store_dump_spr(sprn);
88 }
89
90 #if !defined(CONFIG_USER_ONLY)
91 static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
92 {
93 #ifdef TARGET_PPC64
94 TCGv t0 = tcg_temp_new();
95 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
96 gen_store_spr(sprn, t0);
97 tcg_temp_free(t0);
98 spr_store_dump_spr(sprn);
99 #else
100 spr_write_generic(ctx, sprn, gprn);
101 #endif
102 }
103
104 static void spr_write_clear (DisasContext *ctx, int sprn, int gprn)
105 {
106 TCGv t0 = tcg_temp_new();
107 TCGv t1 = tcg_temp_new();
108 gen_load_spr(t0, sprn);
109 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
110 tcg_gen_and_tl(t0, t0, t1);
111 gen_store_spr(sprn, t0);
112 tcg_temp_free(t0);
113 tcg_temp_free(t1);
114 }
115
116 static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
117 {
118 }
119
120 #endif
121
122 /* SPR common to all PowerPC */
123 /* XER */
124 static void spr_read_xer (DisasContext *ctx, int gprn, int sprn)
125 {
126 gen_read_xer(cpu_gpr[gprn]);
127 }
128
129 static void spr_write_xer (DisasContext *ctx, int sprn, int gprn)
130 {
131 gen_write_xer(cpu_gpr[gprn]);
132 }
133
134 /* LR */
135 static void spr_read_lr (DisasContext *ctx, int gprn, int sprn)
136 {
137 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
138 }
139
140 static void spr_write_lr (DisasContext *ctx, int sprn, int gprn)
141 {
142 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
143 }
144
145 /* CFAR */
146 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
147 static void spr_read_cfar (DisasContext *ctx, int gprn, int sprn)
148 {
149 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
150 }
151
152 static void spr_write_cfar (DisasContext *ctx, int sprn, int gprn)
153 {
154 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
155 }
156 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
157
158 /* CTR */
159 static void spr_read_ctr (DisasContext *ctx, int gprn, int sprn)
160 {
161 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
162 }
163
164 static void spr_write_ctr (DisasContext *ctx, int sprn, int gprn)
165 {
166 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
167 }
168
169 /* User read access to SPR */
170 /* USPRx */
171 /* UMMCRx */
172 /* UPMCx */
173 /* USIA */
174 /* UDECR */
175 static void spr_read_ureg (DisasContext *ctx, int gprn, int sprn)
176 {
177 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
178 }
179
180 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
181 static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
182 {
183 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
184 }
185 #endif
186
187 /* SPR common to all non-embedded PowerPC */
188 /* DECR */
189 #if !defined(CONFIG_USER_ONLY)
190 static void spr_read_decr (DisasContext *ctx, int gprn, int sprn)
191 {
192 if (ctx->tb->cflags & CF_USE_ICOUNT) {
193 gen_io_start();
194 }
195 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
196 if (ctx->tb->cflags & CF_USE_ICOUNT) {
197 gen_io_end();
198 gen_stop_exception(ctx);
199 }
200 }
201
202 static void spr_write_decr (DisasContext *ctx, int sprn, int gprn)
203 {
204 if (ctx->tb->cflags & CF_USE_ICOUNT) {
205 gen_io_start();
206 }
207 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
208 if (ctx->tb->cflags & CF_USE_ICOUNT) {
209 gen_io_end();
210 gen_stop_exception(ctx);
211 }
212 }
213 #endif
214
215 /* SPR common to all non-embedded PowerPC, except 601 */
216 /* Time base */
217 static void spr_read_tbl (DisasContext *ctx, int gprn, int sprn)
218 {
219 if (ctx->tb->cflags & CF_USE_ICOUNT) {
220 gen_io_start();
221 }
222 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
223 if (ctx->tb->cflags & CF_USE_ICOUNT) {
224 gen_io_end();
225 gen_stop_exception(ctx);
226 }
227 }
228
229 static void spr_read_tbu (DisasContext *ctx, int gprn, int sprn)
230 {
231 if (ctx->tb->cflags & CF_USE_ICOUNT) {
232 gen_io_start();
233 }
234 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
235 if (ctx->tb->cflags & CF_USE_ICOUNT) {
236 gen_io_end();
237 gen_stop_exception(ctx);
238 }
239 }
240
241 __attribute__ (( unused ))
242 static void spr_read_atbl (DisasContext *ctx, int gprn, int sprn)
243 {
244 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
245 }
246
247 __attribute__ (( unused ))
248 static void spr_read_atbu (DisasContext *ctx, int gprn, int sprn)
249 {
250 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
251 }
252
253 #if !defined(CONFIG_USER_ONLY)
254 static void spr_write_tbl (DisasContext *ctx, int sprn, int gprn)
255 {
256 if (ctx->tb->cflags & CF_USE_ICOUNT) {
257 gen_io_start();
258 }
259 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
260 if (ctx->tb->cflags & CF_USE_ICOUNT) {
261 gen_io_end();
262 gen_stop_exception(ctx);
263 }
264 }
265
266 static void spr_write_tbu (DisasContext *ctx, int sprn, int gprn)
267 {
268 if (ctx->tb->cflags & CF_USE_ICOUNT) {
269 gen_io_start();
270 }
271 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
272 if (ctx->tb->cflags & CF_USE_ICOUNT) {
273 gen_io_end();
274 gen_stop_exception(ctx);
275 }
276 }
277
278 __attribute__ (( unused ))
279 static void spr_write_atbl (DisasContext *ctx, int sprn, int gprn)
280 {
281 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
282 }
283
284 __attribute__ (( unused ))
285 static void spr_write_atbu (DisasContext *ctx, int sprn, int gprn)
286 {
287 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
288 }
289
290 #if defined(TARGET_PPC64)
291 __attribute__ (( unused ))
292 static void spr_read_purr (DisasContext *ctx, int gprn, int sprn)
293 {
294 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
295 }
296 #endif
297 #endif
298
299 #if !defined(CONFIG_USER_ONLY)
300 /* IBAT0U...IBAT0U */
301 /* IBAT0L...IBAT7L */
302 static void spr_read_ibat (DisasContext *ctx, int gprn, int sprn)
303 {
304 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
305 }
306
307 static void spr_read_ibat_h (DisasContext *ctx, int gprn, int sprn)
308 {
309 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
310 }
311
312 static void spr_write_ibatu (DisasContext *ctx, int sprn, int gprn)
313 {
314 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
315 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
316 tcg_temp_free_i32(t0);
317 }
318
319 static void spr_write_ibatu_h (DisasContext *ctx, int sprn, int gprn)
320 {
321 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
322 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
323 tcg_temp_free_i32(t0);
324 }
325
326 static void spr_write_ibatl (DisasContext *ctx, int sprn, int gprn)
327 {
328 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
329 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
330 tcg_temp_free_i32(t0);
331 }
332
333 static void spr_write_ibatl_h (DisasContext *ctx, int sprn, int gprn)
334 {
335 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
336 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
337 tcg_temp_free_i32(t0);
338 }
339
340 /* DBAT0U...DBAT7U */
341 /* DBAT0L...DBAT7L */
342 static void spr_read_dbat (DisasContext *ctx, int gprn, int sprn)
343 {
344 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
345 }
346
347 static void spr_read_dbat_h (DisasContext *ctx, int gprn, int sprn)
348 {
349 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
350 }
351
352 static void spr_write_dbatu (DisasContext *ctx, int sprn, int gprn)
353 {
354 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
355 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
356 tcg_temp_free_i32(t0);
357 }
358
359 static void spr_write_dbatu_h (DisasContext *ctx, int sprn, int gprn)
360 {
361 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
362 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
363 tcg_temp_free_i32(t0);
364 }
365
366 static void spr_write_dbatl (DisasContext *ctx, int sprn, int gprn)
367 {
368 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
369 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
370 tcg_temp_free_i32(t0);
371 }
372
373 static void spr_write_dbatl_h (DisasContext *ctx, int sprn, int gprn)
374 {
375 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
376 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
377 tcg_temp_free_i32(t0);
378 }
379
380 /* SDR1 */
381 static void spr_write_sdr1 (DisasContext *ctx, int sprn, int gprn)
382 {
383 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
384 }
385
386 /* 64 bits PowerPC specific SPRs */
387 #if defined(TARGET_PPC64)
388 static void spr_read_hior (DisasContext *ctx, int gprn, int sprn)
389 {
390 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
391 }
392
393 static void spr_write_hior (DisasContext *ctx, int sprn, int gprn)
394 {
395 TCGv t0 = tcg_temp_new();
396 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
397 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
398 tcg_temp_free(t0);
399 }
400 #endif
401 #endif
402
403 /* PowerPC 601 specific registers */
404 /* RTC */
405 static void spr_read_601_rtcl (DisasContext *ctx, int gprn, int sprn)
406 {
407 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
408 }
409
410 static void spr_read_601_rtcu (DisasContext *ctx, int gprn, int sprn)
411 {
412 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
413 }
414
415 #if !defined(CONFIG_USER_ONLY)
416 static void spr_write_601_rtcu (DisasContext *ctx, int sprn, int gprn)
417 {
418 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
419 }
420
421 static void spr_write_601_rtcl (DisasContext *ctx, int sprn, int gprn)
422 {
423 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
424 }
425
426 static void spr_write_hid0_601 (DisasContext *ctx, int sprn, int gprn)
427 {
428 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
429 /* Must stop the translation as endianness may have changed */
430 gen_stop_exception(ctx);
431 }
432 #endif
433
434 /* Unified bats */
435 #if !defined(CONFIG_USER_ONLY)
436 static void spr_read_601_ubat (DisasContext *ctx, int gprn, int sprn)
437 {
438 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
439 }
440
441 static void spr_write_601_ubatu (DisasContext *ctx, int sprn, int gprn)
442 {
443 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
444 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
445 tcg_temp_free_i32(t0);
446 }
447
448 static void spr_write_601_ubatl (DisasContext *ctx, int sprn, int gprn)
449 {
450 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
451 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
452 tcg_temp_free_i32(t0);
453 }
454 #endif
455
456 /* PowerPC 40x specific registers */
457 #if !defined(CONFIG_USER_ONLY)
458 static void spr_read_40x_pit (DisasContext *ctx, int gprn, int sprn)
459 {
460 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
461 }
462
463 static void spr_write_40x_pit (DisasContext *ctx, int sprn, int gprn)
464 {
465 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
466 }
467
468 static void spr_write_40x_dbcr0 (DisasContext *ctx, int sprn, int gprn)
469 {
470 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
471 /* We must stop translation as we may have rebooted */
472 gen_stop_exception(ctx);
473 }
474
475 static void spr_write_40x_sler (DisasContext *ctx, int sprn, int gprn)
476 {
477 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
478 }
479
480 static void spr_write_booke_tcr (DisasContext *ctx, int sprn, int gprn)
481 {
482 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
483 }
484
485 static void spr_write_booke_tsr (DisasContext *ctx, int sprn, int gprn)
486 {
487 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
488 }
489 #endif
490
491 /* PowerPC 403 specific registers */
492 /* PBL1 / PBU1 / PBL2 / PBU2 */
493 #if !defined(CONFIG_USER_ONLY)
494 static void spr_read_403_pbr (DisasContext *ctx, int gprn, int sprn)
495 {
496 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
497 }
498
499 static void spr_write_403_pbr (DisasContext *ctx, int sprn, int gprn)
500 {
501 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
502 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
503 tcg_temp_free_i32(t0);
504 }
505
506 static void spr_write_pir (DisasContext *ctx, int sprn, int gprn)
507 {
508 TCGv t0 = tcg_temp_new();
509 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
510 gen_store_spr(SPR_PIR, t0);
511 tcg_temp_free(t0);
512 }
513 #endif
514
515 /* SPE specific registers */
516 static void spr_read_spefscr (DisasContext *ctx, int gprn, int sprn)
517 {
518 TCGv_i32 t0 = tcg_temp_new_i32();
519 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
520 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
521 tcg_temp_free_i32(t0);
522 }
523
524 static void spr_write_spefscr (DisasContext *ctx, int sprn, int gprn)
525 {
526 TCGv_i32 t0 = tcg_temp_new_i32();
527 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
528 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
529 tcg_temp_free_i32(t0);
530 }
531
532 #if !defined(CONFIG_USER_ONLY)
533 /* Callback used to write the exception vector base */
534 static void spr_write_excp_prefix (DisasContext *ctx, int sprn, int gprn)
535 {
536 TCGv t0 = tcg_temp_new();
537 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
538 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
539 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
540 gen_store_spr(sprn, t0);
541 tcg_temp_free(t0);
542 }
543
544 static void spr_write_excp_vector (DisasContext *ctx, int sprn, int gprn)
545 {
546 int sprn_offs;
547
548 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
549 sprn_offs = sprn - SPR_BOOKE_IVOR0;
550 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
551 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
552 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
553 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
554 } else {
555 printf("Trying to write an unknown exception vector %d %03x\n",
556 sprn, sprn);
557 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
558 return;
559 }
560
561 TCGv t0 = tcg_temp_new();
562 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
563 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
564 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
565 gen_store_spr(sprn, t0);
566 tcg_temp_free(t0);
567 }
568 #endif
569
570 static inline void vscr_init (CPUPPCState *env, uint32_t val)
571 {
572 env->vscr = val;
573 /* Altivec always uses round-to-nearest */
574 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
575 set_flush_to_zero(vscr_nj, &env->vec_status);
576 }
577
578 #ifdef CONFIG_USER_ONLY
579 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
580 oea_read, oea_write, one_reg_id, initial_value) \
581 _spr_register(env, num, name, uea_read, uea_write, initial_value)
582 #else
583 #if !defined(CONFIG_KVM)
584 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
585 oea_read, oea_write, one_reg_id, initial_value) \
586 _spr_register(env, num, name, uea_read, uea_write, \
587 oea_read, oea_write, initial_value)
588 #else
589 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
590 oea_read, oea_write, one_reg_id, initial_value) \
591 _spr_register(env, num, name, uea_read, uea_write, \
592 oea_read, oea_write, one_reg_id, initial_value)
593 #endif
594 #endif
595
596 #define spr_register(env, num, name, uea_read, uea_write, \
597 oea_read, oea_write, initial_value) \
598 spr_register_kvm(env, num, name, uea_read, uea_write, \
599 oea_read, oea_write, 0, initial_value)
600
601 static inline void _spr_register(CPUPPCState *env, int num,
602 const char *name,
603 void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
604 void (*uea_write)(DisasContext *ctx, int sprn, int gprn),
605 #if !defined(CONFIG_USER_ONLY)
606
607 void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
608 void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
609 #endif
610 #if defined(CONFIG_KVM)
611 uint64_t one_reg_id,
612 #endif
613 target_ulong initial_value)
614 {
615 ppc_spr_t *spr;
616
617 spr = &env->spr_cb[num];
618 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
619 #if !defined(CONFIG_USER_ONLY)
620 spr->oea_read != NULL || spr->oea_write != NULL ||
621 #endif
622 spr->uea_read != NULL || spr->uea_write != NULL) {
623 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
624 exit(1);
625 }
626 #if defined(PPC_DEBUG_SPR)
627 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
628 name, initial_value);
629 #endif
630 spr->name = name;
631 spr->uea_read = uea_read;
632 spr->uea_write = uea_write;
633 #if !defined(CONFIG_USER_ONLY)
634 spr->oea_read = oea_read;
635 spr->oea_write = oea_write;
636 #endif
637 #if defined(CONFIG_KVM)
638 spr->one_reg_id = one_reg_id,
639 #endif
640 env->spr[num] = spr->default_value = initial_value;
641 }
642
643 /* Generic PowerPC SPRs */
644 static void gen_spr_generic (CPUPPCState *env)
645 {
646 /* Integer processing */
647 spr_register(env, SPR_XER, "XER",
648 &spr_read_xer, &spr_write_xer,
649 &spr_read_xer, &spr_write_xer,
650 0x00000000);
651 /* Branch contol */
652 spr_register(env, SPR_LR, "LR",
653 &spr_read_lr, &spr_write_lr,
654 &spr_read_lr, &spr_write_lr,
655 0x00000000);
656 spr_register(env, SPR_CTR, "CTR",
657 &spr_read_ctr, &spr_write_ctr,
658 &spr_read_ctr, &spr_write_ctr,
659 0x00000000);
660 /* Interrupt processing */
661 spr_register(env, SPR_SRR0, "SRR0",
662 SPR_NOACCESS, SPR_NOACCESS,
663 &spr_read_generic, &spr_write_generic,
664 0x00000000);
665 spr_register(env, SPR_SRR1, "SRR1",
666 SPR_NOACCESS, SPR_NOACCESS,
667 &spr_read_generic, &spr_write_generic,
668 0x00000000);
669 /* Processor control */
670 spr_register(env, SPR_SPRG0, "SPRG0",
671 SPR_NOACCESS, SPR_NOACCESS,
672 &spr_read_generic, &spr_write_generic,
673 0x00000000);
674 spr_register(env, SPR_SPRG1, "SPRG1",
675 SPR_NOACCESS, SPR_NOACCESS,
676 &spr_read_generic, &spr_write_generic,
677 0x00000000);
678 spr_register(env, SPR_SPRG2, "SPRG2",
679 SPR_NOACCESS, SPR_NOACCESS,
680 &spr_read_generic, &spr_write_generic,
681 0x00000000);
682 spr_register(env, SPR_SPRG3, "SPRG3",
683 SPR_NOACCESS, SPR_NOACCESS,
684 &spr_read_generic, &spr_write_generic,
685 0x00000000);
686 }
687
688 /* SPR common to all non-embedded PowerPC, including 601 */
689 static void gen_spr_ne_601 (CPUPPCState *env)
690 {
691 /* Exception processing */
692 spr_register_kvm(env, SPR_DSISR, "DSISR",
693 SPR_NOACCESS, SPR_NOACCESS,
694 &spr_read_generic, &spr_write_generic,
695 KVM_REG_PPC_DSISR, 0x00000000);
696 spr_register_kvm(env, SPR_DAR, "DAR",
697 SPR_NOACCESS, SPR_NOACCESS,
698 &spr_read_generic, &spr_write_generic,
699 KVM_REG_PPC_DAR, 0x00000000);
700 /* Timer */
701 spr_register(env, SPR_DECR, "DECR",
702 SPR_NOACCESS, SPR_NOACCESS,
703 &spr_read_decr, &spr_write_decr,
704 0x00000000);
705 /* Memory management */
706 spr_register(env, SPR_SDR1, "SDR1",
707 SPR_NOACCESS, SPR_NOACCESS,
708 &spr_read_generic, &spr_write_sdr1,
709 0x00000000);
710 }
711
712 /* BATs 0-3 */
713 static void gen_low_BATs (CPUPPCState *env)
714 {
715 #if !defined(CONFIG_USER_ONLY)
716 spr_register(env, SPR_IBAT0U, "IBAT0U",
717 SPR_NOACCESS, SPR_NOACCESS,
718 &spr_read_ibat, &spr_write_ibatu,
719 0x00000000);
720 spr_register(env, SPR_IBAT0L, "IBAT0L",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_ibat, &spr_write_ibatl,
723 0x00000000);
724 spr_register(env, SPR_IBAT1U, "IBAT1U",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_ibat, &spr_write_ibatu,
727 0x00000000);
728 spr_register(env, SPR_IBAT1L, "IBAT1L",
729 SPR_NOACCESS, SPR_NOACCESS,
730 &spr_read_ibat, &spr_write_ibatl,
731 0x00000000);
732 spr_register(env, SPR_IBAT2U, "IBAT2U",
733 SPR_NOACCESS, SPR_NOACCESS,
734 &spr_read_ibat, &spr_write_ibatu,
735 0x00000000);
736 spr_register(env, SPR_IBAT2L, "IBAT2L",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_ibat, &spr_write_ibatl,
739 0x00000000);
740 spr_register(env, SPR_IBAT3U, "IBAT3U",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_ibat, &spr_write_ibatu,
743 0x00000000);
744 spr_register(env, SPR_IBAT3L, "IBAT3L",
745 SPR_NOACCESS, SPR_NOACCESS,
746 &spr_read_ibat, &spr_write_ibatl,
747 0x00000000);
748 spr_register(env, SPR_DBAT0U, "DBAT0U",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_dbat, &spr_write_dbatu,
751 0x00000000);
752 spr_register(env, SPR_DBAT0L, "DBAT0L",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_dbat, &spr_write_dbatl,
755 0x00000000);
756 spr_register(env, SPR_DBAT1U, "DBAT1U",
757 SPR_NOACCESS, SPR_NOACCESS,
758 &spr_read_dbat, &spr_write_dbatu,
759 0x00000000);
760 spr_register(env, SPR_DBAT1L, "DBAT1L",
761 SPR_NOACCESS, SPR_NOACCESS,
762 &spr_read_dbat, &spr_write_dbatl,
763 0x00000000);
764 spr_register(env, SPR_DBAT2U, "DBAT2U",
765 SPR_NOACCESS, SPR_NOACCESS,
766 &spr_read_dbat, &spr_write_dbatu,
767 0x00000000);
768 spr_register(env, SPR_DBAT2L, "DBAT2L",
769 SPR_NOACCESS, SPR_NOACCESS,
770 &spr_read_dbat, &spr_write_dbatl,
771 0x00000000);
772 spr_register(env, SPR_DBAT3U, "DBAT3U",
773 SPR_NOACCESS, SPR_NOACCESS,
774 &spr_read_dbat, &spr_write_dbatu,
775 0x00000000);
776 spr_register(env, SPR_DBAT3L, "DBAT3L",
777 SPR_NOACCESS, SPR_NOACCESS,
778 &spr_read_dbat, &spr_write_dbatl,
779 0x00000000);
780 env->nb_BATs += 4;
781 #endif
782 }
783
784 /* BATs 4-7 */
785 static void gen_high_BATs (CPUPPCState *env)
786 {
787 #if !defined(CONFIG_USER_ONLY)
788 spr_register(env, SPR_IBAT4U, "IBAT4U",
789 SPR_NOACCESS, SPR_NOACCESS,
790 &spr_read_ibat_h, &spr_write_ibatu_h,
791 0x00000000);
792 spr_register(env, SPR_IBAT4L, "IBAT4L",
793 SPR_NOACCESS, SPR_NOACCESS,
794 &spr_read_ibat_h, &spr_write_ibatl_h,
795 0x00000000);
796 spr_register(env, SPR_IBAT5U, "IBAT5U",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_ibat_h, &spr_write_ibatu_h,
799 0x00000000);
800 spr_register(env, SPR_IBAT5L, "IBAT5L",
801 SPR_NOACCESS, SPR_NOACCESS,
802 &spr_read_ibat_h, &spr_write_ibatl_h,
803 0x00000000);
804 spr_register(env, SPR_IBAT6U, "IBAT6U",
805 SPR_NOACCESS, SPR_NOACCESS,
806 &spr_read_ibat_h, &spr_write_ibatu_h,
807 0x00000000);
808 spr_register(env, SPR_IBAT6L, "IBAT6L",
809 SPR_NOACCESS, SPR_NOACCESS,
810 &spr_read_ibat_h, &spr_write_ibatl_h,
811 0x00000000);
812 spr_register(env, SPR_IBAT7U, "IBAT7U",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_ibat_h, &spr_write_ibatu_h,
815 0x00000000);
816 spr_register(env, SPR_IBAT7L, "IBAT7L",
817 SPR_NOACCESS, SPR_NOACCESS,
818 &spr_read_ibat_h, &spr_write_ibatl_h,
819 0x00000000);
820 spr_register(env, SPR_DBAT4U, "DBAT4U",
821 SPR_NOACCESS, SPR_NOACCESS,
822 &spr_read_dbat_h, &spr_write_dbatu_h,
823 0x00000000);
824 spr_register(env, SPR_DBAT4L, "DBAT4L",
825 SPR_NOACCESS, SPR_NOACCESS,
826 &spr_read_dbat_h, &spr_write_dbatl_h,
827 0x00000000);
828 spr_register(env, SPR_DBAT5U, "DBAT5U",
829 SPR_NOACCESS, SPR_NOACCESS,
830 &spr_read_dbat_h, &spr_write_dbatu_h,
831 0x00000000);
832 spr_register(env, SPR_DBAT5L, "DBAT5L",
833 SPR_NOACCESS, SPR_NOACCESS,
834 &spr_read_dbat_h, &spr_write_dbatl_h,
835 0x00000000);
836 spr_register(env, SPR_DBAT6U, "DBAT6U",
837 SPR_NOACCESS, SPR_NOACCESS,
838 &spr_read_dbat_h, &spr_write_dbatu_h,
839 0x00000000);
840 spr_register(env, SPR_DBAT6L, "DBAT6L",
841 SPR_NOACCESS, SPR_NOACCESS,
842 &spr_read_dbat_h, &spr_write_dbatl_h,
843 0x00000000);
844 spr_register(env, SPR_DBAT7U, "DBAT7U",
845 SPR_NOACCESS, SPR_NOACCESS,
846 &spr_read_dbat_h, &spr_write_dbatu_h,
847 0x00000000);
848 spr_register(env, SPR_DBAT7L, "DBAT7L",
849 SPR_NOACCESS, SPR_NOACCESS,
850 &spr_read_dbat_h, &spr_write_dbatl_h,
851 0x00000000);
852 env->nb_BATs += 4;
853 #endif
854 }
855
856 /* Generic PowerPC time base */
857 static void gen_tbl (CPUPPCState *env)
858 {
859 spr_register(env, SPR_VTBL, "TBL",
860 &spr_read_tbl, SPR_NOACCESS,
861 &spr_read_tbl, SPR_NOACCESS,
862 0x00000000);
863 spr_register(env, SPR_TBL, "TBL",
864 &spr_read_tbl, SPR_NOACCESS,
865 &spr_read_tbl, &spr_write_tbl,
866 0x00000000);
867 spr_register(env, SPR_VTBU, "TBU",
868 &spr_read_tbu, SPR_NOACCESS,
869 &spr_read_tbu, SPR_NOACCESS,
870 0x00000000);
871 spr_register(env, SPR_TBU, "TBU",
872 &spr_read_tbu, SPR_NOACCESS,
873 &spr_read_tbu, &spr_write_tbu,
874 0x00000000);
875 }
876
877 /* Softare table search registers */
878 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
879 {
880 #if !defined(CONFIG_USER_ONLY)
881 env->nb_tlb = nb_tlbs;
882 env->nb_ways = nb_ways;
883 env->id_tlbs = 1;
884 env->tlb_type = TLB_6XX;
885 spr_register(env, SPR_DMISS, "DMISS",
886 SPR_NOACCESS, SPR_NOACCESS,
887 &spr_read_generic, SPR_NOACCESS,
888 0x00000000);
889 spr_register(env, SPR_DCMP, "DCMP",
890 SPR_NOACCESS, SPR_NOACCESS,
891 &spr_read_generic, SPR_NOACCESS,
892 0x00000000);
893 spr_register(env, SPR_HASH1, "HASH1",
894 SPR_NOACCESS, SPR_NOACCESS,
895 &spr_read_generic, SPR_NOACCESS,
896 0x00000000);
897 spr_register(env, SPR_HASH2, "HASH2",
898 SPR_NOACCESS, SPR_NOACCESS,
899 &spr_read_generic, SPR_NOACCESS,
900 0x00000000);
901 spr_register(env, SPR_IMISS, "IMISS",
902 SPR_NOACCESS, SPR_NOACCESS,
903 &spr_read_generic, SPR_NOACCESS,
904 0x00000000);
905 spr_register(env, SPR_ICMP, "ICMP",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, SPR_NOACCESS,
908 0x00000000);
909 spr_register(env, SPR_RPA, "RPA",
910 SPR_NOACCESS, SPR_NOACCESS,
911 &spr_read_generic, &spr_write_generic,
912 0x00000000);
913 #endif
914 }
915
916 /* SPR common to MPC755 and G2 */
917 static void gen_spr_G2_755 (CPUPPCState *env)
918 {
919 /* SGPRs */
920 spr_register(env, SPR_SPRG4, "SPRG4",
921 SPR_NOACCESS, SPR_NOACCESS,
922 &spr_read_generic, &spr_write_generic,
923 0x00000000);
924 spr_register(env, SPR_SPRG5, "SPRG5",
925 SPR_NOACCESS, SPR_NOACCESS,
926 &spr_read_generic, &spr_write_generic,
927 0x00000000);
928 spr_register(env, SPR_SPRG6, "SPRG6",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, &spr_write_generic,
931 0x00000000);
932 spr_register(env, SPR_SPRG7, "SPRG7",
933 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_generic, &spr_write_generic,
935 0x00000000);
936 }
937
938 /* SPR common to all 7xx PowerPC implementations */
939 static void gen_spr_7xx (CPUPPCState *env)
940 {
941 /* Breakpoints */
942 /* XXX : not implemented */
943 spr_register_kvm(env, SPR_DABR, "DABR",
944 SPR_NOACCESS, SPR_NOACCESS,
945 &spr_read_generic, &spr_write_generic,
946 KVM_REG_PPC_DABR, 0x00000000);
947 /* XXX : not implemented */
948 spr_register(env, SPR_IABR, "IABR",
949 SPR_NOACCESS, SPR_NOACCESS,
950 &spr_read_generic, &spr_write_generic,
951 0x00000000);
952 /* Cache management */
953 /* XXX : not implemented */
954 spr_register(env, SPR_ICTC, "ICTC",
955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, &spr_write_generic,
957 0x00000000);
958 /* Performance monitors */
959 /* XXX : not implemented */
960 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, &spr_write_generic,
963 0x00000000);
964 /* XXX : not implemented */
965 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, &spr_write_generic,
968 0x00000000);
969 /* XXX : not implemented */
970 spr_register(env, SPR_7XX_PMC1, "PMC1",
971 SPR_NOACCESS, SPR_NOACCESS,
972 &spr_read_generic, &spr_write_generic,
973 0x00000000);
974 /* XXX : not implemented */
975 spr_register(env, SPR_7XX_PMC2, "PMC2",
976 SPR_NOACCESS, SPR_NOACCESS,
977 &spr_read_generic, &spr_write_generic,
978 0x00000000);
979 /* XXX : not implemented */
980 spr_register(env, SPR_7XX_PMC3, "PMC3",
981 SPR_NOACCESS, SPR_NOACCESS,
982 &spr_read_generic, &spr_write_generic,
983 0x00000000);
984 /* XXX : not implemented */
985 spr_register(env, SPR_7XX_PMC4, "PMC4",
986 SPR_NOACCESS, SPR_NOACCESS,
987 &spr_read_generic, &spr_write_generic,
988 0x00000000);
989 /* XXX : not implemented */
990 spr_register(env, SPR_7XX_SIAR, "SIAR",
991 SPR_NOACCESS, SPR_NOACCESS,
992 &spr_read_generic, SPR_NOACCESS,
993 0x00000000);
994 /* XXX : not implemented */
995 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
996 &spr_read_ureg, SPR_NOACCESS,
997 &spr_read_ureg, SPR_NOACCESS,
998 0x00000000);
999 /* XXX : not implemented */
1000 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1001 &spr_read_ureg, SPR_NOACCESS,
1002 &spr_read_ureg, SPR_NOACCESS,
1003 0x00000000);
1004 /* XXX : not implemented */
1005 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1006 &spr_read_ureg, SPR_NOACCESS,
1007 &spr_read_ureg, SPR_NOACCESS,
1008 0x00000000);
1009 /* XXX : not implemented */
1010 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1011 &spr_read_ureg, SPR_NOACCESS,
1012 &spr_read_ureg, SPR_NOACCESS,
1013 0x00000000);
1014 /* XXX : not implemented */
1015 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1016 &spr_read_ureg, SPR_NOACCESS,
1017 &spr_read_ureg, SPR_NOACCESS,
1018 0x00000000);
1019 /* XXX : not implemented */
1020 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1021 &spr_read_ureg, SPR_NOACCESS,
1022 &spr_read_ureg, SPR_NOACCESS,
1023 0x00000000);
1024 /* XXX : not implemented */
1025 spr_register(env, SPR_7XX_USIAR, "USIAR",
1026 &spr_read_ureg, SPR_NOACCESS,
1027 &spr_read_ureg, SPR_NOACCESS,
1028 0x00000000);
1029 /* External access control */
1030 /* XXX : not implemented */
1031 spr_register(env, SPR_EAR, "EAR",
1032 SPR_NOACCESS, SPR_NOACCESS,
1033 &spr_read_generic, &spr_write_generic,
1034 0x00000000);
1035 }
1036
1037 #ifdef TARGET_PPC64
1038 #ifndef CONFIG_USER_ONLY
1039 static void spr_read_uamr (DisasContext *ctx, int gprn, int sprn)
1040 {
1041 gen_load_spr(cpu_gpr[gprn], SPR_AMR);
1042 spr_load_dump_spr(SPR_AMR);
1043 }
1044
1045 static void spr_write_uamr (DisasContext *ctx, int sprn, int gprn)
1046 {
1047 gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
1048 spr_store_dump_spr(SPR_AMR);
1049 }
1050
1051 static void spr_write_uamr_pr (DisasContext *ctx, int sprn, int gprn)
1052 {
1053 TCGv t0 = tcg_temp_new();
1054
1055 gen_load_spr(t0, SPR_UAMOR);
1056 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1057 gen_store_spr(SPR_AMR, t0);
1058 spr_store_dump_spr(SPR_AMR);
1059 }
1060 #endif /* CONFIG_USER_ONLY */
1061
1062 static void gen_spr_amr (CPUPPCState *env)
1063 {
1064 #ifndef CONFIG_USER_ONLY
1065 /* Virtual Page Class Key protection */
1066 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1067 * userspace accessible, 29 is privileged. So we only need to set
1068 * the kvm ONE_REG id on one of them, we use 29 */
1069 spr_register(env, SPR_UAMR, "UAMR",
1070 &spr_read_uamr, &spr_write_uamr_pr,
1071 &spr_read_uamr, &spr_write_uamr,
1072 0);
1073 spr_register_kvm(env, SPR_AMR, "AMR",
1074 SPR_NOACCESS, SPR_NOACCESS,
1075 &spr_read_generic, &spr_write_generic,
1076 KVM_REG_PPC_AMR, 0);
1077 spr_register_kvm(env, SPR_UAMOR, "UAMOR",
1078 SPR_NOACCESS, SPR_NOACCESS,
1079 &spr_read_generic, &spr_write_generic,
1080 KVM_REG_PPC_UAMOR, 0);
1081 #endif /* !CONFIG_USER_ONLY */
1082 }
1083 #endif /* TARGET_PPC64 */
1084
1085 static void gen_spr_thrm (CPUPPCState *env)
1086 {
1087 /* Thermal management */
1088 /* XXX : not implemented */
1089 spr_register(env, SPR_THRM1, "THRM1",
1090 SPR_NOACCESS, SPR_NOACCESS,
1091 &spr_read_generic, &spr_write_generic,
1092 0x00000000);
1093 /* XXX : not implemented */
1094 spr_register(env, SPR_THRM2, "THRM2",
1095 SPR_NOACCESS, SPR_NOACCESS,
1096 &spr_read_generic, &spr_write_generic,
1097 0x00000000);
1098 /* XXX : not implemented */
1099 spr_register(env, SPR_THRM3, "THRM3",
1100 SPR_NOACCESS, SPR_NOACCESS,
1101 &spr_read_generic, &spr_write_generic,
1102 0x00000000);
1103 }
1104
1105 /* SPR specific to PowerPC 604 implementation */
1106 static void gen_spr_604 (CPUPPCState *env)
1107 {
1108 /* Processor identification */
1109 spr_register(env, SPR_PIR, "PIR",
1110 SPR_NOACCESS, SPR_NOACCESS,
1111 &spr_read_generic, &spr_write_pir,
1112 0x00000000);
1113 /* Breakpoints */
1114 /* XXX : not implemented */
1115 spr_register(env, SPR_IABR, "IABR",
1116 SPR_NOACCESS, SPR_NOACCESS,
1117 &spr_read_generic, &spr_write_generic,
1118 0x00000000);
1119 /* XXX : not implemented */
1120 spr_register_kvm(env, SPR_DABR, "DABR",
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_generic, &spr_write_generic,
1123 KVM_REG_PPC_DABR, 0x00000000);
1124 /* Performance counters */
1125 /* XXX : not implemented */
1126 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1127 SPR_NOACCESS, SPR_NOACCESS,
1128 &spr_read_generic, &spr_write_generic,
1129 0x00000000);
1130 /* XXX : not implemented */
1131 spr_register(env, SPR_7XX_PMC1, "PMC1",
1132 SPR_NOACCESS, SPR_NOACCESS,
1133 &spr_read_generic, &spr_write_generic,
1134 0x00000000);
1135 /* XXX : not implemented */
1136 spr_register(env, SPR_7XX_PMC2, "PMC2",
1137 SPR_NOACCESS, SPR_NOACCESS,
1138 &spr_read_generic, &spr_write_generic,
1139 0x00000000);
1140 /* XXX : not implemented */
1141 spr_register(env, SPR_7XX_SIAR, "SIAR",
1142 SPR_NOACCESS, SPR_NOACCESS,
1143 &spr_read_generic, SPR_NOACCESS,
1144 0x00000000);
1145 /* XXX : not implemented */
1146 spr_register(env, SPR_SDA, "SDA",
1147 SPR_NOACCESS, SPR_NOACCESS,
1148 &spr_read_generic, SPR_NOACCESS,
1149 0x00000000);
1150 /* External access control */
1151 /* XXX : not implemented */
1152 spr_register(env, SPR_EAR, "EAR",
1153 SPR_NOACCESS, SPR_NOACCESS,
1154 &spr_read_generic, &spr_write_generic,
1155 0x00000000);
1156 }
1157
1158 /* SPR specific to PowerPC 603 implementation */
1159 static void gen_spr_603 (CPUPPCState *env)
1160 {
1161 /* External access control */
1162 /* XXX : not implemented */
1163 spr_register(env, SPR_EAR, "EAR",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_generic, &spr_write_generic,
1166 0x00000000);
1167 /* Breakpoints */
1168 /* XXX : not implemented */
1169 spr_register(env, SPR_IABR, "IABR",
1170 SPR_NOACCESS, SPR_NOACCESS,
1171 &spr_read_generic, &spr_write_generic,
1172 0x00000000);
1173
1174 }
1175
1176 /* SPR specific to PowerPC G2 implementation */
1177 static void gen_spr_G2 (CPUPPCState *env)
1178 {
1179 /* Memory base address */
1180 /* MBAR */
1181 /* XXX : not implemented */
1182 spr_register(env, SPR_MBAR, "MBAR",
1183 SPR_NOACCESS, SPR_NOACCESS,
1184 &spr_read_generic, &spr_write_generic,
1185 0x00000000);
1186 /* Exception processing */
1187 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1188 SPR_NOACCESS, SPR_NOACCESS,
1189 &spr_read_generic, &spr_write_generic,
1190 0x00000000);
1191 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195 /* Breakpoints */
1196 /* XXX : not implemented */
1197 spr_register(env, SPR_DABR, "DABR",
1198 SPR_NOACCESS, SPR_NOACCESS,
1199 &spr_read_generic, &spr_write_generic,
1200 0x00000000);
1201 /* XXX : not implemented */
1202 spr_register(env, SPR_DABR2, "DABR2",
1203 SPR_NOACCESS, SPR_NOACCESS,
1204 &spr_read_generic, &spr_write_generic,
1205 0x00000000);
1206 /* XXX : not implemented */
1207 spr_register(env, SPR_IABR, "IABR",
1208 SPR_NOACCESS, SPR_NOACCESS,
1209 &spr_read_generic, &spr_write_generic,
1210 0x00000000);
1211 /* XXX : not implemented */
1212 spr_register(env, SPR_IABR2, "IABR2",
1213 SPR_NOACCESS, SPR_NOACCESS,
1214 &spr_read_generic, &spr_write_generic,
1215 0x00000000);
1216 /* XXX : not implemented */
1217 spr_register(env, SPR_IBCR, "IBCR",
1218 SPR_NOACCESS, SPR_NOACCESS,
1219 &spr_read_generic, &spr_write_generic,
1220 0x00000000);
1221 /* XXX : not implemented */
1222 spr_register(env, SPR_DBCR, "DBCR",
1223 SPR_NOACCESS, SPR_NOACCESS,
1224 &spr_read_generic, &spr_write_generic,
1225 0x00000000);
1226 }
1227
1228 /* SPR specific to PowerPC 602 implementation */
1229 static void gen_spr_602 (CPUPPCState *env)
1230 {
1231 /* ESA registers */
1232 /* XXX : not implemented */
1233 spr_register(env, SPR_SER, "SER",
1234 SPR_NOACCESS, SPR_NOACCESS,
1235 &spr_read_generic, &spr_write_generic,
1236 0x00000000);
1237 /* XXX : not implemented */
1238 spr_register(env, SPR_SEBR, "SEBR",
1239 SPR_NOACCESS, SPR_NOACCESS,
1240 &spr_read_generic, &spr_write_generic,
1241 0x00000000);
1242 /* XXX : not implemented */
1243 spr_register(env, SPR_ESASRR, "ESASRR",
1244 SPR_NOACCESS, SPR_NOACCESS,
1245 &spr_read_generic, &spr_write_generic,
1246 0x00000000);
1247 /* Floating point status */
1248 /* XXX : not implemented */
1249 spr_register(env, SPR_SP, "SP",
1250 SPR_NOACCESS, SPR_NOACCESS,
1251 &spr_read_generic, &spr_write_generic,
1252 0x00000000);
1253 /* XXX : not implemented */
1254 spr_register(env, SPR_LT, "LT",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_generic, &spr_write_generic,
1257 0x00000000);
1258 /* Watchdog timer */
1259 /* XXX : not implemented */
1260 spr_register(env, SPR_TCR, "TCR",
1261 SPR_NOACCESS, SPR_NOACCESS,
1262 &spr_read_generic, &spr_write_generic,
1263 0x00000000);
1264 /* Interrupt base */
1265 spr_register(env, SPR_IBR, "IBR",
1266 SPR_NOACCESS, SPR_NOACCESS,
1267 &spr_read_generic, &spr_write_generic,
1268 0x00000000);
1269 /* XXX : not implemented */
1270 spr_register(env, SPR_IABR, "IABR",
1271 SPR_NOACCESS, SPR_NOACCESS,
1272 &spr_read_generic, &spr_write_generic,
1273 0x00000000);
1274 }
1275
1276 /* SPR specific to PowerPC 601 implementation */
1277 static void gen_spr_601 (CPUPPCState *env)
1278 {
1279 /* Multiplication/division register */
1280 /* MQ */
1281 spr_register(env, SPR_MQ, "MQ",
1282 &spr_read_generic, &spr_write_generic,
1283 &spr_read_generic, &spr_write_generic,
1284 0x00000000);
1285 /* RTC registers */
1286 spr_register(env, SPR_601_RTCU, "RTCU",
1287 SPR_NOACCESS, SPR_NOACCESS,
1288 SPR_NOACCESS, &spr_write_601_rtcu,
1289 0x00000000);
1290 spr_register(env, SPR_601_VRTCU, "RTCU",
1291 &spr_read_601_rtcu, SPR_NOACCESS,
1292 &spr_read_601_rtcu, SPR_NOACCESS,
1293 0x00000000);
1294 spr_register(env, SPR_601_RTCL, "RTCL",
1295 SPR_NOACCESS, SPR_NOACCESS,
1296 SPR_NOACCESS, &spr_write_601_rtcl,
1297 0x00000000);
1298 spr_register(env, SPR_601_VRTCL, "RTCL",
1299 &spr_read_601_rtcl, SPR_NOACCESS,
1300 &spr_read_601_rtcl, SPR_NOACCESS,
1301 0x00000000);
1302 /* Timer */
1303 #if 0 /* ? */
1304 spr_register(env, SPR_601_UDECR, "UDECR",
1305 &spr_read_decr, SPR_NOACCESS,
1306 &spr_read_decr, SPR_NOACCESS,
1307 0x00000000);
1308 #endif
1309 /* External access control */
1310 /* XXX : not implemented */
1311 spr_register(env, SPR_EAR, "EAR",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_generic, &spr_write_generic,
1314 0x00000000);
1315 /* Memory management */
1316 #if !defined(CONFIG_USER_ONLY)
1317 spr_register(env, SPR_IBAT0U, "IBAT0U",
1318 SPR_NOACCESS, SPR_NOACCESS,
1319 &spr_read_601_ubat, &spr_write_601_ubatu,
1320 0x00000000);
1321 spr_register(env, SPR_IBAT0L, "IBAT0L",
1322 SPR_NOACCESS, SPR_NOACCESS,
1323 &spr_read_601_ubat, &spr_write_601_ubatl,
1324 0x00000000);
1325 spr_register(env, SPR_IBAT1U, "IBAT1U",
1326 SPR_NOACCESS, SPR_NOACCESS,
1327 &spr_read_601_ubat, &spr_write_601_ubatu,
1328 0x00000000);
1329 spr_register(env, SPR_IBAT1L, "IBAT1L",
1330 SPR_NOACCESS, SPR_NOACCESS,
1331 &spr_read_601_ubat, &spr_write_601_ubatl,
1332 0x00000000);
1333 spr_register(env, SPR_IBAT2U, "IBAT2U",
1334 SPR_NOACCESS, SPR_NOACCESS,
1335 &spr_read_601_ubat, &spr_write_601_ubatu,
1336 0x00000000);
1337 spr_register(env, SPR_IBAT2L, "IBAT2L",
1338 SPR_NOACCESS, SPR_NOACCESS,
1339 &spr_read_601_ubat, &spr_write_601_ubatl,
1340 0x00000000);
1341 spr_register(env, SPR_IBAT3U, "IBAT3U",
1342 SPR_NOACCESS, SPR_NOACCESS,
1343 &spr_read_601_ubat, &spr_write_601_ubatu,
1344 0x00000000);
1345 spr_register(env, SPR_IBAT3L, "IBAT3L",
1346 SPR_NOACCESS, SPR_NOACCESS,
1347 &spr_read_601_ubat, &spr_write_601_ubatl,
1348 0x00000000);
1349 env->nb_BATs = 4;
1350 #endif
1351 }
1352
1353 static void gen_spr_74xx (CPUPPCState *env)
1354 {
1355 /* Processor identification */
1356 spr_register(env, SPR_PIR, "PIR",
1357 SPR_NOACCESS, SPR_NOACCESS,
1358 &spr_read_generic, &spr_write_pir,
1359 0x00000000);
1360 /* XXX : not implemented */
1361 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1362 SPR_NOACCESS, SPR_NOACCESS,
1363 &spr_read_generic, &spr_write_generic,
1364 0x00000000);
1365 /* XXX : not implemented */
1366 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1367 &spr_read_ureg, SPR_NOACCESS,
1368 &spr_read_ureg, SPR_NOACCESS,
1369 0x00000000);
1370 /* XXX: not implemented */
1371 spr_register(env, SPR_BAMR, "BAMR",
1372 SPR_NOACCESS, SPR_NOACCESS,
1373 &spr_read_generic, &spr_write_generic,
1374 0x00000000);
1375 /* XXX : not implemented */
1376 spr_register(env, SPR_MSSCR0, "MSSCR0",
1377 SPR_NOACCESS, SPR_NOACCESS,
1378 &spr_read_generic, &spr_write_generic,
1379 0x00000000);
1380 /* Hardware implementation registers */
1381 /* XXX : not implemented */
1382 spr_register(env, SPR_HID0, "HID0",
1383 SPR_NOACCESS, SPR_NOACCESS,
1384 &spr_read_generic, &spr_write_generic,
1385 0x00000000);
1386 /* XXX : not implemented */
1387 spr_register(env, SPR_HID1, "HID1",
1388 SPR_NOACCESS, SPR_NOACCESS,
1389 &spr_read_generic, &spr_write_generic,
1390 0x00000000);
1391 /* Altivec */
1392 spr_register(env, SPR_VRSAVE, "VRSAVE",
1393 &spr_read_generic, &spr_write_generic,
1394 &spr_read_generic, &spr_write_generic,
1395 0x00000000);
1396 /* XXX : not implemented */
1397 spr_register(env, SPR_L2CR, "L2CR",
1398 SPR_NOACCESS, SPR_NOACCESS,
1399 &spr_read_generic, spr_access_nop,
1400 0x00000000);
1401 /* Not strictly an SPR */
1402 vscr_init(env, 0x00010000);
1403 }
1404
1405 static void gen_l3_ctrl (CPUPPCState *env)
1406 {
1407 /* L3CR */
1408 /* XXX : not implemented */
1409 spr_register(env, SPR_L3CR, "L3CR",
1410 SPR_NOACCESS, SPR_NOACCESS,
1411 &spr_read_generic, &spr_write_generic,
1412 0x00000000);
1413 /* L3ITCR0 */
1414 /* XXX : not implemented */
1415 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1416 SPR_NOACCESS, SPR_NOACCESS,
1417 &spr_read_generic, &spr_write_generic,
1418 0x00000000);
1419 /* L3PM */
1420 /* XXX : not implemented */
1421 spr_register(env, SPR_L3PM, "L3PM",
1422 SPR_NOACCESS, SPR_NOACCESS,
1423 &spr_read_generic, &spr_write_generic,
1424 0x00000000);
1425 }
1426
1427 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1428 {
1429 #if !defined(CONFIG_USER_ONLY)
1430 env->nb_tlb = nb_tlbs;
1431 env->nb_ways = nb_ways;
1432 env->id_tlbs = 1;
1433 env->tlb_type = TLB_6XX;
1434 /* XXX : not implemented */
1435 spr_register(env, SPR_PTEHI, "PTEHI",
1436 SPR_NOACCESS, SPR_NOACCESS,
1437 &spr_read_generic, &spr_write_generic,
1438 0x00000000);
1439 /* XXX : not implemented */
1440 spr_register(env, SPR_PTELO, "PTELO",
1441 SPR_NOACCESS, SPR_NOACCESS,
1442 &spr_read_generic, &spr_write_generic,
1443 0x00000000);
1444 /* XXX : not implemented */
1445 spr_register(env, SPR_TLBMISS, "TLBMISS",
1446 SPR_NOACCESS, SPR_NOACCESS,
1447 &spr_read_generic, &spr_write_generic,
1448 0x00000000);
1449 #endif
1450 }
1451
1452 #if !defined(CONFIG_USER_ONLY)
1453 static void spr_write_e500_l1csr0 (DisasContext *ctx, int sprn, int gprn)
1454 {
1455 TCGv t0 = tcg_temp_new();
1456
1457 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1458 gen_store_spr(sprn, t0);
1459 tcg_temp_free(t0);
1460 }
1461
1462 static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1463 {
1464 TCGv t0 = tcg_temp_new();
1465
1466 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1467 gen_store_spr(sprn, t0);
1468 tcg_temp_free(t0);
1469 }
1470
1471 static void spr_write_booke206_mmucsr0 (DisasContext *ctx, int sprn, int gprn)
1472 {
1473 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1474 }
1475
1476 static void spr_write_booke_pid (DisasContext *ctx, int sprn, int gprn)
1477 {
1478 TCGv_i32 t0 = tcg_const_i32(sprn);
1479 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1480 tcg_temp_free_i32(t0);
1481 }
1482 #endif
1483
1484 static void gen_spr_usprgh (CPUPPCState *env)
1485 {
1486 spr_register(env, SPR_USPRG4, "USPRG4",
1487 &spr_read_ureg, SPR_NOACCESS,
1488 &spr_read_ureg, SPR_NOACCESS,
1489 0x00000000);
1490 spr_register(env, SPR_USPRG5, "USPRG5",
1491 &spr_read_ureg, SPR_NOACCESS,
1492 &spr_read_ureg, SPR_NOACCESS,
1493 0x00000000);
1494 spr_register(env, SPR_USPRG6, "USPRG6",
1495 &spr_read_ureg, SPR_NOACCESS,
1496 &spr_read_ureg, SPR_NOACCESS,
1497 0x00000000);
1498 spr_register(env, SPR_USPRG7, "USPRG7",
1499 &spr_read_ureg, SPR_NOACCESS,
1500 &spr_read_ureg, SPR_NOACCESS,
1501 0x00000000);
1502 }
1503
1504 /* PowerPC BookE SPR */
1505 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1506 {
1507 const char *ivor_names[64] = {
1508 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1509 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1510 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1511 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1512 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1513 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1514 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1515 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1516 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1517 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1518 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1519 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1520 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1521 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1522 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1523 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1524 };
1525 #define SPR_BOOKE_IVORxx (-1)
1526 int ivor_sprn[64] = {
1527 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1528 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1529 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1530 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1531 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1532 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1533 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1534 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1535 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1536 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1537 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1538 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1539 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1540 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1541 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1542 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1543 };
1544 int i;
1545
1546 /* Interrupt processing */
1547 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1548 SPR_NOACCESS, SPR_NOACCESS,
1549 &spr_read_generic, &spr_write_generic,
1550 0x00000000);
1551 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1552 SPR_NOACCESS, SPR_NOACCESS,
1553 &spr_read_generic, &spr_write_generic,
1554 0x00000000);
1555 /* Debug */
1556 /* XXX : not implemented */
1557 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1558 SPR_NOACCESS, SPR_NOACCESS,
1559 &spr_read_generic, &spr_write_generic,
1560 0x00000000);
1561 /* XXX : not implemented */
1562 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1563 SPR_NOACCESS, SPR_NOACCESS,
1564 &spr_read_generic, &spr_write_generic,
1565 0x00000000);
1566 /* XXX : not implemented */
1567 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1568 SPR_NOACCESS, SPR_NOACCESS,
1569 &spr_read_generic, &spr_write_generic,
1570 0x00000000);
1571 /* XXX : not implemented */
1572 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1573 SPR_NOACCESS, SPR_NOACCESS,
1574 &spr_read_generic, &spr_write_generic,
1575 0x00000000);
1576 /* XXX : not implemented */
1577 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1578 SPR_NOACCESS, SPR_NOACCESS,
1579 &spr_read_generic, &spr_write_40x_dbcr0,
1580 0x00000000);
1581 /* XXX : not implemented */
1582 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1583 SPR_NOACCESS, SPR_NOACCESS,
1584 &spr_read_generic, &spr_write_generic,
1585 0x00000000);
1586 /* XXX : not implemented */
1587 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1588 SPR_NOACCESS, SPR_NOACCESS,
1589 &spr_read_generic, &spr_write_generic,
1590 0x00000000);
1591 /* XXX : not implemented */
1592 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1593 SPR_NOACCESS, SPR_NOACCESS,
1594 &spr_read_generic, &spr_write_clear,
1595 0x00000000);
1596 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1597 SPR_NOACCESS, SPR_NOACCESS,
1598 &spr_read_generic, &spr_write_generic,
1599 0x00000000);
1600 spr_register(env, SPR_BOOKE_ESR, "ESR",
1601 SPR_NOACCESS, SPR_NOACCESS,
1602 &spr_read_generic, &spr_write_generic,
1603 0x00000000);
1604 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1605 SPR_NOACCESS, SPR_NOACCESS,
1606 &spr_read_generic, &spr_write_excp_prefix,
1607 0x00000000);
1608 /* Exception vectors */
1609 for (i = 0; i < 64; i++) {
1610 if (ivor_mask & (1ULL << i)) {
1611 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1612 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1613 exit(1);
1614 }
1615 spr_register(env, ivor_sprn[i], ivor_names[i],
1616 SPR_NOACCESS, SPR_NOACCESS,
1617 &spr_read_generic, &spr_write_excp_vector,
1618 0x00000000);
1619 }
1620 }
1621 spr_register(env, SPR_BOOKE_PID, "PID",
1622 SPR_NOACCESS, SPR_NOACCESS,
1623 &spr_read_generic, &spr_write_booke_pid,
1624 0x00000000);
1625 spr_register(env, SPR_BOOKE_TCR, "TCR",
1626 SPR_NOACCESS, SPR_NOACCESS,
1627 &spr_read_generic, &spr_write_booke_tcr,
1628 0x00000000);
1629 spr_register(env, SPR_BOOKE_TSR, "TSR",
1630 SPR_NOACCESS, SPR_NOACCESS,
1631 &spr_read_generic, &spr_write_booke_tsr,
1632 0x00000000);
1633 /* Timer */
1634 spr_register(env, SPR_DECR, "DECR",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_decr, &spr_write_decr,
1637 0x00000000);
1638 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1639 SPR_NOACCESS, SPR_NOACCESS,
1640 SPR_NOACCESS, &spr_write_generic,
1641 0x00000000);
1642 /* SPRGs */
1643 spr_register(env, SPR_USPRG0, "USPRG0",
1644 &spr_read_generic, &spr_write_generic,
1645 &spr_read_generic, &spr_write_generic,
1646 0x00000000);
1647 spr_register(env, SPR_SPRG4, "SPRG4",
1648 SPR_NOACCESS, SPR_NOACCESS,
1649 &spr_read_generic, &spr_write_generic,
1650 0x00000000);
1651 spr_register(env, SPR_SPRG5, "SPRG5",
1652 SPR_NOACCESS, SPR_NOACCESS,
1653 &spr_read_generic, &spr_write_generic,
1654 0x00000000);
1655 spr_register(env, SPR_SPRG6, "SPRG6",
1656 SPR_NOACCESS, SPR_NOACCESS,
1657 &spr_read_generic, &spr_write_generic,
1658 0x00000000);
1659 spr_register(env, SPR_SPRG7, "SPRG7",
1660 SPR_NOACCESS, SPR_NOACCESS,
1661 &spr_read_generic, &spr_write_generic,
1662 0x00000000);
1663 }
1664
1665 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1666 uint32_t maxsize, uint32_t flags,
1667 uint32_t nentries)
1668 {
1669 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1670 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1671 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1672 flags | nentries;
1673 }
1674
1675 /* BookE 2.06 storage control registers */
1676 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1677 uint32_t *tlbncfg)
1678 {
1679 #if !defined(CONFIG_USER_ONLY)
1680 const char *mas_names[8] = {
1681 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1682 };
1683 int mas_sprn[8] = {
1684 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1685 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1686 };
1687 int i;
1688
1689 /* TLB assist registers */
1690 /* XXX : not implemented */
1691 for (i = 0; i < 8; i++) {
1692 void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = &spr_write_generic32;
1693 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1694 uea_write = &spr_write_generic;
1695 }
1696 if (mas_mask & (1 << i)) {
1697 spr_register(env, mas_sprn[i], mas_names[i],
1698 SPR_NOACCESS, SPR_NOACCESS,
1699 &spr_read_generic, uea_write,
1700 0x00000000);
1701 }
1702 }
1703 if (env->nb_pids > 1) {
1704 /* XXX : not implemented */
1705 spr_register(env, SPR_BOOKE_PID1, "PID1",
1706 SPR_NOACCESS, SPR_NOACCESS,
1707 &spr_read_generic, &spr_write_booke_pid,
1708 0x00000000);
1709 }
1710 if (env->nb_pids > 2) {
1711 /* XXX : not implemented */
1712 spr_register(env, SPR_BOOKE_PID2, "PID2",
1713 SPR_NOACCESS, SPR_NOACCESS,
1714 &spr_read_generic, &spr_write_booke_pid,
1715 0x00000000);
1716 }
1717 /* XXX : not implemented */
1718 spr_register(env, SPR_MMUCFG, "MMUCFG",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, SPR_NOACCESS,
1721 0x00000000); /* TOFIX */
1722 switch (env->nb_ways) {
1723 case 4:
1724 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1725 SPR_NOACCESS, SPR_NOACCESS,
1726 &spr_read_generic, SPR_NOACCESS,
1727 tlbncfg[3]);
1728 /* Fallthru */
1729 case 3:
1730 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1731 SPR_NOACCESS, SPR_NOACCESS,
1732 &spr_read_generic, SPR_NOACCESS,
1733 tlbncfg[2]);
1734 /* Fallthru */
1735 case 2:
1736 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1737 SPR_NOACCESS, SPR_NOACCESS,
1738 &spr_read_generic, SPR_NOACCESS,
1739 tlbncfg[1]);
1740 /* Fallthru */
1741 case 1:
1742 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1743 SPR_NOACCESS, SPR_NOACCESS,
1744 &spr_read_generic, SPR_NOACCESS,
1745 tlbncfg[0]);
1746 /* Fallthru */
1747 case 0:
1748 default:
1749 break;
1750 }
1751 #endif
1752
1753 gen_spr_usprgh(env);
1754 }
1755
1756 /* SPR specific to PowerPC 440 implementation */
1757 static void gen_spr_440 (CPUPPCState *env)
1758 {
1759 /* Cache control */
1760 /* XXX : not implemented */
1761 spr_register(env, SPR_440_DNV0, "DNV0",
1762 SPR_NOACCESS, SPR_NOACCESS,
1763 &spr_read_generic, &spr_write_generic,
1764 0x00000000);
1765 /* XXX : not implemented */
1766 spr_register(env, SPR_440_DNV1, "DNV1",
1767 SPR_NOACCESS, SPR_NOACCESS,
1768 &spr_read_generic, &spr_write_generic,
1769 0x00000000);
1770 /* XXX : not implemented */
1771 spr_register(env, SPR_440_DNV2, "DNV2",
1772 SPR_NOACCESS, SPR_NOACCESS,
1773 &spr_read_generic, &spr_write_generic,
1774 0x00000000);
1775 /* XXX : not implemented */
1776 spr_register(env, SPR_440_DNV3, "DNV3",
1777 SPR_NOACCESS, SPR_NOACCESS,
1778 &spr_read_generic, &spr_write_generic,
1779 0x00000000);
1780 /* XXX : not implemented */
1781 spr_register(env, SPR_440_DTV0, "DTV0",
1782 SPR_NOACCESS, SPR_NOACCESS,
1783 &spr_read_generic, &spr_write_generic,
1784 0x00000000);
1785 /* XXX : not implemented */
1786 spr_register(env, SPR_440_DTV1, "DTV1",
1787 SPR_NOACCESS, SPR_NOACCESS,
1788 &spr_read_generic, &spr_write_generic,
1789 0x00000000);
1790 /* XXX : not implemented */
1791 spr_register(env, SPR_440_DTV2, "DTV2",
1792 SPR_NOACCESS, SPR_NOACCESS,
1793 &spr_read_generic, &spr_write_generic,
1794 0x00000000);
1795 /* XXX : not implemented */
1796 spr_register(env, SPR_440_DTV3, "DTV3",
1797 SPR_NOACCESS, SPR_NOACCESS,
1798 &spr_read_generic, &spr_write_generic,
1799 0x00000000);
1800 /* XXX : not implemented */
1801 spr_register(env, SPR_440_DVLIM, "DVLIM",
1802 SPR_NOACCESS, SPR_NOACCESS,
1803 &spr_read_generic, &spr_write_generic,
1804 0x00000000);
1805 /* XXX : not implemented */
1806 spr_register(env, SPR_440_INV0, "INV0",
1807 SPR_NOACCESS, SPR_NOACCESS,
1808 &spr_read_generic, &spr_write_generic,
1809 0x00000000);
1810 /* XXX : not implemented */
1811 spr_register(env, SPR_440_INV1, "INV1",
1812 SPR_NOACCESS, SPR_NOACCESS,
1813 &spr_read_generic, &spr_write_generic,
1814 0x00000000);
1815 /* XXX : not implemented */
1816 spr_register(env, SPR_440_INV2, "INV2",
1817 SPR_NOACCESS, SPR_NOACCESS,
1818 &spr_read_generic, &spr_write_generic,
1819 0x00000000);
1820 /* XXX : not implemented */
1821 spr_register(env, SPR_440_INV3, "INV3",
1822 SPR_NOACCESS, SPR_NOACCESS,
1823 &spr_read_generic, &spr_write_generic,
1824 0x00000000);
1825 /* XXX : not implemented */
1826 spr_register(env, SPR_440_ITV0, "ITV0",
1827 SPR_NOACCESS, SPR_NOACCESS,
1828 &spr_read_generic, &spr_write_generic,
1829 0x00000000);
1830 /* XXX : not implemented */
1831 spr_register(env, SPR_440_ITV1, "ITV1",
1832 SPR_NOACCESS, SPR_NOACCESS,
1833 &spr_read_generic, &spr_write_generic,
1834 0x00000000);
1835 /* XXX : not implemented */
1836 spr_register(env, SPR_440_ITV2, "ITV2",
1837 SPR_NOACCESS, SPR_NOACCESS,
1838 &spr_read_generic, &spr_write_generic,
1839 0x00000000);
1840 /* XXX : not implemented */
1841 spr_register(env, SPR_440_ITV3, "ITV3",
1842 SPR_NOACCESS, SPR_NOACCESS,
1843 &spr_read_generic, &spr_write_generic,
1844 0x00000000);
1845 /* XXX : not implemented */
1846 spr_register(env, SPR_440_IVLIM, "IVLIM",
1847 SPR_NOACCESS, SPR_NOACCESS,
1848 &spr_read_generic, &spr_write_generic,
1849 0x00000000);
1850 /* Cache debug */
1851 /* XXX : not implemented */
1852 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1853 SPR_NOACCESS, SPR_NOACCESS,
1854 &spr_read_generic, SPR_NOACCESS,
1855 0x00000000);
1856 /* XXX : not implemented */
1857 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1858 SPR_NOACCESS, SPR_NOACCESS,
1859 &spr_read_generic, SPR_NOACCESS,
1860 0x00000000);
1861 /* XXX : not implemented */
1862 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1863 SPR_NOACCESS, SPR_NOACCESS,
1864 &spr_read_generic, SPR_NOACCESS,
1865 0x00000000);
1866 /* XXX : not implemented */
1867 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1868 SPR_NOACCESS, SPR_NOACCESS,
1869 &spr_read_generic, SPR_NOACCESS,
1870 0x00000000);
1871 /* XXX : not implemented */
1872 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1873 SPR_NOACCESS, SPR_NOACCESS,
1874 &spr_read_generic, SPR_NOACCESS,
1875 0x00000000);
1876 /* XXX : not implemented */
1877 spr_register(env, SPR_440_DBDR, "DBDR",
1878 SPR_NOACCESS, SPR_NOACCESS,
1879 &spr_read_generic, &spr_write_generic,
1880 0x00000000);
1881 /* Processor control */
1882 spr_register(env, SPR_4xx_CCR0, "CCR0",
1883 SPR_NOACCESS, SPR_NOACCESS,
1884 &spr_read_generic, &spr_write_generic,
1885 0x00000000);
1886 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1887 SPR_NOACCESS, SPR_NOACCESS,
1888 &spr_read_generic, SPR_NOACCESS,
1889 0x00000000);
1890 /* Storage control */
1891 spr_register(env, SPR_440_MMUCR, "MMUCR",
1892 SPR_NOACCESS, SPR_NOACCESS,
1893 &spr_read_generic, &spr_write_generic,
1894 0x00000000);
1895 }
1896
1897 /* SPR shared between PowerPC 40x implementations */
1898 static void gen_spr_40x (CPUPPCState *env)
1899 {
1900 /* Cache */
1901 /* not emulated, as QEMU do not emulate caches */
1902 spr_register(env, SPR_40x_DCCR, "DCCR",
1903 SPR_NOACCESS, SPR_NOACCESS,
1904 &spr_read_generic, &spr_write_generic,
1905 0x00000000);
1906 /* not emulated, as QEMU do not emulate caches */
1907 spr_register(env, SPR_40x_ICCR, "ICCR",
1908 SPR_NOACCESS, SPR_NOACCESS,
1909 &spr_read_generic, &spr_write_generic,
1910 0x00000000);
1911 /* not emulated, as QEMU do not emulate caches */
1912 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1913 SPR_NOACCESS, SPR_NOACCESS,
1914 &spr_read_generic, SPR_NOACCESS,
1915 0x00000000);
1916 /* Exception */
1917 spr_register(env, SPR_40x_DEAR, "DEAR",
1918 SPR_NOACCESS, SPR_NOACCESS,
1919 &spr_read_generic, &spr_write_generic,
1920 0x00000000);
1921 spr_register(env, SPR_40x_ESR, "ESR",
1922 SPR_NOACCESS, SPR_NOACCESS,
1923 &spr_read_generic, &spr_write_generic,
1924 0x00000000);
1925 spr_register(env, SPR_40x_EVPR, "EVPR",
1926 SPR_NOACCESS, SPR_NOACCESS,
1927 &spr_read_generic, &spr_write_excp_prefix,
1928 0x00000000);
1929 spr_register(env, SPR_40x_SRR2, "SRR2",
1930 &spr_read_generic, &spr_write_generic,
1931 &spr_read_generic, &spr_write_generic,
1932 0x00000000);
1933 spr_register(env, SPR_40x_SRR3, "SRR3",
1934 &spr_read_generic, &spr_write_generic,
1935 &spr_read_generic, &spr_write_generic,
1936 0x00000000);
1937 /* Timers */
1938 spr_register(env, SPR_40x_PIT, "PIT",
1939 SPR_NOACCESS, SPR_NOACCESS,
1940 &spr_read_40x_pit, &spr_write_40x_pit,
1941 0x00000000);
1942 spr_register(env, SPR_40x_TCR, "TCR",
1943 SPR_NOACCESS, SPR_NOACCESS,
1944 &spr_read_generic, &spr_write_booke_tcr,
1945 0x00000000);
1946 spr_register(env, SPR_40x_TSR, "TSR",
1947 SPR_NOACCESS, SPR_NOACCESS,
1948 &spr_read_generic, &spr_write_booke_tsr,
1949 0x00000000);
1950 }
1951
1952 /* SPR specific to PowerPC 405 implementation */
1953 static void gen_spr_405 (CPUPPCState *env)
1954 {
1955 /* MMU */
1956 spr_register(env, SPR_40x_PID, "PID",
1957 SPR_NOACCESS, SPR_NOACCESS,
1958 &spr_read_generic, &spr_write_generic,
1959 0x00000000);
1960 spr_register(env, SPR_4xx_CCR0, "CCR0",
1961 SPR_NOACCESS, SPR_NOACCESS,
1962 &spr_read_generic, &spr_write_generic,
1963 0x00700000);
1964 /* Debug interface */
1965 /* XXX : not implemented */
1966 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1967 SPR_NOACCESS, SPR_NOACCESS,
1968 &spr_read_generic, &spr_write_40x_dbcr0,
1969 0x00000000);
1970 /* XXX : not implemented */
1971 spr_register(env, SPR_405_DBCR1, "DBCR1",
1972 SPR_NOACCESS, SPR_NOACCESS,
1973 &spr_read_generic, &spr_write_generic,
1974 0x00000000);
1975 /* XXX : not implemented */
1976 spr_register(env, SPR_40x_DBSR, "DBSR",
1977 SPR_NOACCESS, SPR_NOACCESS,
1978 &spr_read_generic, &spr_write_clear,
1979 /* Last reset was system reset */
1980 0x00000300);
1981 /* XXX : not implemented */
1982 spr_register(env, SPR_40x_DAC1, "DAC1",
1983 SPR_NOACCESS, SPR_NOACCESS,
1984 &spr_read_generic, &spr_write_generic,
1985 0x00000000);
1986 spr_register(env, SPR_40x_DAC2, "DAC2",
1987 SPR_NOACCESS, SPR_NOACCESS,
1988 &spr_read_generic, &spr_write_generic,
1989 0x00000000);
1990 /* XXX : not implemented */
1991 spr_register(env, SPR_405_DVC1, "DVC1",
1992 SPR_NOACCESS, SPR_NOACCESS,
1993 &spr_read_generic, &spr_write_generic,
1994 0x00000000);
1995 /* XXX : not implemented */
1996 spr_register(env, SPR_405_DVC2, "DVC2",
1997 SPR_NOACCESS, SPR_NOACCESS,
1998 &spr_read_generic, &spr_write_generic,
1999 0x00000000);
2000 /* XXX : not implemented */
2001 spr_register(env, SPR_40x_IAC1, "IAC1",
2002 SPR_NOACCESS, SPR_NOACCESS,
2003 &spr_read_generic, &spr_write_generic,
2004 0x00000000);
2005 spr_register(env, SPR_40x_IAC2, "IAC2",
2006 SPR_NOACCESS, SPR_NOACCESS,
2007 &spr_read_generic, &spr_write_generic,
2008 0x00000000);
2009 /* XXX : not implemented */
2010 spr_register(env, SPR_405_IAC3, "IAC3",
2011 SPR_NOACCESS, SPR_NOACCESS,
2012 &spr_read_generic, &spr_write_generic,
2013 0x00000000);
2014 /* XXX : not implemented */
2015 spr_register(env, SPR_405_IAC4, "IAC4",
2016 SPR_NOACCESS, SPR_NOACCESS,
2017 &spr_read_generic, &spr_write_generic,
2018 0x00000000);
2019 /* Storage control */
2020 /* XXX: TODO: not implemented */
2021 spr_register(env, SPR_405_SLER, "SLER",
2022 SPR_NOACCESS, SPR_NOACCESS,
2023 &spr_read_generic, &spr_write_40x_sler,
2024 0x00000000);
2025 spr_register(env, SPR_40x_ZPR, "ZPR",
2026 SPR_NOACCESS, SPR_NOACCESS,
2027 &spr_read_generic, &spr_write_generic,
2028 0x00000000);
2029 /* XXX : not implemented */
2030 spr_register(env, SPR_405_SU0R, "SU0R",
2031 SPR_NOACCESS, SPR_NOACCESS,
2032 &spr_read_generic, &spr_write_generic,
2033 0x00000000);
2034 /* SPRG */
2035 spr_register(env, SPR_USPRG0, "USPRG0",
2036 &spr_read_ureg, SPR_NOACCESS,
2037 &spr_read_ureg, SPR_NOACCESS,
2038 0x00000000);
2039 spr_register(env, SPR_SPRG4, "SPRG4",
2040 SPR_NOACCESS, SPR_NOACCESS,
2041 &spr_read_generic, &spr_write_generic,
2042 0x00000000);
2043 spr_register(env, SPR_SPRG5, "SPRG5",
2044 SPR_NOACCESS, SPR_NOACCESS,
2045 spr_read_generic, &spr_write_generic,
2046 0x00000000);
2047 spr_register(env, SPR_SPRG6, "SPRG6",
2048 SPR_NOACCESS, SPR_NOACCESS,
2049 spr_read_generic, &spr_write_generic,
2050 0x00000000);
2051 spr_register(env, SPR_SPRG7, "SPRG7",
2052 SPR_NOACCESS, SPR_NOACCESS,
2053 spr_read_generic, &spr_write_generic,
2054 0x00000000);
2055 gen_spr_usprgh(env);
2056 }
2057
2058 /* SPR shared between PowerPC 401 & 403 implementations */
2059 static void gen_spr_401_403 (CPUPPCState *env)
2060 {
2061 /* Time base */
2062 spr_register(env, SPR_403_VTBL, "TBL",
2063 &spr_read_tbl, SPR_NOACCESS,
2064 &spr_read_tbl, SPR_NOACCESS,
2065 0x00000000);
2066 spr_register(env, SPR_403_TBL, "TBL",
2067 SPR_NOACCESS, SPR_NOACCESS,
2068 SPR_NOACCESS, &spr_write_tbl,
2069 0x00000000);
2070 spr_register(env, SPR_403_VTBU, "TBU",
2071 &spr_read_tbu, SPR_NOACCESS,
2072 &spr_read_tbu, SPR_NOACCESS,
2073 0x00000000);
2074 spr_register(env, SPR_403_TBU, "TBU",
2075 SPR_NOACCESS, SPR_NOACCESS,
2076 SPR_NOACCESS, &spr_write_tbu,
2077 0x00000000);
2078 /* Debug */
2079 /* not emulated, as QEMU do not emulate caches */
2080 spr_register(env, SPR_403_CDBCR, "CDBCR",
2081 SPR_NOACCESS, SPR_NOACCESS,
2082 &spr_read_generic, &spr_write_generic,
2083 0x00000000);
2084 }
2085
2086 /* SPR specific to PowerPC 401 implementation */
2087 static void gen_spr_401 (CPUPPCState *env)
2088 {
2089 /* Debug interface */
2090 /* XXX : not implemented */
2091 spr_register(env, SPR_40x_DBCR0, "DBCR",
2092 SPR_NOACCESS, SPR_NOACCESS,
2093 &spr_read_generic, &spr_write_40x_dbcr0,
2094 0x00000000);
2095 /* XXX : not implemented */
2096 spr_register(env, SPR_40x_DBSR, "DBSR",
2097 SPR_NOACCESS, SPR_NOACCESS,
2098 &spr_read_generic, &spr_write_clear,
2099 /* Last reset was system reset */
2100 0x00000300);
2101 /* XXX : not implemented */
2102 spr_register(env, SPR_40x_DAC1, "DAC",
2103 SPR_NOACCESS, SPR_NOACCESS,
2104 &spr_read_generic, &spr_write_generic,
2105 0x00000000);
2106 /* XXX : not implemented */
2107 spr_register(env, SPR_40x_IAC1, "IAC",
2108 SPR_NOACCESS, SPR_NOACCESS,
2109 &spr_read_generic, &spr_write_generic,
2110 0x00000000);
2111 /* Storage control */
2112 /* XXX: TODO: not implemented */
2113 spr_register(env, SPR_405_SLER, "SLER",
2114 SPR_NOACCESS, SPR_NOACCESS,
2115 &spr_read_generic, &spr_write_40x_sler,
2116 0x00000000);
2117 /* not emulated, as QEMU never does speculative access */
2118 spr_register(env, SPR_40x_SGR, "SGR",
2119 SPR_NOACCESS, SPR_NOACCESS,
2120 &spr_read_generic, &spr_write_generic,
2121 0xFFFFFFFF);
2122 /* not emulated, as QEMU do not emulate caches */
2123 spr_register(env, SPR_40x_DCWR, "DCWR",
2124 SPR_NOACCESS, SPR_NOACCESS,
2125 &spr_read_generic, &spr_write_generic,
2126 0x00000000);
2127 }
2128
2129 static void gen_spr_401x2 (CPUPPCState *env)
2130 {
2131 gen_spr_401(env);
2132 spr_register(env, SPR_40x_PID, "PID",
2133 SPR_NOACCESS, SPR_NOACCESS,
2134 &spr_read_generic, &spr_write_generic,
2135 0x00000000);
2136 spr_register(env, SPR_40x_ZPR, "ZPR",
2137 SPR_NOACCESS, SPR_NOACCESS,
2138 &spr_read_generic, &spr_write_generic,
2139 0x00000000);
2140 }
2141
2142 /* SPR specific to PowerPC 403 implementation */
2143 static void gen_spr_403 (CPUPPCState *env)
2144 {
2145 /* Debug interface */
2146 /* XXX : not implemented */
2147 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2148 SPR_NOACCESS, SPR_NOACCESS,
2149 &spr_read_generic, &spr_write_40x_dbcr0,
2150 0x00000000);
2151 /* XXX : not implemented */
2152 spr_register(env, SPR_40x_DBSR, "DBSR",
2153 SPR_NOACCESS, SPR_NOACCESS,
2154 &spr_read_generic, &spr_write_clear,
2155 /* Last reset was system reset */
2156 0x00000300);
2157 /* XXX : not implemented */
2158 spr_register(env, SPR_40x_DAC1, "DAC1",
2159 SPR_NOACCESS, SPR_NOACCESS,
2160 &spr_read_generic, &spr_write_generic,
2161 0x00000000);
2162 /* XXX : not implemented */
2163 spr_register(env, SPR_40x_DAC2, "DAC2",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 &spr_read_generic, &spr_write_generic,
2166 0x00000000);
2167 /* XXX : not implemented */
2168 spr_register(env, SPR_40x_IAC1, "IAC1",
2169 SPR_NOACCESS, SPR_NOACCESS,
2170 &spr_read_generic, &spr_write_generic,
2171 0x00000000);
2172 /* XXX : not implemented */
2173 spr_register(env, SPR_40x_IAC2, "IAC2",
2174 SPR_NOACCESS, SPR_NOACCESS,
2175 &spr_read_generic, &spr_write_generic,
2176 0x00000000);
2177 }
2178
2179 static void gen_spr_403_real (CPUPPCState *env)
2180 {
2181 spr_register(env, SPR_403_PBL1, "PBL1",
2182 SPR_NOACCESS, SPR_NOACCESS,
2183 &spr_read_403_pbr, &spr_write_403_pbr,
2184 0x00000000);
2185 spr_register(env, SPR_403_PBU1, "PBU1",
2186 SPR_NOACCESS, SPR_NOACCESS,
2187 &spr_read_403_pbr, &spr_write_403_pbr,
2188 0x00000000);
2189 spr_register(env, SPR_403_PBL2, "PBL2",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_403_pbr, &spr_write_403_pbr,
2192 0x00000000);
2193 spr_register(env, SPR_403_PBU2, "PBU2",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_403_pbr, &spr_write_403_pbr,
2196 0x00000000);
2197 }
2198
2199 static void gen_spr_403_mmu (CPUPPCState *env)
2200 {
2201 /* MMU */
2202 spr_register(env, SPR_40x_PID, "PID",
2203 SPR_NOACCESS, SPR_NOACCESS,
2204 &spr_read_generic, &spr_write_generic,
2205 0x00000000);
2206 spr_register(env, SPR_40x_ZPR, "ZPR",
2207 SPR_NOACCESS, SPR_NOACCESS,
2208 &spr_read_generic, &spr_write_generic,
2209 0x00000000);
2210 }
2211
2212 /* SPR specific to PowerPC compression coprocessor extension */
2213 static void gen_spr_compress (CPUPPCState *env)
2214 {
2215 /* XXX : not implemented */
2216 spr_register(env, SPR_401_SKR, "SKR",
2217 SPR_NOACCESS, SPR_NOACCESS,
2218 &spr_read_generic, &spr_write_generic,
2219 0x00000000);
2220 }
2221
2222 static void gen_spr_5xx_8xx (CPUPPCState *env)
2223 {
2224 /* Exception processing */
2225 spr_register_kvm(env, SPR_DSISR, "DSISR",
2226 SPR_NOACCESS, SPR_NOACCESS,
2227 &spr_read_generic, &spr_write_generic,
2228 KVM_REG_PPC_DSISR, 0x00000000);
2229 spr_register_kvm(env, SPR_DAR, "DAR",
2230 SPR_NOACCESS, SPR_NOACCESS,
2231 &spr_read_generic, &spr_write_generic,
2232 KVM_REG_PPC_DAR, 0x00000000);
2233 /* Timer */
2234 spr_register(env, SPR_DECR, "DECR",
2235 SPR_NOACCESS, SPR_NOACCESS,
2236 &spr_read_decr, &spr_write_decr,
2237 0x00000000);
2238 /* XXX : not implemented */
2239 spr_register(env, SPR_MPC_EIE, "EIE",
2240 SPR_NOACCESS, SPR_NOACCESS,
2241 &spr_read_generic, &spr_write_generic,
2242 0x00000000);
2243 /* XXX : not implemented */
2244 spr_register(env, SPR_MPC_EID, "EID",
2245 SPR_NOACCESS, SPR_NOACCESS,
2246 &spr_read_generic, &spr_write_generic,
2247 0x00000000);
2248 /* XXX : not implemented */
2249 spr_register(env, SPR_MPC_NRI, "NRI",
2250 SPR_NOACCESS, SPR_NOACCESS,
2251 &spr_read_generic, &spr_write_generic,
2252 0x00000000);
2253 /* XXX : not implemented */
2254 spr_register(env, SPR_MPC_CMPA, "CMPA",
2255 SPR_NOACCESS, SPR_NOACCESS,
2256 &spr_read_generic, &spr_write_generic,
2257 0x00000000);
2258 /* XXX : not implemented */
2259 spr_register(env, SPR_MPC_CMPB, "CMPB",
2260 SPR_NOACCESS, SPR_NOACCESS,
2261 &spr_read_generic, &spr_write_generic,
2262 0x00000000);
2263 /* XXX : not implemented */
2264 spr_register(env, SPR_MPC_CMPC, "CMPC",
2265 SPR_NOACCESS, SPR_NOACCESS,
2266 &spr_read_generic, &spr_write_generic,
2267 0x00000000);
2268 /* XXX : not implemented */
2269 spr_register(env, SPR_MPC_CMPD, "CMPD",
2270 SPR_NOACCESS, SPR_NOACCESS,
2271 &spr_read_generic, &spr_write_generic,
2272 0x00000000);
2273 /* XXX : not implemented */
2274 spr_register(env, SPR_MPC_ECR, "ECR",
2275 SPR_NOACCESS, SPR_NOACCESS,
2276 &spr_read_generic, &spr_write_generic,
2277 0x00000000);
2278 /* XXX : not implemented */
2279 spr_register(env, SPR_MPC_DER, "DER",
2280 SPR_NOACCESS, SPR_NOACCESS,
2281 &spr_read_generic, &spr_write_generic,
2282 0x00000000);
2283 /* XXX : not implemented */
2284 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2285 SPR_NOACCESS, SPR_NOACCESS,
2286 &spr_read_generic, &spr_write_generic,
2287 0x00000000);
2288 /* XXX : not implemented */
2289 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2290 SPR_NOACCESS, SPR_NOACCESS,
2291 &spr_read_generic, &spr_write_generic,
2292 0x00000000);
2293 /* XXX : not implemented */
2294 spr_register(env, SPR_MPC_CMPE, "CMPE",
2295 SPR_NOACCESS, SPR_NOACCESS,
2296 &spr_read_generic, &spr_write_generic,
2297 0x00000000);
2298 /* XXX : not implemented */
2299 spr_register(env, SPR_MPC_CMPF, "CMPF",
2300 SPR_NOACCESS, SPR_NOACCESS,
2301 &spr_read_generic, &spr_write_generic,
2302 0x00000000);
2303 /* XXX : not implemented */
2304 spr_register(env, SPR_MPC_CMPG, "CMPG",
2305 SPR_NOACCESS, SPR_NOACCESS,
2306 &spr_read_generic, &spr_write_generic,
2307 0x00000000);
2308 /* XXX : not implemented */
2309 spr_register(env, SPR_MPC_CMPH, "CMPH",
2310 SPR_NOACCESS, SPR_NOACCESS,
2311 &spr_read_generic, &spr_write_generic,
2312 0x00000000);
2313 /* XXX : not implemented */
2314 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2315 SPR_NOACCESS, SPR_NOACCESS,
2316 &spr_read_generic, &spr_write_generic,
2317 0x00000000);
2318 /* XXX : not implemented */
2319 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2320 SPR_NOACCESS, SPR_NOACCESS,
2321 &spr_read_generic, &spr_write_generic,
2322 0x00000000);
2323 /* XXX : not implemented */
2324 spr_register(env, SPR_MPC_BAR, "BAR",
2325 SPR_NOACCESS, SPR_NOACCESS,
2326 &spr_read_generic, &spr_write_generic,
2327 0x00000000);
2328 /* XXX : not implemented */
2329 spr_register(env, SPR_MPC_DPDR, "DPDR",
2330 SPR_NOACCESS, SPR_NOACCESS,
2331 &spr_read_generic, &spr_write_generic,
2332 0x00000000);
2333 /* XXX : not implemented */
2334 spr_register(env, SPR_MPC_IMMR, "IMMR",
2335 SPR_NOACCESS, SPR_NOACCESS,
2336 &spr_read_generic, &spr_write_generic,
2337 0x00000000);
2338 }
2339
2340 static void gen_spr_5xx (CPUPPCState *env)
2341 {
2342 /* XXX : not implemented */
2343 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2344 SPR_NOACCESS, SPR_NOACCESS,
2345 &spr_read_generic, &spr_write_generic,
2346 0x00000000);
2347 /* XXX : not implemented */
2348 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2349 SPR_NOACCESS, SPR_NOACCESS,
2350 &spr_read_generic, &spr_write_generic,
2351 0x00000000);
2352 /* XXX : not implemented */
2353 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2354 SPR_NOACCESS, SPR_NOACCESS,
2355 &spr_read_generic, &spr_write_generic,
2356 0x00000000);
2357 /* XXX : not implemented */
2358 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2359 SPR_NOACCESS, SPR_NOACCESS,
2360 &spr_read_generic, &spr_write_generic,
2361 0x00000000);
2362 /* XXX : not implemented */
2363 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2364 SPR_NOACCESS, SPR_NOACCESS,
2365 &spr_read_generic, &spr_write_generic,
2366 0x00000000);
2367 /* XXX : not implemented */
2368 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2369 SPR_NOACCESS, SPR_NOACCESS,
2370 &spr_read_generic, &spr_write_generic,
2371 0x00000000);
2372 /* XXX : not implemented */
2373 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2374 SPR_NOACCESS, SPR_NOACCESS,
2375 &spr_read_generic, &spr_write_generic,
2376 0x00000000);
2377 /* XXX : not implemented */
2378 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2379 SPR_NOACCESS, SPR_NOACCESS,
2380 &spr_read_generic, &spr_write_generic,
2381 0x00000000);
2382 /* XXX : not implemented */
2383 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2384 SPR_NOACCESS, SPR_NOACCESS,
2385 &spr_read_generic, &spr_write_generic,
2386 0x00000000);
2387 /* XXX : not implemented */
2388 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2389 SPR_NOACCESS, SPR_NOACCESS,
2390 &spr_read_generic, &spr_write_generic,
2391 0x00000000);
2392 /* XXX : not implemented */
2393 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2394 SPR_NOACCESS, SPR_NOACCESS,
2395 &spr_read_generic, &spr_write_generic,
2396 0x00000000);
2397 /* XXX : not implemented */
2398 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2399 SPR_NOACCESS, SPR_NOACCESS,
2400 &spr_read_generic, &spr_write_generic,
2401 0x00000000);
2402 /* XXX : not implemented */
2403 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2404 SPR_NOACCESS, SPR_NOACCESS,
2405 &spr_read_generic, &spr_write_generic,
2406 0x00000000);
2407 /* XXX : not implemented */
2408 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2409 SPR_NOACCESS, SPR_NOACCESS,
2410 &spr_read_generic, &spr_write_generic,
2411 0x00000000);
2412 /* XXX : not implemented */
2413 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2414 SPR_NOACCESS, SPR_NOACCESS,
2415 &spr_read_generic, &spr_write_generic,
2416 0x00000000);
2417 /* XXX : not implemented */
2418 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2419 SPR_NOACCESS, SPR_NOACCESS,
2420 &spr_read_generic, &spr_write_generic,
2421 0x00000000);
2422 /* XXX : not implemented */
2423 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2424 SPR_NOACCESS, SPR_NOACCESS,
2425 &spr_read_generic, &spr_write_generic,
2426 0x00000000);
2427 /* XXX : not implemented */
2428 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2429 SPR_NOACCESS, SPR_NOACCESS,
2430 &spr_read_generic, &spr_write_generic,
2431 0x00000000);
2432 /* XXX : not implemented */
2433 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2434 SPR_NOACCESS, SPR_NOACCESS,
2435 &spr_read_generic, &spr_write_generic,
2436 0x00000000);
2437 /* XXX : not implemented */
2438 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2439 SPR_NOACCESS, SPR_NOACCESS,
2440 &spr_read_generic, &spr_write_generic,
2441 0x00000000);
2442 /* XXX : not implemented */
2443 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2444 SPR_NOACCESS, SPR_NOACCESS,
2445 &spr_read_generic, &spr_write_generic,
2446 0x00000000);
2447 }
2448
2449 static void gen_spr_8xx (CPUPPCState *env)
2450 {
2451 /* XXX : not implemented */
2452 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2453 SPR_NOACCESS, SPR_NOACCESS,
2454 &spr_read_generic, &spr_write_generic,
2455 0x00000000);
2456 /* XXX : not implemented */
2457 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2458 SPR_NOACCESS, SPR_NOACCESS,
2459 &spr_read_generic, &spr_write_generic,
2460 0x00000000);
2461 /* XXX : not implemented */
2462 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2463 SPR_NOACCESS, SPR_NOACCESS,
2464 &spr_read_generic, &spr_write_generic,
2465 0x00000000);
2466 /* XXX : not implemented */
2467 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2468 SPR_NOACCESS, SPR_NOACCESS,
2469 &spr_read_generic, &spr_write_generic,
2470 0x00000000);
2471 /* XXX : not implemented */
2472 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2473 SPR_NOACCESS, SPR_NOACCESS,
2474 &spr_read_generic, &spr_write_generic,
2475 0x00000000);
2476 /* XXX : not implemented */
2477 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2478 SPR_NOACCESS, SPR_NOACCESS,
2479 &spr_read_generic, &spr_write_generic,
2480 0x00000000);
2481 /* XXX : not implemented */
2482 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2483 SPR_NOACCESS, SPR_NOACCESS,
2484 &spr_read_generic, &spr_write_generic,
2485 0x00000000);
2486 /* XXX : not implemented */
2487 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2488 SPR_NOACCESS, SPR_NOACCESS,
2489 &spr_read_generic, &spr_write_generic,
2490 0x00000000);
2491 /* XXX : not implemented */
2492 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2493 SPR_NOACCESS, SPR_NOACCESS,
2494 &spr_read_generic, &spr_write_generic,
2495 0x00000000);
2496 /* XXX : not implemented */
2497 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2498 SPR_NOACCESS, SPR_NOACCESS,
2499 &spr_read_generic, &spr_write_generic,
2500 0x00000000);
2501 /* XXX : not implemented */
2502 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2503 SPR_NOACCESS, SPR_NOACCESS,
2504 &spr_read_generic, &spr_write_generic,
2505 0x00000000);
2506 /* XXX : not implemented */
2507 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2508 SPR_NOACCESS, SPR_NOACCESS,
2509 &spr_read_generic, &spr_write_generic,
2510 0x00000000);
2511 /* XXX : not implemented */
2512 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2513 SPR_NOACCESS, SPR_NOACCESS,
2514 &spr_read_generic, &spr_write_generic,
2515 0x00000000);
2516 /* XXX : not implemented */
2517 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2518 SPR_NOACCESS, SPR_NOACCESS,
2519 &spr_read_generic, &spr_write_generic,
2520 0x00000000);
2521 /* XXX : not implemented */
2522 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2523 SPR_NOACCESS, SPR_NOACCESS,
2524 &spr_read_generic, &spr_write_generic,
2525 0x00000000);
2526 /* XXX : not implemented */
2527 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2528 SPR_NOACCESS, SPR_NOACCESS,
2529 &spr_read_generic, &spr_write_generic,
2530 0x00000000);
2531 /* XXX : not implemented */
2532 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2533 SPR_NOACCESS, SPR_NOACCESS,
2534 &spr_read_generic, &spr_write_generic,
2535 0x00000000);
2536 /* XXX : not implemented */
2537 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2538 SPR_NOACCESS, SPR_NOACCESS,
2539 &spr_read_generic, &spr_write_generic,
2540 0x00000000);
2541 /* XXX : not implemented */
2542 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2543 SPR_NOACCESS, SPR_NOACCESS,
2544 &spr_read_generic, &spr_write_generic,
2545 0x00000000);
2546 /* XXX : not implemented */
2547 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2548 SPR_NOACCESS, SPR_NOACCESS,
2549 &spr_read_generic, &spr_write_generic,
2550 0x00000000);
2551 /* XXX : not implemented */
2552 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2553 SPR_NOACCESS, SPR_NOACCESS,
2554 &spr_read_generic, &spr_write_generic,
2555 0x00000000);
2556 /* XXX : not implemented */
2557 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2558 SPR_NOACCESS, SPR_NOACCESS,
2559 &spr_read_generic, &spr_write_generic,
2560 0x00000000);
2561 /* XXX : not implemented */
2562 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2563 SPR_NOACCESS, SPR_NOACCESS,
2564 &spr_read_generic, &spr_write_generic,
2565 0x00000000);
2566 /* XXX : not implemented */
2567 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2568 SPR_NOACCESS, SPR_NOACCESS,
2569 &spr_read_generic, &spr_write_generic,
2570 0x00000000);
2571 /* XXX : not implemented */
2572 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2573 SPR_NOACCESS, SPR_NOACCESS,
2574 &spr_read_generic, &spr_write_generic,
2575 0x00000000);
2576 }
2577
2578 // XXX: TODO
2579 /*
2580 * AMR => SPR 29 (Power 2.04)
2581 * CTRL => SPR 136 (Power 2.04)
2582 * CTRL => SPR 152 (Power 2.04)
2583 * SCOMC => SPR 276 (64 bits ?)
2584 * SCOMD => SPR 277 (64 bits ?)
2585 * TBU40 => SPR 286 (Power 2.04 hypv)
2586 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2587 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2588 * HDSISR => SPR 306 (Power 2.04 hypv)
2589 * HDAR => SPR 307 (Power 2.04 hypv)
2590 * PURR => SPR 309 (Power 2.04 hypv)
2591 * HDEC => SPR 310 (Power 2.04 hypv)
2592 * HIOR => SPR 311 (hypv)
2593 * RMOR => SPR 312 (970)
2594 * HRMOR => SPR 313 (Power 2.04 hypv)
2595 * HSRR0 => SPR 314 (Power 2.04 hypv)
2596 * HSRR1 => SPR 315 (Power 2.04 hypv)
2597 * LPIDR => SPR 317 (970)
2598 * EPR => SPR 702 (Power 2.04 emb)
2599 * perf => 768-783 (Power 2.04)
2600 * perf => 784-799 (Power 2.04)
2601 * PPR => SPR 896 (Power 2.04)
2602 * EPLC => SPR 947 (Power 2.04 emb)
2603 * EPSC => SPR 948 (Power 2.04 emb)
2604 * DABRX => 1015 (Power 2.04 hypv)
2605 * FPECR => SPR 1022 (?)
2606 * ... and more (thermal management, performance counters, ...)
2607 */
2608
2609 /*****************************************************************************/
2610 /* Exception vectors models */
2611 static void init_excp_4xx_real (CPUPPCState *env)
2612 {
2613 #if !defined(CONFIG_USER_ONLY)
2614 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2615 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2616 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2617 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2618 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2619 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2620 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2621 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2622 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2623 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2624 env->ivor_mask = 0x0000FFF0UL;
2625 env->ivpr_mask = 0xFFFF0000UL;
2626 /* Hardware reset vector */
2627 env->hreset_vector = 0xFFFFFFFCUL;
2628 #endif
2629 }
2630
2631 static void init_excp_4xx_softmmu (CPUPPCState *env)
2632 {
2633 #if !defined(CONFIG_USER_ONLY)
2634 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2635 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2636 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2637 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2638 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2639 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2640 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2641 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2642 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2643 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2644 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2645 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2646 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2647 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2648 env->ivor_mask = 0x0000FFF0UL;
2649 env->ivpr_mask = 0xFFFF0000UL;
2650 /* Hardware reset vector */
2651 env->hreset_vector = 0xFFFFFFFCUL;
2652 #endif
2653 }
2654
2655 static void init_excp_MPC5xx (CPUPPCState *env)
2656 {
2657 #if !defined(CONFIG_USER_ONLY)
2658 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2659 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2660 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2661 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2662 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2663 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2664 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2665 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2666 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2667 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2668 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2669 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2670 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2671 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2672 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2673 env->ivor_mask = 0x0000FFF0UL;
2674 env->ivpr_mask = 0xFFFF0000UL;
2675 /* Hardware reset vector */
2676 env->hreset_vector = 0x00000100UL;
2677 #endif
2678 }
2679
2680 static void init_excp_MPC8xx (CPUPPCState *env)
2681 {
2682 #if !defined(CONFIG_USER_ONLY)
2683 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2684 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2685 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2686 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2687 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2688 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2689 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2690 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2691 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2692 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2693 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2694 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2695 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2696 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2697 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2698 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2699 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2700 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2701 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2702 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2703 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2704 env->ivor_mask = 0x0000FFF0UL;
2705 env->ivpr_mask = 0xFFFF0000UL;
2706 /* Hardware reset vector */
2707 env->hreset_vector = 0x00000100UL;
2708 #endif
2709 }
2710
2711 static void init_excp_G2 (CPUPPCState *env)
2712 {
2713 #if !defined(CONFIG_USER_ONLY)
2714 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2715 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2716 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2717 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2718 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2719 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2720 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2721 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2722 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2723 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2724 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2725 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2726 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2727 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2728 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2729 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2730 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2731 /* Hardware reset vector */
2732 env->hreset_vector = 0x00000100UL;
2733 #endif
2734 }
2735
2736 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2737 {
2738 #if !defined(CONFIG_USER_ONLY)
2739 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2740 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2741 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2742 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2743 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2744 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2745 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2746 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2747 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2748 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2749 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2750 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2751 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2752 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2753 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2754 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2755 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2756 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2757 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2758 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2759 env->ivor_mask = 0x0000FFF7UL;
2760 env->ivpr_mask = ivpr_mask;
2761 /* Hardware reset vector */
2762 env->hreset_vector = 0xFFFFFFFCUL;
2763 #endif
2764 }
2765
2766 static void init_excp_BookE (CPUPPCState *env)
2767 {
2768 #if !defined(CONFIG_USER_ONLY)
2769 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2770 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2771 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2772 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2773 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2774 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2775 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2776 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2777 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2778 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2779 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2780 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2781 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2782 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2783 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2784 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2785 env->ivor_mask = 0x0000FFF0UL;
2786 env->ivpr_mask = 0xFFFF0000UL;
2787 /* Hardware reset vector */
2788 env->hreset_vector = 0xFFFFFFFCUL;
2789 #endif
2790 }
2791
2792 static void init_excp_601 (CPUPPCState *env)
2793 {
2794 #if !defined(CONFIG_USER_ONLY)
2795 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2796 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2797 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2798 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2799 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2800 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2801 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2802 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2803 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2804 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2805 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2806 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2807 /* Hardware reset vector */
2808 env->hreset_vector = 0x00000100UL;
2809 #endif
2810 }
2811
2812 static void init_excp_602 (CPUPPCState *env)
2813 {
2814 #if !defined(CONFIG_USER_ONLY)
2815 /* XXX: exception prefix has a special behavior on 602 */
2816 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2817 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2818 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2819 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2820 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2821 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2822 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2823 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2824 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2825 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2826 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2827 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2828 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2829 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2830 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2831 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2832 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2833 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2834 /* Hardware reset vector */
2835 env->hreset_vector = 0x00000100UL;
2836 #endif
2837 }
2838
2839 static void init_excp_603 (CPUPPCState *env)
2840 {
2841 #if !defined(CONFIG_USER_ONLY)
2842 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2843 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2844 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2845 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2846 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2847 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2848 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2849 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2850 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2851 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2852 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2853 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2854 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2855 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2856 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2857 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2858 /* Hardware reset vector */
2859 env->hreset_vector = 0x00000100UL;
2860 #endif
2861 }
2862
2863 static void init_excp_604 (CPUPPCState *env)
2864 {
2865 #if !defined(CONFIG_USER_ONLY)
2866 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2867 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2868 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2869 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2870 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2871 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2872 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2873 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2874 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2875 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2876 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2877 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2878 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2879 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2880 /* Hardware reset vector */
2881 env->hreset_vector = 0x00000100UL;
2882 #endif
2883 }
2884
2885 static void init_excp_7x0 (CPUPPCState *env)
2886 {
2887 #if !defined(CONFIG_USER_ONLY)
2888 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2889 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2890 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2891 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2892 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2893 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2894 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2895 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2896 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2897 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2898 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2899 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2900 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2901 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2902 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2903 /* Hardware reset vector */
2904 env->hreset_vector = 0x00000100UL;
2905 #endif
2906 }
2907
2908 static void init_excp_750cl (CPUPPCState *env)
2909 {
2910 #if !defined(CONFIG_USER_ONLY)
2911 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2912 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2913 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2914 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2915 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2916 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2917 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2918 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2919 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2920 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2921 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2922 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2923 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2924 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2925 /* Hardware reset vector */
2926 env->hreset_vector = 0x00000100UL;
2927 #endif
2928 }
2929
2930 static void init_excp_750cx (CPUPPCState *env)
2931 {
2932 #if !defined(CONFIG_USER_ONLY)
2933 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2934 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2935 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2936 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2937 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2938 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2939 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2940 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2941 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2942 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2943 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2944 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2945 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2946 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2947 /* Hardware reset vector */
2948 env->hreset_vector = 0x00000100UL;
2949 #endif
2950 }
2951
2952 /* XXX: Check if this is correct */
2953 static void init_excp_7x5 (CPUPPCState *env)
2954 {
2955 #if !defined(CONFIG_USER_ONLY)
2956 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2957 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2958 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2959 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2960 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2961 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2962 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2963 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2964 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2965 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2966 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2967 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2968 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2969 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2970 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2971 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2972 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2973 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2974 /* Hardware reset vector */
2975 env->hreset_vector = 0x00000100UL;
2976 #endif
2977 }
2978
2979 static void init_excp_7400 (CPUPPCState *env)
2980 {
2981 #if !defined(CONFIG_USER_ONLY)
2982 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2983 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2984 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2985 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2986 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2987 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2988 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2989 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2990 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2991 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2992 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2993 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2994 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2995 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2996 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2997 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2998 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2999 /* Hardware reset vector */
3000 env->hreset_vector = 0x00000100UL;
3001 #endif
3002 }
3003
3004 static void init_excp_7450 (CPUPPCState *env)
3005 {
3006 #if !defined(CONFIG_USER_ONLY)
3007 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3008 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3009 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3010 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3011 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3012 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3013 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3014 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3015 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3016 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3017 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3018 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3019 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3020 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3021 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3022 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3023 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3024 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3025 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3026 /* Hardware reset vector */
3027 env->hreset_vector = 0x00000100UL;
3028 #endif
3029 }
3030
3031 #if defined (TARGET_PPC64)
3032 static void init_excp_970 (CPUPPCState *env)
3033 {
3034 #if !defined(CONFIG_USER_ONLY)
3035 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3036 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3037 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3038 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3039 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3040 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3041 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3042 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3043 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3044 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3045 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3046 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3047 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3048 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3049 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3050 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3051 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3052 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3053 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3054 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3055 /* Hardware reset vector */
3056 env->hreset_vector = 0x0000000000000100ULL;
3057 #endif
3058 }
3059
3060 static void init_excp_POWER7 (CPUPPCState *env)
3061 {
3062 #if !defined(CONFIG_USER_ONLY)
3063 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3064 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3065 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3066 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3067 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3068 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3069 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3070 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3071 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3072 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3073 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3074 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3075 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3076 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3077 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3078 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3079 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
3080 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
3081 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3082 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3083 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3084 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3085 /* Hardware reset vector */
3086 env->hreset_vector = 0x0000000000000100ULL;
3087 #endif
3088 }
3089 #endif
3090
3091 /*****************************************************************************/
3092 /* Power management enable checks */
3093 static int check_pow_none (CPUPPCState *env)
3094 {
3095 return 0;
3096 }
3097
3098 static int check_pow_nocheck (CPUPPCState *env)
3099 {
3100 return 1;
3101 }
3102
3103 static int check_pow_hid0 (CPUPPCState *env)
3104 {
3105 if (env->spr[SPR_HID0] & 0x00E00000)
3106 return 1;
3107
3108 return 0;
3109 }
3110
3111 static int check_pow_hid0_74xx (CPUPPCState *env)
3112 {
3113 if (env->spr[SPR_HID0] & 0x00600000)
3114 return 1;
3115
3116 return 0;
3117 }
3118
3119 static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
3120 {
3121 return true;
3122 }
3123
3124 #ifdef TARGET_PPC64
3125 static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
3126 {
3127 return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
3128 }
3129 #endif
3130
3131 /*****************************************************************************/
3132 /* PowerPC implementations definitions */
3133
3134 #define POWERPC_FAMILY(_name) \
3135 static void \
3136 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3137 \
3138 static const TypeInfo \
3139 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3140 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3141 .parent = TYPE_POWERPC_CPU, \
3142 .abstract = true, \
3143 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3144 }; \
3145 \
3146 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3147 { \
3148 type_register_static( \
3149 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3150 } \
3151 \
3152 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3153 \
3154 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3155
3156 static void init_proc_401 (CPUPPCState *env)
3157 {
3158 gen_spr_40x(env);
3159 gen_spr_401_403(env);
3160 gen_spr_401(env);
3161 init_excp_4xx_real(env);
3162 env->dcache_line_size = 32;
3163 env->icache_line_size = 32;
3164 /* Allocate hardware IRQ controller */
3165 ppc40x_irq_init(env);
3166
3167 SET_FIT_PERIOD(12, 16, 20, 24);
3168 SET_WDT_PERIOD(16, 20, 24, 28);
3169 }
3170
3171 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3172 {
3173 DeviceClass *dc = DEVICE_CLASS(oc);
3174 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3175
3176 dc->desc = "PowerPC 401";
3177 pcc->init_proc = init_proc_401;
3178 pcc->check_pow = check_pow_nocheck;
3179 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3180 PPC_WRTEE | PPC_DCR |
3181 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3182 PPC_CACHE_DCBZ |
3183 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3184 PPC_4xx_COMMON | PPC_40x_EXCP;
3185 pcc->msr_mask = (1ull << MSR_KEY) |
3186 (1ull << MSR_POW) |
3187 (1ull << MSR_CE) |
3188 (1ull << MSR_ILE) |
3189 (1ull << MSR_EE) |
3190 (1ull << MSR_PR) |
3191 (1ull << MSR_ME) |
3192 (1ull << MSR_DE) |
3193 (1ull << MSR_LE);
3194 pcc->mmu_model = POWERPC_MMU_REAL;
3195 pcc->excp_model = POWERPC_EXCP_40x;
3196 pcc->bus_model = PPC_FLAGS_INPUT_401;
3197 pcc->bfd_mach = bfd_mach_ppc_403;
3198 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3199 POWERPC_FLAG_BUS_CLK;
3200 }
3201
3202 static void init_proc_401x2 (CPUPPCState *env)
3203 {
3204 gen_spr_40x(env);
3205 gen_spr_401_403(env);
3206 gen_spr_401x2(env);
3207 gen_spr_compress(env);
3208 /* Memory management */
3209 #if !defined(CONFIG_USER_ONLY)
3210 env->nb_tlb = 64;
3211 env->nb_ways = 1;
3212 env->id_tlbs = 0;
3213 env->tlb_type = TLB_EMB;
3214 #endif
3215 init_excp_4xx_softmmu(env);
3216 env->dcache_line_size = 32;
3217 env->icache_line_size = 32;
3218 /* Allocate hardware IRQ controller */
3219 ppc40x_irq_init(env);
3220
3221 SET_FIT_PERIOD(12, 16, 20, 24);
3222 SET_WDT_PERIOD(16, 20, 24, 28);
3223 }
3224
3225 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3226 {
3227 DeviceClass *dc = DEVICE_CLASS(oc);
3228 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3229
3230 dc->desc = "PowerPC 401x2";
3231 pcc->init_proc = init_proc_401x2;
3232 pcc->check_pow = check_pow_nocheck;
3233 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3234 PPC_DCR | PPC_WRTEE |
3235 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3236 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3237 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3238 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3239 PPC_4xx_COMMON | PPC_40x_EXCP;
3240 pcc->msr_mask = (1ull << 20) |
3241 (1ull << MSR_KEY) |
3242 (1ull << MSR_POW) |
3243 (1ull << MSR_CE) |
3244 (1ull << MSR_ILE) |
3245 (1ull << MSR_EE) |
3246 (1ull << MSR_PR) |
3247 (1ull << MSR_ME) |
3248 (1ull << MSR_DE) |
3249 (1ull << MSR_IR) |
3250 (1ull << MSR_DR) |
3251 (1ull << MSR_LE);
3252 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3253 pcc->excp_model = POWERPC_EXCP_40x;
3254 pcc->bus_model = PPC_FLAGS_INPUT_401;
3255 pcc->bfd_mach = bfd_mach_ppc_403;
3256 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3257 POWERPC_FLAG_BUS_CLK;
3258 }
3259
3260 static void init_proc_401x3 (CPUPPCState *env)
3261 {
3262 gen_spr_40x(env);
3263 gen_spr_401_403(env);
3264 gen_spr_401(env);
3265 gen_spr_401x2(env);
3266 gen_spr_compress(env);
3267 init_excp_4xx_softmmu(env);
3268 env->dcache_line_size = 32;
3269 env->icache_line_size = 32;
3270 /* Allocate hardware IRQ controller */
3271 ppc40x_irq_init(env);
3272
3273 SET_FIT_PERIOD(12, 16, 20, 24);
3274 SET_WDT_PERIOD(16, 20, 24, 28);
3275 }
3276
3277 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3278 {
3279 DeviceClass *dc = DEVICE_CLASS(oc);
3280 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3281
3282 dc->desc = "PowerPC 401x3";
3283 pcc->init_proc = init_proc_401x3;
3284 pcc->check_pow = check_pow_nocheck;
3285 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3286 PPC_DCR | PPC_WRTEE |
3287 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3288 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3289 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3290 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3291 PPC_4xx_COMMON | PPC_40x_EXCP;
3292 pcc->msr_mask = (1ull << 20) |
3293 (1ull << MSR_KEY) |
3294 (1ull << MSR_POW) |
3295 (1ull << MSR_CE) |
3296 (1ull << MSR_ILE) |
3297 (1ull << MSR_EE) |
3298 (1ull << MSR_PR) |
3299 (1ull << MSR_ME) |
3300 (1ull << MSR_DWE) |
3301 (1ull << MSR_DE) |
3302 (1ull << MSR_IR) |
3303 (1ull << MSR_DR) |
3304 (1ull << MSR_LE);
3305 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3306 pcc->excp_model = POWERPC_EXCP_40x;
3307 pcc->bus_model = PPC_FLAGS_INPUT_401;
3308 pcc->bfd_mach = bfd_mach_ppc_403;
3309 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3310 POWERPC_FLAG_BUS_CLK;
3311 }
3312
3313 static void init_proc_IOP480 (CPUPPCState *env)
3314 {
3315 gen_spr_40x(env);
3316 gen_spr_401_403(env);
3317 gen_spr_401x2(env);
3318 gen_spr_compress(env);
3319 /* Memory management */
3320 #if !defined(CONFIG_USER_ONLY)
3321 env->nb_tlb = 64;
3322 env->nb_ways = 1;
3323 env->id_tlbs = 0;
3324 env->tlb_type = TLB_EMB;
3325 #endif
3326 init_excp_4xx_softmmu(env);
3327 env->dcache_line_size = 32;
3328 env->icache_line_size = 32;
3329 /* Allocate hardware IRQ controller */
3330 ppc40x_irq_init(env);
3331
3332 SET_FIT_PERIOD(8, 12, 16, 20);
3333 SET_WDT_PERIOD(16, 20, 24, 28);
3334 }
3335
3336 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3337 {
3338 DeviceClass *dc = DEVICE_CLASS(oc);
3339 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3340
3341 dc->desc = "IOP480";
3342 pcc->init_proc = init_proc_IOP480;
3343 pcc->check_pow = check_pow_nocheck;
3344 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3345 PPC_DCR | PPC_WRTEE |
3346 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3347 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3348 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3349 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3350 PPC_4xx_COMMON | PPC_40x_EXCP;
3351 pcc->msr_mask = (1ull << 20) |
3352 (1ull << MSR_KEY) |
3353 (1ull << MSR_POW) |
3354 (1ull << MSR_CE) |
3355 (1ull << MSR_ILE) |
3356 (1ull << MSR_EE) |
3357 (1ull << MSR_PR) |
3358 (1ull << MSR_ME) |
3359 (1ull << MSR_DE) |
3360 (1ull << MSR_IR) |
3361 (1ull << MSR_DR) |
3362 (1ull << MSR_LE);
3363 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3364 pcc->excp_model = POWERPC_EXCP_40x;
3365 pcc->bus_model = PPC_FLAGS_INPUT_401;
3366 pcc->bfd_mach = bfd_mach_ppc_403;
3367 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3368 POWERPC_FLAG_BUS_CLK;
3369 }
3370
3371 static void init_proc_403 (CPUPPCState *env)
3372 {
3373 gen_spr_40x(env);
3374 gen_spr_401_403(env);
3375 gen_spr_403(env);
3376 gen_spr_403_real(env);
3377 init_excp_4xx_real(env);
3378 env->dcache_line_size = 32;
3379 env->icache_line_size = 32;
3380 /* Allocate hardware IRQ controller */
3381 ppc40x_irq_init(env);
3382
3383 SET_FIT_PERIOD(8, 12, 16, 20);
3384 SET_WDT_PERIOD(16, 20, 24, 28);
3385 }
3386
3387 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3388 {
3389 DeviceClass *dc = DEVICE_CLASS(oc);
3390 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3391
3392 dc->desc = "PowerPC 403";
3393 pcc->init_proc = init_proc_403;
3394 pcc->check_pow = check_pow_nocheck;
3395 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3396 PPC_DCR | PPC_WRTEE |
3397 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3398 PPC_CACHE_DCBZ |
3399 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3400 PPC_4xx_COMMON | PPC_40x_EXCP;
3401 pcc->msr_mask = (1ull << MSR_POW) |
3402 (1ull << MSR_CE) |
3403 (1ull << MSR_ILE) |
3404 (1ull << MSR_EE) |
3405 (1ull << MSR_PR) |
3406 (1ull << MSR_ME) |
3407 (1ull << MSR_PE) |
3408 (1ull << MSR_PX) |
3409 (1ull << MSR_LE);
3410 pcc->mmu_model = POWERPC_MMU_REAL;
3411 pcc->excp_model = POWERPC_EXCP_40x;
3412 pcc->bus_model = PPC_FLAGS_INPUT_401;
3413 pcc->bfd_mach = bfd_mach_ppc_403;
3414 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3415 POWERPC_FLAG_BUS_CLK;
3416 }
3417
3418 static void init_proc_403GCX (CPUPPCState *env)
3419 {
3420 gen_spr_40x(env);
3421 gen_spr_401_403(env);
3422 gen_spr_403(env);
3423 gen_spr_403_real(env);
3424 gen_spr_403_mmu(env);
3425 /* Bus access control */
3426 /* not emulated, as QEMU never does speculative access */
3427 spr_register(env, SPR_40x_SGR, "SGR",
3428 SPR_NOACCESS, SPR_NOACCESS,
3429 &spr_read_generic, &spr_write_generic,
3430 0xFFFFFFFF);
3431 /* not emulated, as QEMU do not emulate caches */
3432 spr_register(env, SPR_40x_DCWR, "DCWR",
3433 SPR_NOACCESS, SPR_NOACCESS,
3434 &spr_read_generic, &spr_write_generic,
3435 0x00000000);
3436 /* Memory management */
3437 #if !defined(CONFIG_USER_ONLY)
3438 env->nb_tlb = 64;
3439 env->nb_ways = 1;
3440 env->id_tlbs = 0;
3441 env->tlb_type = TLB_EMB;
3442 #endif
3443 init_excp_4xx_softmmu(env);
3444 env->dcache_line_size = 32;
3445 env->icache_line_size = 32;
3446 /* Allocate hardware IRQ controller */
3447 ppc40x_irq_init(env);
3448
3449 SET_FIT_PERIOD(8, 12, 16, 20);
3450 SET_WDT_PERIOD(16, 20, 24, 28);
3451 }
3452
3453 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3454 {
3455 DeviceClass *dc = DEVICE_CLASS(oc);
3456 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3457
3458 dc->desc = "PowerPC 403 GCX";
3459 pcc->init_proc = init_proc_403GCX;
3460 pcc->check_pow = check_pow_nocheck;
3461 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3462 PPC_DCR | PPC_WRTEE |
3463 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3464 PPC_CACHE_DCBZ |
3465 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3466 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3467 PPC_4xx_COMMON | PPC_40x_EXCP;
3468 pcc->msr_mask = (1ull << MSR_POW) |
3469 (1ull << MSR_CE) |
3470 (1ull << MSR_ILE) |
3471 (1ull << MSR_EE) |
3472 (1ull << MSR_PR) |
3473 (1ull << MSR_ME) |
3474 (1ull << MSR_PE) |
3475 (1ull << MSR_PX) |
3476 (1ull << MSR_LE);
3477 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3478 pcc->excp_model = POWERPC_EXCP_40x;
3479 pcc->bus_model = PPC_FLAGS_INPUT_401;
3480 pcc->bfd_mach = bfd_mach_ppc_403;
3481 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3482 POWERPC_FLAG_BUS_CLK;
3483 }
3484
3485 static void init_proc_405 (CPUPPCState *env)
3486 {
3487 /* Time base */
3488 gen_tbl(env);
3489 gen_spr_40x(env);
3490 gen_spr_405(env);
3491 /* Bus access control */
3492 /* not emulated, as QEMU never does speculative access */
3493 spr_register(env, SPR_40x_SGR, "SGR",
3494 SPR_NOACCESS, SPR_NOACCESS,
3495 &spr_read_generic, &spr_write_generic,
3496 0xFFFFFFFF);
3497 /* not emulated, as QEMU do not emulate caches */
3498 spr_register(env, SPR_40x_DCWR, "DCWR",
3499 SPR_NOACCESS, SPR_NOACCESS,
3500 &spr_read_generic, &spr_write_generic,
3501 0x00000000);
3502 /* Memory management */
3503 #if !defined(CONFIG_USER_ONLY)
3504 env->nb_tlb = 64;
3505 env->nb_ways = 1;
3506 env->id_tlbs = 0;
3507 env->tlb_type = TLB_EMB;
3508 #endif
3509 init_excp_4xx_softmmu(env);
3510 env->dcache_line_size = 32;
3511 env->icache_line_size = 32;
3512 /* Allocate hardware IRQ controller */
3513 ppc40x_irq_init(env);
3514
3515 SET_FIT_PERIOD(8, 12, 16, 20);
3516 SET_WDT_PERIOD(16, 20, 24, 28);
3517 }
3518
3519 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3520 {
3521 DeviceClass *dc = DEVICE_CLASS(oc);
3522 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3523
3524 dc->desc = "PowerPC 405";
3525 pcc->init_proc = init_proc_405;
3526 pcc->check_pow = check_pow_nocheck;
3527 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3528 PPC_DCR | PPC_WRTEE |
3529 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3530 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3531 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3532 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3533 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3534 pcc->msr_mask = (1ull << MSR_POW) |
3535 (1ull << MSR_CE) |
3536 (1ull << MSR_EE) |
3537 (1ull << MSR_PR) |
3538 (1ull << MSR_FP) |
3539 (1ull << MSR_DWE) |
3540 (1ull << MSR_DE) |
3541 (1ull << MSR_IR) |
3542 (1ull << MSR_DR);
3543 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3544 pcc->excp_model = POWERPC_EXCP_40x;
3545 pcc->bus_model = PPC_FLAGS_INPUT_405;
3546 pcc->bfd_mach = bfd_mach_ppc_403;
3547 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3548 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3549 }
3550
3551 static void init_proc_440EP (CPUPPCState *env)
3552 {
3553 /* Time base */
3554 gen_tbl(env);
3555 gen_spr_BookE(env, 0x000000000000FFFFULL);
3556 gen_spr_440(env);
3557 gen_spr_usprgh(env);
3558 /* Processor identification */
3559 spr_register(env, SPR_BOOKE_PIR, "PIR",
3560 SPR_NOACCESS, SPR_NOACCESS,
3561 &spr_read_generic, &spr_write_pir,
3562 0x00000000);
3563 /* XXX : not implemented */
3564 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3565 SPR_NOACCESS, SPR_NOACCESS,
3566 &spr_read_generic, &spr_write_generic,
3567 0x00000000);
3568 /* XXX : not implemented */
3569 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3570 SPR_NOACCESS, SPR_NOACCESS,
3571 &spr_read_generic, &spr_write_generic,
3572 0x00000000);
3573 /* XXX : not implemented */
3574 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3575 SPR_NOACCESS, SPR_NOACCESS,
3576 &spr_read_generic, &spr_write_generic,
3577 0x00000000);
3578 /* XXX : not implemented */
3579 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3580 SPR_NOACCESS, SPR_NOACCESS,
3581 &spr_read_generic, &spr_write_generic,
3582 0x00000000);
3583 /* XXX : not implemented */
3584 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3585 SPR_NOACCESS, SPR_NOACCESS,
3586 &spr_read_generic, &spr_write_generic,
3587 0x00000000);
3588 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3589 SPR_NOACCESS, SPR_NOACCESS,
3590 &spr_read_generic, &spr_write_generic,
3591 0x00000000);
3592 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3593 SPR_NOACCESS, SPR_NOACCESS,
3594 &spr_read_generic, &spr_write_generic,
3595 0x00000000);
3596 /* XXX : not implemented */
3597 spr_register(env, SPR_440_CCR1, "CCR1",
3598 SPR_NOACCESS, SPR_NOACCESS,
3599 &spr_read_generic, &spr_write_generic,
3600 0x00000000);
3601 /* Memory management */
3602 #if !defined(CONFIG_USER_ONLY)
3603 env->nb_tlb = 64;
3604 env->nb_ways = 1;
3605 env->id_tlbs = 0;
3606 env->tlb_type = TLB_EMB;
3607 #endif
3608 init_excp_BookE(env);
3609 env->dcache_line_size = 32;
3610 env->icache_line_size = 32;
3611 ppc40x_irq_init(env);
3612
3613 SET_FIT_PERIOD(12, 16, 20, 24);
3614 SET_WDT_PERIOD(20, 24, 28, 32);
3615 }
3616
3617 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3618 {
3619 DeviceClass *dc = DEVICE_CLASS(oc);
3620 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3621
3622 dc->desc = "PowerPC 440 EP";
3623 pcc->init_proc = init_proc_440EP;
3624 pcc->check_pow = check_pow_nocheck;
3625 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3626 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3627 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3628 PPC_FLOAT_STFIWX |
3629 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3630 PPC_CACHE | PPC_CACHE_ICBI |
3631 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3632 PPC_MEM_TLBSYNC | PPC_MFTB |
3633 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3634 PPC_440_SPEC;
3635 pcc->msr_mask = (1ull << MSR_POW) |
3636 (1ull << MSR_CE) |
3637 (1ull << MSR_EE) |
3638 (1ull << MSR_PR) |
3639 (1ull << MSR_FP) |
3640 (1ull << MSR_ME) |
3641 (1ull << MSR_FE0) |
3642 (1ull << MSR_DWE) |
3643 (1ull << MSR_DE) |
3644 (1ull << MSR_FE1) |
3645 (1ull << MSR_IR) |
3646 (1ull << MSR_DR);
3647 pcc->mmu_model = POWERPC_MMU_BOOKE;
3648 pcc->excp_model = POWERPC_EXCP_BOOKE;
3649 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3650 pcc->bfd_mach = bfd_mach_ppc_403;
3651 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3652 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3653 }
3654
3655 static void init_proc_440GP (CPUPPCState *env)
3656 {
3657 /* Time base */
3658 gen_tbl(env);
3659 gen_spr_BookE(env, 0x000000000000FFFFULL);
3660 gen_spr_440(env);
3661 gen_spr_usprgh(env);
3662 /* Processor identification */
3663 spr_register(env, SPR_BOOKE_PIR, "PIR",
3664 SPR_NOACCESS, SPR_NOACCESS,
3665 &spr_read_generic, &spr_write_pir,
3666 0x00000000);
3667 /* XXX : not implemented */
3668 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3669 SPR_NOACCESS, SPR_NOACCESS,
3670 &spr_read_generic, &spr_write_generic,
3671 0x00000000);
3672 /* XXX : not implemented */
3673 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3674 SPR_NOACCESS, SPR_NOACCESS,
3675 &spr_read_generic, &spr_write_generic,
3676 0x00000000);
3677 /* XXX : not implemented */
3678 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3679 SPR_NOACCESS, SPR_NOACCESS,
3680 &spr_read_generic, &spr_write_generic,
3681 0x00000000);
3682 /* XXX : not implemented */
3683 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3684 SPR_NOACCESS, SPR_NOACCESS,
3685 &spr_read_generic, &spr_write_generic,
3686 0x00000000);
3687 /* Memory management */
3688 #if !defined(CONFIG_USER_ONLY)
3689 env->nb_tlb = 64;
3690 env->nb_ways = 1;
3691 env->id_tlbs = 0;
3692 env->tlb_type = TLB_EMB;
3693 #endif
3694 init_excp_BookE(env);
3695 env->dcache_line_size = 32;
3696 env->icache_line_size = 32;
3697 /* XXX: TODO: allocate internal IRQ controller */
3698
3699 SET_FIT_PERIOD(12, 16, 20, 24);
3700 SET_WDT_PERIOD(20, 24, 28, 32);
3701 }
3702
3703 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3704 {
3705 DeviceClass *dc = DEVICE_CLASS(oc);
3706 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3707
3708 dc->desc = "PowerPC 440 GP";
3709 pcc->init_proc = init_proc_440GP;
3710 pcc->check_pow = check_pow_nocheck;
3711 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3712 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3713 PPC_CACHE | PPC_CACHE_ICBI |
3714 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3715 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3716 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3717 PPC_440_SPEC;
3718 pcc->msr_mask = (1ull << MSR_POW) |
3719 (1ull << MSR_CE) |
3720 (1ull << MSR_EE) |
3721 (1ull << MSR_PR) |
3722 (1ull << MSR_FP) |
3723 (1ull << MSR_ME) |
3724 (1ull << MSR_FE0) |
3725 (1ull << MSR_DWE) |
3726 (1ull << MSR_DE) |
3727 (1ull << MSR_FE1) |
3728 (1ull << MSR_IR) |
3729 (1ull << MSR_DR);
3730 pcc->mmu_model = POWERPC_MMU_BOOKE;
3731 pcc->excp_model = POWERPC_EXCP_BOOKE;
3732 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3733 pcc->bfd_mach = bfd_mach_ppc_403;
3734 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3735 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3736 }
3737
3738 static void init_proc_440x4 (CPUPPCState *env)
3739 {
3740 /* Time base */
3741 gen_tbl(env);
3742 gen_spr_BookE(env, 0x000000000000FFFFULL);
3743 gen_spr_440(env);
3744 gen_spr_usprgh(env);
3745 /* Processor identification */
3746 spr_register(env, SPR_BOOKE_PIR, "PIR",
3747 SPR_NOACCESS, SPR_NOACCESS,
3748 &spr_read_generic, &spr_write_pir,
3749 0x00000000);
3750 /* XXX : not implemented */
3751 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3752 SPR_NOACCESS, SPR_NOACCESS,
3753 &spr_read_generic, &spr_write_generic,
3754 0x00000000);
3755 /* XXX : not implemented */
3756 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3757 SPR_NOACCESS, SPR_NOACCESS,
3758 &spr_read_generic, &spr_write_generic,
3759 0x00000000);
3760 /* XXX : not implemented */
3761 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3762 SPR_NOACCESS, SPR_NOACCESS,
3763 &spr_read_generic, &spr_write_generic,
3764 0x00000000);
3765 /* XXX : not implemented */
3766 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3767 SPR_NOACCESS, SPR_NOACCESS,
3768 &spr_read_generic, &spr_write_generic,
3769 0x00000000);
3770 /* Memory management */
3771 #if !defined(CONFIG_USER_ONLY)
3772 env->nb_tlb = 64;
3773 env->nb_ways = 1;
3774 env->id_tlbs = 0;
3775 env->tlb_type = TLB_EMB;
3776 #endif
3777 init_excp_BookE(env);
3778 env->dcache_line_size = 32;
3779 env->icache_line_size = 32;
3780 /* XXX: TODO: allocate internal IRQ controller */
3781
3782 SET_FIT_PERIOD(12, 16, 20, 24);
3783 SET_WDT_PERIOD(20, 24, 28, 32);
3784 }
3785
3786 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3787 {
3788 DeviceClass *dc = DEVICE_CLASS(oc);
3789 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3790
3791 dc->desc = "PowerPC 440x4";
3792 pcc->init_proc = init_proc_440x4;
3793 pcc->check_pow = check_pow_nocheck;
3794 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3795 PPC_DCR | PPC_WRTEE |
3796 PPC_CACHE | PPC_CACHE_ICBI |
3797 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3798 PPC_MEM_TLBSYNC | PPC_MFTB |
3799 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3800 PPC_440_SPEC;
3801 pcc->msr_mask = (1ull << MSR_POW) |
3802 (1ull << MSR_CE) |
3803 (1ull << MSR_EE) |
3804 (1ull << MSR_PR) |
3805 (1ull << MSR_FP) |
3806 (1ull << MSR_ME) |
3807 (1ull << MSR_FE0) |
3808 (1ull << MSR_DWE) |
3809 (1ull << MSR_DE) |
3810 (1ull << MSR_FE1) |
3811 (1ull << MSR_IR) |
3812 (1ull << MSR_DR);
3813 pcc->mmu_model = POWERPC_MMU_BOOKE;
3814 pcc->excp_model = POWERPC_EXCP_BOOKE;
3815 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3816 pcc->bfd_mach = bfd_mach_ppc_403;
3817 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3818 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3819 }
3820
3821 static void init_proc_440x5 (CPUPPCState *env)
3822 {
3823 /* Time base */
3824 gen_tbl(env);
3825 gen_spr_BookE(env, 0x000000000000FFFFULL);
3826 gen_spr_440(env);
3827 gen_spr_usprgh(env);
3828 /* Processor identification */
3829 spr_register(env, SPR_BOOKE_PIR, "PIR",
3830 SPR_NOACCESS, SPR_NOACCESS,
3831 &spr_read_generic, &spr_write_pir,
3832 0x00000000);
3833 /* XXX : not implemented */
3834 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3835 SPR_NOACCESS, SPR_NOACCESS,
3836 &spr_read_generic, &spr_write_generic,
3837 0x00000000);
3838 /* XXX : not implemented */
3839 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3840 SPR_NOACCESS, SPR_NOACCESS,
3841 &spr_read_generic, &spr_write_generic,
3842 0x00000000);
3843 /* XXX : not implemented */
3844 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3845 SPR_NOACCESS, SPR_NOACCESS,
3846 &spr_read_generic, &spr_write_generic,
3847 0x00000000);
3848 /* XXX : not implemented */
3849 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3850 SPR_NOACCESS, SPR_NOACCESS,
3851 &spr_read_generic, &spr_write_generic,
3852 0x00000000);
3853 /* XXX : not implemented */
3854 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3855 SPR_NOACCESS, SPR_NOACCESS,
3856 &spr_read_generic, &spr_write_generic,
3857 0x00000000);
3858 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3859 SPR_NOACCESS, SPR_NOACCESS,
3860 &spr_read_generic, &spr_write_generic,
3861 0x00000000);
3862 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3863 SPR_NOACCESS, SPR_NOACCESS,
3864 &spr_read_generic, &spr_write_generic,
3865 0x00000000);
3866 /* XXX : not implemented */
3867 spr_register(env, SPR_440_CCR1, "CCR1",
3868 SPR_NOACCESS, SPR_NOACCESS,
3869 &spr_read_generic, &spr_write_generic,
3870 0x00000000);
3871 /* Memory management */
3872 #if !defined(CONFIG_USER_ONLY)
3873 env->nb_tlb = 64;
3874 env->nb_ways = 1;
3875 env->id_tlbs = 0;
3876 env->tlb_type = TLB_EMB;
3877 #endif
3878 init_excp_BookE(env);
3879 env->dcache_line_size = 32;
3880 env->icache_line_size = 32;
3881 ppc40x_irq_init(env);
3882
3883 SET_FIT_PERIOD(12, 16, 20, 24);
3884 SET_WDT_PERIOD(20, 24, 28, 32);
3885 }
3886
3887 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3888 {
3889 DeviceClass *dc = DEVICE_CLASS(oc);
3890 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3891
3892 dc->desc = "PowerPC 440x5";
3893 pcc->init_proc = init_proc_440x5;
3894 pcc->check_pow = check_pow_nocheck;
3895 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3896 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3897 PPC_CACHE | PPC_CACHE_ICBI |
3898 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3899 PPC_MEM_TLBSYNC | PPC_MFTB |
3900 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3901 PPC_440_SPEC;
3902 pcc->msr_mask = (1ull << MSR_POW) |
3903 (1ull << MSR_CE) |
3904 (1ull << MSR_EE) |
3905 (1ull << MSR_PR) |
3906 (1ull << MSR_FP) |
3907 (1ull << MSR_ME) |
3908 (1ull << MSR_FE0) |
3909 (1ull << MSR_DWE) |
3910 (1ull << MSR_DE) |
3911 (1ull << MSR_FE1) |
3912 (1ull << MSR_IR) |
3913 (1ull << MSR_DR);
3914 pcc->mmu_model = POWERPC_MMU_BOOKE;
3915 pcc->excp_model = POWERPC_EXCP_BOOKE;
3916 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3917 pcc->bfd_mach = bfd_mach_ppc_403;
3918 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3919 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3920 }
3921
3922 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
3923 {
3924 DeviceClass *dc = DEVICE_CLASS(oc);
3925 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3926
3927 dc->desc = "PowerPC 440x5 with double precision FPU";
3928 pcc->init_proc = init_proc_440x5;
3929 pcc->check_pow = check_pow_nocheck;
3930 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3931 PPC_FLOAT | PPC_FLOAT_FSQRT |
3932 PPC_FLOAT_STFIWX |
3933 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3934 PPC_CACHE | PPC_CACHE_ICBI |
3935 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3936 PPC_MEM_TLBSYNC | PPC_MFTB |
3937 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3938 PPC_440_SPEC;
3939 pcc->insns_flags2 = PPC2_FP_CVT_S64;
3940 pcc->msr_mask = (1ull << MSR_POW) |
3941 (1ull << MSR_CE) |
3942 (1ull << MSR_EE) |
3943 (1ull << MSR_PR) |
3944 (1ull << MSR_FP) |
3945 (1ull << MSR_ME) |
3946 (1ull << MSR_FE0) |
3947 (1ull << MSR_DWE) |
3948 (1ull << MSR_DE) |
3949 (1ull << MSR_FE1) |
3950 (1ull << MSR_IR) |
3951 (1ull << MSR_DR);
3952 pcc->mmu_model = POWERPC_MMU_BOOKE;
3953 pcc->excp_model = POWERPC_EXCP_BOOKE;
3954 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3955 pcc->bfd_mach = bfd_mach_ppc_403;
3956 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3957 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3958 }
3959
3960 static void init_proc_460 (CPUPPCState *env)
3961 {
3962 /* Time base */
3963 gen_tbl(env);
3964 gen_spr_BookE(env, 0x000000000000FFFFULL);
3965 gen_spr_440(env);
3966 gen_spr_usprgh(env);
3967 /* Processor identification */
3968 spr_register(env, SPR_BOOKE_PIR, "PIR",
3969 SPR_NOACCESS, SPR_NOACCESS,
3970 &spr_read_generic, &spr_write_pir,
3971 0x00000000);
3972 /* XXX : not implemented */
3973 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3974 SPR_NOACCESS, SPR_NOACCESS,
3975 &spr_read_generic, &spr_write_generic,
3976 0x00000000);
3977 /* XXX : not implemented */
3978 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3979 SPR_NOACCESS, SPR_NOACCESS,
3980 &spr_read_generic, &spr_write_generic,
3981 0x00000000);
3982 /* XXX : not implemented */
3983 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3984 SPR_NOACCESS, SPR_NOACCESS,
3985 &spr_read_generic, &spr_write_generic,
3986 0x00000000);
3987 /* XXX : not implemented */
3988 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3989 SPR_NOACCESS, SPR_NOACCESS,
3990 &spr_read_generic, &spr_write_generic,
3991 0x00000000);
3992 /* XXX : not implemented */
3993 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3994 SPR_NOACCESS, SPR_NOACCESS,
3995 &spr_read_generic, &spr_write_generic,
3996 0x00000000);
3997 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3998 SPR_NOACCESS, SPR_NOACCESS,
3999 &spr_read_generic, &spr_write_generic,
4000 0x00000000);
4001 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4002 SPR_NOACCESS, SPR_NOACCESS,
4003 &spr_read_generic, &spr_write_generic,
4004 0x00000000);
4005 /* XXX : not implemented */
4006 spr_register(env, SPR_440_CCR1, "CCR1",
4007 SPR_NOACCESS, SPR_NOACCESS,
4008 &spr_read_generic, &spr_write_generic,
4009 0x00000000);
4010 /* XXX : not implemented */
4011 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4012 &spr_read_generic, &spr_write_generic,
4013 &spr_read_generic, &spr_write_generic,
4014 0x00000000);
4015 /* Memory management */
4016 #if !defined(CONFIG_USER_ONLY)
4017 env->nb_tlb = 64;
4018 env->nb_ways = 1;
4019 env->id_tlbs = 0;
4020 env->tlb_type = TLB_EMB;
4021 #endif
4022 init_excp_BookE(env);
4023 env->dcache_line_size = 32;
4024 env->icache_line_size = 32;
4025 /* XXX: TODO: allocate internal IRQ controller */
4026
4027 SET_FIT_PERIOD(12, 16, 20, 24);
4028 SET_WDT_PERIOD(20, 24, 28, 32);
4029 }
4030
4031 POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
4032 {
4033 DeviceClass *dc = DEVICE_CLASS(oc);
4034 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4035
4036 dc->desc = "PowerPC 460 (guessed)";
4037 pcc->init_proc = init_proc_460;
4038 pcc->check_pow = check_pow_nocheck;
4039 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4040 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4041 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
4042 PPC_CACHE | PPC_CACHE_ICBI |
4043 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4044 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4045 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4046 PPC_440_SPEC;
4047 pcc->msr_mask = (1ull << MSR_POW) |
4048 (1ull << MSR_CE) |
4049 (1ull << MSR_EE) |
4050 (1ull << MSR_PR) |
4051 (1ull << MSR_FP) |
4052 (1ull << MSR_ME) |
4053 (1ull << MSR_FE0) |
4054 (1ull << MSR_DWE) |
4055 (1ull << MSR_DE) |
4056 (1ull << MSR_FE1) |
4057 (1ull << MSR_IR) |
4058 (1ull << MSR_DR);
4059 pcc->mmu_model = POWERPC_MMU_BOOKE;
4060 pcc->excp_model = POWERPC_EXCP_BOOKE;
4061 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4062 pcc->bfd_mach = bfd_mach_ppc_403;
4063 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4064 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4065 }
4066
4067 static void init_proc_460F (CPUPPCState *env)
4068 {
4069 /* Time base */
4070 gen_tbl(env);
4071 gen_spr_BookE(env, 0x000000000000FFFFULL);
4072 gen_spr_440(env);
4073 gen_spr_usprgh(env);
4074 /* Processor identification */
4075 spr_register(env, SPR_BOOKE_PIR, "PIR",
4076 SPR_NOACCESS, SPR_NOACCESS,
4077 &spr_read_generic, &spr_write_pir,
4078 0x00000000);
4079 /* XXX : not implemented */
4080 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4081 SPR_NOACCESS, SPR_NOACCESS,
4082 &spr_read_generic, &spr_write_generic,
4083 0x00000000);
4084 /* XXX : not implemented */
4085 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4086 SPR_NOACCESS, SPR_NOACCESS,
4087 &spr_read_generic, &spr_write_generic,
4088 0x00000000);
4089 /* XXX : not implemented */
4090 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4091 SPR_NOACCESS, SPR_NOACCESS,
4092 &spr_read_generic, &spr_write_generic,
4093 0x00000000);
4094 /* XXX : not implemented */
4095 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4096 SPR_NOACCESS, SPR_NOACCESS,
4097 &spr_read_generic, &spr_write_generic,
4098 0x00000000);
4099 /* XXX : not implemented */
4100 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4101 SPR_NOACCESS, SPR_NOACCESS,
4102 &spr_read_generic, &spr_write_generic,
4103 0x00000000);
4104 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4105 SPR_NOACCESS, SPR_NOACCESS,
4106 &spr_read_generic, &spr_write_generic,
4107 0x00000000);
4108 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4109 SPR_NOACCESS, SPR_NOACCESS,
4110 &spr_read_generic, &spr_write_generic,
4111 0x00000000);
4112 /* XXX : not implemented */
4113 spr_register(env, SPR_440_CCR1, "CCR1",
4114 SPR_NOACCESS, SPR_NOACCESS,
4115 &spr_read_generic, &spr_write_generic,
4116 0x00000000);
4117 /* XXX : not implemented */
4118 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4119 &spr_read_generic, &spr_write_generic,
4120 &spr_read_generic, &spr_write_generic,
4121 0x00000000);
4122 /* Memory management */
4123 #if !defined(CONFIG_USER_ONLY)
4124 env->nb_tlb = 64;
4125 env->nb_ways = 1;
4126 env->id_tlbs = 0;
4127 env->tlb_type = TLB_EMB;
4128 #endif
4129 init_excp_BookE(env);
4130 env->dcache_line_size = 32;
4131 env->icache_line_size = 32;
4132 /* XXX: TODO: allocate internal IRQ controller */
4133
4134 SET_FIT_PERIOD(12, 16, 20, 24);
4135 SET_WDT_PERIOD(20, 24, 28, 32);
4136 }
4137
4138 POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
4139 {
4140 DeviceClass *dc = DEVICE_CLASS(oc);
4141 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4142
4143 dc->desc = "PowerPC 460F (guessed)";
4144 pcc->init_proc = init_proc_460F;
4145 pcc->check_pow = check_pow_nocheck;
4146 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4147 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
4148 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4149 PPC_FLOAT_STFIWX | PPC_MFTB |
4150 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4151 PPC_WRTEE | PPC_MFAPIDI |
4152 PPC_CACHE | PPC_CACHE_ICBI |
4153 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4154 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4155 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4156 PPC_440_SPEC;
4157 pcc->msr_mask = (1ull << MSR_POW) |
4158 (1ull << MSR_CE) |
4159 (1ull << MSR_EE) |
4160 (1ull << MSR_PR) |
4161 (1ull << MSR_FP) |
4162 (1ull << MSR_ME) |
4163 (1ull << MSR_FE0) |
4164 (1ull << MSR_DWE) |
4165 (1ull << MSR_DE) |
4166 (1ull << MSR_FE1) |
4167 (1ull << MSR_IR) |
4168 (1ull << MSR_DR);
4169 pcc->mmu_model = POWERPC_MMU_BOOKE;
4170 pcc->excp_model = POWERPC_EXCP_BOOKE;
4171 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4172 pcc->bfd_mach = bfd_mach_ppc_403;
4173 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4174 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4175 }
4176
4177 static void init_proc_MPC5xx (CPUPPCState *env)
4178 {
4179 /* Time base */
4180 gen_tbl(env);
4181 gen_spr_5xx_8xx(env);
4182 gen_spr_5xx(env);
4183 init_excp_MPC5xx(env);
4184 env->dcache_line_size = 32;
4185 env->icache_line_size = 32;
4186 /* XXX: TODO: allocate internal IRQ controller */
4187 }
4188
4189 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4190 {
4191 DeviceClass *dc = DEVICE_CLASS(oc);
4192 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4193
4194 dc->desc = "Freescale 5xx cores (aka RCPU)";
4195 pcc->init_proc = init_proc_MPC5xx;
4196 pcc->check_pow = check_pow_none;
4197 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4198 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4199 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4200 PPC_MFTB;
4201 pcc->msr_mask = (1ull << MSR_ILE) |
4202 (1ull << MSR_EE) |
4203 (1ull << MSR_PR) |
4204 (1ull << MSR_FP) |
4205 (1ull << MSR_ME) |
4206 (1ull << MSR_FE0) |
4207 (1ull << MSR_SE) |
4208 (1ull << MSR_DE) |
4209 (1ull << MSR_FE1) |
4210 (1ull << MSR_EP) |
4211 (1ull << MSR_RI) |
4212 (1ull << MSR_LE);
4213 pcc->mmu_model = POWERPC_MMU_REAL;
4214 pcc->excp_model = POWERPC_EXCP_603;
4215 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4216 pcc->bfd_mach = bfd_mach_ppc_505;
4217 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4218 POWERPC_FLAG_BUS_CLK;
4219 }
4220
4221 static void init_proc_MPC8xx (CPUPPCState *env)
4222 {
4223 /* Time base */
4224 gen_tbl(env);
4225 gen_spr_5xx_8xx(env);
4226 gen_spr_8xx(env);
4227 init_excp_MPC8xx(env);
4228 env->dcache_line_size = 32;
4229 env->icache_line_size = 32;
4230 /* XXX: TODO: allocate internal IRQ controller */
4231 }
4232
4233 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4234 {
4235 DeviceClass *dc = DEVICE_CLASS(oc);
4236 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4237
4238 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4239 pcc->init_proc = init_proc_MPC8xx;
4240 pcc->check_pow = check_pow_none;
4241 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4242 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4243 PPC_CACHE_ICBI | PPC_MFTB;
4244 pcc->msr_mask = (1ull << MSR_ILE) |
4245 (1ull << MSR_EE) |
4246 (1ull << MSR_PR) |
4247 (1ull << MSR_FP) |
4248 (1ull << MSR_ME) |
4249 (1ull << MSR_SE) |
4250 (1ull << MSR_DE) |
4251 (1ull << MSR_EP) |
4252 (1ull << MSR_IR) |
4253 (1ull << MSR_DR) |
4254 (1ull << MSR_RI) |
4255 (1ull << MSR_LE);
4256 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4257 pcc->excp_model = POWERPC_EXCP_603;
4258 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4259 pcc->bfd_mach = bfd_mach_ppc_860;
4260 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4261 POWERPC_FLAG_BUS_CLK;
4262 }
4263
4264 /* Freescale 82xx cores (aka PowerQUICC-II) */
4265
4266 static void init_proc_G2 (CPUPPCState *env)
4267 {
4268 gen_spr_ne_601(env);
4269 gen_spr_G2_755(env);
4270 gen_spr_G2(env);
4271 /* Time base */
4272 gen_tbl(env);
4273 /* External access control */
4274 /* XXX : not implemented */
4275 spr_register(env, SPR_EAR, "EAR",
4276 SPR_NOACCESS, SPR_NOACCESS,
4277 &spr_read_generic, &spr_write_generic,
4278 0x00000000);
4279 /* Hardware implementation register */
4280 /* XXX : not implemented */
4281 spr_register(env, SPR_HID0, "HID0",
4282 SPR_NOACCESS, SPR_NOACCESS,
4283 &spr_read_generic, &spr_write_generic,
4284 0x00000000);
4285 /* XXX : not implemented */
4286 spr_register(env, SPR_HID1, "HID1",
4287 SPR_NOACCESS, SPR_NOACCESS,
4288 &spr_read_generic, &spr_write_generic,
4289 0x00000000);
4290 /* XXX : not implemented */
4291 spr_register(env, SPR_HID2, "HID2",
4292 SPR_NOACCESS, SPR_NOACCESS,
4293 &spr_read_generic, &spr_write_generic,
4294 0x00000000);
4295 /* Memory management */
4296 gen_low_BATs(env);
4297 gen_high_BATs(env);
4298 gen_6xx_7xx_soft_tlb(env, 64, 2);
4299 init_excp_G2(env);
4300 env->dcache_line_size = 32;
4301 env->icache_line_size = 32;
4302 /* Allocate hardware IRQ controller */
4303 ppc6xx_irq_init(env);
4304 }
4305
4306 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4307 {
4308 DeviceClass *dc = DEVICE_CLASS(oc);
4309 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4310
4311 dc->desc = "PowerPC G2";
4312 pcc->init_proc = init_proc_G2;
4313 pcc->check_pow = check_pow_hid0;
4314 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4315 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4316 PPC_FLOAT_STFIWX |
4317 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4318 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4319 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4320 PPC_SEGMENT | PPC_EXTERN;
4321 pcc->msr_mask = (1ull << MSR_POW) |
4322 (1ull << MSR_TGPR) |
4323 (1ull << MSR_EE) |
4324 (1ull << MSR_PR) |
4325 (1ull << MSR_FP) |
4326 (1ull << MSR_ME) |
4327 (1ull << MSR_FE0) |
4328 (1ull << MSR_SE) |
4329 (1ull << MSR_DE) |
4330 (1ull << MSR_FE1) |
4331 (1ull << MSR_AL) |
4332 (1ull << MSR_EP) |
4333 (1ull << MSR_IR) |
4334 (1ull << MSR_DR) |
4335 (1ull << MSR_RI);
4336 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4337 pcc->excp_model = POWERPC_EXCP_G2;
4338 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4339 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4340 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4341 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4342 }
4343
4344 static void init_proc_G2LE (CPUPPCState *env)
4345 {
4346 gen_spr_ne_601(env);
4347 gen_spr_G2_755(env);
4348 gen_spr_G2(env);
4349 /* Time base */
4350 gen_tbl(env);
4351 /* External access control */
4352 /* XXX : not implemented */
4353 spr_register(env, SPR_EAR, "EAR",
4354 SPR_NOACCESS, SPR_NOACCESS,
4355 &spr_read_generic, &spr_write_generic,
4356 0x00000000);
4357 /* Hardware implementation register */
4358 /* XXX : not implemented */
4359 spr_register(env, SPR_HID0, "HID0",
4360 SPR_NOACCESS, SPR_NOACCESS,
4361 &spr_read_generic, &spr_write_generic,
4362 0x00000000);
4363 /* XXX : not implemented */
4364 spr_register(env, SPR_HID1, "HID1",
4365 SPR_NOACCESS, SPR_NOACCESS,
4366 &spr_read_generic, &spr_write_generic,
4367 0x00000000);
4368 /* XXX : not implemented */
4369 spr_register(env, SPR_HID2, "HID2",
4370 SPR_NOACCESS, SPR_NOACCESS,
4371 &spr_read_generic, &spr_write_generic,
4372 0x00000000);
4373
4374 /* Memory management */
4375 gen_low_BATs(env);
4376 gen_high_BATs(env);
4377 gen_6xx_7xx_soft_tlb(env, 64, 2);
4378 init_excp_G2(env);
4379 env->dcache_line_size = 32;
4380 env->icache_line_size = 32;
4381 /* Allocate hardware IRQ controller */
4382 ppc6xx_irq_init(env);
4383 }
4384
4385 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4386 {
4387 DeviceClass *dc = DEVICE_CLASS(oc);
4388 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4389
4390 dc->desc = "PowerPC G2LE";
4391 pcc->init_proc = init_proc_G2LE;
4392 pcc->check_pow = check_pow_hid0;
4393 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4394 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4395 PPC_FLOAT_STFIWX |
4396 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4397 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4398 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4399 PPC_SEGMENT | PPC_EXTERN;
4400 pcc->msr_mask = (1ull << MSR_POW) |
4401 (1ull << MSR_TGPR) |
4402 (1ull << MSR_ILE) |
4403 (1ull << MSR_EE) |
4404 (1ull << MSR_PR) |
4405 (1ull << MSR_FP) |
4406 (1ull << MSR_ME) |
4407 (1ull << MSR_FE0) |
4408 (1ull << MSR_SE) |
4409 (1ull << MSR_DE) |
4410 (1ull << MSR_FE1) |
4411 (1ull << MSR_AL) |
4412 (1ull << MSR_EP) |
4413 (1ull << MSR_IR) |
4414 (1ull << MSR_DR) |
4415 (1ull << MSR_RI) |
4416 (1ull << MSR_LE);
4417 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4418 pcc->excp_model = POWERPC_EXCP_G2;
4419 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4420 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4421 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4422 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4423 }
4424
4425 static void init_proc_e200 (CPUPPCState *env)
4426 {
4427 /* Time base */
4428 gen_tbl(env);
4429 gen_spr_BookE(env, 0x000000070000FFFFULL);
4430 /* XXX : not implemented */
4431 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4432 &spr_read_spefscr, &spr_write_spefscr,
4433 &spr_read_spefscr, &spr_write_spefscr,
4434 0x00000000);
4435 /* Memory management */
4436 gen_spr_BookE206(env, 0x0000005D, NULL);
4437 /* XXX : not implemented */
4438 spr_register(env, SPR_HID0, "HID0",
4439 SPR_NOACCESS, SPR_NOACCESS,
4440 &spr_read_generic, &spr_write_generic,
4441 0x00000000);
4442 /* XXX : not implemented */
4443 spr_register(env, SPR_HID1, "HID1",
4444 SPR_NOACCESS, SPR_NOACCESS,
4445 &spr_read_generic, &spr_write_generic,
4446 0x00000000);
4447 /* XXX : not implemented */
4448 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4449 SPR_NOACCESS, SPR_NOACCESS,
4450 &spr_read_generic, &spr_write_generic,
4451 0x00000000);
4452 /* XXX : not implemented */
4453 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4454 SPR_NOACCESS, SPR_NOACCESS,
4455 &spr_read_generic, &spr_write_generic,
4456 0x00000000);
4457 /* XXX : not implemented */
4458 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4459 SPR_NOACCESS, SPR_NOACCESS,
4460 &spr_read_generic, &spr_write_generic,
4461 0x00000000);
4462 /* XXX : not implemented */
4463 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4464 SPR_NOACCESS, SPR_NOACCESS,
4465 &spr_read_generic, &spr_write_generic,
4466 0x00000000);
4467 /* XXX : not implemented */
4468 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4469 SPR_NOACCESS, SPR_NOACCESS,
4470 &spr_read_generic, &spr_write_generic,
4471 0x00000000);
4472 /* XXX : not implemented */
4473 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4474 &spr_read_generic, SPR_NOACCESS,
4475 &spr_read_generic, SPR_NOACCESS,
4476 0x00000000);
4477 /* XXX : not implemented */
4478 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4479 SPR_NOACCESS, SPR_NOACCESS,
4480 &spr_read_generic, &spr_write_generic,
4481 0x00000000);
4482 /* XXX : not implemented */
4483 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4484 SPR_NOACCESS, SPR_NOACCESS,
4485 &spr_read_generic, &spr_write_generic,
4486 0x00000000);
4487 /* XXX : not implemented */
4488 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4489 SPR_NOACCESS, SPR_NOACCESS,
4490 &spr_read_generic, &spr_write_generic,
4491 0x00000000);
4492 /* XXX : not implemented */
4493 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4494 SPR_NOACCESS, SPR_NOACCESS,
4495 &spr_read_generic, &spr_write_generic,
4496 0x00000000);
4497 /* XXX : not implemented */
4498 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4499 SPR_NOACCESS, SPR_NOACCESS,
4500 &spr_read_generic, &spr_write_generic,
4501 0x00000000);
4502 /* XXX : not implemented */
4503 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4504 SPR_NOACCESS, SPR_NOACCESS,
4505 &spr_read_generic, &spr_write_generic,
4506 0x00000000);
4507 /* XXX : not implemented */
4508 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4509 SPR_NOACCESS, SPR_NOACCESS,
4510 &spr_read_generic, &spr_write_generic,
4511 0x00000000); /* TOFIX */
4512 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4513 SPR_NOACCESS, SPR_NOACCESS,
4514 &spr_read_generic, &spr_write_generic,
4515 0x00000000);
4516 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4517 SPR_NOACCESS, SPR_NOACCESS,
4518 &spr_read_generic, &spr_write_generic,
4519 0x00000000);
4520 #if !defined(CONFIG_USER_ONLY)
4521 env->nb_tlb = 64;
4522 env->nb_ways = 1;
4523 env->id_tlbs = 0;
4524 env->tlb_type = TLB_EMB;
4525 #endif
4526 init_excp_e200(env, 0xFFFF0000UL);
4527 env->dcache_line_size = 32;
4528 env->icache_line_size = 32;
4529 /* XXX: TODO: allocate internal IRQ controller */
4530 }
4531
4532 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4533 {
4534 DeviceClass *dc = DEVICE_CLASS(oc);
4535 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4536
4537 dc->desc = "e200 core";
4538 pcc->init_proc = init_proc_e200;
4539 pcc->check_pow = check_pow_hid0;
4540 /* XXX: unimplemented instructions:
4541 * dcblc
4542 * dcbtlst
4543 * dcbtstls
4544 * icblc
4545 * icbtls
4546 * tlbivax
4547 * all SPE multiply-accumulate instructions
4548 */
4549 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4550 PPC_SPE | PPC_SPE_SINGLE |
4551 PPC_WRTEE | PPC_RFDI |
4552 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4553 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4554 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4555 PPC_BOOKE;
4556 pcc->msr_mask = (1ull << MSR_UCLE) |
4557 (1ull << MSR_SPE) |
4558 (1ull << MSR_POW) |
4559 (1ull << MSR_CE) |
4560 (1ull << MSR_EE) |
4561 (1ull << MSR_PR) |
4562 (1ull << MSR_FP) |
4563 (1ull << MSR_ME) |
4564 (1ull << MSR_FE0) |
4565 (1ull << MSR_DWE) |
4566 (1ull << MSR_DE) |
4567 (1ull << MSR_FE1) |
4568 (1ull << MSR_IR) |
4569 (1ull << MSR_DR);
4570 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4571 pcc->excp_model = POWERPC_EXCP_BOOKE;
4572 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4573 pcc->bfd_mach = bfd_mach_ppc_860;
4574 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4575 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4576 POWERPC_FLAG_BUS_CLK;
4577 }
4578
4579 static void init_proc_e300 (CPUPPCState *env)
4580 {
4581 gen_spr_ne_601(env);
4582 gen_spr_603(env);
4583 /* Time base */
4584 gen_tbl(env);
4585 /* hardware implementation registers */
4586 /* XXX : not implemented */
4587 spr_register(env, SPR_HID0, "HID0",
4588 SPR_NOACCESS, SPR_NOACCESS,
4589 &spr_read_generic, &spr_write_generic,
4590 0x00000000);
4591 /* XXX : not implemented */
4592 spr_register(env, SPR_HID1, "HID1",
4593 SPR_NOACCESS, SPR_NOACCESS,
4594 &spr_read_generic, &spr_write_generic,
4595 0x00000000);
4596 /* XXX : not implemented */
4597 spr_register(env, SPR_HID2, "HID2",
4598 SPR_NOACCESS, SPR_NOACCESS,
4599 &spr_read_generic, &spr_write_generic,
4600 0x00000000);
4601 /* Breakpoints */
4602 /* XXX : not implemented */
4603 spr_register(env, SPR_DABR, "DABR",
4604 SPR_NOACCESS, SPR_NOACCESS,
4605 &spr_read_generic, &spr_write_generic,
4606 0x00000000);
4607 /* XXX : not implemented */
4608 spr_register(env, SPR_DABR2, "DABR2",
4609 SPR_NOACCESS, SPR_NOACCESS,
4610 &spr_read_generic, &spr_write_generic,
4611 0x00000000);
4612 /* XXX : not implemented */
4613 spr_register(env, SPR_IABR2, "IABR2",
4614 SPR_NOACCESS, SPR_NOACCESS,
4615 &spr_read_generic, &spr_write_generic,
4616 0x00000000);
4617 /* XXX : not implemented */
4618 spr_register(env, SPR_IBCR, "IBCR",
4619 SPR_NOACCESS, SPR_NOACCESS,
4620 &spr_read_generic, &spr_write_generic,
4621 0x00000000);
4622 /* XXX : not implemented */
4623 spr_register(env, SPR_DBCR, "DBCR",
4624 SPR_NOACCESS, SPR_NOACCESS,
4625 &spr_read_generic, &spr_write_generic,
4626 0x00000000);
4627 /* Memory management */
4628 gen_low_BATs(env);
4629 gen_high_BATs(env);
4630 gen_6xx_7xx_soft_tlb(env, 64, 2);
4631 init_excp_603(env);
4632 env->dcache_line_size = 32;
4633 env->icache_line_size = 32;
4634 /* Allocate hardware IRQ controller */
4635 ppc6xx_irq_init(env);
4636 }
4637
4638 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4639 {
4640 DeviceClass *dc = DEVICE_CLASS(oc);
4641 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4642
4643 dc->desc = "e300 core";
4644 pcc->init_proc = init_proc_e300;
4645 pcc->check_pow = check_pow_hid0;
4646 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4647 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4648 PPC_FLOAT_STFIWX |
4649 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4650 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4651 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4652 PPC_SEGMENT | PPC_EXTERN;
4653 pcc->msr_mask = (1ull << MSR_POW) |
4654 (1ull << MSR_TGPR) |
4655 (1ull << MSR_ILE) |
4656 (1ull << MSR_EE) |
4657 (1ull << MSR_PR) |
4658 (1ull << MSR_FP) |
4659 (1ull << MSR_ME) |
4660 (1ull << MSR_FE0) |
4661 (1ull << MSR_SE) |
4662 (1ull << MSR_DE) |
4663 (1ull << MSR_FE1) |
4664 (1ull << MSR_AL) |
4665 (1ull << MSR_EP) |
4666 (1ull << MSR_IR) |
4667 (1ull << MSR_DR) |
4668 (1ull << MSR_RI) |
4669 (1ull << MSR_LE);
4670 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4671 pcc->excp_model = POWERPC_EXCP_603;
4672 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4673 pcc->bfd_mach = bfd_mach_ppc_603;
4674 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4675 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4676 }
4677
4678 #if !defined(CONFIG_USER_ONLY)
4679 static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
4680 {
4681 TCGv val = tcg_temp_new();
4682 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4683 gen_store_spr(SPR_BOOKE_MAS3, val);
4684 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4685 gen_store_spr(SPR_BOOKE_MAS7, val);
4686 tcg_temp_free(val);
4687 }
4688
4689 static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
4690 {
4691 TCGv mas7 = tcg_temp_new();
4692 TCGv mas3 = tcg_temp_new();
4693 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4694 tcg_gen_shli_tl(mas7, mas7, 32);
4695 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4696 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4697 tcg_temp_free(mas3);
4698 tcg_temp_free(mas7);
4699 }
4700
4701 #endif
4702
4703 enum fsl_e500_version {
4704 fsl_e500v1,
4705 fsl_e500v2,
4706 fsl_e500mc,
4707 fsl_e5500,
4708 };
4709
4710 static void init_proc_e500 (CPUPPCState *env, int version)
4711 {
4712 PowerPCCPU *cpu = ppc_env_get_cpu(env);
4713 uint32_t tlbncfg[2];
4714 uint64_t ivor_mask;
4715 uint64_t ivpr_mask = 0xFFFF0000ULL;
4716 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4717 | 0x0020; /* 32 kb */
4718 uint32_t l1cfg1 = 0x3800 /* 8 ways */
4719 | 0x0020; /* 32 kb */
4720 #if !defined(CONFIG_USER_ONLY)
4721 int i;
4722 #endif
4723
4724 /* Time base */
4725 gen_tbl(env);
4726 /*
4727 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4728 * complain when accessing them.
4729 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4730 */
4731 switch (version) {
4732 case fsl_e500v1:
4733 case fsl_e500v2:
4734 default:
4735 ivor_mask = 0x0000000F0000FFFFULL;
4736 break;
4737 case fsl_e500mc:
4738 case fsl_e5500:
4739 ivor_mask = 0x000003FE0000FFFFULL;
4740 break;
4741 }
4742 gen_spr_BookE(env, ivor_mask);
4743 /* Processor identification */
4744 spr_register(env, SPR_BOOKE_PIR, "PIR",
4745 SPR_NOACCESS, SPR_NOACCESS,
4746 &spr_read_generic, &spr_write_pir,
4747 0x00000000);
4748 /* XXX : not implemented */
4749 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4750 &spr_read_spefscr, &spr_write_spefscr,
4751 &spr_read_spefscr, &spr_write_spefscr,
4752 0x00000000);
4753 #if !defined(CONFIG_USER_ONLY)
4754 /* Memory management */
4755 env->nb_pids = 3;
4756 env->nb_ways = 2;
4757 env->id_tlbs = 0;
4758 switch (version) {
4759 case fsl_e500v1:
4760 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4761 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4762 break;
4763 case fsl_e500v2:
4764 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4765 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4766 break;
4767 case fsl_e500mc:
4768 case fsl_e5500:
4769 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4770 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4771 break;
4772 default:
4773 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4774 }
4775 #endif
4776 /* Cache sizes */
4777 switch (version) {
4778 case fsl_e500v1:
4779 case fsl_e500v2:
4780 env->dcache_line_size = 32;
4781 env->icache_line_size = 32;
4782 break;
4783 case fsl_e500mc:
4784 case fsl_e5500:
4785 env->dcache_line_size = 64;
4786 env->icache_line_size = 64;
4787 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4788 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4789 break;
4790 default:
4791 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4792 }
4793 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4794 /* XXX : not implemented */
4795 spr_register(env, SPR_HID0, "HID0",
4796 SPR_NOACCESS, SPR_NOACCESS,
4797 &spr_read_generic, &spr_write_generic,
4798 0x00000000);
4799 /* XXX : not implemented */
4800 spr_register(env, SPR_HID1, "HID1",
4801 SPR_NOACCESS, SPR_NOACCESS,
4802 &spr_read_generic, &spr_write_generic,
4803 0x00000000);
4804 /* XXX : not implemented */
4805 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4806 SPR_NOACCESS, SPR_NOACCESS,
4807 &spr_read_generic, &spr_write_generic,
4808 0x00000000);
4809 /* XXX : not implemented */
4810 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4811 SPR_NOACCESS, SPR_NOACCESS,
4812 &spr_read_generic, &spr_write_generic,
4813 0x00000000);
4814 /* XXX : not implemented */
4815 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4816 SPR_NOACCESS, SPR_NOACCESS,
4817 &spr_read_generic, &spr_write_generic,
4818 0x00000000);
4819 /* XXX : not implemented */
4820 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4821 SPR_NOACCESS, SPR_NOACCESS,
4822 &spr_read_generic, &spr_write_generic,
4823 0x00000000);
4824 /* XXX : not implemented */
4825 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4826 SPR_NOACCESS, SPR_NOACCESS,
4827 &spr_read_generic, &spr_write_generic,
4828 0x00000000);
4829 /* XXX : not implemented */
4830 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4831 SPR_NOACCESS, SPR_NOACCESS,
4832 &spr_read_generic, &spr_write_generic,
4833 0x00000000);
4834 /* XXX : not implemented */
4835 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4836 &spr_read_generic, SPR_NOACCESS,
4837 &spr_read_generic, SPR_NOACCESS,
4838 l1cfg0);
4839 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
4840 &spr_read_generic, SPR_NOACCESS,
4841 &spr_read_generic, SPR_NOACCESS,
4842 l1cfg1);
4843 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4844 SPR_NOACCESS, SPR_NOACCESS,
4845 &spr_read_generic, &spr_write_e500_l1csr0,
4846 0x00000000);
4847 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4848 SPR_NOACCESS, SPR_NOACCESS,
4849 &spr_read_generic, &spr_write_e500_l1csr1,
4850 0x00000000);
4851 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4852 SPR_NOACCESS, SPR_NOACCESS,
4853 &spr_read_generic, &spr_write_generic,
4854 0x00000000);
4855 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4856 SPR_NOACCESS, SPR_NOACCESS,
4857 &spr_read_generic, &spr_write_generic,
4858 0x00000000);
4859 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4860 SPR_NOACCESS, SPR_NOACCESS,
4861 &spr_read_generic, &spr_write_booke206_mmucsr0,
4862 0x00000000);
4863 spr_register(env, SPR_BOOKE_EPR, "EPR",
4864 SPR_NOACCESS, SPR_NOACCESS,
4865 &spr_read_generic, SPR_NOACCESS,
4866 0x00000000);
4867 /* XXX better abstract into Emb.xxx features */
4868 if (version == fsl_e5500) {
4869 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4870 SPR_NOACCESS, SPR_NOACCESS,
4871 &spr_read_generic, &spr_write_generic,
4872 0x00000000);
4873 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4874 SPR_NOACCESS, SPR_NOACCESS,
4875 &spr_read_mas73, &spr_write_mas73,
4876 0x00000000);
4877 ivpr_mask = (target_ulong)~0xFFFFULL;
4878 }
4879
4880 #if !defined(CONFIG_USER_ONLY)
4881 env->nb_tlb = 0;
4882 env->tlb_type = TLB_MAS;
4883 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4884 env->nb_tlb += booke206_tlb_size(env, i);
4885 }
4886 #endif
4887
4888 init_excp_e200(env, ivpr_mask);
4889 /* Allocate hardware IRQ controller */
4890 ppce500_irq_init(env);
4891 }
4892
4893 static void init_proc_e500v1(CPUPPCState *env)
4894 {
4895 init_proc_e500(env, fsl_e500v1);
4896 }
4897
4898 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4899 {
4900 DeviceClass *dc = DEVICE_CLASS(oc);
4901 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4902
4903 dc->desc = "e500v1 core";
4904 pcc->init_proc = init_proc_e500v1;
4905 pcc->check_pow = check_pow_hid0;
4906 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4907 PPC_SPE | PPC_SPE_SINGLE |
4908 PPC_WRTEE | PPC_RFDI |
4909 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4910 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4911 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4912 pcc->insns_flags2 = PPC2_BOOKE206;
4913 pcc->msr_mask = (1ull << MSR_UCLE) |
4914 (1ull << MSR_SPE) |
4915 (1ull << MSR_POW) |
4916 (1ull << MSR_CE) |
4917 (1ull << MSR_EE) |
4918 (1ull << MSR_PR) |
4919 (1ull << MSR_FP) |
4920 (1ull << MSR_ME) |
4921 (1ull << MSR_FE0) |
4922 (1ull << MSR_DWE) |
4923 (1ull << MSR_DE) |
4924 (1ull << MSR_FE1) |
4925 (1ull << MSR_IR) |
4926 (1ull << MSR_DR);
4927 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4928 pcc->excp_model = POWERPC_EXCP_BOOKE;
4929 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4930 pcc->bfd_mach = bfd_mach_ppc_860;
4931 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4932 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4933 POWERPC_FLAG_BUS_CLK;
4934 }
4935
4936 static void init_proc_e500v2(CPUPPCState *env)
4937 {
4938 init_proc_e500(env, fsl_e500v2);
4939 }
4940
4941 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4942 {
4943 DeviceClass *dc = DEVICE_CLASS(oc);
4944 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4945
4946 dc->desc = "e500v2 core";
4947 pcc->init_proc = init_proc_e500v2;
4948 pcc->check_pow = check_pow_hid0;
4949 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4950 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4951 PPC_WRTEE | PPC_RFDI |
4952 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4953 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4954 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4955 pcc->insns_flags2 = PPC2_BOOKE206;
4956 pcc->msr_mask = (1ull << MSR_UCLE) |
4957 (1ull << MSR_SPE) |
4958 (1ull << MSR_POW) |
4959 (1ull << MSR_CE) |
4960 (1ull << MSR_EE) |
4961 (1ull << MSR_PR) |
4962 (1ull << MSR_FP) |
4963 (1ull << MSR_ME) |
4964 (1ull << MSR_FE0) |
4965 (1ull << MSR_DWE) |
4966 (1ull << MSR_DE) |
4967 (1ull << MSR_FE1) |
4968 (1ull << MSR_IR) |
4969 (1ull << MSR_DR);
4970 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4971 pcc->excp_model = POWERPC_EXCP_BOOKE;
4972 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4973 pcc->bfd_mach = bfd_mach_ppc_860;
4974 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4975 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4976 POWERPC_FLAG_BUS_CLK;
4977 }
4978
4979 static void init_proc_e500mc(CPUPPCState *env)
4980 {
4981 init_proc_e500(env, fsl_e500mc);
4982 }
4983
4984 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4985 {
4986 DeviceClass *dc = DEVICE_CLASS(oc);
4987 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4988
4989 dc->desc = "e500mc core";
4990 pcc->init_proc = init_proc_e500mc;
4991 pcc->check_pow = check_pow_none;
4992 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4993 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4994 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4995 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4996 PPC_FLOAT | PPC_FLOAT_FRES |
4997 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4998 PPC_FLOAT_STFIWX | PPC_WAIT |
4999 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5000 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
5001 pcc->msr_mask = (1ull << MSR_GS) |
5002 (1ull << MSR_UCLE) |
5003 (1ull << MSR_CE) |
5004 (1ull << MSR_EE) |
5005 (1ull << MSR_PR) |
5006 (1ull << MSR_FP) |
5007 (1ull << MSR_ME) |
5008 (1ull << MSR_FE0) |
5009 (1ull << MSR_DE) |
5010 (1ull << MSR_FE1) |
5011 (1ull << MSR_IR) |
5012 (1ull << MSR_DR) |
5013 (1ull << MSR_PX) |
5014 (1ull << MSR_RI);
5015 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5016 pcc->excp_model = POWERPC_EXCP_BOOKE;
5017 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5018 /* FIXME: figure out the correct flag for e500mc */
5019 pcc->bfd_mach = bfd_mach_ppc_e500;
5020 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5021 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5022 }
5023
5024 #ifdef TARGET_PPC64
5025 static void init_proc_e5500(CPUPPCState *env)
5026 {
5027 init_proc_e500(env, fsl_e5500);
5028 }
5029
5030 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
5031 {
5032 DeviceClass *dc = DEVICE_CLASS(oc);
5033 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5034
5035 dc->desc = "e5500 core";
5036 pcc->init_proc = init_proc_e5500;
5037 pcc->check_pow = check_pow_none;
5038 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5039 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5040 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5041 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5042 PPC_FLOAT | PPC_FLOAT_FRES |
5043 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5044 PPC_FLOAT_STFIWX | PPC_WAIT |
5045 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
5046 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
5047 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \
5048 PPC2_FP_CVT_S64;
5049 pcc->msr_mask = (1ull << MSR_CM) |
5050 (1ull << MSR_GS) |
5051 (1ull << MSR_UCLE) |
5052 (1ull << MSR_CE) |
5053 (1ull << MSR_EE) |
5054 (1ull << MSR_PR) |
5055 (1ull << MSR_FP) |
5056 (1ull << MSR_ME) |
5057 (1ull << MSR_FE0) |
5058 (1ull << MSR_DE) |
5059 (1ull << MSR_FE1) |
5060 (1ull << MSR_IR) |
5061 (1ull << MSR_DR) |
5062 (1ull << MSR_PX) |
5063 (1ull << MSR_RI);
5064 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5065 pcc->excp_model = POWERPC_EXCP_BOOKE;
5066 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5067 /* FIXME: figure out the correct flag for e5500 */
5068 pcc->bfd_mach = bfd_mach_ppc_e500;
5069 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5070 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5071 }
5072 #endif
5073
5074 /* Non-embedded PowerPC */
5075
5076 /* POWER : same as 601, without mfmsr, mfsr */
5077 POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
5078 {
5079 DeviceClass *dc = DEVICE_CLASS(oc);
5080 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5081
5082 dc->desc = "POWER";
5083 /* pcc->insns_flags = XXX_TODO; */
5084 /* POWER RSC (from RAD6000) */
5085 pcc->msr_mask = (1ull << MSR_EE) |
5086 (1ull << MSR_PR) |
5087 (1ull << MSR_FP) |
5088 (1ull << MSR_ME) |
5089 (1ull << MSR_FE0) |
5090 (1ull << MSR_SE) |
5091 (1ull << MSR_DE) |
5092 (1ull << MSR_AL) |
5093 (1ull << MSR_EP) |
5094 (1ull << MSR_IR) |
5095 (1ull << MSR_DR);
5096 }
5097
5098 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
5099
5100 static void init_proc_601 (CPUPPCState *env)
5101 {
5102 gen_spr_ne_601(env);
5103 gen_spr_601(env);
5104 /* Hardware implementation registers */
5105 /* XXX : not implemented */
5106 spr_register(env, SPR_HID0, "HID0",
5107 SPR_NOACCESS, SPR_NOACCESS,
5108 &spr_read_generic, &spr_write_hid0_601,
5109 0x80010080);
5110 /* XXX : not implemented */
5111 spr_register(env, SPR_HID1, "HID1",
5112 SPR_NOACCESS, SPR_NOACCESS,
5113 &spr_read_generic, &spr_write_generic,
5114 0x00000000);
5115 /* XXX : not implemented */
5116 spr_register(env, SPR_601_HID2, "HID2",
5117 SPR_NOACCESS, SPR_NOACCESS,
5118 &spr_read_generic, &spr_write_generic,
5119 0x00000000);
5120 /* XXX : not implemented */
5121 spr_register(env, SPR_601_HID5, "HID5",
5122 SPR_NOACCESS, SPR_NOACCESS,
5123 &spr_read_generic, &spr_write_generic,
5124 0x00000000);
5125 /* Memory management */
5126 init_excp_601(env);
5127 /* XXX: beware that dcache line size is 64
5128 * but dcbz uses 32 bytes "sectors"
5129 * XXX: this breaks clcs instruction !
5130 */
5131 env->dcache_line_size = 32;
5132 env->icache_line_size = 64;
5133 /* Allocate hardware IRQ controller */
5134 ppc6xx_irq_init(env);
5135 }
5136
5137 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
5138 {
5139 DeviceClass *dc = DEVICE_CLASS(oc);
5140 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5141
5142 dc->desc = "PowerPC 601";
5143 pcc->init_proc = init_proc_601;
5144 pcc->check_pow = check_pow_none;
5145 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5146 PPC_FLOAT |
5147 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5148 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5149 PPC_SEGMENT | PPC_EXTERN;
5150 pcc->msr_mask = (1ull << MSR_EE) |
5151 (1ull << MSR_PR) |
5152 (1ull << MSR_FP) |
5153 (1ull << MSR_ME) |
5154 (1ull << MSR_FE0) |
5155 (1ull << MSR_SE) |
5156 (1ull << MSR_FE1) |
5157 (1ull << MSR_EP) |
5158 (1ull << MSR_IR) |
5159 (1ull << MSR_DR);
5160 pcc->mmu_model = POWERPC_MMU_601;
5161 #if defined(CONFIG_SOFTMMU)
5162 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5163 #endif
5164 pcc->excp_model = POWERPC_EXCP_601;
5165 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5166 pcc->bfd_mach = bfd_mach_ppc_601;
5167 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5168 }
5169
5170 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
5171
5172 static void init_proc_601v (CPUPPCState *env)
5173 {
5174 init_proc_601(env);
5175 /* XXX : not implemented */
5176 spr_register(env, SPR_601_HID15, "HID15",
5177 SPR_NOACCESS, SPR_NOACCESS,
5178 &spr_read_generic, &spr_write_generic,
5179 0x00000000);
5180 }
5181
5182 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
5183 {
5184 DeviceClass *dc = DEVICE_CLASS(oc);
5185 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5186
5187 dc->desc = "PowerPC 601v";
5188 pcc->init_proc = init_proc_601v;
5189 pcc->check_pow = check_pow_none;
5190 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5191 PPC_FLOAT |
5192 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5193 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5194 PPC_SEGMENT | PPC_EXTERN;
5195 pcc->msr_mask = (1ull << MSR_EE) |
5196 (1ull << MSR_PR) |
5197 (1ull << MSR_FP) |
5198 (1ull << MSR_ME) |
5199 (1ull << MSR_FE0) |
5200 (1ull << MSR_SE) |
5201 (1ull << MSR_FE1) |
5202 (1ull << MSR_EP) |
5203 (1ull << MSR_IR) |
5204 (1ull << MSR_DR);
5205 pcc->mmu_model = POWERPC_MMU_601;
5206 #if defined(CONFIG_SOFTMMU)
5207 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5208 #endif
5209 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5210 pcc->bfd_mach = bfd_mach_ppc_601;
5211 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5212 }
5213
5214 static void init_proc_602 (CPUPPCState *env)
5215 {
5216 gen_spr_ne_601(env);
5217 gen_spr_602(env);
5218 /* Time base */
5219 gen_tbl(env);
5220 /* hardware implementation registers */
5221 /* XXX : not implemented */
5222 spr_register(env, SPR_HID0, "HID0",
5223 SPR_NOACCESS, SPR_NOACCESS,
5224 &spr_read_generic, &spr_write_generic,
5225 0x00000000);
5226 /* XXX : not implemented */
5227 spr_register(env, SPR_HID1, "HID1",
5228 SPR_NOACCESS, SPR_NOACCESS,
5229 &spr_read_generic, &spr_write_generic,
5230 0x00000000);
5231 /* Memory management */
5232 gen_low_BATs(env);
5233 gen_6xx_7xx_soft_tlb(env, 64, 2);
5234 init_excp_602(env);
5235 env->dcache_line_size = 32;
5236 env->icache_line_size = 32;
5237 /* Allocate hardware IRQ controller */
5238 ppc6xx_irq_init(env);
5239 }
5240
5241 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5242 {
5243 DeviceClass *dc = DEVICE_CLASS(oc);
5244 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5245
5246 dc->desc = "PowerPC 602";
5247 pcc->init_proc = init_proc_602;
5248 pcc->check_pow = check_pow_hid0;
5249 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5250 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5251 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5252 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5253 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5254 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5255 PPC_SEGMENT | PPC_602_SPEC;
5256 pcc->msr_mask = (1ull << MSR_VSX) |
5257 (1ull << MSR_SA) |
5258 (1ull << MSR_POW) |
5259 (1ull << MSR_TGPR) |
5260 (1ull << MSR_ILE) |
5261 (1ull << MSR_EE) |
5262 (1ull << MSR_PR) |
5263 (1ull << MSR_FP) |
5264 (1ull << MSR_ME) |
5265 (1ull << MSR_FE0) |
5266 (1ull << MSR_SE) |
5267 (1ull << MSR_DE) |
5268 (1ull << MSR_FE1) |
5269 (1ull << MSR_EP) |
5270 (1ull << MSR_IR) |
5271 (1ull << MSR_DR) |
5272 (1ull << MSR_RI) |
5273 (1ull << MSR_LE);
5274 /* XXX: 602 MMU is quite specific. Should add a special case */
5275 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5276 pcc->excp_model = POWERPC_EXCP_602;
5277 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5278 pcc->bfd_mach = bfd_mach_ppc_602;
5279 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5280 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5281 }
5282
5283 static void init_proc_603 (CPUPPCState *env)
5284 {
5285 gen_spr_ne_601(env);
5286 gen_spr_603(env);
5287 /* Time base */
5288 gen_tbl(env);
5289 /* hardware implementation registers */
5290 /* XXX : not implemented */
5291 spr_register(env, SPR_HID0, "HID0",
5292 SPR_NOACCESS, SPR_NOACCESS,
5293 &spr_read_generic, &spr_write_generic,
5294 0x00000000);
5295 /* XXX : not implemented */
5296 spr_register(env, SPR_HID1, "HID1",
5297 SPR_NOACCESS, SPR_NOACCESS,
5298 &spr_read_generic, &spr_write_generic,
5299 0x00000000);
5300 /* Memory management */
5301 gen_low_BATs(env);
5302 gen_6xx_7xx_soft_tlb(env, 64, 2);
5303 init_excp_603(env);
5304 env->dcache_line_size = 32;
5305 env->icache_line_size = 32;
5306 /* Allocate hardware IRQ controller */
5307 ppc6xx_irq_init(env);
5308 }
5309
5310 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5311 {
5312 DeviceClass *dc = DEVICE_CLASS(oc);
5313 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5314
5315 dc->desc = "PowerPC 603";
5316 pcc->init_proc = init_proc_603;
5317 pcc->check_pow = check_pow_hid0;
5318 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5319 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5320 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5321 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5322 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5323 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5324 PPC_SEGMENT | PPC_EXTERN;
5325 pcc->msr_mask = (1ull << MSR_POW) |
5326 (1ull << MSR_TGPR) |
5327 (1ull << MSR_ILE) |
5328 (1ull << MSR_EE) |
5329 (1ull << MSR_PR) |
5330 (1ull << MSR_FP) |
5331 (1ull << MSR_ME) |
5332 (1ull << MSR_FE0) |
5333 (1ull << MSR_SE) |
5334 (1ull << MSR_DE) |
5335 (1ull << MSR_FE1) |
5336 (1ull << MSR_EP) |
5337 (1ull << MSR_IR) |
5338 (1ull << MSR_DR) |
5339 (1ull << MSR_RI) |
5340 (1ull << MSR_LE);
5341 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5342 pcc->excp_model = POWERPC_EXCP_603;
5343 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5344 pcc->bfd_mach = bfd_mach_ppc_603;
5345 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5346 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5347 }
5348
5349 static void init_proc_603E (CPUPPCState *env)
5350 {
5351 gen_spr_ne_601(env);
5352 gen_spr_603(env);
5353 /* Time base */
5354 gen_tbl(env);
5355 /* hardware implementation registers */
5356 /* XXX : not implemented */
5357 spr_register(env, SPR_HID0, "HID0",
5358 SPR_NOACCESS, SPR_NOACCESS,
5359 &spr_read_generic, &spr_write_generic,
5360 0x00000000);
5361 /* XXX : not implemented */
5362 spr_register(env, SPR_HID1, "HID1",
5363 SPR_NOACCESS, SPR_NOACCESS,
5364 &spr_read_generic, &spr_write_generic,
5365 0x00000000);
5366 /* Memory management */
5367 gen_low_BATs(env);
5368 gen_6xx_7xx_soft_tlb(env, 64, 2);
5369 init_excp_603(env);
5370 env->dcache_line_size = 32;
5371 env->icache_line_size = 32;
5372 /* Allocate hardware IRQ controller */
5373 ppc6xx_irq_init(env);
5374 }
5375
5376 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5377 {
5378 DeviceClass *dc = DEVICE_CLASS(oc);
5379 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5380
5381 dc->desc = "PowerPC 603e";
5382 pcc->init_proc = init_proc_603E;
5383 pcc->check_pow = check_pow_hid0;
5384 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5385 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5386 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5387 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5388 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5389 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5390 PPC_SEGMENT | PPC_EXTERN;
5391 pcc->msr_mask = (1ull << MSR_POW) |
5392 (1ull << MSR_TGPR) |
5393 (1ull << MSR_ILE) |
5394 (1ull << MSR_EE) |
5395 (1ull << MSR_PR) |
5396 (1ull << MSR_FP) |
5397 (1ull << MSR_ME) |
5398 (1ull << MSR_FE0) |
5399 (1ull << MSR_SE) |
5400 (1ull << MSR_DE) |
5401 (1ull << MSR_FE1) |
5402 (1ull << MSR_EP) |
5403 (1ull << MSR_IR) |
5404 (1ull << MSR_DR) |
5405 (1ull << MSR_RI) |
5406 (1ull << MSR_LE);
5407 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5408 pcc->excp_model = POWERPC_EXCP_603E;
5409 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5410 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5411 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5412 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5413 }
5414
5415 static void init_proc_604 (CPUPPCState *env)
5416 {
5417 gen_spr_ne_601(env);
5418 gen_spr_604(env);
5419 /* Time base */
5420 gen_tbl(env);
5421 /* Hardware implementation registers */
5422 /* XXX : not implemented */
5423 spr_register(env, SPR_HID0, "HID0",
5424 SPR_NOACCESS, SPR_NOACCESS,
5425 &spr_read_generic, &spr_write_generic,
5426 0x00000000);
5427 /* Memory management */
5428 gen_low_BATs(env);
5429 init_excp_604(env);
5430 env->dcache_line_size = 32;
5431 env->icache_line_size = 32;
5432 /* Allocate hardware IRQ controller */
5433 ppc6xx_irq_init(env);
5434 }
5435
5436 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5437 {
5438 DeviceClass *dc = DEVICE_CLASS(oc);
5439 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5440
5441 dc->desc = "PowerPC 604";
5442 pcc->init_proc = init_proc_604;
5443 pcc->check_pow = check_pow_nocheck;
5444 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5445 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5446 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5447 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5448 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5449 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5450 PPC_SEGMENT | PPC_EXTERN;
5451 pcc->msr_mask = (1ull << MSR_POW) |
5452 (1ull << MSR_ILE) |
5453 (1ull << MSR_EE) |
5454 (1ull << MSR_PR) |
5455 (1ull << MSR_FP) |
5456 (1ull << MSR_ME) |
5457 (1ull << MSR_FE0) |
5458 (1ull << MSR_SE) |
5459 (1ull << MSR_DE) |
5460 (1ull << MSR_FE1) |
5461 (1ull << MSR_EP) |
5462 (1ull << MSR_IR) |
5463 (1ull << MSR_DR) |
5464 (1ull << MSR_PMM) |
5465 (1ull << MSR_RI) |
5466 (1ull << MSR_LE);
5467 pcc->mmu_model = POWERPC_MMU_32B;
5468 #if defined(CONFIG_SOFTMMU)
5469 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5470 #endif
5471 pcc->excp_model = POWERPC_EXCP_604;
5472 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5473 pcc->bfd_mach = bfd_mach_ppc_604;
5474 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5475 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5476 }
5477
5478 static void init_proc_604E (CPUPPCState *env)
5479 {
5480 gen_spr_ne_601(env);
5481 gen_spr_604(env);
5482 /* XXX : not implemented */
5483 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
5484 SPR_NOACCESS, SPR_NOACCESS,
5485 &spr_read_generic, &spr_write_generic,
5486 0x00000000);
5487 /* XXX : not implemented */
5488 spr_register(env, SPR_7XX_PMC3, "PMC3",
5489 SPR_NOACCESS, SPR_NOACCESS,
5490 &spr_read_generic, &spr_write_generic,
5491 0x00000000);
5492 /* XXX : not implemented */
5493 spr_register(env, SPR_7XX_PMC4, "PMC4",
5494 SPR_NOACCESS, SPR_NOACCESS,
5495 &spr_read_generic, &spr_write_generic,
5496 0x00000000);
5497 /* Time base */
5498 gen_tbl(env);
5499 /* Hardware implementation registers */
5500 /* XXX : not implemented */
5501 spr_register(env, SPR_HID0, "HID0",
5502 SPR_NOACCESS, SPR_NOACCESS,
5503 &spr_read_generic, &spr_write_generic,
5504 0x00000000);
5505 /* XXX : not implemented */
5506 spr_register(env, SPR_HID1, "HID1",
5507 SPR_NOACCESS, SPR_NOACCESS,
5508 &spr_read_generic, &spr_write_generic,
5509 0x00000000);
5510 /* Memory management */
5511 gen_low_BATs(env);
5512 init_excp_604(env);
5513 env->dcache_line_size = 32;
5514 env->icache_line_size = 32;
5515 /* Allocate hardware IRQ controller */
5516 ppc6xx_irq_init(env);
5517 }
5518
5519 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5520 {
5521 DeviceClass *dc = DEVICE_CLASS(oc);
5522 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5523
5524 dc->desc = "PowerPC 604E";
5525 pcc->init_proc = init_proc_604E;
5526 pcc->check_pow = check_pow_nocheck;
5527 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5528 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5529 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5530 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5531 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5532 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5533 PPC_SEGMENT | PPC_EXTERN;
5534 pcc->msr_mask = (1ull << MSR_POW) |
5535 (1ull << MSR_ILE) |
5536 (1ull << MSR_EE) |
5537 (1ull << MSR_PR) |
5538 (1ull << MSR_FP) |
5539 (1ull << MSR_ME) |
5540 (1ull << MSR_FE0) |
5541 (1ull << MSR_SE) |
5542 (1ull << MSR_DE) |
5543 (1ull << MSR_FE1) |
5544 (1ull << MSR_EP) |
5545 (1ull << MSR_IR) |
5546 (1ull << MSR_DR) |
5547 (1ull << MSR_PMM) |
5548 (1ull << MSR_RI) |
5549 (1ull << MSR_LE);
5550 pcc->mmu_model = POWERPC_MMU_32B;
5551 #if defined(CONFIG_SOFTMMU)
5552 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5553 #endif
5554 pcc->excp_model = POWERPC_EXCP_604;
5555 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5556 pcc->bfd_mach = bfd_mach_ppc_604;
5557 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5558 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5559 }
5560
5561 static void init_proc_740 (CPUPPCState *env)
5562 {
5563 gen_spr_ne_601(env);
5564 gen_spr_7xx(env);
5565 /* Time base */
5566 gen_tbl(env);
5567 /* Thermal management */
5568 gen_spr_thrm(env);
5569 /* Hardware implementation registers */
5570 /* XXX : not implemented */
5571 spr_register(env, SPR_HID0, "HID0",
5572 SPR_NOACCESS, SPR_NOACCESS,
5573 &spr_read_generic, &spr_write_generic,
5574 0x00000000);
5575 /* XXX : not implemented */
5576 spr_register(env, SPR_HID1, "HID1",
5577 SPR_NOACCESS, SPR_NOACCESS,
5578 &spr_read_generic, &spr_write_generic,
5579 0x00000000);
5580 /* Memory management */
5581 gen_low_BATs(env);
5582 init_excp_7x0(env);
5583 env->dcache_line_size = 32;
5584 env->icache_line_size = 32;
5585 /* Allocate hardware IRQ controller */
5586 ppc6xx_irq_init(env);
5587 }
5588
5589 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5590 {
5591 DeviceClass *dc = DEVICE_CLASS(oc);
5592 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5593
5594 dc->desc = "PowerPC 740";
5595 pcc->init_proc = init_proc_740;
5596 pcc->check_pow = check_pow_hid0;
5597 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5598 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5599 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5600 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5601 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5602 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5603 PPC_SEGMENT | PPC_EXTERN;
5604 pcc->msr_mask = (1ull << MSR_POW) |
5605 (1ull << MSR_ILE) |
5606 (1ull << MSR_EE) |
5607 (1ull << MSR_PR) |
5608 (1ull << MSR_FP) |
5609 (1ull << MSR_ME) |
5610 (1ull << MSR_FE0) |
5611 (1ull << MSR_SE) |
5612 (1ull << MSR_DE) |
5613 (1ull << MSR_FE1) |
5614 (1ull << MSR_EP) |
5615 (1ull << MSR_IR) |
5616 (1ull << MSR_DR) |
5617 (1ull << MSR_PMM) |
5618 (1ull << MSR_RI) |
5619 (1ull << MSR_LE);
5620 pcc->mmu_model = POWERPC_MMU_32B;
5621 #if defined(CONFIG_SOFTMMU)
5622 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5623 #endif
5624 pcc->excp_model = POWERPC_EXCP_7x0;
5625 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5626 pcc->bfd_mach = bfd_mach_ppc_750;
5627 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5628 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5629 }
5630
5631 static void init_proc_750 (CPUPPCState *env)
5632 {
5633 gen_spr_ne_601(env);
5634 gen_spr_7xx(env);
5635 /* XXX : not implemented */
5636 spr_register(env, SPR_L2CR, "L2CR",
5637 SPR_NOACCESS, SPR_NOACCESS,
5638 &spr_read_generic, spr_access_nop,
5639 0x00000000);
5640 /* Time base */
5641 gen_tbl(env);
5642 /* Thermal management */
5643 gen_spr_thrm(env);
5644 /* Hardware implementation registers */
5645 /* XXX : not implemented */
5646 spr_register(env, SPR_HID0, "HID0",
5647 SPR_NOACCESS, SPR_NOACCESS,
5648 &spr_read_generic, &spr_write_generic,
5649 0x00000000);
5650 /* XXX : not implemented */
5651 spr_register(env, SPR_HID1, "HID1",
5652 SPR_NOACCESS, SPR_NOACCESS,
5653 &spr_read_generic, &spr_write_generic,
5654 0x00000000);
5655 /* Memory management */
5656 gen_low_BATs(env);
5657 /* XXX: high BATs are also present but are known to be bugged on
5658 * die version 1.x
5659 */
5660 init_excp_7x0(env);
5661 env->dcache_line_size = 32;
5662 env->icache_line_size = 32;
5663 /* Allocate hardware IRQ controller */
5664 ppc6xx_irq_init(env);
5665 }
5666
5667 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5668 {
5669 DeviceClass *dc = DEVICE_CLASS(oc);
5670 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5671
5672 dc->desc = "PowerPC 750";
5673 pcc->init_proc = init_proc_750;
5674 pcc->check_pow = check_pow_hid0;
5675 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5676 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5677 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5678 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5679 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5680 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5681 PPC_SEGMENT | PPC_EXTERN;
5682 pcc->msr_mask = (1ull << MSR_POW) |
5683 (1ull << MSR_ILE) |
5684 (1ull << MSR_EE) |
5685 (1ull << MSR_PR) |
5686 (1ull << MSR_FP) |
5687 (1ull << MSR_ME) |
5688 (1ull << MSR_FE0) |
5689 (1ull << MSR_SE) |
5690 (1ull << MSR_DE) |
5691 (1ull << MSR_FE1) |
5692 (1ull << MSR_EP) |
5693 (1ull << MSR_IR) |
5694 (1ull << MSR_DR) |
5695 (1ull << MSR_PMM) |
5696 (1ull << MSR_RI) |
5697 (1ull << MSR_LE);
5698 pcc->mmu_model = POWERPC_MMU_32B;
5699 #if defined(CONFIG_SOFTMMU)
5700 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5701 #endif
5702 pcc->excp_model = POWERPC_EXCP_7x0;
5703 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5704 pcc->bfd_mach = bfd_mach_ppc_750;
5705 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5706 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5707 }
5708
5709 static void init_proc_750cl (CPUPPCState *env)
5710 {
5711 gen_spr_ne_601(env);
5712 gen_spr_7xx(env);
5713 /* XXX : not implemented */
5714 spr_register(env, SPR_L2CR, "L2CR",
5715 SPR_NOACCESS, SPR_NOACCESS,
5716 &spr_read_generic, spr_access_nop,
5717 0x00000000);
5718 /* Time base */
5719 gen_tbl(env);
5720 /* Thermal management */
5721 /* Those registers are fake on 750CL */
5722 spr_register(env, SPR_THRM1, "THRM1",
5723 SPR_NOACCESS, SPR_NOACCESS,
5724 &spr_read_generic, &spr_write_generic,
5725 0x00000000);
5726 spr_register(env, SPR_THRM2, "THRM2",
5727 SPR_NOACCESS, SPR_NOACCESS,
5728 &spr_read_generic, &spr_write_generic,
5729 0x00000000);
5730 spr_register(env, SPR_THRM3, "THRM3",
5731 SPR_NOACCESS, SPR_NOACCESS,
5732 &spr_read_generic, &spr_write_generic,
5733 0x00000000);
5734 /* XXX: not implemented */
5735 spr_register(env, SPR_750_TDCL, "TDCL",
5736 SPR_NOACCESS, SPR_NOACCESS,
5737 &spr_read_generic, &spr_write_generic,
5738 0x00000000);
5739 spr_register(env, SPR_750_TDCH, "TDCH",
5740 SPR_NOACCESS, SPR_NOACCESS,
5741 &spr_read_generic, &spr_write_generic,
5742 0x00000000);
5743 /* DMA */
5744 /* XXX : not implemented */
5745 spr_register(env, SPR_750_WPAR, "WPAR",
5746 SPR_NOACCESS, SPR_NOACCESS,
5747 &spr_read_generic, &spr_write_generic,
5748 0x00000000);
5749 spr_register(env, SPR_750_DMAL, "DMAL",
5750 SPR_NOACCESS, SPR_NOACCESS,
5751 &spr_read_generic, &spr_write_generic,
5752 0x00000000);
5753 spr_register(env, SPR_750_DMAU, "DMAU",
5754 SPR_NOACCESS, SPR_NOACCESS,
5755 &spr_read_generic, &spr_write_generic,
5756 0x00000000);
5757 /* Hardware implementation registers */
5758 /* XXX : not implemented */
5759 spr_register(env, SPR_HID0, "HID0",
5760 SPR_NOACCESS, SPR_NOACCESS,
5761 &spr_read_generic, &spr_write_generic,
5762 0x00000000);
5763 /* XXX : not implemented */
5764 spr_register(env, SPR_HID1, "HID1",
5765 SPR_NOACCESS, SPR_NOACCESS,
5766 &spr_read_generic, &spr_write_generic,
5767 0x00000000);
5768 /* XXX : not implemented */
5769 spr_register(env, SPR_750CL_HID2, "HID2",
5770 SPR_NOACCESS, SPR_NOACCESS,
5771 &spr_read_generic, &spr_write_generic,
5772 0x00000000);
5773 /* XXX : not implemented */
5774 spr_register(env, SPR_750CL_HID4, "HID4",
5775 SPR_NOACCESS, SPR_NOACCESS,
5776 &spr_read_generic, &spr_write_generic,
5777 0x00000000);
5778 /* Quantization registers */
5779 /* XXX : not implemented */
5780 spr_register(env, SPR_750_GQR0, "GQR0",
5781 SPR_NOACCESS, SPR_NOACCESS,
5782 &spr_read_generic, &spr_write_generic,
5783 0x00000000);
5784 /* XXX : not implemented */
5785 spr_register(env, SPR_750_GQR1, "GQR1",
5786 SPR_NOACCESS, SPR_NOACCESS,
5787 &spr_read_generic, &spr_write_generic,
5788 0x00000000);
5789 /* XXX : not implemented */
5790 spr_register(env, SPR_750_GQR2, "GQR2",
5791 SPR_NOACCESS, SPR_NOACCESS,
5792 &spr_read_generic, &spr_write_generic,
5793 0x00000000);
5794 /* XXX : not implemented */
5795 spr_register(env, SPR_750_GQR3, "GQR3",
5796 SPR_NOACCESS, SPR_NOACCESS,
5797 &spr_read_generic, &spr_write_generic,
5798 0x00000000);
5799 /* XXX : not implemented */
5800 spr_register(env, SPR_750_GQR4, "GQR4",
5801 SPR_NOACCESS, SPR_NOACCESS,
5802 &spr_read_generic, &spr_write_generic,
5803 0x00000000);
5804 /* XXX : not implemented */
5805 spr_register(env, SPR_750_GQR5, "GQR5",
5806 SPR_NOACCESS, SPR_NOACCESS,
5807 &spr_read_generic, &spr_write_generic,
5808 0x00000000);
5809 /* XXX : not implemented */
5810 spr_register(env, SPR_750_GQR6, "GQR6",
5811 SPR_NOACCESS, SPR_NOACCESS,
5812 &spr_read_generic, &spr_write_generic,
5813 0x00000000);
5814 /* XXX : not implemented */
5815 spr_register(env, SPR_750_GQR7, "GQR7",
5816 SPR_NOACCESS, SPR_NOACCESS,
5817 &spr_read_generic, &spr_write_generic,
5818 0x00000000);
5819 /* Memory management */
5820 gen_low_BATs(env);
5821 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5822 gen_high_BATs(env);
5823 init_excp_750cl(env);
5824 env->dcache_line_size = 32;
5825 env->icache_line_size = 32;
5826 /* Allocate hardware IRQ controller */
5827 ppc6xx_irq_init(env);
5828 }
5829
5830 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5831 {
5832 DeviceClass *dc = DEVICE_CLASS(oc);
5833 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5834
5835 dc->desc = "PowerPC 750 CL";
5836 pcc->init_proc = init_proc_750cl;
5837 pcc->check_pow = check_pow_hid0;
5838 /* XXX: not implemented:
5839 * cache lock instructions:
5840 * dcbz_l
5841 * floating point paired instructions
5842 * psq_lux
5843 * psq_lx
5844 * psq_stux
5845 * psq_stx
5846 * ps_abs
5847 * ps_add
5848 * ps_cmpo0
5849 * ps_cmpo1
5850 * ps_cmpu0
5851 * ps_cmpu1
5852 * ps_div
5853 * ps_madd
5854 * ps_madds0
5855 * ps_madds1
5856 * ps_merge00
5857 * ps_merge01
5858 * ps_merge10
5859 * ps_merge11
5860 * ps_mr
5861 * ps_msub
5862 * ps_mul
5863 * ps_muls0
5864 * ps_muls1
5865 * ps_nabs
5866 * ps_neg
5867 * ps_nmadd
5868 * ps_nmsub
5869 * ps_res
5870 * ps_rsqrte
5871 * ps_sel
5872 * ps_sub
5873 * ps_sum0
5874 * ps_sum1
5875 */
5876 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5877 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5878 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5879 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5880 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5881 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5882 PPC_SEGMENT | PPC_EXTERN;
5883 pcc->msr_mask = (1ull << MSR_POW) |
5884 (1ull << MSR_ILE) |
5885 (1ull << MSR_EE) |
5886 (1ull << MSR_PR) |
5887 (1ull << MSR_FP) |
5888 (1ull << MSR_ME) |
5889 (1ull << MSR_FE0) |
5890 (1ull << MSR_SE) |
5891 (1ull << MSR_DE) |
5892 (1ull << MSR_FE1) |
5893 (1ull << MSR_EP) |
5894 (1ull << MSR_IR) |
5895 (1ull << MSR_DR) |
5896 (1ull << MSR_PMM) |
5897 (1ull << MSR_RI) |
5898 (1ull << MSR_LE);
5899 pcc->mmu_model = POWERPC_MMU_32B;
5900 #if defined(CONFIG_SOFTMMU)
5901 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5902 #endif
5903 pcc->excp_model = POWERPC_EXCP_7x0;
5904 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5905 pcc->bfd_mach = bfd_mach_ppc_750;
5906 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5907 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5908 }
5909
5910 static void init_proc_750cx (CPUPPCState *env)
5911 {
5912 gen_spr_ne_601(env);
5913 gen_spr_7xx(env);
5914 /* XXX : not implemented */
5915 spr_register(env, SPR_L2CR, "L2CR",
5916 SPR_NOACCESS, SPR_NOACCESS,
5917 &spr_read_generic, spr_access_nop,
5918 0x00000000);
5919 /* Time base */
5920 gen_tbl(env);
5921 /* Thermal management */
5922 gen_spr_thrm(env);
5923 /* This register is not implemented but is present for compatibility */
5924 spr_register(env, SPR_SDA, "SDA",
5925 SPR_NOACCESS, SPR_NOACCESS,
5926 &spr_read_generic, &spr_write_generic,
5927 0x00000000);
5928 /* Hardware implementation registers */
5929 /* XXX : not implemented */
5930 spr_register(env, SPR_HID0, "HID0",
5931 SPR_NOACCESS, SPR_NOACCESS,
5932 &spr_read_generic, &spr_write_generic,
5933 0x00000000);
5934 /* XXX : not implemented */
5935 spr_register(env, SPR_HID1, "HID1",
5936 SPR_NOACCESS, SPR_NOACCESS,
5937 &spr_read_generic, &spr_write_generic,
5938 0x00000000);
5939 /* Memory management */
5940 gen_low_BATs(env);
5941 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5942 gen_high_BATs(env);
5943 init_excp_750cx(env);
5944 env->dcache_line_size = 32;
5945 env->icache_line_size = 32;
5946 /* Allocate hardware IRQ controller */
5947 ppc6xx_irq_init(env);
5948 }
5949
5950 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5951 {
5952 DeviceClass *dc = DEVICE_CLASS(oc);
5953 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5954
5955 dc->desc = "PowerPC 750CX";
5956 pcc->init_proc = init_proc_750cx;
5957 pcc->check_pow = check_pow_hid0;
5958 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5959 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5960 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5961 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5962 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5963 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5964 PPC_SEGMENT | PPC_EXTERN;
5965 pcc->msr_mask = (1ull << MSR_POW) |
5966 (1ull << MSR_ILE) |
5967 (1ull << MSR_EE) |
5968 (1ull << MSR_PR) |
5969 (1ull << MSR_FP) |
5970 (1ull << MSR_ME) |
5971 (1ull << MSR_FE0) |
5972 (1ull << MSR_SE) |
5973 (1ull << MSR_DE) |
5974 (1ull << MSR_FE1) |
5975 (1ull << MSR_EP) |
5976 (1ull << MSR_IR) |
5977 (1ull << MSR_DR) |
5978 (1ull << MSR_PMM) |
5979 (1ull << MSR_RI) |
5980 (1ull << MSR_LE);
5981 pcc->mmu_model = POWERPC_MMU_32B;
5982 #if defined(CONFIG_SOFTMMU)
5983 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5984 #endif
5985 pcc->excp_model = POWERPC_EXCP_7x0;
5986 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5987 pcc->bfd_mach = bfd_mach_ppc_750;
5988 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5989 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5990 }
5991
5992 static void init_proc_750fx (CPUPPCState *env)
5993 {
5994 gen_spr_ne_601(env);
5995 gen_spr_7xx(env);
5996 /* XXX : not implemented */
5997 spr_register(env, SPR_L2CR, "L2CR",
5998 SPR_NOACCESS, SPR_NOACCESS,
5999 &spr_read_generic, spr_access_nop,
6000 0x00000000);
6001 /* Time base */
6002 gen_tbl(env);
6003 /* Thermal management */
6004 gen_spr_thrm(env);
6005 /* XXX : not implemented */
6006 spr_register(env, SPR_750_THRM4, "THRM4",
6007 SPR_NOACCESS, SPR_NOACCESS,
6008 &spr_read_generic, &spr_write_generic,
6009 0x00000000);
6010 /* Hardware implementation registers */
6011 /* XXX : not implemented */
6012 spr_register(env, SPR_HID0, "HID0",
6013 SPR_NOACCESS, SPR_NOACCESS,
6014 &spr_read_generic, &spr_write_generic,
6015 0x00000000);
6016 /* XXX : not implemented */
6017 spr_register(env, SPR_HID1, "HID1",
6018 SPR_NOACCESS, SPR_NOACCESS,
6019 &spr_read_generic, &spr_write_generic,
6020 0x00000000);
6021 /* XXX : not implemented */
6022 spr_register(env, SPR_750FX_HID2, "HID2",
6023 SPR_NOACCESS, SPR_NOACCESS,
6024 &spr_read_generic, &spr_write_generic,
6025 0x00000000);
6026 /* Memory management */
6027 gen_low_BATs(env);
6028 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6029 gen_high_BATs(env);
6030 init_excp_7x0(env);
6031 env->dcache_line_size = 32;
6032 env->icache_line_size = 32;
6033 /* Allocate hardware IRQ controller */
6034 ppc6xx_irq_init(env);
6035 }
6036
6037 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
6038 {
6039 DeviceClass *dc = DEVICE_CLASS(oc);
6040 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6041
6042 dc->desc = "PowerPC 750FX";
6043 pcc->init_proc = init_proc_750fx;
6044 pcc->check_pow = check_pow_hid0;
6045 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6046 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6047 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6048 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6049 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6050 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6051 PPC_SEGMENT | PPC_EXTERN;
6052 pcc->msr_mask = (1ull << MSR_POW) |
6053 (1ull << MSR_ILE) |
6054 (1ull << MSR_EE) |
6055 (1ull << MSR_PR) |
6056 (1ull << MSR_FP) |
6057 (1ull << MSR_ME) |
6058 (1ull << MSR_FE0) |
6059 (1ull << MSR_SE) |
6060 (1ull << MSR_DE) |
6061 (1ull << MSR_FE1) |
6062 (1ull << MSR_EP) |
6063 (1ull << MSR_IR) |
6064 (1ull << MSR_DR) |
6065 (1ull << MSR_PMM) |
6066 (1ull << MSR_RI) |
6067 (1ull << MSR_LE);
6068 pcc->mmu_model = POWERPC_MMU_32B;
6069 #if defined(CONFIG_SOFTMMU)
6070 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6071 #endif
6072 pcc->excp_model = POWERPC_EXCP_7x0;
6073 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6074 pcc->bfd_mach = bfd_mach_ppc_750;
6075 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6076 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6077 }
6078
6079 static void init_proc_750gx (CPUPPCState *env)
6080 {
6081 gen_spr_ne_601(env);
6082 gen_spr_7xx(env);
6083 /* XXX : not implemented (XXX: different from 750fx) */
6084 spr_register(env, SPR_L2CR, "L2CR",
6085 SPR_NOACCESS, SPR_NOACCESS,
6086 &spr_read_generic, spr_access_nop,
6087 0x00000000);
6088 /* Time base */
6089 gen_tbl(env);
6090 /* Thermal management */
6091 gen_spr_thrm(env);
6092 /* XXX : not implemented */
6093 spr_register(env, SPR_750_THRM4, "THRM4",
6094 SPR_NOACCESS, SPR_NOACCESS,
6095 &spr_read_generic, &spr_write_generic,
6096 0x00000000);
6097 /* Hardware implementation registers */
6098 /* XXX : not implemented (XXX: different from 750fx) */
6099 spr_register(env, SPR_HID0, "HID0",
6100 SPR_NOACCESS, SPR_NOACCESS,
6101 &spr_read_generic, &spr_write_generic,
6102 0x00000000);
6103 /* XXX : not implemented */
6104 spr_register(env, SPR_HID1, "HID1",
6105 SPR_NOACCESS, SPR_NOACCESS,
6106 &spr_read_generic, &spr_write_generic,
6107 0x00000000);
6108 /* XXX : not implemented (XXX: different from 750fx) */
6109 spr_register(env, SPR_750FX_HID2, "HID2",
6110 SPR_NOACCESS, SPR_NOACCESS,
6111 &spr_read_generic, &spr_write_generic,
6112 0x00000000);
6113 /* Memory management */
6114 gen_low_BATs(env);
6115 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6116 gen_high_BATs(env);
6117 init_excp_7x0(env);
6118 env->dcache_line_size = 32;
6119 env->icache_line_size = 32;
6120 /* Allocate hardware IRQ controller */
6121 ppc6xx_irq_init(env);
6122 }
6123
6124 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
6125 {
6126 DeviceClass *dc = DEVICE_CLASS(oc);
6127 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6128
6129 dc->desc = "PowerPC 750GX";
6130 pcc->init_proc = init_proc_750gx;
6131 pcc->check_pow = check_pow_hid0;
6132 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6133 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6134 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6135 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6136 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6137 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6138 PPC_SEGMENT | PPC_EXTERN;
6139 pcc->msr_mask = (1ull << MSR_POW) |
6140 (1ull << MSR_ILE) |
6141 (1ull << MSR_EE) |
6142 (1ull << MSR_PR) |
6143 (1ull << MSR_FP) |
6144 (1ull << MSR_ME) |
6145 (1ull << MSR_FE0) |
6146 (1ull << MSR_SE) |
6147 (1ull << MSR_DE) |
6148 (1ull << MSR_FE1) |
6149 (1ull << MSR_EP) |
6150 (1ull << MSR_IR) |
6151 (1ull << MSR_DR) |
6152 (1ull << MSR_PMM) |
6153 (1ull << MSR_RI) |
6154 (1ull << MSR_LE);
6155 pcc->mmu_model = POWERPC_MMU_32B;
6156 #if defined(CONFIG_SOFTMMU)
6157 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6158 #endif
6159 pcc->excp_model = POWERPC_EXCP_7x0;
6160 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6161 pcc->bfd_mach = bfd_mach_ppc_750;
6162 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6163 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6164 }
6165
6166 static void init_proc_745 (CPUPPCState *env)
6167 {
6168 gen_spr_ne_601(env);
6169 gen_spr_7xx(env);
6170 gen_spr_G2_755(env);
6171 /* Time base */
6172 gen_tbl(env);
6173 /* Thermal management */
6174 gen_spr_thrm(env);
6175 /* Hardware implementation registers */
6176 /* XXX : not implemented */
6177 spr_register(env, SPR_HID0, "HID0",
6178 SPR_NOACCESS, SPR_NOACCESS,
6179 &spr_read_generic, &spr_write_generic,
6180 0x00000000);
6181 /* XXX : not implemented */
6182 spr_register(env, SPR_HID1, "HID1",
6183 SPR_NOACCESS, SPR_NOACCESS,
6184 &spr_read_generic, &spr_write_generic,
6185 0x00000000);
6186 /* XXX : not implemented */
6187 spr_register(env, SPR_HID2, "HID2",
6188 SPR_NOACCESS, SPR_NOACCESS,
6189 &spr_read_generic, &spr_write_generic,
6190 0x00000000);
6191 /* Memory management */
6192 gen_low_BATs(env);
6193 gen_high_BATs(env);
6194 gen_6xx_7xx_soft_tlb(env, 64, 2);
6195 init_excp_7x5(env);
6196 env->dcache_line_size = 32;
6197 env->icache_line_size = 32;
6198 /* Allocate hardware IRQ controller */
6199 ppc6xx_irq_init(env);
6200 }
6201
6202 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
6203 {
6204 DeviceClass *dc = DEVICE_CLASS(oc);
6205 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6206
6207 dc->desc = "PowerPC 745";
6208 pcc->init_proc = init_proc_745;
6209 pcc->check_pow = check_pow_hid0;
6210 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6211 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6212 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6213 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6214 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6215 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6216 PPC_SEGMENT | PPC_EXTERN;
6217 pcc->msr_mask = (1ull << MSR_POW) |
6218 (1ull << MSR_ILE) |
6219 (1ull << MSR_EE) |
6220 (1ull << MSR_PR) |
6221 (1ull << MSR_FP) |
6222 (1ull << MSR_ME) |
6223 (1ull << MSR_FE0) |
6224 (1ull << MSR_SE) |
6225 (1ull << MSR_DE) |
6226 (1ull << MSR_FE1) |
6227 (1ull << MSR_EP) |
6228 (1ull << MSR_IR) |
6229 (1ull << MSR_DR) |
6230 (1ull << MSR_PMM) |
6231 (1ull << MSR_RI) |
6232 (1ull << MSR_LE);
6233 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6234 pcc->excp_model = POWERPC_EXCP_7x5;
6235 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6236 pcc->bfd_mach = bfd_mach_ppc_750;
6237 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6238 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6239 }
6240
6241 static void init_proc_755 (CPUPPCState *env)
6242 {
6243 gen_spr_ne_601(env);
6244 gen_spr_7xx(env);
6245 gen_spr_G2_755(env);
6246 /* Time base */
6247 gen_tbl(env);
6248 /* L2 cache control */
6249 /* XXX : not implemented */
6250 spr_register(env, SPR_L2CR, "L2CR",
6251 SPR_NOACCESS, SPR_NOACCESS,
6252 &spr_read_generic, spr_access_nop,
6253 0x00000000);
6254 /* XXX : not implemented */
6255 spr_register(env, SPR_L2PMCR, "L2PMCR",
6256 SPR_NOACCESS, SPR_NOACCESS,
6257 &spr_read_generic, &spr_write_generic,
6258 0x00000000);
6259 /* Thermal management */
6260 gen_spr_thrm(env);
6261 /* Hardware implementation registers */
6262 /* XXX : not implemented */
6263 spr_register(env, SPR_HID0, "HID0",
6264 SPR_NOACCESS, SPR_NOACCESS,
6265 &spr_read_generic, &spr_write_generic,
6266 0x00000000);
6267 /* XXX : not implemented */
6268 spr_register(env, SPR_HID1, "HID1",
6269 SPR_NOACCESS, SPR_NOACCESS,
6270 &spr_read_generic, &spr_write_generic,
6271 0x00000000);
6272 /* XXX : not implemented */
6273 spr_register(env, SPR_HID2, "HID2",
6274 SPR_NOACCESS, SPR_NOACCESS,
6275 &spr_read_generic, &spr_write_generic,
6276 0x00000000);
6277 /* Memory management */
6278 gen_low_BATs(env);
6279 gen_high_BATs(env);
6280 gen_6xx_7xx_soft_tlb(env, 64, 2);
6281 init_excp_7x5(env);
6282 env->dcache_line_size = 32;
6283 env->icache_line_size = 32;
6284 /* Allocate hardware IRQ controller */
6285 ppc6xx_irq_init(env);
6286 }
6287
6288 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
6289 {
6290 DeviceClass *dc = DEVICE_CLASS(oc);
6291 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6292
6293 dc->desc = "PowerPC 755";
6294 pcc->init_proc = init_proc_755;
6295 pcc->check_pow = check_pow_hid0;
6296 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6297 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6298 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6299 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6300 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6301 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6302 PPC_SEGMENT | PPC_EXTERN;
6303 pcc->msr_mask = (1ull << MSR_POW) |
6304 (1ull << MSR_ILE) |
6305 (1ull << MSR_EE) |
6306 (1ull << MSR_PR) |
6307 (1ull << MSR_FP) |
6308 (1ull << MSR_ME) |
6309 (1ull << MSR_FE0) |
6310 (1ull << MSR_SE) |
6311 (1ull << MSR_DE) |
6312 (1ull << MSR_FE1) |
6313 (1ull << MSR_EP) |
6314 (1ull << MSR_IR) |
6315 (1ull << MSR_DR) |
6316 (1ull << MSR_PMM) |
6317 (1ull << MSR_RI) |
6318 (1ull << MSR_LE);
6319 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6320 pcc->excp_model = POWERPC_EXCP_7x5;
6321 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6322 pcc->bfd_mach = bfd_mach_ppc_750;
6323 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6324 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6325 }
6326
6327 static void init_proc_7400 (CPUPPCState *env)
6328 {
6329 gen_spr_ne_601(env);
6330 gen_spr_7xx(env);
6331 /* Time base */
6332 gen_tbl(env);
6333 /* 74xx specific SPR */
6334 gen_spr_74xx(env);
6335 /* XXX : not implemented */
6336 spr_register(env, SPR_UBAMR, "UBAMR",
6337 &spr_read_ureg, SPR_NOACCESS,
6338 &spr_read_ureg, SPR_NOACCESS,
6339 0x00000000);
6340 /* XXX: this seems not implemented on all revisions. */
6341 /* XXX : not implemented */
6342 spr_register(env, SPR_MSSCR1, "MSSCR1",
6343 SPR_NOACCESS, SPR_NOACCESS,
6344 &spr_read_generic, &spr_write_generic,
6345 0x00000000);
6346 /* Thermal management */
6347 gen_spr_thrm(env);
6348 /* Memory management */
6349 gen_low_BATs(env);
6350 init_excp_7400(env);
6351 env->dcache_line_size = 32;
6352 env->icache_line_size = 32;
6353 /* Allocate hardware IRQ controller */
6354 ppc6xx_irq_init(env);
6355 }
6356
6357 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
6358 {
6359 DeviceClass *dc = DEVICE_CLASS(oc);
6360 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6361
6362 dc->desc = "PowerPC 7400 (aka G4)";
6363 pcc->init_proc = init_proc_7400;
6364 pcc->check_pow = check_pow_hid0;
6365 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6366 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6367 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6368 PPC_FLOAT_STFIWX |
6369 PPC_CACHE | PPC_CACHE_ICBI |
6370 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6371 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6372 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6373 PPC_MEM_TLBIA |
6374 PPC_SEGMENT | PPC_EXTERN |
6375 PPC_ALTIVEC;
6376 pcc->msr_mask = (1ull << MSR_VR) |
6377 (1ull << MSR_POW) |
6378 (1ull << MSR_ILE) |
6379 (1ull << MSR_EE) |
6380 (1ull << MSR_PR) |
6381 (1ull << MSR_FP) |
6382 (1ull << MSR_ME) |
6383 (1ull << MSR_FE0) |
6384 (1ull << MSR_SE) |
6385 (1ull << MSR_DE) |
6386 (1ull << MSR_FE1) |
6387 (1ull << MSR_EP) |
6388 (1ull << MSR_IR) |
6389 (1ull << MSR_DR) |
6390 (1ull << MSR_PMM) |
6391 (1ull << MSR_RI) |
6392 (1ull << MSR_LE);
6393 pcc->mmu_model = POWERPC_MMU_32B;
6394 #if defined(CONFIG_SOFTMMU)
6395 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6396 #endif
6397 pcc->excp_model = POWERPC_EXCP_74xx;
6398 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6399 pcc->bfd_mach = bfd_mach_ppc_7400;
6400 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6401 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6402 POWERPC_FLAG_BUS_CLK;
6403 }
6404
6405 static void init_proc_7410 (CPUPPCState *env)
6406 {
6407 gen_spr_ne_601(env);
6408 gen_spr_7xx(env);
6409 /* Time base */
6410 gen_tbl(env);
6411 /* 74xx specific SPR */
6412 gen_spr_74xx(env);
6413 /* XXX : not implemented */
6414 spr_register(env, SPR_UBAMR, "UBAMR",
6415 &spr_read_ureg, SPR_NOACCESS,
6416 &spr_read_ureg, SPR_NOACCESS,
6417 0x00000000);
6418 /* Thermal management */
6419 gen_spr_thrm(env);
6420 /* L2PMCR */
6421 /* XXX : not implemented */
6422 spr_register(env, SPR_L2PMCR, "L2PMCR",
6423 SPR_NOACCESS, SPR_NOACCESS,
6424 &spr_read_generic, &spr_write_generic,
6425 0x00000000);
6426 /* LDSTDB */
6427 /* XXX : not implemented */
6428 spr_register(env, SPR_LDSTDB, "LDSTDB",
6429 SPR_NOACCESS, SPR_NOACCESS,
6430 &spr_read_generic, &spr_write_generic,
6431 0x00000000);
6432 /* Memory management */
6433 gen_low_BATs(env);
6434 init_excp_7400(env);
6435 env->dcache_line_size = 32;
6436 env->icache_line_size = 32;
6437 /* Allocate hardware IRQ controller */
6438 ppc6xx_irq_init(env);
6439 }
6440
6441 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
6442 {
6443 DeviceClass *dc = DEVICE_CLASS(oc);
6444 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6445
6446 dc->desc = "PowerPC 7410 (aka G4)";
6447 pcc->init_proc = init_proc_7410;
6448 pcc->check_pow = check_pow_hid0;
6449 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6450 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6451 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6452 PPC_FLOAT_STFIWX |
6453 PPC_CACHE | PPC_CACHE_ICBI |
6454 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6455 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6456 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6457 PPC_MEM_TLBIA |
6458 PPC_SEGMENT | PPC_EXTERN |
6459 PPC_ALTIVEC;
6460 pcc->msr_mask = (1ull << MSR_VR) |
6461 (1ull << MSR_POW) |
6462 (1ull << MSR_ILE) |
6463 (1ull << MSR_EE) |
6464 (1ull << MSR_PR) |
6465 (1ull << MSR_FP) |
6466 (1ull << MSR_ME) |
6467 (1ull << MSR_FE0) |
6468 (1ull << MSR_SE) |
6469 (1ull << MSR_DE) |
6470 (1ull << MSR_FE1) |
6471 (1ull << MSR_EP) |
6472 (1ull << MSR_IR) |
6473 (1ull << MSR_DR) |
6474 (1ull << MSR_PMM) |
6475 (1ull << MSR_RI) |
6476 (1ull << MSR_LE);
6477 pcc->mmu_model = POWERPC_MMU_32B;
6478 #if defined(CONFIG_SOFTMMU)
6479 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6480 #endif
6481 pcc->excp_model = POWERPC_EXCP_74xx;
6482 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6483 pcc->bfd_mach = bfd_mach_ppc_7400;
6484 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6485 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6486 POWERPC_FLAG_BUS_CLK;
6487 }
6488
6489 static void init_proc_7440 (CPUPPCState *env)
6490 {
6491 gen_spr_ne_601(env);
6492 gen_spr_7xx(env);
6493 /* Time base */
6494 gen_tbl(env);
6495 /* 74xx specific SPR */
6496 gen_spr_74xx(env);
6497 /* XXX : not implemented */
6498 spr_register(env, SPR_UBAMR, "UBAMR",
6499 &spr_read_ureg, SPR_NOACCESS,
6500 &spr_read_ureg, SPR_NOACCESS,
6501 0x00000000);
6502 /* LDSTCR */
6503 /* XXX : not implemented */
6504 spr_register(env, SPR_LDSTCR, "LDSTCR",
6505 SPR_NOACCESS, SPR_NOACCESS,
6506 &spr_read_generic, &spr_write_generic,
6507 0x00000000);
6508 /* ICTRL */
6509 /* XXX : not implemented */
6510 spr_register(env, SPR_ICTRL, "ICTRL",
6511 SPR_NOACCESS, SPR_NOACCESS,
6512 &spr_read_generic, &spr_write_generic,
6513 0x00000000);
6514 /* MSSSR0 */
6515 /* XXX : not implemented */
6516 spr_register(env, SPR_MSSSR0, "MSSSR0",
6517 SPR_NOACCESS, SPR_NOACCESS,
6518 &spr_read_generic, &spr_write_generic,
6519 0x00000000);
6520 /* PMC */
6521 /* XXX : not implemented */
6522 spr_register(env, SPR_7XX_PMC5, "PMC5",
6523 SPR_NOACCESS, SPR_NOACCESS,
6524 &spr_read_generic, &spr_write_generic,
6525 0x00000000);
6526 /* XXX : not implemented */
6527 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6528 &spr_read_ureg, SPR_NOACCESS,
6529 &spr_read_ureg, SPR_NOACCESS,
6530 0x00000000);
6531 /* XXX : not implemented */
6532 spr_register(env, SPR_7XX_PMC6, "PMC6",
6533 SPR_NOACCESS, SPR_NOACCESS,
6534 &spr_read_generic, &spr_write_generic,
6535 0x00000000);
6536 /* XXX : not implemented */
6537 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6538 &spr_read_ureg, SPR_NOACCESS,
6539 &spr_read_ureg, SPR_NOACCESS,
6540 0x00000000);
6541 /* Memory management */
6542 gen_low_BATs(env);
6543 gen_74xx_soft_tlb(env, 128, 2);
6544 init_excp_7450(env);
6545 env->dcache_line_size = 32;
6546 env->icache_line_size = 32;
6547 /* Allocate hardware IRQ controller */
6548 ppc6xx_irq_init(env);
6549 }
6550
6551 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6552 {
6553 DeviceClass *dc = DEVICE_CLASS(oc);
6554 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6555
6556 dc->desc = "PowerPC 7440 (aka G4)";
6557 pcc->init_proc = init_proc_7440;
6558 pcc->check_pow = check_pow_hid0_74xx;
6559 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6560 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6561 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6562 PPC_FLOAT_STFIWX |
6563 PPC_CACHE | PPC_CACHE_ICBI |
6564 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6565 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6566 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6567 PPC_MEM_TLBIA | PPC_74xx_TLB |
6568 PPC_SEGMENT | PPC_EXTERN |
6569 PPC_ALTIVEC;
6570 pcc->msr_mask = (1ull << MSR_VR) |
6571 (1ull << MSR_POW) |
6572 (1ull << MSR_ILE) |
6573 (1ull << MSR_EE) |
6574 (1ull << MSR_PR) |
6575 (1ull << MSR_FP) |
6576 (1ull << MSR_ME) |
6577 (1ull << MSR_FE0) |
6578 (1ull << MSR_SE) |
6579 (1ull << MSR_DE) |
6580 (1ull << MSR_FE1) |
6581 (1ull << MSR_EP) |
6582 (1ull << MSR_IR) |
6583 (1ull << MSR_DR) |
6584 (1ull << MSR_PMM) |
6585 (1ull << MSR_RI) |
6586 (1ull << MSR_LE);
6587 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6588 pcc->excp_model = POWERPC_EXCP_74xx;
6589 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6590 pcc->bfd_mach = bfd_mach_ppc_7400;
6591 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6592 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6593 POWERPC_FLAG_BUS_CLK;
6594 }
6595
6596 static void init_proc_7450 (CPUPPCState *env)
6597 {
6598 gen_spr_ne_601(env);
6599 gen_spr_7xx(env);
6600 /* Time base */
6601 gen_tbl(env);
6602 /* 74xx specific SPR */
6603 gen_spr_74xx(env);
6604 /* Level 3 cache control */
6605 gen_l3_ctrl(env);
6606 /* L3ITCR1 */
6607 /* XXX : not implemented */
6608 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6609 SPR_NOACCESS, SPR_NOACCESS,
6610 &spr_read_generic, &spr_write_generic,
6611 0x00000000);
6612 /* L3ITCR2 */
6613 /* XXX : not implemented */
6614 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6615 SPR_NOACCESS, SPR_NOACCESS,
6616 &spr_read_generic, &spr_write_generic,
6617 0x00000000);
6618 /* L3ITCR3 */
6619 /* XXX : not implemented */
6620 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6621 SPR_NOACCESS, SPR_NOACCESS,
6622 &spr_read_generic, &spr_write_generic,
6623 0x00000000);
6624 /* L3OHCR */
6625 /* XXX : not implemented */
6626 spr_register(env, SPR_L3OHCR, "L3OHCR",
6627 SPR_NOACCESS, SPR_NOACCESS,
6628 &spr_read_generic, &spr_write_generic,
6629 0x00000000);
6630 /* XXX : not implemented */
6631 spr_register(env, SPR_UBAMR, "UBAMR",
6632 &spr_read_ureg, SPR_NOACCESS,
6633 &spr_read_ureg, SPR_NOACCESS,
6634 0x00000000);
6635 /* LDSTCR */
6636 /* XXX : not implemented */
6637 spr_register(env, SPR_LDSTCR, "LDSTCR",
6638 SPR_NOACCESS, SPR_NOACCESS,
6639 &spr_read_generic, &spr_write_generic,
6640 0x00000000);
6641 /* ICTRL */
6642 /* XXX : not implemented */
6643 spr_register(env, SPR_ICTRL, "ICTRL",
6644 SPR_NOACCESS, SPR_NOACCESS,
6645 &spr_read_generic, &spr_write_generic,
6646 0x00000000);
6647 /* MSSSR0 */
6648 /* XXX : not implemented */
6649 spr_register(env, SPR_MSSSR0, "MSSSR0",
6650 SPR_NOACCESS, SPR_NOACCESS,
6651 &spr_read_generic, &spr_write_generic,
6652 0x00000000);
6653 /* PMC */
6654 /* XXX : not implemented */
6655 spr_register(env, SPR_7XX_PMC5, "PMC5",
6656 SPR_NOACCESS, SPR_NOACCESS,
6657 &spr_read_generic, &spr_write_generic,
6658 0x00000000);
6659 /* XXX : not implemented */
6660 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6661 &spr_read_ureg, SPR_NOACCESS,
6662 &spr_read_ureg, SPR_NOACCESS,
6663 0x00000000);
6664 /* XXX : not implemented */
6665 spr_register(env, SPR_7XX_PMC6, "PMC6",
6666 SPR_NOACCESS, SPR_NOACCESS,
6667 &spr_read_generic, &spr_write_generic,
6668 0x00000000);
6669 /* XXX : not implemented */
6670 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6671 &spr_read_ureg, SPR_NOACCESS,
6672 &spr_read_ureg, SPR_NOACCESS,
6673 0x00000000);
6674 /* Memory management */
6675 gen_low_BATs(env);
6676 gen_74xx_soft_tlb(env, 128, 2);
6677 init_excp_7450(env);
6678 env->dcache_line_size = 32;
6679 env->icache_line_size = 32;
6680 /* Allocate hardware IRQ controller */
6681 ppc6xx_irq_init(env);
6682 }
6683
6684 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6685 {
6686 DeviceClass *dc = DEVICE_CLASS(oc);
6687 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6688
6689 dc->desc = "PowerPC 7450 (aka G4)";
6690 pcc->init_proc = init_proc_7450;
6691 pcc->check_pow = check_pow_hid0_74xx;
6692 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6693 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6694 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6695 PPC_FLOAT_STFIWX |
6696 PPC_CACHE | PPC_CACHE_ICBI |
6697 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6698 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6699 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6700 PPC_MEM_TLBIA | PPC_74xx_TLB |
6701 PPC_SEGMENT | PPC_EXTERN |
6702 PPC_ALTIVEC;
6703 pcc->msr_mask = (1ull << MSR_VR) |
6704 (1ull << MSR_POW) |
6705 (1ull << MSR_ILE) |
6706 (1ull << MSR_EE) |
6707 (1ull << MSR_PR) |
6708 (1ull << MSR_FP) |
6709 (1ull << MSR_ME) |
6710 (1ull << MSR_FE0) |
6711 (1ull << MSR_SE) |
6712 (1ull << MSR_DE) |
6713 (1ull << MSR_FE1) |
6714 (1ull << MSR_EP) |
6715 (1ull << MSR_IR) |
6716 (1ull << MSR_DR) |
6717 (1ull << MSR_PMM) |
6718 (1ull << MSR_RI) |
6719 (1ull << MSR_LE);
6720 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6721 pcc->excp_model = POWERPC_EXCP_74xx;
6722 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6723 pcc->bfd_mach = bfd_mach_ppc_7400;
6724 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6725 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6726 POWERPC_FLAG_BUS_CLK;
6727 }
6728
6729 static void init_proc_7445 (CPUPPCState *env)
6730 {
6731 gen_spr_ne_601(env);
6732 gen_spr_7xx(env);
6733 /* Time base */
6734 gen_tbl(env);
6735 /* 74xx specific SPR */
6736 gen_spr_74xx(env);
6737 /* LDSTCR */
6738 /* XXX : not implemented */
6739 spr_register(env, SPR_LDSTCR, "LDSTCR",
6740 SPR_NOACCESS, SPR_NOACCESS,
6741 &spr_read_generic, &spr_write_generic,
6742 0x00000000);
6743 /* ICTRL */
6744 /* XXX : not implemented */
6745 spr_register(env, SPR_ICTRL, "ICTRL",
6746 SPR_NOACCESS, SPR_NOACCESS,
6747 &spr_read_generic, &spr_write_generic,
6748 0x00000000);
6749 /* MSSSR0 */
6750 /* XXX : not implemented */
6751 spr_register(env, SPR_MSSSR0, "MSSSR0",
6752 SPR_NOACCESS, SPR_NOACCESS,
6753 &spr_read_generic, &spr_write_generic,
6754 0x00000000);
6755 /* PMC */
6756 /* XXX : not implemented */
6757 spr_register(env, SPR_7XX_PMC5, "PMC5",
6758 SPR_NOACCESS, SPR_NOACCESS,
6759 &spr_read_generic, &spr_write_generic,
6760 0x00000000);
6761 /* XXX : not implemented */
6762 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6763 &spr_read_ureg, SPR_NOACCESS,
6764 &spr_read_ureg, SPR_NOACCESS,
6765 0x00000000);
6766 /* XXX : not implemented */
6767 spr_register(env, SPR_7XX_PMC6, "PMC6",
6768 SPR_NOACCESS, SPR_NOACCESS,
6769 &spr_read_generic, &spr_write_generic,
6770 0x00000000);
6771 /* XXX : not implemented */
6772 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6773 &spr_read_ureg, SPR_NOACCESS,
6774 &spr_read_ureg, SPR_NOACCESS,
6775 0x00000000);
6776 /* SPRGs */
6777 spr_register(env, SPR_SPRG4, "SPRG4",
6778 SPR_NOACCESS, SPR_NOACCESS,
6779 &spr_read_generic, &spr_write_generic,
6780 0x00000000);
6781 spr_register(env, SPR_USPRG4, "USPRG4",
6782 &spr_read_ureg, SPR_NOACCESS,
6783 &spr_read_ureg, SPR_NOACCESS,
6784 0x00000000);
6785 spr_register(env, SPR_SPRG5, "SPRG5",
6786 SPR_NOACCESS, SPR_NOACCESS,
6787 &spr_read_generic, &spr_write_generic,
6788 0x00000000);
6789 spr_register(env, SPR_USPRG5, "USPRG5",
6790 &spr_read_ureg, SPR_NOACCESS,
6791 &spr_read_ureg, SPR_NOACCESS,
6792 0x00000000);
6793 spr_register(env, SPR_SPRG6, "SPRG6",
6794 SPR_NOACCESS, SPR_NOACCESS,
6795 &spr_read_generic, &spr_write_generic,
6796 0x00000000);
6797 spr_register(env, SPR_USPRG6, "USPRG6",
6798 &spr_read_ureg, SPR_NOACCESS,
6799 &spr_read_ureg, SPR_NOACCESS,
6800 0x00000000);
6801 spr_register(env, SPR_SPRG7, "SPRG7",
6802 SPR_NOACCESS, SPR_NOACCESS,
6803 &spr_read_generic, &spr_write_generic,
6804 0x00000000);
6805 spr_register(env, SPR_USPRG7, "USPRG7",
6806 &spr_read_ureg, SPR_NOACCESS,
6807 &spr_read_ureg, SPR_NOACCESS,
6808 0x00000000);
6809 /* Memory management */
6810 gen_low_BATs(env);
6811 gen_high_BATs(env);
6812 gen_74xx_soft_tlb(env, 128, 2);
6813 init_excp_7450(env);
6814 env->dcache_line_size = 32;
6815 env->icache_line_size = 32;
6816 /* Allocate hardware IRQ controller */
6817 ppc6xx_irq_init(env);
6818 }
6819
6820 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6821 {
6822 DeviceClass *dc = DEVICE_CLASS(oc);
6823 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6824
6825 dc->desc = "PowerPC 7445 (aka G4)";
6826 pcc->init_proc = init_proc_7445;
6827 pcc->check_pow = check_pow_hid0_74xx;
6828 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6829 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6830 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6831 PPC_FLOAT_STFIWX |
6832 PPC_CACHE | PPC_CACHE_ICBI |
6833 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6834 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6835 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6836 PPC_MEM_TLBIA | PPC_74xx_TLB |
6837 PPC_SEGMENT | PPC_EXTERN |
6838 PPC_ALTIVEC;
6839 pcc->msr_mask = (1ull << MSR_VR) |
6840 (1ull << MSR_POW) |
6841 (1ull << MSR_ILE) |
6842 (1ull << MSR_EE) |
6843 (1ull << MSR_PR) |
6844 (1ull << MSR_FP) |
6845 (1ull << MSR_ME) |
6846 (1ull << MSR_FE0) |
6847 (1ull << MSR_SE) |
6848 (1ull << MSR_DE) |
6849 (1ull << MSR_FE1) |
6850 (1ull << MSR_EP) |
6851 (1ull << MSR_IR) |
6852 (1ull << MSR_DR) |
6853 (1ull << MSR_PMM) |
6854 (1ull << MSR_RI) |
6855 (1ull << MSR_LE);
6856 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6857 pcc->excp_model = POWERPC_EXCP_74xx;
6858 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6859 pcc->bfd_mach = bfd_mach_ppc_7400;
6860 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6861 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6862 POWERPC_FLAG_BUS_CLK;
6863 }
6864
6865 static void init_proc_7455 (CPUPPCState *env)
6866 {
6867 gen_spr_ne_601(env);
6868 gen_spr_7xx(env);
6869 /* Time base */
6870 gen_tbl(env);
6871 /* 74xx specific SPR */
6872 gen_spr_74xx(env);
6873 /* Level 3 cache control */
6874 gen_l3_ctrl(env);
6875 /* LDSTCR */
6876 /* XXX : not implemented */
6877 spr_register(env, SPR_LDSTCR, "LDSTCR",
6878 SPR_NOACCESS, SPR_NOACCESS,
6879 &spr_read_generic, &spr_write_generic,
6880 0x00000000);
6881 /* ICTRL */
6882 /* XXX : not implemented */
6883 spr_register(env, SPR_ICTRL, "ICTRL",
6884 SPR_NOACCESS, SPR_NOACCESS,
6885 &spr_read_generic, &spr_write_generic,
6886 0x00000000);
6887 /* MSSSR0 */
6888 /* XXX : not implemented */
6889 spr_register(env, SPR_MSSSR0, "MSSSR0",
6890 SPR_NOACCESS, SPR_NOACCESS,
6891 &spr_read_generic, &spr_write_generic,
6892 0x00000000);
6893 /* PMC */
6894 /* XXX : not implemented */
6895 spr_register(env, SPR_7XX_PMC5, "PMC5",
6896 SPR_NOACCESS, SPR_NOACCESS,
6897 &spr_read_generic, &spr_write_generic,
6898 0x00000000);
6899 /* XXX : not implemented */
6900 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6901 &spr_read_ureg, SPR_NOACCESS,
6902 &spr_read_ureg, SPR_NOACCESS,
6903 0x00000000);
6904 /* XXX : not implemented */
6905 spr_register(env, SPR_7XX_PMC6, "PMC6",
6906 SPR_NOACCESS, SPR_NOACCESS,
6907 &spr_read_generic, &spr_write_generic,
6908 0x00000000);
6909 /* XXX : not implemented */
6910 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6911 &spr_read_ureg, SPR_NOACCESS,
6912 &spr_read_ureg, SPR_NOACCESS,
6913 0x00000000);
6914 /* SPRGs */
6915 spr_register(env, SPR_SPRG4, "SPRG4",
6916 SPR_NOACCESS, SPR_NOACCESS,
6917 &spr_read_generic, &spr_write_generic,
6918 0x00000000);
6919 spr_register(env, SPR_USPRG4, "USPRG4",
6920 &spr_read_ureg, SPR_NOACCESS,
6921 &spr_read_ureg, SPR_NOACCESS,
6922 0x00000000);
6923 spr_register(env, SPR_SPRG5, "SPRG5",
6924 SPR_NOACCESS, SPR_NOACCESS,
6925 &spr_read_generic, &spr_write_generic,
6926 0x00000000);
6927 spr_register(env, SPR_USPRG5, "USPRG5",
6928 &spr_read_ureg, SPR_NOACCESS,
6929 &spr_read_ureg, SPR_NOACCESS,
6930 0x00000000);
6931 spr_register(env, SPR_SPRG6, "SPRG6",
6932 SPR_NOACCESS, SPR_NOACCESS,
6933 &spr_read_generic, &spr_write_generic,
6934 0x00000000);
6935 spr_register(env, SPR_USPRG6, "USPRG6",
6936 &spr_read_ureg, SPR_NOACCESS,
6937 &spr_read_ureg, SPR_NOACCESS,
6938 0x00000000);
6939 spr_register(env, SPR_SPRG7, "SPRG7",
6940 SPR_NOACCESS, SPR_NOACCESS,
6941 &spr_read_generic, &spr_write_generic,
6942 0x00000000);
6943 spr_register(env, SPR_USPRG7, "USPRG7",
6944 &spr_read_ureg, SPR_NOACCESS,
6945 &spr_read_ureg, SPR_NOACCESS,
6946 0x00000000);
6947 /* Memory management */
6948 gen_low_BATs(env);
6949 gen_high_BATs(env);
6950 gen_74xx_soft_tlb(env, 128, 2);
6951 init_excp_7450(env);
6952 env->dcache_line_size = 32;
6953 env->icache_line_size = 32;
6954 /* Allocate hardware IRQ controller */
6955 ppc6xx_irq_init(env);
6956 }
6957
6958 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6959 {
6960 DeviceClass *dc = DEVICE_CLASS(oc);
6961 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6962
6963 dc->desc = "PowerPC 7455 (aka G4)";
6964 pcc->init_proc = init_proc_7455;
6965 pcc->check_pow = check_pow_hid0_74xx;
6966 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6967 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6968 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6969 PPC_FLOAT_STFIWX |
6970 PPC_CACHE | PPC_CACHE_ICBI |
6971 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6972 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6973 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6974 PPC_MEM_TLBIA | PPC_74xx_TLB |
6975 PPC_SEGMENT | PPC_EXTERN |
6976 PPC_ALTIVEC;
6977 pcc->msr_mask = (1ull << MSR_VR) |
6978 (1ull << MSR_POW) |
6979 (1ull << MSR_ILE) |
6980 (1ull << MSR_EE) |
6981 (1ull << MSR_PR) |
6982 (1ull << MSR_FP) |
6983 (1ull << MSR_ME) |
6984 (1ull << MSR_FE0) |
6985 (1ull << MSR_SE) |
6986 (1ull << MSR_DE) |
6987 (1ull << MSR_FE1) |
6988 (1ull << MSR_EP) |
6989 (1ull << MSR_IR) |
6990 (1ull << MSR_DR) |
6991 (1ull << MSR_PMM) |
6992 (1ull << MSR_RI) |
6993 (1ull << MSR_LE);
6994 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6995 pcc->excp_model = POWERPC_EXCP_74xx;
6996 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6997 pcc->bfd_mach = bfd_mach_ppc_7400;
6998 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6999 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7000 POWERPC_FLAG_BUS_CLK;
7001 }
7002
7003 static void init_proc_7457 (CPUPPCState *env)
7004 {
7005 gen_spr_ne_601(env);
7006 gen_spr_7xx(env);
7007 /* Time base */
7008 gen_tbl(env);
7009 /* 74xx specific SPR */
7010 gen_spr_74xx(env);
7011 /* Level 3 cache control */
7012 gen_l3_ctrl(env);
7013 /* L3ITCR1 */
7014 /* XXX : not implemented */
7015 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
7016 SPR_NOACCESS, SPR_NOACCESS,
7017 &spr_read_generic, &spr_write_generic,
7018 0x00000000);
7019 /* L3ITCR2 */
7020 /* XXX : not implemented */
7021 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
7022 SPR_NOACCESS, SPR_NOACCESS,
7023 &spr_read_generic, &spr_write_generic,
7024 0x00000000);
7025 /* L3ITCR3 */
7026 /* XXX : not implemented */
7027 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
7028 SPR_NOACCESS, SPR_NOACCESS,
7029 &spr_read_generic, &spr_write_generic,
7030 0x00000000);
7031 /* L3OHCR */
7032 /* XXX : not implemented */
7033 spr_register(env, SPR_L3OHCR, "L3OHCR",
7034 SPR_NOACCESS, SPR_NOACCESS,
7035 &spr_read_generic, &spr_write_generic,
7036 0x00000000);
7037 /* LDSTCR */
7038 /* XXX : not implemented */
7039 spr_register(env, SPR_LDSTCR, "LDSTCR",
7040 SPR_NOACCESS, SPR_NOACCESS,
7041 &spr_read_generic, &spr_write_generic,
7042 0x00000000);
7043 /* ICTRL */
7044 /* XXX : not implemented */
7045 spr_register(env, SPR_ICTRL, "ICTRL",
7046 SPR_NOACCESS, SPR_NOACCESS,
7047 &spr_read_generic, &spr_write_generic,
7048 0x00000000);
7049 /* MSSSR0 */
7050 /* XXX : not implemented */
7051 spr_register(env, SPR_MSSSR0, "MSSSR0",
7052 SPR_NOACCESS, SPR_NOACCESS,
7053 &spr_read_generic, &spr_write_generic,
7054 0x00000000);
7055 /* PMC */
7056 /* XXX : not implemented */
7057 spr_register(env, SPR_7XX_PMC5, "PMC5",
7058 SPR_NOACCESS, SPR_NOACCESS,
7059 &spr_read_generic, &spr_write_generic,
7060 0x00000000);
7061 /* XXX : not implemented */
7062 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7063 &spr_read_ureg, SPR_NOACCESS,
7064 &spr_read_ureg, SPR_NOACCESS,
7065 0x00000000);
7066 /* XXX : not implemented */
7067 spr_register(env, SPR_7XX_PMC6, "PMC6",
7068 SPR_NOACCESS, SPR_NOACCESS,
7069 &spr_read_generic, &spr_write_generic,
7070 0x00000000);
7071 /* XXX : not implemented */
7072 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7073 &spr_read_ureg, SPR_NOACCESS,
7074 &spr_read_ureg, SPR_NOACCESS,
7075 0x00000000);
7076 /* SPRGs */
7077 spr_register(env, SPR_SPRG4, "SPRG4",
7078 SPR_NOACCESS, SPR_NOACCESS,
7079 &spr_read_generic, &spr_write_generic,
7080 0x00000000);
7081 spr_register(env, SPR_USPRG4, "USPRG4",
7082 &spr_read_ureg, SPR_NOACCESS,
7083 &spr_read_ureg, SPR_NOACCESS,
7084 0x00000000);
7085 spr_register(env, SPR_SPRG5, "SPRG5",
7086 SPR_NOACCESS, SPR_NOACCESS,
7087 &spr_read_generic, &spr_write_generic,
7088 0x00000000);
7089 spr_register(env, SPR_USPRG5, "USPRG5",
7090 &spr_read_ureg, SPR_NOACCESS,
7091 &spr_read_ureg, SPR_NOACCESS,
7092 0x00000000);
7093 spr_register(env, SPR_SPRG6, "SPRG6",
7094 SPR_NOACCESS, SPR_NOACCESS,
7095 &spr_read_generic, &spr_write_generic,
7096 0x00000000);
7097 spr_register(env, SPR_USPRG6, "USPRG6",
7098 &spr_read_ureg, SPR_NOACCESS,
7099 &spr_read_ureg, SPR_NOACCESS,
7100 0x00000000);
7101 spr_register(env, SPR_SPRG7, "SPRG7",
7102 SPR_NOACCESS, SPR_NOACCESS,
7103 &spr_read_generic, &spr_write_generic,
7104 0x00000000);
7105 spr_register(env, SPR_USPRG7, "USPRG7",
7106 &spr_read_ureg, SPR_NOACCESS,
7107 &spr_read_ureg, SPR_NOACCESS,
7108 0x00000000);
7109 /* Memory management */
7110 gen_low_BATs(env);
7111 gen_high_BATs(env);
7112 gen_74xx_soft_tlb(env, 128, 2);
7113 init_excp_7450(env);
7114 env->dcache_line_size = 32;
7115 env->icache_line_size = 32;
7116 /* Allocate hardware IRQ controller */
7117 ppc6xx_irq_init(env);
7118 }
7119
7120 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
7121 {
7122 DeviceClass *dc = DEVICE_CLASS(oc);
7123 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7124
7125 dc->desc = "PowerPC 7457 (aka G4)";
7126 pcc->init_proc = init_proc_7457;
7127 pcc->check_pow = check_pow_hid0_74xx;
7128 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7129 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7130 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7131 PPC_FLOAT_STFIWX |
7132 PPC_CACHE | PPC_CACHE_ICBI |
7133 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7134 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7135 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7136 PPC_MEM_TLBIA | PPC_74xx_TLB |
7137 PPC_SEGMENT | PPC_EXTERN |
7138 PPC_ALTIVEC;
7139 pcc->msr_mask = (1ull << MSR_VR) |
7140 (1ull << MSR_POW) |
7141 (1ull << MSR_ILE) |
7142 (1ull << MSR_EE) |
7143 (1ull << MSR_PR) |
7144 (1ull << MSR_FP) |
7145 (1ull << MSR_ME) |
7146 (1ull << MSR_FE0) |
7147 (1ull << MSR_SE) |
7148 (1ull << MSR_DE) |
7149 (1ull << MSR_FE1) |
7150 (1ull << MSR_EP) |
7151 (1ull << MSR_IR) |
7152 (1ull << MSR_DR) |
7153 (1ull << MSR_PMM) |
7154 (1ull << MSR_RI) |
7155 (1ull << MSR_LE);
7156 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7157 pcc->excp_model = POWERPC_EXCP_74xx;
7158 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7159 pcc->bfd_mach = bfd_mach_ppc_7400;
7160 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7161 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7162 POWERPC_FLAG_BUS_CLK;
7163 }
7164
7165 static void init_proc_e600 (CPUPPCState *env)
7166 {
7167 gen_spr_ne_601(env);
7168 gen_spr_7xx(env);
7169 /* Time base */
7170 gen_tbl(env);
7171 /* 74xx specific SPR */
7172 gen_spr_74xx(env);
7173 /* XXX : not implemented */
7174 spr_register(env, SPR_UBAMR, "UBAMR",
7175 &spr_read_ureg, SPR_NOACCESS,
7176 &spr_read_ureg, SPR_NOACCESS,
7177 0x00000000);
7178 /* XXX : not implemented */
7179 spr_register(env, SPR_LDSTCR, "LDSTCR",
7180 SPR_NOACCESS, SPR_NOACCESS,
7181 &spr_read_generic, &spr_write_generic,
7182 0x00000000);
7183 /* XXX : not implemented */
7184 spr_register(env, SPR_ICTRL, "ICTRL",
7185 SPR_NOACCESS, SPR_NOACCESS,
7186 &spr_read_generic, &spr_write_generic,
7187 0x00000000);
7188 /* XXX : not implemented */
7189 spr_register(env, SPR_MSSSR0, "MSSSR0",
7190 SPR_NOACCESS, SPR_NOACCESS,
7191 &spr_read_generic, &spr_write_generic,
7192 0x00000000);
7193 /* XXX : not implemented */
7194 spr_register(env, SPR_7XX_PMC5, "PMC5",
7195 SPR_NOACCESS, SPR_NOACCESS,
7196 &spr_read_generic, &spr_write_generic,
7197 0x00000000);
7198 /* XXX : not implemented */
7199 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7200 &spr_read_ureg, SPR_NOACCESS,
7201 &spr_read_ureg, SPR_NOACCESS,
7202 0x00000000);
7203 /* XXX : not implemented */
7204 spr_register(env, SPR_7XX_PMC6, "PMC6",
7205 SPR_NOACCESS, SPR_NOACCESS,
7206 &spr_read_generic, &spr_write_generic,
7207 0x00000000);
7208 /* XXX : not implemented */
7209 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7210 &spr_read_ureg, SPR_NOACCESS,
7211 &spr_read_ureg, SPR_NOACCESS,
7212 0x00000000);
7213 /* SPRGs */
7214 spr_register(env, SPR_SPRG4, "SPRG4",
7215 SPR_NOACCESS, SPR_NOACCESS,
7216 &spr_read_generic, &spr_write_generic,
7217 0x00000000);
7218 spr_register(env, SPR_USPRG4, "USPRG4",
7219 &spr_read_ureg, SPR_NOACCESS,
7220 &spr_read_ureg, SPR_NOACCESS,
7221 0x00000000);
7222 spr_register(env, SPR_SPRG5, "SPRG5",
7223 SPR_NOACCESS, SPR_NOACCESS,
7224 &spr_read_generic, &spr_write_generic,
7225 0x00000000);
7226 spr_register(env, SPR_USPRG5, "USPRG5",
7227 &spr_read_ureg, SPR_NOACCESS,
7228 &spr_read_ureg, SPR_NOACCESS,
7229 0x00000000);
7230 spr_register(env, SPR_SPRG6, "SPRG6",
7231 SPR_NOACCESS, SPR_NOACCESS,
7232 &spr_read_generic, &spr_write_generic,
7233 0x00000000);
7234 spr_register(env, SPR_USPRG6, "USPRG6",
7235 &spr_read_ureg, SPR_NOACCESS,
7236 &spr_read_ureg, SPR_NOACCESS,
7237 0x00000000);
7238 spr_register(env, SPR_SPRG7, "SPRG7",
7239 SPR_NOACCESS, SPR_NOACCESS,
7240 &spr_read_generic, &spr_write_generic,
7241 0x00000000);
7242 spr_register(env, SPR_USPRG7, "USPRG7",
7243 &spr_read_ureg, SPR_NOACCESS,
7244 &spr_read_ureg, SPR_NOACCESS,
7245 0x00000000);
7246 /* Memory management */
7247 gen_low_BATs(env);
7248 gen_high_BATs(env);
7249 gen_74xx_soft_tlb(env, 128, 2);
7250 init_excp_7450(env);
7251 env->dcache_line_size = 32;
7252 env->icache_line_size = 32;
7253 /* Allocate hardware IRQ controller */
7254 ppc6xx_irq_init(env);
7255 }
7256
7257 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
7258 {
7259 DeviceClass *dc = DEVICE_CLASS(oc);
7260 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7261
7262 dc->desc = "PowerPC e600";
7263 pcc->init_proc = init_proc_e600;
7264 pcc->check_pow = check_pow_hid0_74xx;
7265 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7266 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7267 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7268 PPC_FLOAT_STFIWX |
7269 PPC_CACHE | PPC_CACHE_ICBI |
7270 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7271 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7272 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7273 PPC_MEM_TLBIA | PPC_74xx_TLB |
7274 PPC_SEGMENT | PPC_EXTERN |
7275 PPC_ALTIVEC;
7276 pcc->insns_flags2 = PPC_NONE;
7277 pcc->msr_mask = (1ull << MSR_VR) |
7278 (1ull << MSR_POW) |
7279 (1ull << MSR_ILE) |
7280 (1ull << MSR_EE) |
7281 (1ull << MSR_PR) |
7282 (1ull << MSR_FP) |
7283 (1ull << MSR_ME) |
7284 (1ull << MSR_FE0) |
7285 (1ull << MSR_SE) |
7286 (1ull << MSR_DE) |
7287 (1ull << MSR_FE1) |
7288 (1ull << MSR_EP) |
7289 (1ull << MSR_IR) |
7290 (1ull << MSR_DR) |
7291 (1ull << MSR_PMM) |
7292 (1ull << MSR_RI) |
7293 (1ull << MSR_LE);
7294 pcc->mmu_model = POWERPC_MMU_32B;
7295 #if defined(CONFIG_SOFTMMU)
7296 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
7297 #endif
7298 pcc->excp_model = POWERPC_EXCP_74xx;
7299 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7300 pcc->bfd_mach = bfd_mach_ppc_7400;
7301 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7302 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7303 POWERPC_FLAG_BUS_CLK;
7304 }
7305
7306 #if defined (TARGET_PPC64)
7307 #if defined(CONFIG_USER_ONLY)
7308 #define POWERPC970_HID5_INIT 0x00000080
7309 #else
7310 #define POWERPC970_HID5_INIT 0x00000000
7311 #endif
7312
7313 enum BOOK3S_CPU_TYPE {
7314 BOOK3S_CPU_970,
7315 BOOK3S_CPU_POWER5PLUS,
7316 BOOK3S_CPU_POWER6,
7317 BOOK3S_CPU_POWER7,
7318 BOOK3S_CPU_POWER8
7319 };
7320
7321 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
7322 int bit, int sprn, int cause)
7323 {
7324 TCGv_i32 t1 = tcg_const_i32(bit);
7325 TCGv_i32 t2 = tcg_const_i32(sprn);
7326 TCGv_i32 t3 = tcg_const_i32(cause);
7327
7328 gen_update_current_nip(ctx);
7329 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
7330
7331 tcg_temp_free_i32(t3);
7332 tcg_temp_free_i32(t2);
7333 tcg_temp_free_i32(t1);
7334 }
7335
7336 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
7337 int bit, int sprn, int cause)
7338 {
7339 TCGv_i32 t1 = tcg_const_i32(bit);
7340 TCGv_i32 t2 = tcg_const_i32(sprn);
7341 TCGv_i32 t3 = tcg_const_i32(cause);
7342
7343 gen_update_current_nip(ctx);
7344 gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
7345
7346 tcg_temp_free_i32(t3);
7347 tcg_temp_free_i32(t2);
7348 tcg_temp_free_i32(t1);
7349 }
7350
7351 static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
7352 {
7353 TCGv spr_up = tcg_temp_new();
7354 TCGv spr = tcg_temp_new();
7355
7356 gen_load_spr(spr, sprn - 1);
7357 tcg_gen_shri_tl(spr_up, spr, 32);
7358 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
7359
7360 tcg_temp_free(spr);
7361 tcg_temp_free(spr_up);
7362 }
7363
7364 static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
7365 {
7366 TCGv spr = tcg_temp_new();
7367
7368 gen_load_spr(spr, sprn - 1);
7369 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
7370 gen_store_spr(sprn - 1, spr);
7371
7372 tcg_temp_free(spr);
7373 }
7374
7375 static int check_pow_970 (CPUPPCState *env)
7376 {
7377 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
7378 return 1;
7379 }
7380
7381 return 0;
7382 }
7383
7384 static void gen_spr_970_hid(CPUPPCState *env)
7385 {
7386 /* Hardware implementation registers */
7387 /* XXX : not implemented */
7388 spr_register(env, SPR_HID0, "HID0",
7389 SPR_NOACCESS, SPR_NOACCESS,
7390 &spr_read_generic, &spr_write_clear,
7391 0x60000000);
7392 spr_register(env, SPR_HID1, "HID1",
7393 SPR_NOACCESS, SPR_NOACCESS,
7394 &spr_read_generic, &spr_write_generic,
7395 0x00000000);
7396 spr_register(env, SPR_970_HID5, "HID5",
7397 SPR_NOACCESS, SPR_NOACCESS,
7398 &spr_read_generic, &spr_write_generic,
7399 POWERPC970_HID5_INIT);
7400 }
7401
7402 static void gen_spr_970_hior(CPUPPCState *env)
7403 {
7404 spr_register(env, SPR_HIOR, "SPR_HIOR",
7405 SPR_NOACCESS, SPR_NOACCESS,
7406 &spr_read_hior, &spr_write_hior,
7407 0x00000000);
7408 }
7409
7410 static void gen_spr_970_lpar(CPUPPCState *env)
7411 {
7412 /* Logical partitionning */
7413 /* PPC970: HID4 is effectively the LPCR */
7414 spr_register(env, SPR_970_HID4, "HID4",
7415 SPR_NOACCESS, SPR_NOACCESS,
7416 &spr_read_generic, &spr_write_generic,
7417 0x00000000);
7418 }
7419
7420 static void gen_spr_book3s_common(CPUPPCState *env)
7421 {
7422 spr_register(env, SPR_CTRL, "SPR_CTRL",
7423 SPR_NOACCESS, SPR_NOACCESS,
7424 SPR_NOACCESS, &spr_write_generic,
7425 0x00000000);
7426 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
7427 &spr_read_ureg, SPR_NOACCESS,
7428 &spr_read_ureg, SPR_NOACCESS,
7429 0x00000000);
7430 }
7431
7432 static void gen_spr_book3s_altivec(CPUPPCState *env)
7433 {
7434 if (!(env->insns_flags & PPC_ALTIVEC)) {
7435 return;
7436 }
7437
7438 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
7439 &spr_read_generic, &spr_write_generic,
7440 &spr_read_generic, &spr_write_generic,
7441 KVM_REG_PPC_VRSAVE, 0x00000000);
7442
7443 /* Can't find information on what this should be on reset. This
7444 * value is the one used by 74xx processors. */
7445 vscr_init(env, 0x00010000);
7446 }
7447
7448 static void gen_spr_book3s_dbg(CPUPPCState *env)
7449 {
7450 /*
7451 * TODO: different specs define different scopes for these,
7452 * will have to address this:
7453 * 970: super/write and super/read
7454 * powerisa 2.03..2.04: hypv/write and super/read.
7455 * powerisa 2.05 and newer: hypv/write and hypv/read.
7456 */
7457 spr_register_kvm(env, SPR_DABR, "DABR",
7458 SPR_NOACCESS, SPR_NOACCESS,
7459 &spr_read_generic, &spr_write_generic,
7460 KVM_REG_PPC_DABR, 0x00000000);
7461 spr_register_kvm(env, SPR_DABRX, "DABRX",
7462 SPR_NOACCESS, SPR_NOACCESS,
7463 &spr_read_generic, &spr_write_generic,
7464 KVM_REG_PPC_DABRX, 0x00000000);
7465 }
7466
7467 static void gen_spr_970_dbg(CPUPPCState *env)
7468 {
7469 /* Breakpoints */
7470 spr_register(env, SPR_IABR, "IABR",
7471 SPR_NOACCESS, SPR_NOACCESS,
7472 &spr_read_generic, &spr_write_generic,
7473 0x00000000);
7474 }
7475
7476 static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
7477 {
7478 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
7479 SPR_NOACCESS, SPR_NOACCESS,
7480 &spr_read_generic, &spr_write_generic,
7481 KVM_REG_PPC_MMCR0, 0x00000000);
7482 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
7483 SPR_NOACCESS, SPR_NOACCESS,
7484 &spr_read_generic, &spr_write_generic,
7485 KVM_REG_PPC_MMCR1, 0x00000000);
7486 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
7487 SPR_NOACCESS, SPR_NOACCESS,
7488 &spr_read_generic, &spr_write_generic,
7489 KVM_REG_PPC_MMCRA, 0x00000000);
7490 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
7491 SPR_NOACCESS, SPR_NOACCESS,
7492 &spr_read_generic, &spr_write_generic,
7493 KVM_REG_PPC_PMC1, 0x00000000);
7494 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
7495 SPR_NOACCESS, SPR_NOACCESS,
7496 &spr_read_generic, &spr_write_generic,
7497 KVM_REG_PPC_PMC2, 0x00000000);
7498 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
7499 SPR_NOACCESS, SPR_NOACCESS,
7500 &spr_read_generic, &spr_write_generic,
7501 KVM_REG_PPC_PMC3, 0x00000000);
7502 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
7503 SPR_NOACCESS, SPR_NOACCESS,
7504 &spr_read_generic, &spr_write_generic,
7505 KVM_REG_PPC_PMC4, 0x00000000);
7506 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
7507 SPR_NOACCESS, SPR_NOACCESS,
7508 &spr_read_generic, &spr_write_generic,
7509 KVM_REG_PPC_PMC5, 0x00000000);
7510 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
7511 SPR_NOACCESS, SPR_NOACCESS,
7512 &spr_read_generic, &spr_write_generic,
7513 KVM_REG_PPC_PMC6, 0x00000000);
7514 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
7515 SPR_NOACCESS, SPR_NOACCESS,
7516 &spr_read_generic, &spr_write_generic,
7517 KVM_REG_PPC_SIAR, 0x00000000);
7518 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
7519 SPR_NOACCESS, SPR_NOACCESS,
7520 &spr_read_generic, &spr_write_generic,
7521 KVM_REG_PPC_SDAR, 0x00000000);
7522 }
7523
7524 static void gen_spr_book3s_pmu_user(CPUPPCState *env)
7525 {
7526 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
7527 &spr_read_ureg, SPR_NOACCESS,
7528 &spr_read_ureg, &spr_write_ureg,
7529 0x00000000);
7530 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
7531 &spr_read_ureg, SPR_NOACCESS,
7532 &spr_read_ureg, &spr_write_ureg,
7533 0x00000000);
7534 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
7535 &spr_read_ureg, SPR_NOACCESS,
7536 &spr_read_ureg, &spr_write_ureg,
7537 0x00000000);
7538 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
7539 &spr_read_ureg, SPR_NOACCESS,
7540 &spr_read_ureg, &spr_write_ureg,
7541 0x00000000);
7542 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
7543 &spr_read_ureg, SPR_NOACCESS,
7544 &spr_read_ureg, &spr_write_ureg,
7545 0x00000000);
7546 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
7547 &spr_read_ureg, SPR_NOACCESS,
7548 &spr_read_ureg, &spr_write_ureg,
7549 0x00000000);
7550 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
7551 &spr_read_ureg, SPR_NOACCESS,
7552 &spr_read_ureg, &spr_write_ureg,
7553 0x00000000);
7554 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
7555 &spr_read_ureg, SPR_NOACCESS,
7556 &spr_read_ureg, &spr_write_ureg,
7557 0x00000000);
7558 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
7559 &spr_read_ureg, SPR_NOACCESS,
7560 &spr_read_ureg, &spr_write_ureg,
7561 0x00000000);
7562 spr_register(env, SPR_POWER_USIAR, "USIAR",
7563 &spr_read_ureg, SPR_NOACCESS,
7564 &spr_read_ureg, &spr_write_ureg,
7565 0x00000000);
7566 spr_register(env, SPR_POWER_USDAR, "USDAR",
7567 &spr_read_ureg, SPR_NOACCESS,
7568 &spr_read_ureg, &spr_write_ureg,
7569 0x00000000);
7570 }
7571
7572 static void gen_spr_970_pmu_sup(CPUPPCState *env)
7573 {
7574 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
7575 SPR_NOACCESS, SPR_NOACCESS,
7576 &spr_read_generic, &spr_write_generic,
7577 KVM_REG_PPC_PMC7, 0x00000000);
7578 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
7579 SPR_NOACCESS, SPR_NOACCESS,
7580 &spr_read_generic, &spr_write_generic,
7581 KVM_REG_PPC_PMC8, 0x00000000);
7582 }
7583
7584 static void gen_spr_970_pmu_user(CPUPPCState *env)
7585 {
7586 spr_register(env, SPR_970_UPMC7, "UPMC7",
7587 &spr_read_ureg, SPR_NOACCESS,
7588 &spr_read_ureg, &spr_write_ureg,
7589 0x00000000);
7590 spr_register(env, SPR_970_UPMC8, "UPMC8",
7591 &spr_read_ureg, SPR_NOACCESS,
7592 &spr_read_ureg, &spr_write_ureg,
7593 0x00000000);
7594 }
7595
7596 static void gen_spr_power8_pmu_sup(CPUPPCState *env)
7597 {
7598 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
7599 SPR_NOACCESS, SPR_NOACCESS,
7600 &spr_read_generic, &spr_write_generic,
7601 KVM_REG_PPC_MMCR2, 0x00000000);
7602 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
7603 SPR_NOACCESS, SPR_NOACCESS,
7604 &spr_read_generic, &spr_write_generic,
7605 KVM_REG_PPC_MMCRS, 0x00000000);
7606 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
7607 SPR_NOACCESS, SPR_NOACCESS,
7608 &spr_read_generic, &spr_write_generic,
7609 KVM_REG_PPC_SIER, 0x00000000);
7610 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
7611 SPR_NOACCESS, SPR_NOACCESS,
7612 &spr_read_generic, &spr_write_generic,
7613 KVM_REG_PPC_SPMC1, 0x00000000);
7614 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
7615 SPR_NOACCESS, SPR_NOACCESS,
7616 &spr_read_generic, &spr_write_generic,
7617 KVM_REG_PPC_SPMC2, 0x00000000);
7618 spr_register_kvm(env, SPR_TACR, "TACR",
7619 SPR_NOACCESS, SPR_NOACCESS,
7620 &spr_read_generic, &spr_write_generic,
7621 KVM_REG_PPC_TACR, 0x00000000);
7622 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
7623 SPR_NOACCESS, SPR_NOACCESS,
7624 &spr_read_generic, &spr_write_generic,
7625 KVM_REG_PPC_TCSCR, 0x00000000);
7626 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
7627 SPR_NOACCESS, SPR_NOACCESS,
7628 &spr_read_generic, &spr_write_generic,
7629 KVM_REG_PPC_CSIGR, 0x00000000);
7630 }
7631
7632 static void gen_spr_power8_pmu_user(CPUPPCState *env)
7633 {
7634 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
7635 &spr_read_ureg, SPR_NOACCESS,
7636 &spr_read_ureg, &spr_write_ureg,
7637 0x00000000);
7638 spr_register(env, SPR_POWER_USIER, "USIER",
7639 &spr_read_generic, SPR_NOACCESS,
7640 &spr_read_generic, &spr_write_generic,
7641 0x00000000);
7642 }
7643
7644 static void gen_spr_power5p_ear(CPUPPCState *env)
7645 {
7646 /* External access control */
7647 spr_register(env, SPR_EAR, "EAR",
7648 SPR_NOACCESS, SPR_NOACCESS,
7649 &spr_read_generic, &spr_write_generic,
7650 0x00000000);
7651 }
7652
7653 static void gen_spr_power5p_lpar(CPUPPCState *env)
7654 {
7655 /* Logical partitionning */
7656 spr_register_kvm(env, SPR_LPCR, "LPCR",
7657 SPR_NOACCESS, SPR_NOACCESS,
7658 &spr_read_generic, &spr_write_generic,
7659 KVM_REG_PPC_LPCR, 0x00000000);
7660 }
7661
7662 static void gen_spr_book3s_ids(CPUPPCState *env)
7663 {
7664 /* Processor identification */
7665 spr_register(env, SPR_PIR, "PIR",
7666 SPR_NOACCESS, SPR_NOACCESS,
7667 &spr_read_generic, &spr_write_pir,
7668 0x00000000);
7669 }
7670
7671 static void gen_spr_power8_ids(CPUPPCState *env)
7672 {
7673 /* Thread identification */
7674 spr_register(env, SPR_TIR, "TIR",
7675 SPR_NOACCESS, SPR_NOACCESS,
7676 &spr_read_generic, SPR_NOACCESS,
7677 0x00000000);
7678 }
7679
7680 static void gen_spr_book3s_purr(CPUPPCState *env)
7681 {
7682 #if !defined(CONFIG_USER_ONLY)
7683 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7684 spr_register_kvm(env, SPR_PURR, "PURR",
7685 &spr_read_purr, SPR_NOACCESS,
7686 &spr_read_purr, SPR_NOACCESS,
7687 KVM_REG_PPC_PURR, 0x00000000);
7688 spr_register_kvm(env, SPR_SPURR, "SPURR",
7689 &spr_read_purr, SPR_NOACCESS,
7690 &spr_read_purr, SPR_NOACCESS,
7691 KVM_REG_PPC_SPURR, 0x00000000);
7692 #endif
7693 }
7694
7695 static void gen_spr_power6_dbg(CPUPPCState *env)
7696 {
7697 #if !defined(CONFIG_USER_ONLY)
7698 spr_register(env, SPR_CFAR, "SPR_CFAR",
7699 SPR_NOACCESS, SPR_NOACCESS,
7700 &spr_read_cfar, &spr_write_cfar,
7701 0x00000000);
7702 #endif
7703 }
7704
7705 static void gen_spr_power5p_common(CPUPPCState *env)
7706 {
7707 spr_register_kvm(env, SPR_PPR, "PPR",
7708 &spr_read_generic, &spr_write_generic,
7709 &spr_read_generic, &spr_write_generic,
7710 KVM_REG_PPC_PPR, 0x00000000);
7711 }
7712
7713 static void gen_spr_power6_common(CPUPPCState *env)
7714 {
7715 #if !defined(CONFIG_USER_ONLY)
7716 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
7717 SPR_NOACCESS, SPR_NOACCESS,
7718 &spr_read_generic, &spr_write_generic,
7719 KVM_REG_PPC_DSCR, 0x00000000);
7720 #endif
7721 /*
7722 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
7723 * POWERPC_EXCP_INVAL_SPR.
7724 */
7725 spr_register(env, SPR_PCR, "PCR",
7726 SPR_NOACCESS, SPR_NOACCESS,
7727 SPR_NOACCESS, SPR_NOACCESS,
7728 0x00000000);
7729 }
7730
7731 static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
7732 {
7733 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
7734 spr_read_generic(ctx, gprn, sprn);
7735 }
7736
7737 static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
7738 {
7739 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
7740 spr_write_generic(ctx, sprn, gprn);
7741 }
7742
7743 static void gen_spr_power8_tce_address_control(CPUPPCState *env)
7744 {
7745 spr_register_kvm(env, SPR_TAR, "TAR",
7746 &spr_read_tar, &spr_write_tar,
7747 &spr_read_generic, &spr_write_generic,
7748 KVM_REG_PPC_TAR, 0x00000000);
7749 }
7750
7751 static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
7752 {
7753 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7754 spr_read_generic(ctx, gprn, sprn);
7755 }
7756
7757 static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
7758 {
7759 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7760 spr_write_generic(ctx, sprn, gprn);
7761 }
7762
7763 static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
7764 {
7765 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7766 spr_read_prev_upper32(ctx, gprn, sprn);
7767 }
7768
7769 static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
7770 {
7771 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7772 spr_write_prev_upper32(ctx, sprn, gprn);
7773 }
7774
7775 static void gen_spr_power8_tm(CPUPPCState *env)
7776 {
7777 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
7778 &spr_read_tm, &spr_write_tm,
7779 &spr_read_tm, &spr_write_tm,
7780 KVM_REG_PPC_TFHAR, 0x00000000);
7781 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
7782 &spr_read_tm, &spr_write_tm,
7783 &spr_read_tm, &spr_write_tm,
7784 KVM_REG_PPC_TFIAR, 0x00000000);
7785 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
7786 &spr_read_tm, &spr_write_tm,
7787 &spr_read_tm, &spr_write_tm,
7788 KVM_REG_PPC_TEXASR, 0x00000000);
7789 spr_register(env, SPR_TEXASRU, "TEXASRU",
7790 &spr_read_tm_upper32, &spr_write_tm_upper32,
7791 &spr_read_tm_upper32, &spr_write_tm_upper32,
7792 0x00000000);
7793 }
7794
7795 static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
7796 {
7797 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7798 spr_read_generic(ctx, gprn, sprn);
7799 }
7800
7801 static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
7802 {
7803 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7804 spr_write_generic(ctx, sprn, gprn);
7805 }
7806
7807 static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
7808 {
7809 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7810 spr_read_prev_upper32(ctx, gprn, sprn);
7811 }
7812
7813 static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
7814 {
7815 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7816 spr_write_prev_upper32(ctx, sprn, gprn);
7817 }
7818
7819 static void gen_spr_power8_ebb(CPUPPCState *env)
7820 {
7821 spr_register(env, SPR_BESCRS, "BESCRS",
7822 &spr_read_ebb, &spr_write_ebb,
7823 &spr_read_generic, &spr_write_generic,
7824 0x00000000);
7825 spr_register(env, SPR_BESCRSU, "BESCRSU",
7826 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
7827 &spr_read_prev_upper32, &spr_write_prev_upper32,
7828 0x00000000);
7829 spr_register(env, SPR_BESCRR, "BESCRR",
7830 &spr_read_ebb, &spr_write_ebb,
7831 &spr_read_generic, &spr_write_generic,
7832 0x00000000);
7833 spr_register(env, SPR_BESCRRU, "BESCRRU",
7834 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
7835 &spr_read_prev_upper32, &spr_write_prev_upper32,
7836 0x00000000);
7837 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
7838 &spr_read_ebb, &spr_write_ebb,
7839 &spr_read_generic, &spr_write_generic,
7840 KVM_REG_PPC_EBBHR, 0x00000000);
7841 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
7842 &spr_read_ebb, &spr_write_ebb,
7843 &spr_read_generic, &spr_write_generic,
7844 KVM_REG_PPC_EBBRR, 0x00000000);
7845 spr_register_kvm(env, SPR_BESCR, "BESCR",
7846 &spr_read_ebb, &spr_write_ebb,
7847 &spr_read_generic, &spr_write_generic,
7848 KVM_REG_PPC_BESCR, 0x00000000);
7849 }
7850
7851 /* Virtual Time Base */
7852 static void gen_spr_vtb(CPUPPCState *env)
7853 {
7854 spr_register(env, SPR_VTB, "VTB",
7855 SPR_NOACCESS, SPR_NOACCESS,
7856 &spr_read_tbl, SPR_NOACCESS,
7857 0x00000000);
7858 }
7859
7860 static void gen_spr_power8_fscr(CPUPPCState *env)
7861 {
7862 #if defined(CONFIG_USER_ONLY)
7863 target_ulong initval = 1ULL << FSCR_TAR;
7864 #else
7865 target_ulong initval = 0;
7866 #endif
7867 spr_register_kvm(env, SPR_FSCR, "FSCR",
7868 SPR_NOACCESS, SPR_NOACCESS,
7869 &spr_read_generic, &spr_write_generic,
7870 KVM_REG_PPC_FSCR, initval);
7871 }
7872
7873 static void gen_spr_power8_pspb(CPUPPCState *env)
7874 {
7875 spr_register_kvm(env, SPR_PSPB, "PSPB",
7876 SPR_NOACCESS, SPR_NOACCESS,
7877 &spr_read_generic, &spr_write_generic32,
7878 KVM_REG_PPC_PSPB, 0);
7879 }
7880
7881 static void init_proc_book3s_64(CPUPPCState *env, int version)
7882 {
7883 gen_spr_ne_601(env);
7884 gen_tbl(env);
7885 gen_spr_book3s_altivec(env);
7886 gen_spr_book3s_pmu_sup(env);
7887 gen_spr_book3s_pmu_user(env);
7888 gen_spr_book3s_common(env);
7889
7890 switch (version) {
7891 case BOOK3S_CPU_970:
7892 case BOOK3S_CPU_POWER5PLUS:
7893 gen_spr_970_hid(env);
7894 gen_spr_970_hior(env);
7895 gen_low_BATs(env);
7896 gen_spr_970_pmu_sup(env);
7897 gen_spr_970_pmu_user(env);
7898 break;
7899 case BOOK3S_CPU_POWER7:
7900 case BOOK3S_CPU_POWER8:
7901 gen_spr_book3s_ids(env);
7902 gen_spr_amr(env);
7903 gen_spr_book3s_purr(env);
7904 env->ci_large_pages = true;
7905 break;
7906 default:
7907 g_assert_not_reached();
7908 }
7909 if (version >= BOOK3S_CPU_POWER5PLUS) {
7910 gen_spr_power5p_common(env);
7911 gen_spr_power5p_lpar(env);
7912 gen_spr_power5p_ear(env);
7913 } else {
7914 gen_spr_970_lpar(env);
7915 }
7916 if (version == BOOK3S_CPU_970) {
7917 gen_spr_970_dbg(env);
7918 }
7919 if (version >= BOOK3S_CPU_POWER6) {
7920 gen_spr_power6_common(env);
7921 gen_spr_power6_dbg(env);
7922 }
7923 if (version >= BOOK3S_CPU_POWER8) {
7924 gen_spr_power8_tce_address_control(env);
7925 gen_spr_power8_ids(env);
7926 gen_spr_power8_ebb(env);
7927 gen_spr_power8_fscr(env);
7928 gen_spr_power8_pmu_sup(env);
7929 gen_spr_power8_pmu_user(env);
7930 gen_spr_power8_tm(env);
7931 gen_spr_power8_pspb(env);
7932 gen_spr_vtb(env);
7933 }
7934 if (version < BOOK3S_CPU_POWER8) {
7935 gen_spr_book3s_dbg(env);
7936 }
7937 #if !defined(CONFIG_USER_ONLY)
7938 switch (version) {
7939 case BOOK3S_CPU_970:
7940 case BOOK3S_CPU_POWER5PLUS:
7941 env->slb_nr = 64;
7942 break;
7943 case BOOK3S_CPU_POWER7:
7944 case BOOK3S_CPU_POWER8:
7945 default:
7946 env->slb_nr = 32;
7947 break;
7948 }
7949 #endif
7950 /* Allocate hardware IRQ controller */
7951 switch (version) {
7952 case BOOK3S_CPU_970:
7953 case BOOK3S_CPU_POWER5PLUS:
7954 init_excp_970(env);
7955 ppc970_irq_init(env);
7956 break;
7957 case BOOK3S_CPU_POWER7:
7958 case BOOK3S_CPU_POWER8:
7959 init_excp_POWER7(env);
7960 ppcPOWER7_irq_init(env);
7961 break;
7962 default:
7963 g_assert_not_reached();
7964 }
7965
7966 env->dcache_line_size = 128;
7967 env->icache_line_size = 128;
7968 }
7969
7970 static void init_proc_970(CPUPPCState *env)
7971 {
7972 init_proc_book3s_64(env, BOOK3S_CPU_970);
7973 }
7974
7975 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
7976 {
7977 DeviceClass *dc = DEVICE_CLASS(oc);
7978 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7979
7980 dc->desc = "PowerPC 970";
7981 pcc->init_proc = init_proc_970;
7982 pcc->check_pow = check_pow_970;
7983 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7984 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7985 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7986 PPC_FLOAT_STFIWX |
7987 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7988 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7989 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7990 PPC_64B | PPC_ALTIVEC |
7991 PPC_SEGMENT_64B | PPC_SLBI;
7992 pcc->insns_flags2 = PPC2_FP_CVT_S64;
7993 pcc->msr_mask = (1ull << MSR_SF) |
7994 (1ull << MSR_VR) |
7995 (1ull << MSR_POW) |
7996 (1ull << MSR_EE) |
7997 (1ull << MSR_PR) |
7998 (1ull << MSR_FP) |
7999 (1ull << MSR_ME) |
8000 (1ull << MSR_FE0) |
8001 (1ull << MSR_SE) |
8002 (1ull << MSR_DE) |
8003 (1ull << MSR_FE1) |
8004 (1ull << MSR_IR) |
8005 (1ull << MSR_DR) |
8006 (1ull << MSR_PMM) |
8007 (1ull << MSR_RI);
8008 pcc->mmu_model = POWERPC_MMU_64B;
8009 #if defined(CONFIG_SOFTMMU)
8010 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8011 #endif
8012 pcc->excp_model = POWERPC_EXCP_970;
8013 pcc->bus_model = PPC_FLAGS_INPUT_970;
8014 pcc->bfd_mach = bfd_mach_ppc64;
8015 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8016 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8017 POWERPC_FLAG_BUS_CLK;
8018 pcc->l1_dcache_size = 0x8000;
8019 pcc->l1_icache_size = 0x10000;
8020 }
8021
8022 static void init_proc_power5plus(CPUPPCState *env)
8023 {
8024 init_proc_book3s_64(env, BOOK3S_CPU_POWER5PLUS);
8025 }
8026
8027 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
8028 {
8029 DeviceClass *dc = DEVICE_CLASS(oc);
8030 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8031
8032 dc->fw_name = "PowerPC,POWER5";
8033 dc->desc = "POWER5+";
8034 pcc->init_proc = init_proc_power5plus;
8035 pcc->check_pow = check_pow_970;
8036 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8037 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8038 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8039 PPC_FLOAT_STFIWX |
8040 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8041 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8042 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8043 PPC_64B |
8044 PPC_SEGMENT_64B | PPC_SLBI;
8045 pcc->insns_flags2 = PPC2_FP_CVT_S64;
8046 pcc->msr_mask = (1ull << MSR_SF) |
8047 (1ull << MSR_VR) |
8048 (1ull << MSR_POW) |
8049 (1ull << MSR_EE) |
8050 (1ull << MSR_PR) |
8051 (1ull << MSR_FP) |
8052 (1ull << MSR_ME) |
8053 (1ull << MSR_FE0) |
8054 (1ull << MSR_SE) |
8055 (1ull << MSR_DE) |
8056 (1ull << MSR_FE1) |
8057 (1ull << MSR_IR) |
8058 (1ull << MSR_DR) |
8059 (1ull << MSR_PMM) |
8060 (1ull << MSR_RI);
8061 pcc->mmu_model = POWERPC_MMU_2_03;
8062 #if defined(CONFIG_SOFTMMU)
8063 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8064 #endif
8065 pcc->excp_model = POWERPC_EXCP_970;
8066 pcc->bus_model = PPC_FLAGS_INPUT_970;
8067 pcc->bfd_mach = bfd_mach_ppc64;
8068 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8069 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8070 POWERPC_FLAG_BUS_CLK;
8071 pcc->l1_dcache_size = 0x8000;
8072 pcc->l1_icache_size = 0x10000;
8073 }
8074
8075 static void powerpc_get_compat(Object *obj, Visitor *v, const char *name,
8076 void *opaque, Error **errp)
8077 {
8078 char *value = (char *)"";
8079 Property *prop = opaque;
8080 uint32_t *max_compat = qdev_get_prop_ptr(DEVICE(obj), prop);
8081
8082 switch (*max_compat) {
8083 case CPU_POWERPC_LOGICAL_2_05:
8084 value = (char *)"power6";
8085 break;
8086 case CPU_POWERPC_LOGICAL_2_06:
8087 value = (char *)"power7";
8088 break;
8089 case CPU_POWERPC_LOGICAL_2_07:
8090 value = (char *)"power8";
8091 break;
8092 case 0:
8093 break;
8094 default:
8095 error_setg(errp, "Internal error: compat is set to %x",
8096 max_compat ? *max_compat : -1);
8097 break;
8098 }
8099
8100 visit_type_str(v, name, &value, errp);
8101 }
8102
8103 static void powerpc_set_compat(Object *obj, Visitor *v, const char *name,
8104 void *opaque, Error **errp)
8105 {
8106 Error *error = NULL;
8107 char *value = NULL;
8108 Property *prop = opaque;
8109 uint32_t *max_compat = qdev_get_prop_ptr(DEVICE(obj), prop);
8110
8111 visit_type_str(v, name, &value, &error);
8112 if (error) {
8113 error_propagate(errp, error);
8114 return;
8115 }
8116
8117 if (strcmp(value, "power6") == 0) {
8118 *max_compat = CPU_POWERPC_LOGICAL_2_05;
8119 } else if (strcmp(value, "power7") == 0) {
8120 *max_compat = CPU_POWERPC_LOGICAL_2_06;
8121 } else if (strcmp(value, "power8") == 0) {
8122 *max_compat = CPU_POWERPC_LOGICAL_2_07;
8123 } else {
8124 error_setg(errp, "Invalid compatibility mode \"%s\"", value);
8125 }
8126
8127 g_free(value);
8128 }
8129
8130 static PropertyInfo powerpc_compat_propinfo = {
8131 .name = "str",
8132 .description = "compatibility mode, power6/power7/power8",
8133 .get = powerpc_get_compat,
8134 .set = powerpc_set_compat,
8135 };
8136
8137 #define DEFINE_PROP_POWERPC_COMPAT(_n, _s, _f) \
8138 DEFINE_PROP(_n, _s, _f, powerpc_compat_propinfo, uint32_t)
8139
8140 static Property powerpc_servercpu_properties[] = {
8141 DEFINE_PROP_POWERPC_COMPAT("compat", PowerPCCPU, max_compat),
8142 DEFINE_PROP_END_OF_LIST(),
8143 };
8144
8145 #ifdef CONFIG_SOFTMMU
8146 static const struct ppc_segment_page_sizes POWER7_POWER8_sps = {
8147 .sps = {
8148 {
8149 .page_shift = 12, /* 4K */
8150 .slb_enc = 0,
8151 .enc = { { .page_shift = 12, .pte_enc = 0 },
8152 { .page_shift = 16, .pte_enc = 0x7 },
8153 { .page_shift = 24, .pte_enc = 0x38 }, },
8154 },
8155 {
8156 .page_shift = 16, /* 64K */
8157 .slb_enc = SLB_VSID_64K,
8158 .enc = { { .page_shift = 16, .pte_enc = 0x1 },
8159 { .page_shift = 24, .pte_enc = 0x8 }, },
8160 },
8161 {
8162 .page_shift = 24, /* 16M */
8163 .slb_enc = SLB_VSID_16M,
8164 .enc = { { .page_shift = 24, .pte_enc = 0 }, },
8165 },
8166 {
8167 .page_shift = 34, /* 16G */
8168 .slb_enc = SLB_VSID_16G,
8169 .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
8170 },
8171 }
8172 };
8173 #endif /* CONFIG_SOFTMMU */
8174
8175 static void init_proc_POWER7 (CPUPPCState *env)
8176 {
8177 init_proc_book3s_64(env, BOOK3S_CPU_POWER7);
8178 }
8179
8180 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
8181 {
8182 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
8183 return true;
8184 }
8185 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
8186 return true;
8187 }
8188 return false;
8189 }
8190
8191 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
8192 {
8193 DeviceClass *dc = DEVICE_CLASS(oc);
8194 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8195
8196 dc->fw_name = "PowerPC,POWER7";
8197 dc->desc = "POWER7";
8198 dc->props = powerpc_servercpu_properties;
8199 pcc->pvr_match = ppc_pvr_match_power7;
8200 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06;
8201 pcc->init_proc = init_proc_POWER7;
8202 pcc->check_pow = check_pow_nocheck;
8203 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8204 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8205 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8206 PPC_FLOAT_FRSQRTES |
8207 PPC_FLOAT_STFIWX |
8208 PPC_FLOAT_EXT |
8209 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8210 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8211 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8212 PPC_64B | PPC_ALTIVEC |
8213 PPC_SEGMENT_64B | PPC_SLBI |
8214 PPC_POPCNTB | PPC_POPCNTWD;
8215 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
8216 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8217 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8218 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64;
8219 pcc->msr_mask = (1ull << MSR_SF) |
8220 (1ull << MSR_VR) |
8221 (1ull << MSR_VSX) |
8222 (1ull << MSR_EE) |
8223 (1ull << MSR_PR) |
8224 (1ull << MSR_FP) |
8225 (1ull << MSR_ME) |
8226 (1ull << MSR_FE0) |
8227 (1ull << MSR_SE) |
8228 (1ull << MSR_DE) |
8229 (1ull << MSR_FE1) |
8230 (1ull << MSR_IR) |
8231 (1ull << MSR_DR) |
8232 (1ull << MSR_PMM) |
8233 (1ull << MSR_RI) |
8234 (1ull << MSR_LE);
8235 pcc->mmu_model = POWERPC_MMU_2_06;
8236 #if defined(CONFIG_SOFTMMU)
8237 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8238 pcc->sps = &POWER7_POWER8_sps;
8239 #endif
8240 pcc->excp_model = POWERPC_EXCP_POWER7;
8241 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8242 pcc->bfd_mach = bfd_mach_ppc64;
8243 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8244 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8245 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8246 POWERPC_FLAG_VSX;
8247 pcc->l1_dcache_size = 0x8000;
8248 pcc->l1_icache_size = 0x8000;
8249 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8250 }
8251
8252 static void init_proc_POWER8(CPUPPCState *env)
8253 {
8254 init_proc_book3s_64(env, BOOK3S_CPU_POWER8);
8255 }
8256
8257 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
8258 {
8259 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
8260 return true;
8261 }
8262 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
8263 return true;
8264 }
8265 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
8266 return true;
8267 }
8268 return false;
8269 }
8270
8271 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
8272 {
8273 DeviceClass *dc = DEVICE_CLASS(oc);
8274 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8275
8276 dc->fw_name = "PowerPC,POWER8";
8277 dc->desc = "POWER8";
8278 dc->props = powerpc_servercpu_properties;
8279 pcc->pvr_match = ppc_pvr_match_power8;
8280 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06;
8281 pcc->init_proc = init_proc_POWER8;
8282 pcc->check_pow = check_pow_nocheck;
8283 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8284 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8285 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8286 PPC_FLOAT_FRSQRTES |
8287 PPC_FLOAT_STFIWX |
8288 PPC_FLOAT_EXT |
8289 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8290 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8291 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8292 PPC_64B | PPC_64BX | PPC_ALTIVEC |
8293 PPC_SEGMENT_64B | PPC_SLBI |
8294 PPC_POPCNTB | PPC_POPCNTWD;
8295 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8296 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8297 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8298 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8299 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8300 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8301 PPC2_TM;
8302 pcc->msr_mask = (1ull << MSR_SF) |
8303 (1ull << MSR_TM) |
8304 (1ull << MSR_VR) |
8305 (1ull << MSR_VSX) |
8306 (1ull << MSR_EE) |
8307 (1ull << MSR_PR) |
8308 (1ull << MSR_FP) |
8309 (1ull << MSR_ME) |
8310 (1ull << MSR_FE0) |
8311 (1ull << MSR_SE) |
8312 (1ull << MSR_DE) |
8313 (1ull << MSR_FE1) |
8314 (1ull << MSR_IR) |
8315 (1ull << MSR_DR) |
8316 (1ull << MSR_PMM) |
8317 (1ull << MSR_RI) |
8318 (1ull << MSR_LE);
8319 pcc->mmu_model = POWERPC_MMU_2_07;
8320 #if defined(CONFIG_SOFTMMU)
8321 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8322 pcc->sps = &POWER7_POWER8_sps;
8323 #endif
8324 pcc->excp_model = POWERPC_EXCP_POWER7;
8325 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8326 pcc->bfd_mach = bfd_mach_ppc64;
8327 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8328 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8329 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8330 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
8331 pcc->l1_dcache_size = 0x8000;
8332 pcc->l1_icache_size = 0x8000;
8333 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8334 }
8335 #endif /* defined (TARGET_PPC64) */
8336
8337
8338 /*****************************************************************************/
8339 /* Generic CPU instantiation routine */
8340 static void init_ppc_proc(PowerPCCPU *cpu)
8341 {
8342 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8343 CPUPPCState *env = &cpu->env;
8344 #if !defined(CONFIG_USER_ONLY)
8345 int i;
8346
8347 env->irq_inputs = NULL;
8348 /* Set all exception vectors to an invalid address */
8349 for (i = 0; i < POWERPC_EXCP_NB; i++)
8350 env->excp_vectors[i] = (target_ulong)(-1ULL);
8351 env->ivor_mask = 0x00000000;
8352 env->ivpr_mask = 0x00000000;
8353 /* Default MMU definitions */
8354 env->nb_BATs = 0;
8355 env->nb_tlb = 0;
8356 env->nb_ways = 0;
8357 env->tlb_type = TLB_NONE;
8358 #endif
8359 /* Register SPR common to all PowerPC implementations */
8360 gen_spr_generic(env);
8361 spr_register(env, SPR_PVR, "PVR",
8362 /* Linux permits userspace to read PVR */
8363 #if defined(CONFIG_LINUX_USER)
8364 &spr_read_generic,
8365 #else
8366 SPR_NOACCESS,
8367 #endif
8368 SPR_NOACCESS,
8369 &spr_read_generic, SPR_NOACCESS,
8370 pcc->pvr);
8371 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8372 if (pcc->svr != POWERPC_SVR_NONE) {
8373 if (pcc->svr & POWERPC_SVR_E500) {
8374 spr_register(env, SPR_E500_SVR, "SVR",
8375 SPR_NOACCESS, SPR_NOACCESS,
8376 &spr_read_generic, SPR_NOACCESS,
8377 pcc->svr & ~POWERPC_SVR_E500);
8378 } else {
8379 spr_register(env, SPR_SVR, "SVR",
8380 SPR_NOACCESS, SPR_NOACCESS,
8381 &spr_read_generic, SPR_NOACCESS,
8382 pcc->svr);
8383 }
8384 }
8385 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8386 (*pcc->init_proc)(env);
8387
8388 /* MSR bits & flags consistency checks */
8389 if (env->msr_mask & (1 << 25)) {
8390 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8391 case POWERPC_FLAG_SPE:
8392 case POWERPC_FLAG_VRE:
8393 break;
8394 default:
8395 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8396 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8397 exit(1);
8398 }
8399 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8400 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8401 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8402 exit(1);
8403 }
8404 if (env->msr_mask & (1 << 17)) {
8405 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8406 case POWERPC_FLAG_TGPR:
8407 case POWERPC_FLAG_CE:
8408 break;
8409 default:
8410 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8411 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8412 exit(1);
8413 }
8414 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8415 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8416 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8417 exit(1);
8418 }
8419 if (env->msr_mask & (1 << 10)) {
8420 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8421 POWERPC_FLAG_UBLE)) {
8422 case POWERPC_FLAG_SE:
8423 case POWERPC_FLAG_DWE:
8424 case POWERPC_FLAG_UBLE:
8425 break;
8426 default:
8427 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8428 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8429 "POWERPC_FLAG_UBLE\n");
8430 exit(1);
8431 }
8432 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8433 POWERPC_FLAG_UBLE)) {
8434 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8435 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8436 "POWERPC_FLAG_UBLE\n");
8437 exit(1);
8438 }
8439 if (env->msr_mask & (1 << 9)) {
8440 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8441 case POWERPC_FLAG_BE:
8442 case POWERPC_FLAG_DE:
8443 break;
8444 default:
8445 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8446 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8447 exit(1);
8448 }
8449 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8450 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8451 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8452 exit(1);
8453 }
8454 if (env->msr_mask & (1 << 2)) {
8455 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8456 case POWERPC_FLAG_PX:
8457 case POWERPC_FLAG_PMM:
8458 break;
8459 default:
8460 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8461 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8462 exit(1);
8463 }
8464 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8465 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8466 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8467 exit(1);
8468 }
8469 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8470 fprintf(stderr, "PowerPC flags inconsistency\n"
8471 "Should define the time-base and decrementer clock source\n");
8472 exit(1);
8473 }
8474 /* Allocate TLBs buffer when needed */
8475 #if !defined(CONFIG_USER_ONLY)
8476 if (env->nb_tlb != 0) {
8477 int nb_tlb = env->nb_tlb;
8478 if (env->id_tlbs != 0)
8479 nb_tlb *= 2;
8480 switch (env->tlb_type) {
8481 case TLB_6XX:
8482 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
8483 break;
8484 case TLB_EMB:
8485 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
8486 break;
8487 case TLB_MAS:
8488 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
8489 break;
8490 }
8491 /* Pre-compute some useful values */
8492 env->tlb_per_way = env->nb_tlb / env->nb_ways;
8493 }
8494 if (env->irq_inputs == NULL) {
8495 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
8496 " Attempt QEMU to crash very soon !\n");
8497 }
8498 #endif
8499 if (env->check_pow == NULL) {
8500 fprintf(stderr, "WARNING: no power management check handler "
8501 "registered.\n"
8502 " Attempt QEMU to crash very soon !\n");
8503 }
8504 }
8505
8506 #if defined(PPC_DUMP_CPU)
8507 static void dump_ppc_sprs (CPUPPCState *env)
8508 {
8509 ppc_spr_t *spr;
8510 #if !defined(CONFIG_USER_ONLY)
8511 uint32_t sr, sw;
8512 #endif
8513 uint32_t ur, uw;
8514 int i, j, n;
8515
8516 printf("Special purpose registers:\n");
8517 for (i = 0; i < 32; i++) {
8518 for (j = 0; j < 32; j++) {
8519 n = (i << 5) | j;
8520 spr = &env->spr_cb[n];
8521 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
8522 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
8523 #if !defined(CONFIG_USER_ONLY)
8524 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
8525 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
8526 if (sw || sr || uw || ur) {
8527 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
8528 (i << 5) | j, (i << 5) | j, spr->name,
8529 sw ? 'w' : '-', sr ? 'r' : '-',
8530 uw ? 'w' : '-', ur ? 'r' : '-');
8531 }
8532 #else
8533 if (uw || ur) {
8534 printf("SPR: %4d (%03x) %-8s u%c%c\n",
8535 (i << 5) | j, (i << 5) | j, spr->name,
8536 uw ? 'w' : '-', ur ? 'r' : '-');
8537 }
8538 #endif
8539 }
8540 }
8541 fflush(stdout);
8542 fflush(stderr);
8543 }
8544 #endif
8545
8546 /*****************************************************************************/
8547
8548 /* Opcode types */
8549 enum {
8550 PPC_DIRECT = 0, /* Opcode routine */
8551 PPC_INDIRECT = 1, /* Indirect opcode table */
8552 };
8553
8554 #define PPC_OPCODE_MASK 0x3
8555
8556 static inline int is_indirect_opcode (void *handler)
8557 {
8558 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
8559 }
8560
8561 static inline opc_handler_t **ind_table(void *handler)
8562 {
8563 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
8564 }
8565
8566 /* Instruction table creation */
8567 /* Opcodes tables creation */
8568 static void fill_new_table (opc_handler_t **table, int len)
8569 {
8570 int i;
8571
8572 for (i = 0; i < len; i++)
8573 table[i] = &invalid_handler;
8574 }
8575
8576 static int create_new_table (opc_handler_t **table, unsigned char idx)
8577 {
8578 opc_handler_t **tmp;
8579
8580 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
8581 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
8582 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
8583
8584 return 0;
8585 }
8586
8587 static int insert_in_table (opc_handler_t **table, unsigned char idx,
8588 opc_handler_t *handler)
8589 {
8590 if (table[idx] != &invalid_handler)
8591 return -1;
8592 table[idx] = handler;
8593
8594 return 0;
8595 }
8596
8597 static int register_direct_insn (opc_handler_t **ppc_opcodes,
8598 unsigned char idx, opc_handler_t *handler)
8599 {
8600 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
8601 printf("*** ERROR: opcode %02x already assigned in main "
8602 "opcode table\n", idx);
8603 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8604 printf(" Registered handler '%s' - new handler '%s'\n",
8605 ppc_opcodes[idx]->oname, handler->oname);
8606 #endif
8607 return -1;
8608 }
8609
8610 return 0;
8611 }
8612
8613 static int register_ind_in_table (opc_handler_t **table,
8614 unsigned char idx1, unsigned char idx2,
8615 opc_handler_t *handler)
8616 {
8617 if (table[idx1] == &invalid_handler) {
8618 if (create_new_table(table, idx1) < 0) {
8619 printf("*** ERROR: unable to create indirect table "
8620 "idx=%02x\n", idx1);
8621 return -1;
8622 }
8623 } else {
8624 if (!is_indirect_opcode(table[idx1])) {
8625 printf("*** ERROR: idx %02x already assigned to a direct "
8626 "opcode\n", idx1);
8627 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8628 printf(" Registered handler '%s' - new handler '%s'\n",
8629 ind_table(table[idx1])[idx2]->oname, handler->oname);
8630 #endif
8631 return -1;
8632 }
8633 }
8634 if (handler != NULL &&
8635 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
8636 printf("*** ERROR: opcode %02x already assigned in "
8637 "opcode table %02x\n", idx2, idx1);
8638 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8639 printf(" Registered handler '%s' - new handler '%s'\n",
8640 ind_table(table[idx1])[idx2]->oname, handler->oname);
8641 #endif
8642 return -1;
8643 }
8644
8645 return 0;
8646 }
8647
8648 static int register_ind_insn (opc_handler_t **ppc_opcodes,
8649 unsigned char idx1, unsigned char idx2,
8650 opc_handler_t *handler)
8651 {
8652 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
8653 }
8654
8655 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
8656 unsigned char idx1, unsigned char idx2,
8657 unsigned char idx3, opc_handler_t *handler)
8658 {
8659 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8660 printf("*** ERROR: unable to join indirect table idx "
8661 "[%02x-%02x]\n", idx1, idx2);
8662 return -1;
8663 }
8664 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
8665 handler) < 0) {
8666 printf("*** ERROR: unable to insert opcode "
8667 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8668 return -1;
8669 }
8670
8671 return 0;
8672 }
8673
8674 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
8675 {
8676 if (insn->opc2 != 0xFF) {
8677 if (insn->opc3 != 0xFF) {
8678 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8679 insn->opc3, &insn->handler) < 0)
8680 return -1;
8681 } else {
8682 if (register_ind_insn(ppc_opcodes, insn->opc1,
8683 insn->opc2, &insn->handler) < 0)
8684 return -1;
8685 }
8686 } else {
8687 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
8688 return -1;
8689 }
8690
8691 return 0;
8692 }
8693
8694 static int test_opcode_table (opc_handler_t **table, int len)
8695 {
8696 int i, count, tmp;
8697
8698 for (i = 0, count = 0; i < len; i++) {
8699 /* Consistency fixup */
8700 if (table[i] == NULL)
8701 table[i] = &invalid_handler;
8702 if (table[i] != &invalid_handler) {
8703 if (is_indirect_opcode(table[i])) {
8704 tmp = test_opcode_table(ind_table(table[i]),
8705 PPC_CPU_INDIRECT_OPCODES_LEN);
8706 if (tmp == 0) {
8707 free(table[i]);
8708 table[i] = &invalid_handler;
8709 } else {
8710 count++;
8711 }
8712 } else {
8713 count++;
8714 }
8715 }
8716 }
8717
8718 return count;
8719 }
8720
8721 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
8722 {
8723 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0)
8724 printf("*** WARNING: no opcode defined !\n");
8725 }
8726
8727 /*****************************************************************************/
8728 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
8729 {
8730 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8731 CPUPPCState *env = &cpu->env;
8732 opcode_t *opc;
8733
8734 fill_new_table(env->opcodes, PPC_CPU_OPCODES_LEN);
8735 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
8736 if (((opc->handler.type & pcc->insns_flags) != 0) ||
8737 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
8738 if (register_insn(env->opcodes, opc) < 0) {
8739 error_setg(errp, "ERROR initializing PowerPC instruction "
8740 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
8741 opc->opc3);
8742 return;
8743 }
8744 }
8745 }
8746 fix_opcode_tables(env->opcodes);
8747 fflush(stdout);
8748 fflush(stderr);
8749 }
8750
8751 #if defined(PPC_DUMP_CPU)
8752 static void dump_ppc_insns (CPUPPCState *env)
8753 {
8754 opc_handler_t **table, *handler;
8755 const char *p, *q;
8756 uint8_t opc1, opc2, opc3;
8757
8758 printf("Instructions set:\n");
8759 /* opc1 is 6 bits long */
8760 for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) {
8761 table = env->opcodes;
8762 handler = table[opc1];
8763 if (is_indirect_opcode(handler)) {
8764 /* opc2 is 5 bits long */
8765 for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) {
8766 table = env->opcodes;
8767 handler = env->opcodes[opc1];
8768 table = ind_table(handler);
8769 handler = table[opc2];
8770 if (is_indirect_opcode(handler)) {
8771 table = ind_table(handler);
8772 /* opc3 is 5 bits long */
8773 for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN;
8774 opc3++) {
8775 handler = table[opc3];
8776 if (handler->handler != &gen_invalid) {
8777 /* Special hack to properly dump SPE insns */
8778 p = strchr(handler->oname, '_');
8779 if (p == NULL) {
8780 printf("INSN: %02x %02x %02x (%02d %04d) : "
8781 "%s\n",
8782 opc1, opc2, opc3, opc1,
8783 (opc3 << 5) | opc2,
8784 handler->oname);
8785 } else {
8786 q = "speundef";
8787 if ((p - handler->oname) != strlen(q) ||
8788 memcmp(handler->oname, q, strlen(q)) != 0) {
8789 /* First instruction */
8790 printf("INSN: %02x %02x %02x (%02d %04d) : "
8791 "%.*s\n",
8792 opc1, opc2 << 1, opc3, opc1,
8793 (opc3 << 6) | (opc2 << 1),
8794 (int)(p - handler->oname),
8795 handler->oname);
8796 }
8797 if (strcmp(p + 1, q) != 0) {
8798 /* Second instruction */
8799 printf("INSN: %02x %02x %02x (%02d %04d) : "
8800 "%s\n",
8801 opc1, (opc2 << 1) | 1, opc3, opc1,
8802 (opc3 << 6) | (opc2 << 1) | 1,
8803 p + 1);
8804 }
8805 }
8806 }
8807 }
8808 } else {
8809 if (handler->handler != &gen_invalid) {
8810 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
8811 opc1, opc2, opc1, opc2, handler->oname);
8812 }
8813 }
8814 }
8815 } else {
8816 if (handler->handler != &gen_invalid) {
8817 printf("INSN: %02x -- -- (%02d ----) : %s\n",
8818 opc1, opc1, handler->oname);
8819 }
8820 }
8821 }
8822 }
8823 #endif
8824
8825 static bool avr_need_swap(CPUPPCState *env)
8826 {
8827 #ifdef HOST_WORDS_BIGENDIAN
8828 return msr_le;
8829 #else
8830 return !msr_le;
8831 #endif
8832 }
8833
8834 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8835 {
8836 if (n < 32) {
8837 stfq_p(mem_buf, env->fpr[n]);
8838 ppc_maybe_bswap_register(env, mem_buf, 8);
8839 return 8;
8840 }
8841 if (n == 32) {
8842 stl_p(mem_buf, env->fpscr);
8843 ppc_maybe_bswap_register(env, mem_buf, 4);
8844 return 4;
8845 }
8846 return 0;
8847 }
8848
8849 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8850 {
8851 if (n < 32) {
8852 ppc_maybe_bswap_register(env, mem_buf, 8);
8853 env->fpr[n] = ldfq_p(mem_buf);
8854 return 8;
8855 }
8856 if (n == 32) {
8857 ppc_maybe_bswap_register(env, mem_buf, 4);
8858 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
8859 return 4;
8860 }
8861 return 0;
8862 }
8863
8864 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8865 {
8866 if (n < 32) {
8867 if (!avr_need_swap(env)) {
8868 stq_p(mem_buf, env->avr[n].u64[0]);
8869 stq_p(mem_buf+8, env->avr[n].u64[1]);
8870 } else {
8871 stq_p(mem_buf, env->avr[n].u64[1]);
8872 stq_p(mem_buf+8, env->avr[n].u64[0]);
8873 }
8874 ppc_maybe_bswap_register(env, mem_buf, 8);
8875 ppc_maybe_bswap_register(env, mem_buf + 8, 8);
8876 return 16;
8877 }
8878 if (n == 32) {
8879 stl_p(mem_buf, env->vscr);
8880 ppc_maybe_bswap_register(env, mem_buf, 4);
8881 return 4;
8882 }
8883 if (n == 33) {
8884 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
8885 ppc_maybe_bswap_register(env, mem_buf, 4);
8886 return 4;
8887 }
8888 return 0;
8889 }
8890
8891 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8892 {
8893 if (n < 32) {
8894 ppc_maybe_bswap_register(env, mem_buf, 8);
8895 ppc_maybe_bswap_register(env, mem_buf + 8, 8);
8896 if (!avr_need_swap(env)) {
8897 env->avr[n].u64[0] = ldq_p(mem_buf);
8898 env->avr[n].u64[1] = ldq_p(mem_buf+8);
8899 } else {
8900 env->avr[n].u64[1] = ldq_p(mem_buf);
8901 env->avr[n].u64[0] = ldq_p(mem_buf+8);
8902 }
8903 return 16;
8904 }
8905 if (n == 32) {
8906 ppc_maybe_bswap_register(env, mem_buf, 4);
8907 env->vscr = ldl_p(mem_buf);
8908 return 4;
8909 }
8910 if (n == 33) {
8911 ppc_maybe_bswap_register(env, mem_buf, 4);
8912 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
8913 return 4;
8914 }
8915 return 0;
8916 }
8917
8918 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8919 {
8920 if (n < 32) {
8921 #if defined(TARGET_PPC64)
8922 stl_p(mem_buf, env->gpr[n] >> 32);
8923 ppc_maybe_bswap_register(env, mem_buf, 4);
8924 #else
8925 stl_p(mem_buf, env->gprh[n]);
8926 #endif
8927 return 4;
8928 }
8929 if (n == 32) {
8930 stq_p(mem_buf, env->spe_acc);
8931 ppc_maybe_bswap_register(env, mem_buf, 8);
8932 return 8;
8933 }
8934 if (n == 33) {
8935 stl_p(mem_buf, env->spe_fscr);
8936 ppc_maybe_bswap_register(env, mem_buf, 4);
8937 return 4;
8938 }
8939 return 0;
8940 }
8941
8942 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8943 {
8944 if (n < 32) {
8945 #if defined(TARGET_PPC64)
8946 target_ulong lo = (uint32_t)env->gpr[n];
8947 target_ulong hi;
8948
8949 ppc_maybe_bswap_register(env, mem_buf, 4);
8950
8951 hi = (target_ulong)ldl_p(mem_buf) << 32;
8952 env->gpr[n] = lo | hi;
8953 #else
8954 env->gprh[n] = ldl_p(mem_buf);
8955 #endif
8956 return 4;
8957 }
8958 if (n == 32) {
8959 ppc_maybe_bswap_register(env, mem_buf, 8);
8960 env->spe_acc = ldq_p(mem_buf);
8961 return 8;
8962 }
8963 if (n == 33) {
8964 ppc_maybe_bswap_register(env, mem_buf, 4);
8965 env->spe_fscr = ldl_p(mem_buf);
8966 return 4;
8967 }
8968 return 0;
8969 }
8970
8971 static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8972 {
8973 if (n < 32) {
8974 stq_p(mem_buf, env->vsr[n]);
8975 ppc_maybe_bswap_register(env, mem_buf, 8);
8976 return 8;
8977 }
8978 return 0;
8979 }
8980
8981 static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8982 {
8983 if (n < 32) {
8984 ppc_maybe_bswap_register(env, mem_buf, 8);
8985 env->vsr[n] = ldq_p(mem_buf);
8986 return 8;
8987 }
8988 return 0;
8989 }
8990
8991 static int ppc_fixup_cpu(PowerPCCPU *cpu)
8992 {
8993 CPUPPCState *env = &cpu->env;
8994
8995 /* TCG doesn't (yet) emulate some groups of instructions that
8996 * are implemented on some otherwise supported CPUs (e.g. VSX
8997 * and decimal floating point instructions on POWER7). We
8998 * remove unsupported instruction groups from the cpu state's
8999 * instruction masks and hope the guest can cope. For at
9000 * least the pseries machine, the unavailability of these
9001 * instructions can be advertised to the guest via the device
9002 * tree. */
9003 if ((env->insns_flags & ~PPC_TCG_INSNS)
9004 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
9005 fprintf(stderr, "Warning: Disabling some instructions which are not "
9006 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
9007 env->insns_flags & ~PPC_TCG_INSNS,
9008 env->insns_flags2 & ~PPC_TCG_INSNS2);
9009 }
9010 env->insns_flags &= PPC_TCG_INSNS;
9011 env->insns_flags2 &= PPC_TCG_INSNS2;
9012 return 0;
9013 }
9014
9015 static inline bool ppc_cpu_is_valid(PowerPCCPUClass *pcc)
9016 {
9017 #ifdef TARGET_PPCEMB
9018 return pcc->mmu_model == POWERPC_MMU_BOOKE ||
9019 pcc->mmu_model == POWERPC_MMU_SOFT_4xx ||
9020 pcc->mmu_model == POWERPC_MMU_SOFT_4xx_Z;
9021 #else
9022 return true;
9023 #endif
9024 }
9025
9026 static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
9027 {
9028 CPUState *cs = CPU(dev);
9029 PowerPCCPU *cpu = POWERPC_CPU(dev);
9030 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9031 Error *local_err = NULL;
9032 #if !defined(CONFIG_USER_ONLY)
9033 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
9034 #endif
9035
9036 #if !defined(CONFIG_USER_ONLY)
9037 if (smp_threads > max_smt) {
9038 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
9039 max_smt, kvm_enabled() ? "KVM" : "TCG");
9040 return;
9041 }
9042 if (!is_power_of_2(smp_threads)) {
9043 error_setg(errp, "Cannot support %d threads on PPC with %s, "
9044 "threads count must be a power of 2.",
9045 smp_threads, kvm_enabled() ? "KVM" : "TCG");
9046 return;
9047 }
9048 #endif
9049
9050 cpu_exec_init(cs, &local_err);
9051 if (local_err != NULL) {
9052 error_propagate(errp, local_err);
9053 return;
9054 }
9055
9056 #if !defined(CONFIG_USER_ONLY)
9057 cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt
9058 + (cs->cpu_index % smp_threads);
9059 #endif
9060
9061 if (tcg_enabled()) {
9062 if (ppc_fixup_cpu(cpu) != 0) {
9063 error_setg(errp, "Unable to emulate selected CPU with TCG");
9064 return;
9065 }
9066 }
9067
9068 #if defined(TARGET_PPCEMB)
9069 if (!ppc_cpu_is_valid(pcc)) {
9070 error_setg(errp, "CPU does not possess a BookE or 4xx MMU. "
9071 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
9072 "or choose another CPU model.");
9073 return;
9074 }
9075 #endif
9076
9077 create_ppc_opcodes(cpu, &local_err);
9078 if (local_err != NULL) {
9079 error_propagate(errp, local_err);
9080 return;
9081 }
9082 init_ppc_proc(cpu);
9083
9084 if (pcc->insns_flags & PPC_FLOAT) {
9085 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
9086 33, "power-fpu.xml", 0);
9087 }
9088 if (pcc->insns_flags & PPC_ALTIVEC) {
9089 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
9090 34, "power-altivec.xml", 0);
9091 }
9092 if (pcc->insns_flags & PPC_SPE) {
9093 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
9094 34, "power-spe.xml", 0);
9095 }
9096 if (pcc->insns_flags2 & PPC2_VSX) {
9097 gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
9098 32, "power-vsx.xml", 0);
9099 }
9100
9101 qemu_init_vcpu(cs);
9102
9103 pcc->parent_realize(dev, errp);
9104
9105 #if defined(PPC_DUMP_CPU)
9106 {
9107 CPUPPCState *env = &cpu->env;
9108 const char *mmu_model, *excp_model, *bus_model;
9109 switch (env->mmu_model) {
9110 case POWERPC_MMU_32B:
9111 mmu_model = "PowerPC 32";
9112 break;
9113 case POWERPC_MMU_SOFT_6xx:
9114 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9115 break;
9116 case POWERPC_MMU_SOFT_74xx:
9117 mmu_model = "PowerPC 74xx with software driven TLBs";
9118 break;
9119 case POWERPC_MMU_SOFT_4xx:
9120 mmu_model = "PowerPC 4xx with software driven TLBs";
9121 break;
9122 case POWERPC_MMU_SOFT_4xx_Z:
9123 mmu_model = "PowerPC 4xx with software driven TLBs "
9124 "and zones protections";
9125 break;
9126 case POWERPC_MMU_REAL:
9127 mmu_model = "PowerPC real mode only";
9128 break;
9129 case POWERPC_MMU_MPC8xx:
9130 mmu_model = "PowerPC MPC8xx";
9131 break;
9132 case POWERPC_MMU_BOOKE:
9133 mmu_model = "PowerPC BookE";
9134 break;
9135 case POWERPC_MMU_BOOKE206:
9136 mmu_model = "PowerPC BookE 2.06";
9137 break;
9138 case POWERPC_MMU_601:
9139 mmu_model = "PowerPC 601";
9140 break;
9141 #if defined (TARGET_PPC64)
9142 case POWERPC_MMU_64B:
9143 mmu_model = "PowerPC 64";
9144 break;
9145 #endif
9146 default:
9147 mmu_model = "Unknown or invalid";
9148 break;
9149 }
9150 switch (env->excp_model) {
9151 case POWERPC_EXCP_STD:
9152 excp_model = "PowerPC";
9153 break;
9154 case POWERPC_EXCP_40x:
9155 excp_model = "PowerPC 40x";
9156 break;
9157 case POWERPC_EXCP_601:
9158 excp_model = "PowerPC 601";
9159 break;
9160 case POWERPC_EXCP_602:
9161 excp_model = "PowerPC 602";
9162 break;
9163 case POWERPC_EXCP_603:
9164 excp_model = "PowerPC 603";
9165 break;
9166 case POWERPC_EXCP_603E:
9167 excp_model = "PowerPC 603e";
9168 break;
9169 case POWERPC_EXCP_604:
9170 excp_model = "PowerPC 604";
9171 break;
9172 case POWERPC_EXCP_7x0:
9173 excp_model = "PowerPC 740/750";
9174 break;
9175 case POWERPC_EXCP_7x5:
9176 excp_model = "PowerPC 745/755";
9177 break;
9178 case POWERPC_EXCP_74xx:
9179 excp_model = "PowerPC 74xx";
9180 break;
9181 case POWERPC_EXCP_BOOKE:
9182 excp_model = "PowerPC BookE";
9183 break;
9184 #if defined (TARGET_PPC64)
9185 case POWERPC_EXCP_970:
9186 excp_model = "PowerPC 970";
9187 break;
9188 #endif
9189 default:
9190 excp_model = "Unknown or invalid";
9191 break;
9192 }
9193 switch (env->bus_model) {
9194 case PPC_FLAGS_INPUT_6xx:
9195 bus_model = "PowerPC 6xx";
9196 break;
9197 case PPC_FLAGS_INPUT_BookE:
9198 bus_model = "PowerPC BookE";
9199 break;
9200 case PPC_FLAGS_INPUT_405:
9201 bus_model = "PowerPC 405";
9202 break;
9203 case PPC_FLAGS_INPUT_401:
9204 bus_model = "PowerPC 401/403";
9205 break;
9206 case PPC_FLAGS_INPUT_RCPU:
9207 bus_model = "RCPU / MPC8xx";
9208 break;
9209 #if defined (TARGET_PPC64)
9210 case PPC_FLAGS_INPUT_970:
9211 bus_model = "PowerPC 970";
9212 break;
9213 #endif
9214 default:
9215 bus_model = "Unknown or invalid";
9216 break;
9217 }
9218 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9219 " MMU model : %s\n",
9220 object_class_get_name(OBJECT_CLASS(pcc)),
9221 pcc->pvr, pcc->msr_mask, mmu_model);
9222 #if !defined(CONFIG_USER_ONLY)
9223 if (env->tlb.tlb6) {
9224 printf(" %d %s TLB in %d ways\n",
9225 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9226 env->nb_ways);
9227 }
9228 #endif
9229 printf(" Exceptions model : %s\n"
9230 " Bus model : %s\n",
9231 excp_model, bus_model);
9232 printf(" MSR features :\n");
9233 if (env->flags & POWERPC_FLAG_SPE)
9234 printf(" signal processing engine enable"
9235 "\n");
9236 else if (env->flags & POWERPC_FLAG_VRE)
9237 printf(" vector processor enable\n");
9238 if (env->flags & POWERPC_FLAG_TGPR)
9239 printf(" temporary GPRs\n");
9240 else if (env->flags & POWERPC_FLAG_CE)
9241 printf(" critical input enable\n");
9242 if (env->flags & POWERPC_FLAG_SE)
9243 printf(" single-step trace mode\n");
9244 else if (env->flags & POWERPC_FLAG_DWE)
9245 printf(" debug wait enable\n");
9246 else if (env->flags & POWERPC_FLAG_UBLE)
9247 printf(" user BTB lock enable\n");
9248 if (env->flags & POWERPC_FLAG_BE)
9249 printf(" branch-step trace mode\n");
9250 else if (env->flags & POWERPC_FLAG_DE)
9251 printf(" debug interrupt enable\n");
9252 if (env->flags & POWERPC_FLAG_PX)
9253 printf(" inclusive protection\n");
9254 else if (env->flags & POWERPC_FLAG_PMM)
9255 printf(" performance monitor mark\n");
9256 if (env->flags == POWERPC_FLAG_NONE)
9257 printf(" none\n");
9258 printf(" Time-base/decrementer clock source: %s\n",
9259 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
9260 dump_ppc_insns(env);
9261 dump_ppc_sprs(env);
9262 fflush(stdout);
9263 }
9264 #endif
9265 }
9266
9267 static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
9268 {
9269 PowerPCCPU *cpu = POWERPC_CPU(dev);
9270 CPUPPCState *env = &cpu->env;
9271 opc_handler_t **table;
9272 int i, j;
9273
9274 cpu_exec_exit(CPU(dev));
9275
9276 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
9277 if (env->opcodes[i] == &invalid_handler) {
9278 continue;
9279 }
9280 if (is_indirect_opcode(env->opcodes[i])) {
9281 table = ind_table(env->opcodes[i]);
9282 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
9283 if (table[j] != &invalid_handler &&
9284 is_indirect_opcode(table[j])) {
9285 g_free((opc_handler_t *)((uintptr_t)table[j] &
9286 ~PPC_INDIRECT));
9287 }
9288 }
9289 g_free((opc_handler_t *)((uintptr_t)env->opcodes[i] &
9290 ~PPC_INDIRECT));
9291 }
9292 }
9293 }
9294
9295 int ppc_get_compat_smt_threads(PowerPCCPU *cpu)
9296 {
9297 int ret = MIN(smp_threads, kvmppc_smt_threads());
9298
9299 switch (cpu->cpu_version) {
9300 case CPU_POWERPC_LOGICAL_2_05:
9301 ret = MIN(ret, 2);
9302 break;
9303 case CPU_POWERPC_LOGICAL_2_06:
9304 ret = MIN(ret, 4);
9305 break;
9306 case CPU_POWERPC_LOGICAL_2_07:
9307 ret = MIN(ret, 8);
9308 break;
9309 }
9310
9311 return ret;
9312 }
9313
9314 void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp)
9315 {
9316 int ret = 0;
9317 CPUPPCState *env = &cpu->env;
9318
9319 cpu->cpu_version = cpu_version;
9320
9321 switch (cpu_version) {
9322 case CPU_POWERPC_LOGICAL_2_05:
9323 env->spr[SPR_PCR] = PCR_COMPAT_2_05;
9324 break;
9325 case CPU_POWERPC_LOGICAL_2_06:
9326 env->spr[SPR_PCR] = PCR_COMPAT_2_06;
9327 break;
9328 case CPU_POWERPC_LOGICAL_2_06_PLUS:
9329 env->spr[SPR_PCR] = PCR_COMPAT_2_06;
9330 break;
9331 default:
9332 env->spr[SPR_PCR] = 0;
9333 break;
9334 }
9335
9336 if (kvm_enabled()) {
9337 ret = kvmppc_set_compat(cpu, cpu->cpu_version);
9338 if (ret < 0) {
9339 error_setg_errno(errp, -ret,
9340 "Unable to set CPU compatibility mode in KVM");
9341 }
9342 }
9343 }
9344
9345 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
9346 {
9347 ObjectClass *oc = (ObjectClass *)a;
9348 uint32_t pvr = *(uint32_t *)b;
9349 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
9350
9351 /* -cpu host does a PVR lookup during construction */
9352 if (unlikely(strcmp(object_class_get_name(oc),
9353 TYPE_HOST_POWERPC_CPU) == 0)) {
9354 return -1;
9355 }
9356
9357 if (!ppc_cpu_is_valid(pcc)) {
9358 return -1;
9359 }
9360
9361 return pcc->pvr == pvr ? 0 : -1;
9362 }
9363
9364 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
9365 {
9366 GSList *list, *item;
9367 PowerPCCPUClass *pcc = NULL;
9368
9369 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9370 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
9371 if (item != NULL) {
9372 pcc = POWERPC_CPU_CLASS(item->data);
9373 }
9374 g_slist_free(list);
9375
9376 return pcc;
9377 }
9378
9379 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
9380 {
9381 ObjectClass *oc = (ObjectClass *)a;
9382 uint32_t pvr = *(uint32_t *)b;
9383 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
9384
9385 /* -cpu host does a PVR lookup during construction */
9386 if (unlikely(strcmp(object_class_get_name(oc),
9387 TYPE_HOST_POWERPC_CPU) == 0)) {
9388 return -1;
9389 }
9390
9391 if (!ppc_cpu_is_valid(pcc)) {
9392 return -1;
9393 }
9394
9395 if (pcc->pvr_match(pcc, pvr)) {
9396 return 0;
9397 }
9398
9399 return -1;
9400 }
9401
9402 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
9403 {
9404 GSList *list, *item;
9405 PowerPCCPUClass *pcc = NULL;
9406
9407 list = object_class_get_list(TYPE_POWERPC_CPU, true);
9408 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
9409 if (item != NULL) {
9410 pcc = POWERPC_CPU_CLASS(item->data);
9411 }
9412 g_slist_free(list);
9413
9414 return pcc;
9415 }
9416
9417 static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
9418 {
9419 ObjectClass *oc = (ObjectClass *)a;
9420 const char *name = b;
9421 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9422
9423 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
9424 ppc_cpu_is_valid(pcc) &&
9425 strcmp(object_class_get_name(oc) + strlen(name),
9426 "-" TYPE_POWERPC_CPU) == 0) {
9427 return 0;
9428 }
9429 return -1;
9430 }
9431
9432
9433 static ObjectClass *ppc_cpu_class_by_name(const char *name);
9434
9435 static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
9436 {
9437 ObjectClass *invalid_class = (void*)ppc_cpu_class_by_alias;
9438
9439 /* Cache target class lookups in the alias table */
9440 if (!alias->oc) {
9441 alias->oc = ppc_cpu_class_by_name(alias->model);
9442 if (!alias->oc) {
9443 /* Fast check for non-existing aliases */
9444 alias->oc = invalid_class;
9445 }
9446 }
9447
9448 if (alias->oc == invalid_class) {
9449 return NULL;
9450 } else {
9451 return alias->oc;
9452 }
9453 }
9454
9455 static ObjectClass *ppc_cpu_class_by_name(const char *name)
9456 {
9457 GSList *list, *item;
9458 ObjectClass *ret = NULL;
9459 const char *p;
9460 int i, len;
9461
9462 /* Check if the given name is a PVR */
9463 len = strlen(name);
9464 if (len == 10 && name[0] == '0' && name[1] == 'x') {
9465 p = name + 2;
9466 goto check_pvr;
9467 } else if (len == 8) {
9468 p = name;
9469 check_pvr:
9470 for (i = 0; i < 8; i++) {
9471 if (!qemu_isxdigit(*p++))
9472 break;
9473 }
9474 if (i == 8) {
9475 return OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
9476 }
9477 }
9478
9479 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9480 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
9481 if (item != NULL) {
9482 ret = OBJECT_CLASS(item->data);
9483 }
9484 g_slist_free(list);
9485
9486 if (ret) {
9487 return ret;
9488 }
9489
9490 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9491 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
9492 return ppc_cpu_class_by_alias(&ppc_cpu_aliases[i]);
9493 }
9494 }
9495
9496 return NULL;
9497 }
9498
9499 PowerPCCPU *cpu_ppc_init(const char *cpu_model)
9500 {
9501 return POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model));
9502 }
9503
9504 /* Sort by PVR, ordering special case "host" last. */
9505 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
9506 {
9507 ObjectClass *oc_a = (ObjectClass *)a;
9508 ObjectClass *oc_b = (ObjectClass *)b;
9509 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
9510 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
9511 const char *name_a = object_class_get_name(oc_a);
9512 const char *name_b = object_class_get_name(oc_b);
9513
9514 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
9515 return 1;
9516 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
9517 return -1;
9518 } else {
9519 /* Avoid an integer overflow during subtraction */
9520 if (pcc_a->pvr < pcc_b->pvr) {
9521 return -1;
9522 } else if (pcc_a->pvr > pcc_b->pvr) {
9523 return 1;
9524 } else {
9525 return 0;
9526 }
9527 }
9528 }
9529
9530 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
9531 {
9532 ObjectClass *oc = data;
9533 CPUListState *s = user_data;
9534 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9535 const char *typename = object_class_get_name(oc);
9536 char *name;
9537 int i;
9538
9539 if (!ppc_cpu_is_valid(pcc)) {
9540 return;
9541 }
9542 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
9543 return;
9544 }
9545
9546 name = g_strndup(typename,
9547 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
9548 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
9549 name, pcc->pvr);
9550 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9551 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
9552 ObjectClass *alias_oc = ppc_cpu_class_by_alias(alias);
9553
9554 if (alias_oc != oc) {
9555 continue;
9556 }
9557 (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
9558 alias->alias, name);
9559 }
9560 g_free(name);
9561 }
9562
9563 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
9564 {
9565 CPUListState s = {
9566 .file = f,
9567 .cpu_fprintf = cpu_fprintf,
9568 };
9569 GSList *list;
9570
9571 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9572 list = g_slist_sort(list, ppc_cpu_list_compare);
9573 g_slist_foreach(list, ppc_cpu_list_entry, &s);
9574 g_slist_free(list);
9575
9576 #ifdef CONFIG_KVM
9577 cpu_fprintf(f, "\n");
9578 cpu_fprintf(f, "PowerPC %-16s\n", "host");
9579 #endif
9580 }
9581
9582 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
9583 {
9584 ObjectClass *oc = data;
9585 CpuDefinitionInfoList **first = user_data;
9586 const char *typename;
9587 CpuDefinitionInfoList *entry;
9588 CpuDefinitionInfo *info;
9589 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9590
9591 if (!ppc_cpu_is_valid(pcc)) {
9592 return;
9593 }
9594
9595 typename = object_class_get_name(oc);
9596 info = g_malloc0(sizeof(*info));
9597 info->name = g_strndup(typename,
9598 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
9599
9600 entry = g_malloc0(sizeof(*entry));
9601 entry->value = info;
9602 entry->next = *first;
9603 *first = entry;
9604 }
9605
9606 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
9607 {
9608 CpuDefinitionInfoList *cpu_list = NULL;
9609 GSList *list;
9610 int i;
9611
9612 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9613 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
9614 g_slist_free(list);
9615
9616 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9617 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
9618 ObjectClass *oc;
9619 CpuDefinitionInfoList *entry;
9620 CpuDefinitionInfo *info;
9621
9622 oc = ppc_cpu_class_by_alias(alias);
9623 if (oc == NULL) {
9624 continue;
9625 }
9626
9627 info = g_malloc0(sizeof(*info));
9628 info->name = g_strdup(alias->alias);
9629
9630 entry = g_malloc0(sizeof(*entry));
9631 entry->value = info;
9632 entry->next = cpu_list;
9633 cpu_list = entry;
9634 }
9635
9636 return cpu_list;
9637 }
9638
9639 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
9640 {
9641 PowerPCCPU *cpu = POWERPC_CPU(cs);
9642
9643 cpu->env.nip = value;
9644 }
9645
9646 static bool ppc_cpu_has_work(CPUState *cs)
9647 {
9648 PowerPCCPU *cpu = POWERPC_CPU(cs);
9649 CPUPPCState *env = &cpu->env;
9650
9651 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
9652 }
9653
9654 static void ppc_cpu_exec_enter(CPUState *cs)
9655 {
9656 PowerPCCPU *cpu = POWERPC_CPU(cs);
9657 CPUPPCState *env = &cpu->env;
9658
9659 env->reserve_addr = -1;
9660 }
9661
9662 /* CPUClass::reset() */
9663 static void ppc_cpu_reset(CPUState *s)
9664 {
9665 PowerPCCPU *cpu = POWERPC_CPU(s);
9666 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9667 CPUPPCState *env = &cpu->env;
9668 target_ulong msr;
9669 int i;
9670
9671 pcc->parent_reset(s);
9672
9673 msr = (target_ulong)0;
9674 if (0) {
9675 /* XXX: find a suitable condition to enable the hypervisor mode */
9676 msr |= (target_ulong)MSR_HVB;
9677 }
9678 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
9679 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
9680 msr |= (target_ulong)1 << MSR_EP;
9681 #if defined(DO_SINGLE_STEP) && 0
9682 /* Single step trace mode */
9683 msr |= (target_ulong)1 << MSR_SE;
9684 msr |= (target_ulong)1 << MSR_BE;
9685 #endif
9686 #if defined(CONFIG_USER_ONLY)
9687 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
9688 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
9689 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
9690 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
9691 msr |= (target_ulong)1 << MSR_PR;
9692 #if defined(TARGET_PPC64)
9693 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
9694 #endif
9695 #if !defined(TARGET_WORDS_BIGENDIAN)
9696 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
9697 if (!((env->msr_mask >> MSR_LE) & 1)) {
9698 fprintf(stderr, "Selected CPU does not support little-endian.\n");
9699 exit(1);
9700 }
9701 #endif
9702 #endif
9703
9704 #if defined(TARGET_PPC64)
9705 if (env->mmu_model & POWERPC_MMU_64) {
9706 env->msr |= (1ULL << MSR_SF);
9707 }
9708 #endif
9709
9710 hreg_store_msr(env, msr, 1);
9711
9712 #if !defined(CONFIG_USER_ONLY)
9713 env->nip = env->hreset_vector | env->excp_prefix;
9714 if (env->mmu_model != POWERPC_MMU_REAL) {
9715 ppc_tlb_invalidate_all(env);
9716 }
9717 #endif
9718
9719 hreg_compute_hflags(env);
9720 env->reserve_addr = (target_ulong)-1ULL;
9721 /* Be sure no exception or interrupt is pending */
9722 env->pending_interrupts = 0;
9723 s->exception_index = POWERPC_EXCP_NONE;
9724 env->error_code = 0;
9725
9726 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
9727 env->vpa_addr = 0;
9728 env->slb_shadow_addr = 0;
9729 env->slb_shadow_size = 0;
9730 env->dtl_addr = 0;
9731 env->dtl_size = 0;
9732 #endif /* TARGET_PPC64 */
9733
9734 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
9735 ppc_spr_t *spr = &env->spr_cb[i];
9736
9737 if (!spr->name) {
9738 continue;
9739 }
9740 env->spr[i] = spr->default_value;
9741 }
9742
9743 /* Flush all TLBs */
9744 tlb_flush(s, 1);
9745 }
9746
9747 #ifndef CONFIG_USER_ONLY
9748 static bool ppc_cpu_is_big_endian(CPUState *cs)
9749 {
9750 PowerPCCPU *cpu = POWERPC_CPU(cs);
9751 CPUPPCState *env = &cpu->env;
9752
9753 cpu_synchronize_state(cs);
9754
9755 return !msr_le;
9756 }
9757 #endif
9758
9759 static void ppc_cpu_initfn(Object *obj)
9760 {
9761 CPUState *cs = CPU(obj);
9762 PowerPCCPU *cpu = POWERPC_CPU(obj);
9763 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9764 CPUPPCState *env = &cpu->env;
9765
9766 cs->env_ptr = env;
9767
9768 env->msr_mask = pcc->msr_mask;
9769 env->mmu_model = pcc->mmu_model;
9770 env->excp_model = pcc->excp_model;
9771 env->bus_model = pcc->bus_model;
9772 env->insns_flags = pcc->insns_flags;
9773 env->insns_flags2 = pcc->insns_flags2;
9774 env->flags = pcc->flags;
9775 env->bfd_mach = pcc->bfd_mach;
9776 env->check_pow = pcc->check_pow;
9777
9778 #if defined(TARGET_PPC64)
9779 if (pcc->sps) {
9780 env->sps = *pcc->sps;
9781 } else if (env->mmu_model & POWERPC_MMU_64) {
9782 /* Use default sets of page sizes */
9783 static const struct ppc_segment_page_sizes defsps = {
9784 .sps = {
9785 { .page_shift = 12, /* 4K */
9786 .slb_enc = 0,
9787 .enc = { { .page_shift = 12, .pte_enc = 0 } }
9788 },
9789 { .page_shift = 24, /* 16M */
9790 .slb_enc = 0x100,
9791 .enc = { { .page_shift = 24, .pte_enc = 0 } }
9792 },
9793 },
9794 };
9795 env->sps = defsps;
9796 }
9797 #endif /* defined(TARGET_PPC64) */
9798
9799 if (tcg_enabled()) {
9800 ppc_translate_init();
9801 }
9802 }
9803
9804 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
9805 {
9806 return pcc->pvr == pvr;
9807 }
9808
9809 static gchar *ppc_gdb_arch_name(CPUState *cs)
9810 {
9811 #if defined(TARGET_PPC64)
9812 return g_strdup("powerpc:common64");
9813 #else
9814 return g_strdup("powerpc:common");
9815 #endif
9816 }
9817
9818 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
9819 {
9820 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9821 CPUClass *cc = CPU_CLASS(oc);
9822 DeviceClass *dc = DEVICE_CLASS(oc);
9823
9824 pcc->parent_realize = dc->realize;
9825 pcc->pvr_match = ppc_pvr_match_default;
9826 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
9827 dc->realize = ppc_cpu_realizefn;
9828 dc->unrealize = ppc_cpu_unrealizefn;
9829
9830 pcc->parent_reset = cc->reset;
9831 cc->reset = ppc_cpu_reset;
9832
9833 cc->class_by_name = ppc_cpu_class_by_name;
9834 cc->has_work = ppc_cpu_has_work;
9835 cc->do_interrupt = ppc_cpu_do_interrupt;
9836 cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt;
9837 cc->dump_state = ppc_cpu_dump_state;
9838 cc->dump_statistics = ppc_cpu_dump_statistics;
9839 cc->set_pc = ppc_cpu_set_pc;
9840 cc->gdb_read_register = ppc_cpu_gdb_read_register;
9841 cc->gdb_write_register = ppc_cpu_gdb_write_register;
9842 #ifdef CONFIG_USER_ONLY
9843 cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault;
9844 #else
9845 cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
9846 cc->vmsd = &vmstate_ppc_cpu;
9847 #if defined(TARGET_PPC64)
9848 cc->write_elf64_note = ppc64_cpu_write_elf64_note;
9849 #endif
9850 #endif
9851 cc->cpu_exec_enter = ppc_cpu_exec_enter;
9852
9853 cc->gdb_num_core_regs = 71;
9854
9855 #ifdef USE_APPLE_GDB
9856 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
9857 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
9858 cc->gdb_num_core_regs = 71 + 32;
9859 #endif
9860
9861 cc->gdb_arch_name = ppc_gdb_arch_name;
9862 #if defined(TARGET_PPC64)
9863 cc->gdb_core_xml_file = "power64-core.xml";
9864 #else
9865 cc->gdb_core_xml_file = "power-core.xml";
9866 #endif
9867 #ifndef CONFIG_USER_ONLY
9868 cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
9869 #endif
9870
9871 dc->fw_name = "PowerPC,UNKNOWN";
9872 }
9873
9874 static const TypeInfo ppc_cpu_type_info = {
9875 .name = TYPE_POWERPC_CPU,
9876 .parent = TYPE_CPU,
9877 .instance_size = sizeof(PowerPCCPU),
9878 .instance_init = ppc_cpu_initfn,
9879 .abstract = true,
9880 .class_size = sizeof(PowerPCCPUClass),
9881 .class_init = ppc_cpu_class_init,
9882 };
9883
9884 static void ppc_cpu_register_types(void)
9885 {
9886 type_register_static(&ppc_cpu_type_info);
9887 }
9888
9889 type_init(ppc_cpu_register_types)
AR7 emulation for QEMU