?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
virtio-scsi: dataplane: fail setup gracefully
[qemu/ar7.git] / hw / display / pxa2xx_lcd.c
blobac3c018822f5df659591f747d80d2bdce987d025
1 /*
2 * Intel XScale PXA255/270 LCDC emulation.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPLv2.
8 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
11 */
12
13 #include "hw/hw.h"
14 #include "ui/console.h"
15 #include "hw/arm/pxa.h"
16 #include "ui/pixel_ops.h"
17 /* FIXME: For graphic_rotate. Should probably be done in common code. */
18 #include "sysemu/sysemu.h"
19 #include "framebuffer.h"
20
21 struct DMAChannel {
22 uint32_t branch;
23 uint8_t up;
24 uint8_t palette[1024];
25 uint8_t pbuffer[1024];
26 void (*redraw)(PXA2xxLCDState *s, hwaddr addr,
27 int *miny, int *maxy);
28
29 uint32_t descriptor;
30 uint32_t source;
31 uint32_t id;
32 uint32_t command;
33 };
34
35 struct PXA2xxLCDState {
36 MemoryRegion *sysmem;
37 MemoryRegion iomem;
38 qemu_irq irq;
39 int irqlevel;
40
41 int invalidated;
42 QemuConsole *con;
43 drawfn *line_fn[2];
44 int dest_width;
45 int xres, yres;
46 int pal_for;
47 int transp;
48 enum {
49 pxa_lcdc_2bpp = 1,
50 pxa_lcdc_4bpp = 2,
51 pxa_lcdc_8bpp = 3,
52 pxa_lcdc_16bpp = 4,
53 pxa_lcdc_18bpp = 5,
54 pxa_lcdc_18pbpp = 6,
55 pxa_lcdc_19bpp = 7,
56 pxa_lcdc_19pbpp = 8,
57 pxa_lcdc_24bpp = 9,
58 pxa_lcdc_25bpp = 10,
59 } bpp;
60
61 uint32_t control[6];
62 uint32_t status[2];
63 uint32_t ovl1c[2];
64 uint32_t ovl2c[2];
65 uint32_t ccr;
66 uint32_t cmdcr;
67 uint32_t trgbr;
68 uint32_t tcr;
69 uint32_t liidr;
70 uint8_t bscntr;
71
72 struct DMAChannel dma_ch[7];
73
74 qemu_irq vsync_cb;
75 int orientation;
76 };
77
78 typedef struct QEMU_PACKED {
79 uint32_t fdaddr;
80 uint32_t fsaddr;
81 uint32_t fidr;
82 uint32_t ldcmd;
83 } PXAFrameDescriptor;
84
85 #define LCCR0 0x000 /* LCD Controller Control register 0 */
86 #define LCCR1 0x004 /* LCD Controller Control register 1 */
87 #define LCCR2 0x008 /* LCD Controller Control register 2 */
88 #define LCCR3 0x00c /* LCD Controller Control register 3 */
89 #define LCCR4 0x010 /* LCD Controller Control register 4 */
90 #define LCCR5 0x014 /* LCD Controller Control register 5 */
91
92 #define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
93 #define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
94 #define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
95 #define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
96 #define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
97 #define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
98 #define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
99
100 #define LCSR1 0x034 /* LCD Controller Status register 1 */
101 #define LCSR0 0x038 /* LCD Controller Status register 0 */
102 #define LIIDR 0x03c /* LCD Controller Interrupt ID register */
103
104 #define TRGBR 0x040 /* TMED RGB Seed register */
105 #define TCR 0x044 /* TMED Control register */
106
107 #define OVL1C1 0x050 /* Overlay 1 Control register 1 */
108 #define OVL1C2 0x060 /* Overlay 1 Control register 2 */
109 #define OVL2C1 0x070 /* Overlay 2 Control register 1 */
110 #define OVL2C2 0x080 /* Overlay 2 Control register 2 */
111 #define CCR 0x090 /* Cursor Control register */
112
113 #define CMDCR 0x100 /* Command Control register */
114 #define PRSR 0x104 /* Panel Read Status register */
115
116 #define PXA_LCDDMA_CHANS 7
117 #define DMA_FDADR 0x00 /* Frame Descriptor Address register */
118 #define DMA_FSADR 0x04 /* Frame Source Address register */
119 #define DMA_FIDR 0x08 /* Frame ID register */
120 #define DMA_LDCMD 0x0c /* Command register */
121
122 /* LCD Buffer Strength Control register */
123 #define BSCNTR 0x04000054
124
125 /* Bitfield masks */
126 #define LCCR0_ENB (1 << 0)
127 #define LCCR0_CMS (1 << 1)
128 #define LCCR0_SDS (1 << 2)
129 #define LCCR0_LDM (1 << 3)
130 #define LCCR0_SOFM0 (1 << 4)
131 #define LCCR0_IUM (1 << 5)
132 #define LCCR0_EOFM0 (1 << 6)
133 #define LCCR0_PAS (1 << 7)
134 #define LCCR0_DPD (1 << 9)
135 #define LCCR0_DIS (1 << 10)
136 #define LCCR0_QDM (1 << 11)
137 #define LCCR0_PDD (0xff << 12)
138 #define LCCR0_BSM0 (1 << 20)
139 #define LCCR0_OUM (1 << 21)
140 #define LCCR0_LCDT (1 << 22)
141 #define LCCR0_RDSTM (1 << 23)
142 #define LCCR0_CMDIM (1 << 24)
143 #define LCCR0_OUC (1 << 25)
144 #define LCCR0_LDDALT (1 << 26)
145 #define LCCR1_PPL(x) ((x) & 0x3ff)
146 #define LCCR2_LPP(x) ((x) & 0x3ff)
147 #define LCCR3_API (15 << 16)
148 #define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
149 #define LCCR3_PDFOR(x) (((x) >> 30) & 3)
150 #define LCCR4_K1(x) (((x) >> 0) & 7)
151 #define LCCR4_K2(x) (((x) >> 3) & 7)
152 #define LCCR4_K3(x) (((x) >> 6) & 7)
153 #define LCCR4_PALFOR(x) (((x) >> 15) & 3)
154 #define LCCR5_SOFM(ch) (1 << (ch - 1))
155 #define LCCR5_EOFM(ch) (1 << (ch + 7))
156 #define LCCR5_BSM(ch) (1 << (ch + 15))
157 #define LCCR5_IUM(ch) (1 << (ch + 23))
158 #define OVLC1_EN (1 << 31)
159 #define CCR_CEN (1 << 31)
160 #define FBR_BRA (1 << 0)
161 #define FBR_BINT (1 << 1)
162 #define FBR_SRCADDR (0xfffffff << 4)
163 #define LCSR0_LDD (1 << 0)
164 #define LCSR0_SOF0 (1 << 1)
165 #define LCSR0_BER (1 << 2)
166 #define LCSR0_ABC (1 << 3)
167 #define LCSR0_IU0 (1 << 4)
168 #define LCSR0_IU1 (1 << 5)
169 #define LCSR0_OU (1 << 6)
170 #define LCSR0_QD (1 << 7)
171 #define LCSR0_EOF0 (1 << 8)
172 #define LCSR0_BS0 (1 << 9)
173 #define LCSR0_SINT (1 << 10)
174 #define LCSR0_RDST (1 << 11)
175 #define LCSR0_CMDINT (1 << 12)
176 #define LCSR0_BERCH(x) (((x) & 7) << 28)
177 #define LCSR1_SOF(ch) (1 << (ch - 1))
178 #define LCSR1_EOF(ch) (1 << (ch + 7))
179 #define LCSR1_BS(ch) (1 << (ch + 15))
180 #define LCSR1_IU(ch) (1 << (ch + 23))
181 #define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
182 #define LDCMD_EOFINT (1 << 21)
183 #define LDCMD_SOFINT (1 << 22)
184 #define LDCMD_PAL (1 << 26)
185
186 /* Route internal interrupt lines to the global IC */
187 static void pxa2xx_lcdc_int_update(PXA2xxLCDState *s)
188 {
189 int level = 0;
190 level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM);
191 level |= (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SOFM0);
192 level |= (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IUM);
193 level |= (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IUM(1));
194 level |= (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OUM);
195 level |= (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QDM);
196 level |= (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EOFM0);
197 level |= (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BSM0);
198 level |= (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RDSTM);
199 level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM);
200 level |= (s->status[1] & ~s->control[5]);
201
202 qemu_set_irq(s->irq, !!level);
203 s->irqlevel = level;
204 }
205
206 /* Set Branch Status interrupt high and poke associated registers */
207 static inline void pxa2xx_dma_bs_set(PXA2xxLCDState *s, int ch)
208 {
209 int unmasked;
210 if (ch == 0) {
211 s->status[0] |= LCSR0_BS0;
212 unmasked = !(s->control[0] & LCCR0_BSM0);
213 } else {
214 s->status[1] |= LCSR1_BS(ch);
215 unmasked = !(s->control[5] & LCCR5_BSM(ch));
216 }
217
218 if (unmasked) {
219 if (s->irqlevel)
220 s->status[0] |= LCSR0_SINT;
221 else
222 s->liidr = s->dma_ch[ch].id;
223 }
224 }
225
226 /* Set Start Of Frame Status interrupt high and poke associated registers */
227 static inline void pxa2xx_dma_sof_set(PXA2xxLCDState *s, int ch)
228 {
229 int unmasked;
230 if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
231 return;
232
233 if (ch == 0) {
234 s->status[0] |= LCSR0_SOF0;
235 unmasked = !(s->control[0] & LCCR0_SOFM0);
236 } else {
237 s->status[1] |= LCSR1_SOF(ch);
238 unmasked = !(s->control[5] & LCCR5_SOFM(ch));
239 }
240
241 if (unmasked) {
242 if (s->irqlevel)
243 s->status[0] |= LCSR0_SINT;
244 else
245 s->liidr = s->dma_ch[ch].id;
246 }
247 }
248
249 /* Set End Of Frame Status interrupt high and poke associated registers */
250 static inline void pxa2xx_dma_eof_set(PXA2xxLCDState *s, int ch)
251 {
252 int unmasked;
253 if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
254 return;
255
256 if (ch == 0) {
257 s->status[0] |= LCSR0_EOF0;
258 unmasked = !(s->control[0] & LCCR0_EOFM0);
259 } else {
260 s->status[1] |= LCSR1_EOF(ch);
261 unmasked = !(s->control[5] & LCCR5_EOFM(ch));
262 }
263
264 if (unmasked) {
265 if (s->irqlevel)
266 s->status[0] |= LCSR0_SINT;
267 else
268 s->liidr = s->dma_ch[ch].id;
269 }
270 }
271
272 /* Set Bus Error Status interrupt high and poke associated registers */
273 static inline void pxa2xx_dma_ber_set(PXA2xxLCDState *s, int ch)
274 {
275 s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
276 if (s->irqlevel)
277 s->status[0] |= LCSR0_SINT;
278 else
279 s->liidr = s->dma_ch[ch].id;
280 }
281
282 /* Load new Frame Descriptors from DMA */
283 static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
284 {
285 PXAFrameDescriptor desc;
286 hwaddr descptr;
287 int i;
288
289 for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
290 s->dma_ch[i].source = 0;
291
292 if (!s->dma_ch[i].up)
293 continue;
294
295 if (s->dma_ch[i].branch & FBR_BRA) {
296 descptr = s->dma_ch[i].branch & FBR_SRCADDR;
297 if (s->dma_ch[i].branch & FBR_BINT)
298 pxa2xx_dma_bs_set(s, i);
299 s->dma_ch[i].branch &= ~FBR_BRA;
300 } else
301 descptr = s->dma_ch[i].descriptor;
302
303 if (!((descptr >= PXA2XX_SDRAM_BASE && descptr +
304 sizeof(desc) <= PXA2XX_SDRAM_BASE + ram_size) ||
305 (descptr >= PXA2XX_INTERNAL_BASE && descptr + sizeof(desc) <=
306 PXA2XX_INTERNAL_BASE + PXA2XX_INTERNAL_SIZE))) {
307 continue;
308 }
309
310 cpu_physical_memory_read(descptr, &desc, sizeof(desc));
311 s->dma_ch[i].descriptor = tswap32(desc.fdaddr);
312 s->dma_ch[i].source = tswap32(desc.fsaddr);
313 s->dma_ch[i].id = tswap32(desc.fidr);
314 s->dma_ch[i].command = tswap32(desc.ldcmd);
315 }
316 }
317
318 static uint64_t pxa2xx_lcdc_read(void *opaque, hwaddr offset,
319 unsigned size)
320 {
321 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
322 int ch;
323
324 switch (offset) {
325 case LCCR0:
326 return s->control[0];
327 case LCCR1:
328 return s->control[1];
329 case LCCR2:
330 return s->control[2];
331 case LCCR3:
332 return s->control[3];
333 case LCCR4:
334 return s->control[4];
335 case LCCR5:
336 return s->control[5];
337
338 case OVL1C1:
339 return s->ovl1c[0];
340 case OVL1C2:
341 return s->ovl1c[1];
342 case OVL2C1:
343 return s->ovl2c[0];
344 case OVL2C2:
345 return s->ovl2c[1];
346
347 case CCR:
348 return s->ccr;
349
350 case CMDCR:
351 return s->cmdcr;
352
353 case TRGBR:
354 return s->trgbr;
355 case TCR:
356 return s->tcr;
357
358 case 0x200 ... 0x1000: /* DMA per-channel registers */
359 ch = (offset - 0x200) >> 4;
360 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
361 goto fail;
362
363 switch (offset & 0xf) {
364 case DMA_FDADR:
365 return s->dma_ch[ch].descriptor;
366 case DMA_FSADR:
367 return s->dma_ch[ch].source;
368 case DMA_FIDR:
369 return s->dma_ch[ch].id;
370 case DMA_LDCMD:
371 return s->dma_ch[ch].command;
372 default:
373 goto fail;
374 }
375
376 case FBR0:
377 return s->dma_ch[0].branch;
378 case FBR1:
379 return s->dma_ch[1].branch;
380 case FBR2:
381 return s->dma_ch[2].branch;
382 case FBR3:
383 return s->dma_ch[3].branch;
384 case FBR4:
385 return s->dma_ch[4].branch;
386 case FBR5:
387 return s->dma_ch[5].branch;
388 case FBR6:
389 return s->dma_ch[6].branch;
390
391 case BSCNTR:
392 return s->bscntr;
393
394 case PRSR:
395 return 0;
396
397 case LCSR0:
398 return s->status[0];
399 case LCSR1:
400 return s->status[1];
401 case LIIDR:
402 return s->liidr;
403
404 default:
405 fail:
406 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
407 }
408
409 return 0;
410 }
411
412 static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
413 uint64_t value, unsigned size)
414 {
415 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
416 int ch;
417
418 switch (offset) {
419 case LCCR0:
420 /* ACK Quick Disable done */
421 if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
422 s->status[0] |= LCSR0_QD;
423
424 if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
425 printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
426
427 if ((s->control[3] & LCCR3_API) &&
428 (value & LCCR0_ENB) && !(value & LCCR0_LCDT))
429 s->status[0] |= LCSR0_ABC;
430
431 s->control[0] = value & 0x07ffffff;
432 pxa2xx_lcdc_int_update(s);
433
434 s->dma_ch[0].up = !!(value & LCCR0_ENB);
435 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS);
436 break;
437
438 case LCCR1:
439 s->control[1] = value;
440 break;
441
442 case LCCR2:
443 s->control[2] = value;
444 break;
445
446 case LCCR3:
447 s->control[3] = value & 0xefffffff;
448 s->bpp = LCCR3_BPP(value);
449 break;
450
451 case LCCR4:
452 s->control[4] = value & 0x83ff81ff;
453 break;
454
455 case LCCR5:
456 s->control[5] = value & 0x3f3f3f3f;
457 break;
458
459 case OVL1C1:
460 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
461 printf("%s: Overlay 1 not supported\n", __FUNCTION__);
462
463 s->ovl1c[0] = value & 0x80ffffff;
464 s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
465 break;
466
467 case OVL1C2:
468 s->ovl1c[1] = value & 0x000fffff;
469 break;
470
471 case OVL2C1:
472 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
473 printf("%s: Overlay 2 not supported\n", __FUNCTION__);
474
475 s->ovl2c[0] = value & 0x80ffffff;
476 s->dma_ch[2].up = !!(value & OVLC1_EN);
477 s->dma_ch[3].up = !!(value & OVLC1_EN);
478 s->dma_ch[4].up = !!(value & OVLC1_EN);
479 break;
480
481 case OVL2C2:
482 s->ovl2c[1] = value & 0x007fffff;
483 break;
484
485 case CCR:
486 if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
487 printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
488
489 s->ccr = value & 0x81ffffe7;
490 s->dma_ch[5].up = !!(value & CCR_CEN);
491 break;
492
493 case CMDCR:
494 s->cmdcr = value & 0xff;
495 break;
496
497 case TRGBR:
498 s->trgbr = value & 0x00ffffff;
499 break;
500
501 case TCR:
502 s->tcr = value & 0x7fff;
503 break;
504
505 case 0x200 ... 0x1000: /* DMA per-channel registers */
506 ch = (offset - 0x200) >> 4;
507 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
508 goto fail;
509
510 switch (offset & 0xf) {
511 case DMA_FDADR:
512 s->dma_ch[ch].descriptor = value & 0xfffffff0;
513 break;
514
515 default:
516 goto fail;
517 }
518 break;
519
520 case FBR0:
521 s->dma_ch[0].branch = value & 0xfffffff3;
522 break;
523 case FBR1:
524 s->dma_ch[1].branch = value & 0xfffffff3;
525 break;
526 case FBR2:
527 s->dma_ch[2].branch = value & 0xfffffff3;
528 break;
529 case FBR3:
530 s->dma_ch[3].branch = value & 0xfffffff3;
531 break;
532 case FBR4:
533 s->dma_ch[4].branch = value & 0xfffffff3;
534 break;
535 case FBR5:
536 s->dma_ch[5].branch = value & 0xfffffff3;
537 break;
538 case FBR6:
539 s->dma_ch[6].branch = value & 0xfffffff3;
540 break;
541
542 case BSCNTR:
543 s->bscntr = value & 0xf;
544 break;
545
546 case PRSR:
547 break;
548
549 case LCSR0:
550 s->status[0] &= ~(value & 0xfff);
551 if (value & LCSR0_BER)
552 s->status[0] &= ~LCSR0_BERCH(7);
553 break;
554
555 case LCSR1:
556 s->status[1] &= ~(value & 0x3e3f3f);
557 break;
558
559 default:
560 fail:
561 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
562 }
563 }
564
565 static const MemoryRegionOps pxa2xx_lcdc_ops = {
566 .read = pxa2xx_lcdc_read,
567 .write = pxa2xx_lcdc_write,
568 .endianness = DEVICE_NATIVE_ENDIAN,
569 };
570
571 /* Load new palette for a given DMA channel, convert to internal format */
572 static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
573 {
574 DisplaySurface *surface = qemu_console_surface(s->con);
575 int i, n, format, r, g, b, alpha;
576 uint32_t *dest;
577 uint8_t *src;
578 s->pal_for = LCCR4_PALFOR(s->control[4]);
579 format = s->pal_for;
580
581 switch (bpp) {
582 case pxa_lcdc_2bpp:
583 n = 4;
584 break;
585 case pxa_lcdc_4bpp:
586 n = 16;
587 break;
588 case pxa_lcdc_8bpp:
589 n = 256;
590 break;
591 default:
592 format = 0;
593 return;
594 }
595
596 src = (uint8_t *) s->dma_ch[ch].pbuffer;
597 dest = (uint32_t *) s->dma_ch[ch].palette;
598 alpha = r = g = b = 0;
599
600 for (i = 0; i < n; i ++) {
601 switch (format) {
602 case 0: /* 16 bpp, no transparency */
603 alpha = 0;
604 if (s->control[0] & LCCR0_CMS) {
605 r = g = b = *(uint16_t *) src & 0xff;
606 }
607 else {
608 r = (*(uint16_t *) src & 0xf800) >> 8;
609 g = (*(uint16_t *) src & 0x07e0) >> 3;
610 b = (*(uint16_t *) src & 0x001f) << 3;
611 }
612 src += 2;
613 break;
614 case 1: /* 16 bpp plus transparency */
615 alpha = *(uint32_t *) src & (1 << 24);
616 if (s->control[0] & LCCR0_CMS)
617 r = g = b = *(uint32_t *) src & 0xff;
618 else {
619 r = (*(uint32_t *) src & 0xf80000) >> 16;
620 g = (*(uint32_t *) src & 0x00fc00) >> 8;
621 b = (*(uint32_t *) src & 0x0000f8);
622 }
623 src += 4;
624 break;
625 case 2: /* 18 bpp plus transparency */
626 alpha = *(uint32_t *) src & (1 << 24);
627 if (s->control[0] & LCCR0_CMS)
628 r = g = b = *(uint32_t *) src & 0xff;
629 else {
630 r = (*(uint32_t *) src & 0xfc0000) >> 16;
631 g = (*(uint32_t *) src & 0x00fc00) >> 8;
632 b = (*(uint32_t *) src & 0x0000fc);
633 }
634 src += 4;
635 break;
636 case 3: /* 24 bpp plus transparency */
637 alpha = *(uint32_t *) src & (1 << 24);
638 if (s->control[0] & LCCR0_CMS)
639 r = g = b = *(uint32_t *) src & 0xff;
640 else {
641 r = (*(uint32_t *) src & 0xff0000) >> 16;
642 g = (*(uint32_t *) src & 0x00ff00) >> 8;
643 b = (*(uint32_t *) src & 0x0000ff);
644 }
645 src += 4;
646 break;
647 }
648 switch (surface_bits_per_pixel(surface)) {
649 case 8:
650 *dest = rgb_to_pixel8(r, g, b) | alpha;
651 break;
652 case 15:
653 *dest = rgb_to_pixel15(r, g, b) | alpha;
654 break;
655 case 16:
656 *dest = rgb_to_pixel16(r, g, b) | alpha;
657 break;
658 case 24:
659 *dest = rgb_to_pixel24(r, g, b) | alpha;
660 break;
661 case 32:
662 *dest = rgb_to_pixel32(r, g, b) | alpha;
663 break;
664 }
665 dest ++;
666 }
667 }
668
669 static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
670 hwaddr addr, int *miny, int *maxy)
671 {
672 DisplaySurface *surface = qemu_console_surface(s->con);
673 int src_width, dest_width;
674 drawfn fn = NULL;
675 if (s->dest_width)
676 fn = s->line_fn[s->transp][s->bpp];
677 if (!fn)
678 return;
679
680 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
681 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
682 src_width *= 3;
683 else if (s->bpp > pxa_lcdc_16bpp)
684 src_width *= 4;
685 else if (s->bpp > pxa_lcdc_8bpp)
686 src_width *= 2;
687
688 dest_width = s->xres * s->dest_width;
689 *miny = 0;
690 framebuffer_update_display(surface, s->sysmem,
691 addr, s->xres, s->yres,
692 src_width, dest_width, s->dest_width,
693 s->invalidated,
694 fn, s->dma_ch[0].palette, miny, maxy);
695 }
696
697 static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
698 hwaddr addr, int *miny, int *maxy)
699 {
700 DisplaySurface *surface = qemu_console_surface(s->con);
701 int src_width, dest_width;
702 drawfn fn = NULL;
703 if (s->dest_width)
704 fn = s->line_fn[s->transp][s->bpp];
705 if (!fn)
706 return;
707
708 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
709 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
710 src_width *= 3;
711 else if (s->bpp > pxa_lcdc_16bpp)
712 src_width *= 4;
713 else if (s->bpp > pxa_lcdc_8bpp)
714 src_width *= 2;
715
716 dest_width = s->yres * s->dest_width;
717 *miny = 0;
718 framebuffer_update_display(surface, s->sysmem,
719 addr, s->xres, s->yres,
720 src_width, s->dest_width, -dest_width,
721 s->invalidated,
722 fn, s->dma_ch[0].palette,
723 miny, maxy);
724 }
725
726 static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
727 hwaddr addr, int *miny, int *maxy)
728 {
729 DisplaySurface *surface = qemu_console_surface(s->con);
730 int src_width, dest_width;
731 drawfn fn = NULL;
732 if (s->dest_width) {
733 fn = s->line_fn[s->transp][s->bpp];
734 }
735 if (!fn) {
736 return;
737 }
738
739 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
740 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
741 src_width *= 3;
742 } else if (s->bpp > pxa_lcdc_16bpp) {
743 src_width *= 4;
744 } else if (s->bpp > pxa_lcdc_8bpp) {
745 src_width *= 2;
746 }
747
748 dest_width = s->xres * s->dest_width;
749 *miny = 0;
750 framebuffer_update_display(surface, s->sysmem,
751 addr, s->xres, s->yres,
752 src_width, -dest_width, -s->dest_width,
753 s->invalidated,
754 fn, s->dma_ch[0].palette, miny, maxy);
755 }
756
757 static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s,
758 hwaddr addr, int *miny, int *maxy)
759 {
760 DisplaySurface *surface = qemu_console_surface(s->con);
761 int src_width, dest_width;
762 drawfn fn = NULL;
763 if (s->dest_width) {
764 fn = s->line_fn[s->transp][s->bpp];
765 }
766 if (!fn) {
767 return;
768 }
769
770 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
771 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
772 src_width *= 3;
773 } else if (s->bpp > pxa_lcdc_16bpp) {
774 src_width *= 4;
775 } else if (s->bpp > pxa_lcdc_8bpp) {
776 src_width *= 2;
777 }
778
779 dest_width = s->yres * s->dest_width;
780 *miny = 0;
781 framebuffer_update_display(surface, s->sysmem,
782 addr, s->xres, s->yres,
783 src_width, -s->dest_width, dest_width,
784 s->invalidated,
785 fn, s->dma_ch[0].palette,
786 miny, maxy);
787 }
788
789 static void pxa2xx_lcdc_resize(PXA2xxLCDState *s)
790 {
791 int width, height;
792 if (!(s->control[0] & LCCR0_ENB))
793 return;
794
795 width = LCCR1_PPL(s->control[1]) + 1;
796 height = LCCR2_LPP(s->control[2]) + 1;
797
798 if (width != s->xres || height != s->yres) {
799 if (s->orientation == 90 || s->orientation == 270) {
800 qemu_console_resize(s->con, height, width);
801 } else {
802 qemu_console_resize(s->con, width, height);
803 }
804 s->invalidated = 1;
805 s->xres = width;
806 s->yres = height;
807 }
808 }
809
810 static void pxa2xx_update_display(void *opaque)
811 {
812 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
813 hwaddr fbptr;
814 int miny, maxy;
815 int ch;
816 if (!(s->control[0] & LCCR0_ENB))
817 return;
818
819 pxa2xx_descriptor_load(s);
820
821 pxa2xx_lcdc_resize(s);
822 miny = s->yres;
823 maxy = 0;
824 s->transp = s->dma_ch[2].up || s->dma_ch[3].up;
825 /* Note: With overlay planes the order depends on LCCR0 bit 25. */
826 for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++)
827 if (s->dma_ch[ch].up) {
828 if (!s->dma_ch[ch].source) {
829 pxa2xx_dma_ber_set(s, ch);
830 continue;
831 }
832 fbptr = s->dma_ch[ch].source;
833 if (!((fbptr >= PXA2XX_SDRAM_BASE &&
834 fbptr <= PXA2XX_SDRAM_BASE + ram_size) ||
835 (fbptr >= PXA2XX_INTERNAL_BASE &&
836 fbptr <= PXA2XX_INTERNAL_BASE + PXA2XX_INTERNAL_SIZE))) {
837 pxa2xx_dma_ber_set(s, ch);
838 continue;
839 }
840
841 if (s->dma_ch[ch].command & LDCMD_PAL) {
842 cpu_physical_memory_read(fbptr, s->dma_ch[ch].pbuffer,
843 MAX(LDCMD_LENGTH(s->dma_ch[ch].command),
844 sizeof(s->dma_ch[ch].pbuffer)));
845 pxa2xx_palette_parse(s, ch, s->bpp);
846 } else {
847 /* Do we need to reparse palette */
848 if (LCCR4_PALFOR(s->control[4]) != s->pal_for)
849 pxa2xx_palette_parse(s, ch, s->bpp);
850
851 /* ACK frame start */
852 pxa2xx_dma_sof_set(s, ch);
853
854 s->dma_ch[ch].redraw(s, fbptr, &miny, &maxy);
855 s->invalidated = 0;
856
857 /* ACK frame completed */
858 pxa2xx_dma_eof_set(s, ch);
859 }
860 }
861
862 if (s->control[0] & LCCR0_DIS) {
863 /* ACK last frame completed */
864 s->control[0] &= ~LCCR0_ENB;
865 s->status[0] |= LCSR0_LDD;
866 }
867
868 if (miny >= 0) {
869 switch (s->orientation) {
870 case 0:
871 dpy_gfx_update(s->con, 0, miny, s->xres, maxy - miny + 1);
872 break;
873 case 90:
874 dpy_gfx_update(s->con, miny, 0, maxy - miny + 1, s->xres);
875 break;
876 case 180:
877 maxy = s->yres - maxy - 1;
878 miny = s->yres - miny - 1;
879 dpy_gfx_update(s->con, 0, maxy, s->xres, miny - maxy + 1);
880 break;
881 case 270:
882 maxy = s->yres - maxy - 1;
883 miny = s->yres - miny - 1;
884 dpy_gfx_update(s->con, maxy, 0, miny - maxy + 1, s->xres);
885 break;
886 }
887 }
888 pxa2xx_lcdc_int_update(s);
889
890 qemu_irq_raise(s->vsync_cb);
891 }
892
893 static void pxa2xx_invalidate_display(void *opaque)
894 {
895 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
896 s->invalidated = 1;
897 }
898
899 static void pxa2xx_lcdc_orientation(void *opaque, int angle)
900 {
901 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
902
903 switch (angle) {
904 case 0:
905 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot0;
906 break;
907 case 90:
908 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot90;
909 break;
910 case 180:
911 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot180;
912 break;
913 case 270:
914 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot270;
915 break;
916 }
917
918 s->orientation = angle;
919 s->xres = s->yres = -1;
920 pxa2xx_lcdc_resize(s);
921 }
922
923 static const VMStateDescription vmstate_dma_channel = {
924 .name = "dma_channel",
925 .version_id = 0,
926 .minimum_version_id = 0,
927 .fields = (VMStateField[]) {
928 VMSTATE_UINT32(branch, struct DMAChannel),
929 VMSTATE_UINT8(up, struct DMAChannel),
930 VMSTATE_BUFFER(pbuffer, struct DMAChannel),
931 VMSTATE_UINT32(descriptor, struct DMAChannel),
932 VMSTATE_UINT32(source, struct DMAChannel),
933 VMSTATE_UINT32(id, struct DMAChannel),
934 VMSTATE_UINT32(command, struct DMAChannel),
935 VMSTATE_END_OF_LIST()
936 }
937 };
938
939 static int pxa2xx_lcdc_post_load(void *opaque, int version_id)
940 {
941 PXA2xxLCDState *s = opaque;
942
943 s->bpp = LCCR3_BPP(s->control[3]);
944 s->xres = s->yres = s->pal_for = -1;
945
946 return 0;
947 }
948
949 static const VMStateDescription vmstate_pxa2xx_lcdc = {
950 .name = "pxa2xx_lcdc",
951 .version_id = 0,
952 .minimum_version_id = 0,
953 .post_load = pxa2xx_lcdc_post_load,
954 .fields = (VMStateField[]) {
955 VMSTATE_INT32(irqlevel, PXA2xxLCDState),
956 VMSTATE_INT32(transp, PXA2xxLCDState),
957 VMSTATE_UINT32_ARRAY(control, PXA2xxLCDState, 6),
958 VMSTATE_UINT32_ARRAY(status, PXA2xxLCDState, 2),
959 VMSTATE_UINT32_ARRAY(ovl1c, PXA2xxLCDState, 2),
960 VMSTATE_UINT32_ARRAY(ovl2c, PXA2xxLCDState, 2),
961 VMSTATE_UINT32(ccr, PXA2xxLCDState),
962 VMSTATE_UINT32(cmdcr, PXA2xxLCDState),
963 VMSTATE_UINT32(trgbr, PXA2xxLCDState),
964 VMSTATE_UINT32(tcr, PXA2xxLCDState),
965 VMSTATE_UINT32(liidr, PXA2xxLCDState),
966 VMSTATE_UINT8(bscntr, PXA2xxLCDState),
967 VMSTATE_STRUCT_ARRAY(dma_ch, PXA2xxLCDState, 7, 0,
968 vmstate_dma_channel, struct DMAChannel),
969 VMSTATE_END_OF_LIST()
970 }
971 };
972
973 #define BITS 8
974 #include "pxa2xx_template.h"
975 #define BITS 15
976 #include "pxa2xx_template.h"
977 #define BITS 16
978 #include "pxa2xx_template.h"
979 #define BITS 24
980 #include "pxa2xx_template.h"
981 #define BITS 32
982 #include "pxa2xx_template.h"
983
984 static const GraphicHwOps pxa2xx_ops = {
985 .invalidate = pxa2xx_invalidate_display,
986 .gfx_update = pxa2xx_update_display,
987 };
988
989 PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
990 hwaddr base, qemu_irq irq)
991 {
992 PXA2xxLCDState *s;
993 DisplaySurface *surface;
994
995 s = (PXA2xxLCDState *) g_malloc0(sizeof(PXA2xxLCDState));
996 s->invalidated = 1;
997 s->irq = irq;
998 s->sysmem = sysmem;
999
1000 pxa2xx_lcdc_orientation(s, graphic_rotate);
1001
1002 memory_region_init_io(&s->iomem, NULL, &pxa2xx_lcdc_ops, s,
1003 "pxa2xx-lcd-controller", 0x00100000);
1004 memory_region_add_subregion(sysmem, base, &s->iomem);
1005
1006 s->con = graphic_console_init(NULL, 0, &pxa2xx_ops, s);
1007 surface = qemu_console_surface(s->con);
1008
1009 switch (surface_bits_per_pixel(surface)) {
1010 case 0:
1011 s->dest_width = 0;
1012 break;
1013 case 8:
1014 s->line_fn[0] = pxa2xx_draw_fn_8;
1015 s->line_fn[1] = pxa2xx_draw_fn_8t;
1016 s->dest_width = 1;
1017 break;
1018 case 15:
1019 s->line_fn[0] = pxa2xx_draw_fn_15;
1020 s->line_fn[1] = pxa2xx_draw_fn_15t;
1021 s->dest_width = 2;
1022 break;
1023 case 16:
1024 s->line_fn[0] = pxa2xx_draw_fn_16;
1025 s->line_fn[1] = pxa2xx_draw_fn_16t;
1026 s->dest_width = 2;
1027 break;
1028 case 24:
1029 s->line_fn[0] = pxa2xx_draw_fn_24;
1030 s->line_fn[1] = pxa2xx_draw_fn_24t;
1031 s->dest_width = 3;
1032 break;
1033 case 32:
1034 s->line_fn[0] = pxa2xx_draw_fn_32;
1035 s->line_fn[1] = pxa2xx_draw_fn_32t;
1036 s->dest_width = 4;
1037 break;
1038 default:
1039 fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
1040 exit(1);
1041 }
1042
1043 vmstate_register(NULL, 0, &vmstate_pxa2xx_lcdc, s);
1044
1045 return s;
1046 }
1047
1048 void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler)
1049 {
1050 s->vsync_cb = handler;
1051 }
AR7 emulation for QEMU