2 * PA-RISC emulation cpu definitions for qemu.
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "exec/cpu-defs.h"
25 #include "qemu/cpu-float.h"
27 /* PA-RISC 1.x processors have a strong memory model. */
28 /* ??? While we do not yet implement PA-RISC 2.0, those processors have
29 a weak memory model, but with TLB bits that force ordering on a per-page
30 basis. It's probably easier to fall back to a strong memory model. */
31 #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
33 #define MMU_KERNEL_IDX 11
34 #define MMU_PL1_IDX 12
35 #define MMU_PL2_IDX 13
36 #define MMU_USER_IDX 14
37 #define MMU_PHYS_IDX 15
39 #define PRIV_TO_MMU_IDX(priv) (MMU_KERNEL_IDX + (priv))
40 #define MMU_IDX_TO_PRIV(mmu_idx) ((mmu_idx) - MMU_KERNEL_IDX)
42 #define TARGET_INSN_START_EXTRA_WORDS 1
44 /* No need to flush MMU_PHYS_IDX */
45 #define HPPA_MMU_FLUSH_MASK \
46 (1 << MMU_KERNEL_IDX | 1 << MMU_PL1_IDX | \
47 1 << MMU_PL2_IDX | 1 << MMU_USER_IDX)
49 /* Hardware exceptions, interrupts, faults, and traps. */
50 #define EXCP_HPMC 1 /* high priority machine check */
51 #define EXCP_POWER_FAIL 2
52 #define EXCP_RC 3 /* recovery counter */
53 #define EXCP_EXT_INTERRUPT 4 /* external interrupt */
54 #define EXCP_LPMC 5 /* low priority machine check */
55 #define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */
56 #define EXCP_IMP 7 /* instruction memory protection trap */
57 #define EXCP_ILL 8 /* illegal instruction trap */
58 #define EXCP_BREAK 9 /* break instruction */
59 #define EXCP_PRIV_OPR 10 /* privileged operation trap */
60 #define EXCP_PRIV_REG 11 /* privileged register trap */
61 #define EXCP_OVERFLOW 12 /* signed overflow trap */
62 #define EXCP_COND 13 /* trap-on-condition */
63 #define EXCP_ASSIST 14 /* assist exception trap */
64 #define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */
65 #define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */
66 #define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */
67 #define EXCP_DMP 18 /* data memory protection trap */
68 #define EXCP_DMB 19 /* data memory break trap */
69 #define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */
70 #define EXCP_PAGE_REF 21 /* page reference trap */
71 #define EXCP_ASSIST_EMU 22 /* assist emulation trap */
72 #define EXCP_HPT 23 /* high-privilege transfer trap */
73 #define EXCP_LPT 24 /* low-privilege transfer trap */
74 #define EXCP_TB 25 /* taken branch trap */
75 #define EXCP_DMAR 26 /* data memory access rights trap */
76 #define EXCP_DMPI 27 /* data memory protection id trap */
77 #define EXCP_UNALIGN 28 /* unaligned data reference trap */
78 #define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */
80 /* Exceptions for linux-user emulation. */
81 #define EXCP_SYSCALL 30
82 #define EXCP_SYSCALL_LWS 31
84 /* Emulated hardware TOC button */
85 #define EXCP_TOC 32 /* TOC = Transfer of control (NMI) */
87 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 /* TOC */
89 /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */
90 #define PSW_I 0x00000001
91 #define PSW_D 0x00000002
92 #define PSW_P 0x00000004
93 #define PSW_Q 0x00000008
94 #define PSW_R 0x00000010
95 #define PSW_F 0x00000020
96 #define PSW_G 0x00000040 /* PA1.x only */
97 #define PSW_O 0x00000080 /* PA2.0 only */
98 #define PSW_CB 0x0000ff00
99 #define PSW_M 0x00010000
100 #define PSW_V 0x00020000
101 #define PSW_C 0x00040000
102 #define PSW_B 0x00080000
103 #define PSW_X 0x00100000
104 #define PSW_N 0x00200000
105 #define PSW_L 0x00400000
106 #define PSW_H 0x00800000
107 #define PSW_T 0x01000000
108 #define PSW_S 0x02000000
109 #define PSW_E 0x04000000
111 #define PSW_W 0x08000000 /* PA2.0 only */
115 #define PSW_Z 0x40000000 /* PA1.x only */
116 #define PSW_Y 0x80000000 /* PA1.x only */
118 #define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \
119 | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I)
121 /* ssm/rsm instructions number PSW_W and PSW_E differently */
122 #define PSW_SM_I PSW_I /* Enable External Interrupts */
123 #define PSW_SM_D PSW_D
124 #define PSW_SM_P PSW_P
125 #define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */
126 #define PSW_SM_R PSW_R /* Enable Recover Counter Trap */
128 #define PSW_SM_E 0x100
129 #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */
153 #if TARGET_REGISTER_BITS == 32
154 typedef uint32_t target_ureg
;
155 typedef int32_t target_sreg
;
156 #define TREG_FMT_lx "%08"PRIx32
157 #define TREG_FMT_ld "%"PRId32
159 typedef uint64_t target_ureg
;
160 typedef int64_t target_sreg
;
161 #define TREG_FMT_lx "%016"PRIx64
162 #define TREG_FMT_ld "%"PRId64
173 unsigned page_size
: 4;
174 unsigned ar_type
: 3;
177 unsigned entry_valid
: 1;
178 unsigned access_id
: 16;
181 typedef struct CPUArchState
{
182 target_ureg iaoq_f
; /* front */
183 target_ureg iaoq_b
; /* back, aka next instruction */
187 uint64_t sr
[8]; /* stored shifted into place for gva */
189 target_ureg psw
; /* All psw bits except the following: */
190 target_ureg psw_n
; /* boolean */
191 target_sreg psw_v
; /* in most significant bit */
193 /* Splitting the carry-borrow field into the MSB and "the rest", allows
194 * for "the rest" to be deleted when it is unused, but the MSB is in use.
195 * In addition, it's easier to compute carry-in for bit B+1 than it is to
196 * compute carry-out for bit B (3 vs 4 insns for addition, assuming the
197 * host has the appropriate add-with-carry insn to compute the msb).
198 * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110.
200 target_ureg psw_cb
; /* in least significant bit of next nibble */
201 target_ureg psw_cb_msb
; /* boolean */
206 uint32_t fr0_shadow
; /* flags, c, ca/cq, rm, d, enables */
207 float_status fp_status
;
209 target_ureg cr
[32]; /* control registers */
210 target_ureg cr_back
[2]; /* back of cr17/cr18 */
211 target_ureg shadow
[7]; /* shadow registers */
213 /* ??? The number of entries isn't specified by the architecture. */
215 #define HPPA_BTLB_FIXED 0 /* BTLBs are not supported in 64-bit machines */
217 #define HPPA_BTLB_FIXED 16
219 #define HPPA_BTLB_VARIABLE 0
220 #define HPPA_TLB_ENTRIES 256
221 #define HPPA_BTLB_ENTRIES (HPPA_BTLB_FIXED + HPPA_BTLB_VARIABLE)
223 /* ??? Implement a unified itlb/dtlb for the moment. */
224 /* ??? We should use a more intelligent data structure. */
225 hppa_tlb_entry tlb
[HPPA_TLB_ENTRIES
];
231 * @env: #CPUHPPAState
241 QEMUTimer
*alarm_timer
;
244 #include "exec/cpu-all.h"
246 static inline int cpu_mmu_index(CPUHPPAState
*env
, bool ifetch
)
248 #ifdef CONFIG_USER_ONLY
251 if (env
->psw
& (ifetch
? PSW_C
: PSW_D
)) {
252 return PRIV_TO_MMU_IDX(env
->iaoq_f
& 3);
254 return MMU_PHYS_IDX
; /* mmu disabled */
258 void hppa_translate_init(void);
260 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
262 static inline target_ulong
hppa_form_gva_psw(target_ureg psw
, uint64_t spc
,
265 #ifdef CONFIG_USER_ONLY
268 off
&= (psw
& PSW_W
? 0x3fffffffffffffffull
: 0xffffffffull
);
273 static inline target_ulong
hppa_form_gva(CPUHPPAState
*env
, uint64_t spc
,
276 return hppa_form_gva_psw(env
->psw
, spc
, off
);
280 * Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
281 * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the
284 #define TB_FLAG_SR_SAME PSW_I
285 #define TB_FLAG_PRIV_SHIFT 8
286 #define TB_FLAG_UNALIGN 0x400
288 static inline void cpu_get_tb_cpu_state(CPUHPPAState
*env
, vaddr
*pc
,
289 uint64_t *cs_base
, uint32_t *pflags
)
291 uint32_t flags
= env
->psw_n
* PSW_N
;
293 /* TB lookup assumes that PC contains the complete virtual address.
294 If we leave space+offset separate, we'll get ITLB misses to an
295 incomplete virtual address. This also means that we must separate
296 out current cpu privilege from the low bits of IAOQ_F. */
297 #ifdef CONFIG_USER_ONLY
298 *pc
= env
->iaoq_f
& -4;
299 *cs_base
= env
->iaoq_b
& -4;
300 flags
|= TB_FLAG_UNALIGN
* !env_cpu(env
)->prctl_unalign_sigbus
;
302 /* ??? E, T, H, L, B, P bits need to be here, when implemented. */
303 flags
|= env
->psw
& (PSW_W
| PSW_C
| PSW_D
);
304 flags
|= (env
->iaoq_f
& 3) << TB_FLAG_PRIV_SHIFT
;
306 *pc
= (env
->psw
& PSW_C
307 ? hppa_form_gva_psw(env
->psw
, env
->iasq_f
, env
->iaoq_f
& -4)
309 *cs_base
= env
->iasq_f
;
311 /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero
312 low 32-bits of CS_BASE. This will succeed for all direct branches,
313 which is the primary case we care about -- using goto_tb within a page.
314 Failure is indicated by a zero difference. */
315 if (env
->iasq_f
== env
->iasq_b
) {
316 target_sreg diff
= env
->iaoq_b
- env
->iaoq_f
;
317 if (TARGET_REGISTER_BITS
== 32 || diff
== (int32_t)diff
) {
318 *cs_base
|= (uint32_t)diff
;
321 if ((env
->sr
[4] == env
->sr
[5])
322 & (env
->sr
[4] == env
->sr
[6])
323 & (env
->sr
[4] == env
->sr
[7])) {
324 flags
|= TB_FLAG_SR_SAME
;
331 target_ureg
cpu_hppa_get_psw(CPUHPPAState
*env
);
332 void cpu_hppa_put_psw(CPUHPPAState
*env
, target_ureg
);
333 void cpu_hppa_loaded_fr0(CPUHPPAState
*env
);
335 #ifdef CONFIG_USER_ONLY
336 static inline void cpu_hppa_change_prot_id(CPUHPPAState
*env
) { }
338 void cpu_hppa_change_prot_id(CPUHPPAState
*env
);
341 int hppa_cpu_gdb_read_register(CPUState
*cpu
, GByteArray
*buf
, int reg
);
342 int hppa_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
343 void hppa_cpu_dump_state(CPUState
*cs
, FILE *f
, int);
344 #ifndef CONFIG_USER_ONLY
345 hwaddr
hppa_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
);
346 bool hppa_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
347 MMUAccessType access_type
, int mmu_idx
,
348 bool probe
, uintptr_t retaddr
);
349 void hppa_cpu_do_interrupt(CPUState
*cpu
);
350 bool hppa_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
351 int hppa_get_physical_address(CPUHPPAState
*env
, vaddr addr
, int mmu_idx
,
352 int type
, hwaddr
*pphys
, int *pprot
,
353 hppa_tlb_entry
**tlb_entry
);
354 extern const MemoryRegionOps hppa_io_eir_ops
;
355 extern const VMStateDescription vmstate_hppa_cpu
;
356 void hppa_cpu_alarm_timer(void *);
357 int hppa_artype_for_page(CPUHPPAState
*env
, target_ulong vaddr
);
359 G_NORETURN
void hppa_dynamic_excp(CPUHPPAState
*env
, int excp
, uintptr_t ra
);
361 #endif /* HPPA_CPU_H */