2 * QEMU Bochs-style debug console ("port E9") emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2008 Citrix Systems, Inc.
6 * Copyright (c) Intel Corporation; author: H. Peter Anvin
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
29 #include "sysemu/char.h"
30 #include "hw/isa/isa.h"
31 #include "hw/i386/pc.h"
33 #define TYPE_ISA_DEBUGCON_DEVICE "isa-debugcon"
34 #define ISA_DEBUGCON_DEVICE(obj) \
35 OBJECT_CHECK(ISADebugconState, (obj), TYPE_ISA_DEBUGCON_DEVICE)
37 //#define DEBUG_DEBUGCON
39 typedef struct DebugconState
{
45 typedef struct ISADebugconState
{
52 static void debugcon_ioport_write(void *opaque
, hwaddr addr
, uint64_t val
,
55 DebugconState
*s
= opaque
;
56 unsigned char ch
= val
;
59 printf(" [debugcon: write addr=0x%04" HWADDR_PRIx
" val=0x%02" PRIx64
"]\n", addr
, val
);
62 qemu_chr_fe_write(s
->chr
, &ch
, 1);
66 static uint64_t debugcon_ioport_read(void *opaque
, hwaddr addr
, unsigned width
)
68 DebugconState
*s
= opaque
;
71 printf("debugcon: read addr=0x%04" HWADDR_PRIx
"\n", addr
);
77 static const MemoryRegionOps debugcon_ops
= {
78 .read
= debugcon_ioport_read
,
79 .write
= debugcon_ioport_write
,
80 .valid
.min_access_size
= 1,
81 .valid
.max_access_size
= 1,
82 .endianness
= DEVICE_LITTLE_ENDIAN
,
85 static void debugcon_realize_core(DebugconState
*s
, Error
**errp
)
88 error_setg(errp
, "Can't create debugcon device, empty char device");
92 qemu_chr_add_handlers(s
->chr
, NULL
, NULL
, NULL
, s
);
95 static void debugcon_isa_realizefn(DeviceState
*dev
, Error
**errp
)
97 ISADevice
*d
= ISA_DEVICE(dev
);
98 ISADebugconState
*isa
= ISA_DEBUGCON_DEVICE(dev
);
99 DebugconState
*s
= &isa
->state
;
102 debugcon_realize_core(s
, &err
);
104 error_propagate(errp
, err
);
107 memory_region_init_io(&s
->io
, OBJECT(dev
), &debugcon_ops
, s
,
108 TYPE_ISA_DEBUGCON_DEVICE
, 1);
109 memory_region_add_subregion(isa_address_space_io(d
),
110 isa
->iobase
, &s
->io
);
113 static Property debugcon_isa_properties
[] = {
114 DEFINE_PROP_UINT32("iobase", ISADebugconState
, iobase
, 0xe9),
115 DEFINE_PROP_CHR("chardev", ISADebugconState
, state
.chr
),
116 DEFINE_PROP_UINT32("readback", ISADebugconState
, state
.readback
, 0xe9),
117 DEFINE_PROP_END_OF_LIST(),
120 static void debugcon_isa_class_initfn(ObjectClass
*klass
, void *data
)
122 DeviceClass
*dc
= DEVICE_CLASS(klass
);
124 dc
->realize
= debugcon_isa_realizefn
;
125 dc
->props
= debugcon_isa_properties
;
126 set_bit(DEVICE_CATEGORY_MISC
, dc
->categories
);
129 static const TypeInfo debugcon_isa_info
= {
130 .name
= TYPE_ISA_DEBUGCON_DEVICE
,
131 .parent
= TYPE_ISA_DEVICE
,
132 .instance_size
= sizeof(ISADebugconState
),
133 .class_init
= debugcon_isa_class_initfn
,
136 static void debugcon_register_types(void)
138 type_register_static(&debugcon_isa_info
);
141 type_init(debugcon_register_types
)