2 * QEMU ARM CPU -- internal functions and types
4 * Copyright (c) 2014 Linaro Ltd
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
20 * This header defines functions, types, etc which need to be shared
21 * between different source files within target-arm/ but which are
22 * private to it and not required by the rest of QEMU.
25 #ifndef TARGET_ARM_INTERNALS_H
26 #define TARGET_ARM_INTERNALS_H
28 static inline bool excp_is_internal(int excp
)
30 /* Return true if this exception number represents a QEMU-internal
31 * exception that will not be passed to the guest.
33 return excp
== EXCP_INTERRUPT
36 || excp
== EXCP_HALTED
37 || excp
== EXCP_EXCEPTION_EXIT
38 || excp
== EXCP_KERNEL_TRAP
39 || excp
== EXCP_STREX
;
42 /* Exception names for debug logging; note that not all of these
43 * precisely correspond to architectural exceptions.
45 static const char * const excnames
[] = {
46 [EXCP_UDEF
] = "Undefined Instruction",
48 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
49 [EXCP_DATA_ABORT
] = "Data Abort",
52 [EXCP_BKPT
] = "Breakpoint",
53 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
54 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
55 [EXCP_STREX
] = "QEMU intercept of STREX",
56 [EXCP_HVC
] = "Hypervisor Call",
59 static inline void arm_log_exception(int idx
)
61 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
62 const char *exc
= NULL
;
64 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
70 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s]\n", idx
, exc
);
74 /* Scale factor for generic timers, ie number of ns per tick.
75 * This gives a 62.5MHz timer.
77 #define GTIMER_SCALE 16
80 * For AArch64, map a given EL to an index in the banked_spsr array.
82 static inline unsigned int aarch64_banked_spsr_index(unsigned int el
)
84 static const unsigned int map
[4] = {
89 assert(el
>= 1 && el
<= 3);
93 int bank_number(int mode
);
94 void switch_mode(CPUARMState
*, int);
95 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
);
96 void arm_translate_init(void);
107 int arm_rmode_to_sf(int rmode
);
109 static inline void aarch64_save_sp(CPUARMState
*env
, int el
)
111 if (env
->pstate
& PSTATE_SP
) {
112 env
->sp_el
[el
] = env
->xregs
[31];
114 env
->sp_el
[0] = env
->xregs
[31];
118 static inline void aarch64_restore_sp(CPUARMState
*env
, int el
)
120 if (env
->pstate
& PSTATE_SP
) {
121 env
->xregs
[31] = env
->sp_el
[el
];
123 env
->xregs
[31] = env
->sp_el
[0];
127 static inline void update_spsel(CPUARMState
*env
, uint32_t imm
)
129 unsigned int cur_el
= arm_current_pl(env
);
130 /* Update PSTATE SPSel bit; this requires us to update the
131 * working stack pointer in xregs[31].
133 if (!((imm
^ env
->pstate
) & PSTATE_SP
)) {
136 aarch64_save_sp(env
, cur_el
);
137 env
->pstate
= deposit32(env
->pstate
, 0, 1, imm
);
139 /* We rely on illegal updates to SPsel from EL0 to get trapped
140 * at translation time.
142 assert(cur_el
>= 1 && cur_el
<= 3);
143 aarch64_restore_sp(env
, cur_el
);
146 /* Return true if extended addresses are enabled.
147 * This is always the case if our translation regime is 64 bit,
148 * but depends on TTBCR.EAE for 32 bit.
150 static inline bool extended_addresses_enabled(CPUARMState
*env
)
152 return arm_el_is_aa64(env
, 1)
153 || ((arm_feature(env
, ARM_FEATURE_LPAE
)
154 && (env
->cp15
.c2_control
& TTBCR_EAE
)));
157 /* Valid Syndrome Register EC field values */
158 enum arm_exception_class
{
159 EC_UNCATEGORIZED
= 0x00,
161 EC_CP15RTTRAP
= 0x03,
162 EC_CP15RRTTRAP
= 0x04,
163 EC_CP14RTTRAP
= 0x05,
164 EC_CP14DTTRAP
= 0x06,
165 EC_ADVSIMDFPACCESSTRAP
= 0x07,
167 EC_CP14RRTTRAP
= 0x0c,
168 EC_ILLEGALSTATE
= 0x0e,
175 EC_SYSTEMREGISTERTRAP
= 0x18,
177 EC_INSNABORT_SAME_EL
= 0x21,
178 EC_PCALIGNMENT
= 0x22,
180 EC_DATAABORT_SAME_EL
= 0x25,
181 EC_SPALIGNMENT
= 0x26,
182 EC_AA32_FPTRAP
= 0x28,
183 EC_AA64_FPTRAP
= 0x2c,
185 EC_BREAKPOINT
= 0x30,
186 EC_BREAKPOINT_SAME_EL
= 0x31,
187 EC_SOFTWARESTEP
= 0x32,
188 EC_SOFTWARESTEP_SAME_EL
= 0x33,
189 EC_WATCHPOINT
= 0x34,
190 EC_WATCHPOINT_SAME_EL
= 0x35,
192 EC_VECTORCATCH
= 0x3a,
196 #define ARM_EL_EC_SHIFT 26
197 #define ARM_EL_IL_SHIFT 25
198 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
200 /* Utility functions for constructing various kinds of syndrome value.
201 * Note that in general we follow the AArch64 syndrome values; in a
202 * few cases the value in HSR for exceptions taken to AArch32 Hyp
203 * mode differs slightly, so if we ever implemented Hyp mode then the
204 * syndrome value would need some massaging on exception entry.
205 * (One example of this is that AArch64 defaults to IL bit set for
206 * exceptions which don't specifically indicate information about the
207 * trapping instruction, whereas AArch32 defaults to IL bit clear.)
209 static inline uint32_t syn_uncategorized(void)
211 return (EC_UNCATEGORIZED
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
;
214 static inline uint32_t syn_aa64_svc(uint32_t imm16
)
216 return (EC_AA64_SVC
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
| (imm16
& 0xffff);
219 static inline uint32_t syn_aa64_hvc(uint32_t imm16
)
221 return (EC_AA64_HVC
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
| (imm16
& 0xffff);
224 static inline uint32_t syn_aa32_svc(uint32_t imm16
, bool is_thumb
)
226 return (EC_AA32_SVC
<< ARM_EL_EC_SHIFT
) | (imm16
& 0xffff)
227 | (is_thumb
? 0 : ARM_EL_IL
);
230 static inline uint32_t syn_aa64_bkpt(uint32_t imm16
)
232 return (EC_AA64_BKPT
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
| (imm16
& 0xffff);
235 static inline uint32_t syn_aa32_bkpt(uint32_t imm16
, bool is_thumb
)
237 return (EC_AA32_BKPT
<< ARM_EL_EC_SHIFT
) | (imm16
& 0xffff)
238 | (is_thumb
? 0 : ARM_EL_IL
);
241 static inline uint32_t syn_aa64_sysregtrap(int op0
, int op1
, int op2
,
242 int crn
, int crm
, int rt
,
245 return (EC_SYSTEMREGISTERTRAP
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
246 | (op0
<< 20) | (op2
<< 17) | (op1
<< 14) | (crn
<< 10) | (rt
<< 5)
247 | (crm
<< 1) | isread
;
250 static inline uint32_t syn_cp14_rt_trap(int cv
, int cond
, int opc1
, int opc2
,
251 int crn
, int crm
, int rt
, int isread
,
254 return (EC_CP14RTTRAP
<< ARM_EL_EC_SHIFT
)
255 | (is_thumb
? 0 : ARM_EL_IL
)
256 | (cv
<< 24) | (cond
<< 20) | (opc2
<< 17) | (opc1
<< 14)
257 | (crn
<< 10) | (rt
<< 5) | (crm
<< 1) | isread
;
260 static inline uint32_t syn_cp15_rt_trap(int cv
, int cond
, int opc1
, int opc2
,
261 int crn
, int crm
, int rt
, int isread
,
264 return (EC_CP15RTTRAP
<< ARM_EL_EC_SHIFT
)
265 | (is_thumb
? 0 : ARM_EL_IL
)
266 | (cv
<< 24) | (cond
<< 20) | (opc2
<< 17) | (opc1
<< 14)
267 | (crn
<< 10) | (rt
<< 5) | (crm
<< 1) | isread
;
270 static inline uint32_t syn_cp14_rrt_trap(int cv
, int cond
, int opc1
, int crm
,
271 int rt
, int rt2
, int isread
,
274 return (EC_CP14RRTTRAP
<< ARM_EL_EC_SHIFT
)
275 | (is_thumb
? 0 : ARM_EL_IL
)
276 | (cv
<< 24) | (cond
<< 20) | (opc1
<< 16)
277 | (rt2
<< 10) | (rt
<< 5) | (crm
<< 1) | isread
;
280 static inline uint32_t syn_cp15_rrt_trap(int cv
, int cond
, int opc1
, int crm
,
281 int rt
, int rt2
, int isread
,
284 return (EC_CP15RRTTRAP
<< ARM_EL_EC_SHIFT
)
285 | (is_thumb
? 0 : ARM_EL_IL
)
286 | (cv
<< 24) | (cond
<< 20) | (opc1
<< 16)
287 | (rt2
<< 10) | (rt
<< 5) | (crm
<< 1) | isread
;
290 static inline uint32_t syn_fp_access_trap(int cv
, int cond
, bool is_thumb
)
292 return (EC_ADVSIMDFPACCESSTRAP
<< ARM_EL_EC_SHIFT
)
293 | (is_thumb
? 0 : ARM_EL_IL
)
294 | (cv
<< 24) | (cond
<< 20);
297 static inline uint32_t syn_insn_abort(int same_el
, int ea
, int s1ptw
, int fsc
)
299 return (EC_INSNABORT
<< ARM_EL_EC_SHIFT
) | (same_el
<< ARM_EL_EC_SHIFT
)
300 | (ea
<< 9) | (s1ptw
<< 7) | fsc
;
303 static inline uint32_t syn_data_abort(int same_el
, int ea
, int cm
, int s1ptw
,
306 return (EC_DATAABORT
<< ARM_EL_EC_SHIFT
) | (same_el
<< ARM_EL_EC_SHIFT
)
307 | (ea
<< 9) | (cm
<< 8) | (s1ptw
<< 7) | (wnr
<< 6) | fsc
;
310 static inline uint32_t syn_swstep(int same_el
, int isv
, int ex
)
312 return (EC_SOFTWARESTEP
<< ARM_EL_EC_SHIFT
) | (same_el
<< ARM_EL_EC_SHIFT
)
313 | (isv
<< 24) | (ex
<< 6) | 0x22;
316 static inline uint32_t syn_watchpoint(int same_el
, int cm
, int wnr
)
318 return (EC_WATCHPOINT
<< ARM_EL_EC_SHIFT
) | (same_el
<< ARM_EL_EC_SHIFT
)
319 | (cm
<< 8) | (wnr
<< 6) | 0x22;
322 static inline uint32_t syn_breakpoint(int same_el
)
324 return (EC_BREAKPOINT
<< ARM_EL_EC_SHIFT
) | (same_el
<< ARM_EL_EC_SHIFT
)
328 /* Update a QEMU watchpoint based on the information the guest has set in the
329 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
331 void hw_watchpoint_update(ARMCPU
*cpu
, int n
);
332 /* Update the QEMU watchpoints for every guest watchpoint. This does a
333 * complete delete-and-reinstate of the QEMU watchpoint list and so is
334 * suitable for use after migration or on reset.
336 void hw_watchpoint_update_all(ARMCPU
*cpu
);
337 /* Update a QEMU breakpoint based on the information the guest has set in the
338 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
340 void hw_breakpoint_update(ARMCPU
*cpu
, int n
);
341 /* Update the QEMU breakpoints for every guest breakpoint. This does a
342 * complete delete-and-reinstate of the QEMU breakpoint list and so is
343 * suitable for use after migration or on reset.
345 void hw_breakpoint_update_all(ARMCPU
*cpu
);
347 /* Callback function for when a watchpoint or breakpoint triggers. */
348 void arm_debug_excp_handler(CPUState
*cs
);