hw/char/serial.c

   1 /*
   2  * QEMU 16550A UART emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2008 Citrix Systems, Inc.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/char/serial.h"
  28 #include "sysemu/char.h"
  29 #include "qapi/error.h"
  30 #include "qemu/timer.h"
  31 #include "exec/address-spaces.h"
  32 #include "qemu/error-report.h"
  33
  34 //#define DEBUG_SERIAL
  35
  36 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  37
  38 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  39 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  40 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
  41 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
  42
  43 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  44 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  45
  46 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
  47 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  48 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  49 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  50 #define UART_IIR_CTI    0x0C    /* Character Timeout Indication */
  51
  52 #define UART_IIR_FENF   0x80    /* Fifo enabled, but not functionning */
  53 #define UART_IIR_FE     0xC0    /* Fifo enabled */
  54
  55 /*
  56  * These are the definitions for the Modem Control Register
  57  */
  58 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
  59 #define UART_MCR_OUT2   0x08    /* Out2 complement */
  60 #define UART_MCR_OUT1   0x04    /* Out1 complement */
  61 #define UART_MCR_RTS    0x02    /* RTS complement */
  62 #define UART_MCR_DTR    0x01    /* DTR complement */
  63
  64 /*
  65  * These are the definitions for the Modem Status Register
  66  */
  67 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
  68 #define UART_MSR_RI     0x40    /* Ring Indicator */
  69 #define UART_MSR_DSR    0x20    /* Data Set Ready */
  70 #define UART_MSR_CTS    0x10    /* Clear to Send */
  71 #define UART_MSR_DDCD   0x08    /* Delta DCD */
  72 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
  73 #define UART_MSR_DDSR   0x02    /* Delta DSR */
  74 #define UART_MSR_DCTS   0x01    /* Delta CTS */
  75 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
  76
  77 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  78 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  79 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  80 #define UART_LSR_FE     0x08    /* Frame error indicator */
  81 #define UART_LSR_PE     0x04    /* Parity error indicator */
  82 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  83 #define UART_LSR_DR     0x01    /* Receiver data ready */
  84 #define UART_LSR_INT_ANY 0x1E   /* Any of the lsr-interrupt-triggering status bits */
  85
  86 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
  87
  88 #define UART_FCR_ITL_1      0x00 /* 1 byte ITL */
  89 #define UART_FCR_ITL_2      0x40 /* 4 bytes ITL */
  90 #define UART_FCR_ITL_3      0x80 /* 8 bytes ITL */
  91 #define UART_FCR_ITL_4      0xC0 /* 14 bytes ITL */
  92
  93 #define UART_FCR_DMS        0x08    /* DMA Mode Select */
  94 #define UART_FCR_XFR        0x04    /* XMIT Fifo Reset */
  95 #define UART_FCR_RFR        0x02    /* RCVR Fifo Reset */
  96 #define UART_FCR_FE         0x01    /* FIFO Enable */
  97
  98 #define MAX_XMIT_RETRY      4
  99
 100 #ifdef DEBUG_SERIAL
 101 #define DPRINTF(fmt, ...) \
 102 do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0)
 103 #else
 104 #define DPRINTF(fmt, ...) \
 105 do {} while (0)
 106 #endif
 107
 108 static void serial_receive1(void *opaque, const uint8_t *buf, int size);
 109 static void serial_xmit(SerialState *s);
 110
 111 static inline void recv_fifo_put(SerialState *s, uint8_t chr)
 112 {
 113     /* Receive overruns do not overwrite FIFO contents. */
 114     if (!fifo8_is_full(&s->recv_fifo)) {
 115         fifo8_push(&s->recv_fifo, chr);
 116     } else {
 117         s->lsr |= UART_LSR_OE;
 118     }
 119 }
 120
 121 static void serial_update_irq(SerialState *s)
 122 {
 123     uint8_t tmp_iir = UART_IIR_NO_INT;
 124
 125     if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
 126         tmp_iir = UART_IIR_RLSI;
 127     } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
 128         /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
 129          * this is not in the specification but is observed on existing
 130          * hardware.  */
 131         tmp_iir = UART_IIR_CTI;
 132     } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
 133                (!(s->fcr & UART_FCR_FE) ||
 134                 s->recv_fifo.num >= s->recv_fifo_itl)) {
 135         tmp_iir = UART_IIR_RDI;
 136     } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
 137         tmp_iir = UART_IIR_THRI;
 138     } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
 139         tmp_iir = UART_IIR_MSI;
 140     }
 141
 142     s->iir = tmp_iir | (s->iir & 0xF0);
 143
 144     if (tmp_iir != UART_IIR_NO_INT) {
 145         qemu_irq_raise(s->irq);
 146     } else {
 147         qemu_irq_lower(s->irq);
 148     }
 149 }
 150
 151 static void serial_update_parameters(SerialState *s)
 152 {
 153     int speed, parity, data_bits, stop_bits, frame_size;
 154     QEMUSerialSetParams ssp;
 155
 156     if (s->divider == 0 || s->divider > s->baudbase) {
 157         return;
 158     }
 159
 160     /* Start bit. */
 161     frame_size = 1;
 162     if (s->lcr & 0x08) {
 163         /* Parity bit. */
 164         frame_size++;
 165         if (s->lcr & 0x10)
 166             parity = 'E';
 167         else
 168             parity = 'O';
 169     } else {
 170             parity = 'N';
 171     }
 172     if (s->lcr & 0x04)
 173         stop_bits = 2;
 174     else
 175         stop_bits = 1;
 176
 177     data_bits = (s->lcr & 0x03) + 5;
 178     frame_size += data_bits + stop_bits;
 179     speed = s->baudbase / s->divider;
 180     ssp.speed = speed;
 181     ssp.parity = parity;
 182     ssp.data_bits = data_bits;
 183     ssp.stop_bits = stop_bits;
 184     s->char_transmit_time =  (NANOSECONDS_PER_SECOND / speed) * frame_size;
 185     qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 186
 187     DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
 188            speed, parity, data_bits, stop_bits);
 189 }
 190
 191 static void serial_update_msl(SerialState *s)
 192 {
 193     uint8_t omsr;
 194     int flags;
 195
 196     timer_del(s->modem_status_poll);
 197
 198     if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
 199         s->poll_msl = -1;
 200         return;
 201     }
 202
 203     omsr = s->msr;
 204
 205     s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
 206     s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
 207     s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
 208     s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
 209
 210     if (s->msr != omsr) {
 211          /* Set delta bits */
 212          s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
 213          /* UART_MSR_TERI only if change was from 1 -> 0 */
 214          if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
 215              s->msr &= ~UART_MSR_TERI;
 216          serial_update_irq(s);
 217     }
 218
 219     /* The real 16550A apparently has a 250ns response latency to line status changes.
 220        We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
 221
 222     if (s->poll_msl) {
 223         timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 224                   NANOSECONDS_PER_SECOND / 100);
 225     }
 226 }
 227
 228 static gboolean serial_watch_cb(GIOChannel *chan, GIOCondition cond,
 229                                 void *opaque)
 230 {
 231     SerialState *s = opaque;
 232     s->watch_tag = 0;
 233     serial_xmit(s);
 234     return FALSE;
 235 }
 236
 237 static void serial_xmit(SerialState *s)
 238 {
 239     do {
 240         assert(!(s->lsr & UART_LSR_TEMT));
 241         if (s->tsr_retry == 0) {
 242             assert(!(s->lsr & UART_LSR_THRE));
 243
 244             if (s->fcr & UART_FCR_FE) {
 245                 assert(!fifo8_is_empty(&s->xmit_fifo));
 246                 s->tsr = fifo8_pop(&s->xmit_fifo);
 247                 if (!s->xmit_fifo.num) {
 248                     s->lsr |= UART_LSR_THRE;
 249                 }
 250             } else {
 251                 s->tsr = s->thr;
 252                 s->lsr |= UART_LSR_THRE;
 253             }
 254             if ((s->lsr & UART_LSR_THRE) && !s->thr_ipending) {
 255                 s->thr_ipending = 1;
 256                 serial_update_irq(s);
 257             }
 258         }
 259
 260         if (s->mcr & UART_MCR_LOOP) {
 261             /* in loopback mode, say that we just received a char */
 262             serial_receive1(s, &s->tsr, 1);
 263         } else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1 &&
 264                    s->tsr_retry < MAX_XMIT_RETRY) {
 265             assert(s->watch_tag == 0);
 266             s->watch_tag = qemu_chr_fe_add_watch(s->chr, G_IO_OUT|G_IO_HUP,
 267                                                  serial_watch_cb, s);
 268             if (s->watch_tag > 0) {
 269                 s->tsr_retry++;
 270                 return;
 271             }
 272         }
 273         s->tsr_retry = 0;
 274
 275         /* Transmit another byte if it is already available. It is only
 276            possible when FIFO is enabled and not empty. */
 277     } while (!(s->lsr & UART_LSR_THRE));
 278
 279     s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 280     s->lsr |= UART_LSR_TEMT;
 281 }
 282
 283 /* Setter for FCR.
 284    is_load flag means, that value is set while loading VM state
 285    and interrupt should not be invoked */
 286 static void serial_write_fcr(SerialState *s, uint8_t val)
 287 {
 288     /* Set fcr - val only has the bits that are supposed to "stick" */
 289     s->fcr = val;
 290
 291     if (val & UART_FCR_FE) {
 292         s->iir |= UART_IIR_FE;
 293         /* Set recv_fifo trigger Level */
 294         switch (val & 0xC0) {
 295         case UART_FCR_ITL_1:
 296             s->recv_fifo_itl = 1;
 297             break;
 298         case UART_FCR_ITL_2:
 299             s->recv_fifo_itl = 4;
 300             break;
 301         case UART_FCR_ITL_3:
 302             s->recv_fifo_itl = 8;
 303             break;
 304         case UART_FCR_ITL_4:
 305             s->recv_fifo_itl = 14;
 306             break;
 307         }
 308     } else {
 309         s->iir &= ~UART_IIR_FE;
 310     }
 311 }
 312
 313 static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
 314                                 unsigned size)
 315 {
 316     SerialState *s = opaque;
 317
 318     addr &= 7;
 319     DPRINTF("write addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 "\n", addr, val);
 320     switch(addr) {
 321     default:
 322     case 0:
 323         if (s->lcr & UART_LCR_DLAB) {
 324             s->divider = (s->divider & 0xff00) | val;
 325             serial_update_parameters(s);
 326         } else {
 327             s->thr = (uint8_t) val;
 328             if(s->fcr & UART_FCR_FE) {
 329                 /* xmit overruns overwrite data, so make space if needed */
 330                 if (fifo8_is_full(&s->xmit_fifo)) {
 331                     fifo8_pop(&s->xmit_fifo);
 332                 }
 333                 fifo8_push(&s->xmit_fifo, s->thr);
 334             }
 335             s->thr_ipending = 0;
 336             s->lsr &= ~UART_LSR_THRE;
 337             s->lsr &= ~UART_LSR_TEMT;
 338             serial_update_irq(s);
 339             if (s->tsr_retry == 0) {
 340                 serial_xmit(s);
 341             }
 342         }
 343         break;
 344     case 1:
 345         if (s->lcr & UART_LCR_DLAB) {
 346             s->divider = (s->divider & 0x00ff) | (val << 8);
 347             serial_update_parameters(s);
 348         } else {
 349             uint8_t changed = (s->ier ^ val) & 0x0f;
 350             s->ier = val & 0x0f;
 351             /* If the backend device is a real serial port, turn polling of the modem
 352              * status lines on physical port on or off depending on UART_IER_MSI state.
 353              */
 354             if ((changed & UART_IER_MSI) && s->poll_msl >= 0) {
 355                 if (s->ier & UART_IER_MSI) {
 356                      s->poll_msl = 1;
 357                      serial_update_msl(s);
 358                 } else {
 359                      timer_del(s->modem_status_poll);
 360                      s->poll_msl = 0;
 361                 }
 362             }
 363
 364             /* Turning on the THRE interrupt on IER can trigger the interrupt
 365              * if LSR.THRE=1, even if it had been masked before by reading IIR.
 366              * This is not in the datasheet, but Windows relies on it.  It is
 367              * unclear if THRE has to be resampled every time THRI becomes
 368              * 1, or only on the rising edge.  Bochs does the latter, and Windows
 369              * always toggles IER to all zeroes and back to all ones, so do the
 370              * same.
 371              *
 372              * If IER.THRI is zero, thr_ipending is not used.  Set it to zero
 373              * so that the thr_ipending subsection is not migrated.
 374              */
 375             if (changed & UART_IER_THRI) {
 376                 if ((s->ier & UART_IER_THRI) && (s->lsr & UART_LSR_THRE)) {
 377                     s->thr_ipending = 1;
 378                 } else {
 379                     s->thr_ipending = 0;
 380                 }
 381             }
 382
 383             if (changed) {
 384                 serial_update_irq(s);
 385             }
 386         }
 387         break;
 388     case 2:
 389         /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
 390         if ((val ^ s->fcr) & UART_FCR_FE) {
 391             val |= UART_FCR_XFR | UART_FCR_RFR;
 392         }
 393
 394         /* FIFO clear */
 395
 396         if (val & UART_FCR_RFR) {
 397             s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 398             timer_del(s->fifo_timeout_timer);
 399             s->timeout_ipending = 0;
 400             fifo8_reset(&s->recv_fifo);
 401         }
 402
 403         if (val & UART_FCR_XFR) {
 404             s->lsr |= UART_LSR_THRE;
 405             s->thr_ipending = 1;
 406             fifo8_reset(&s->xmit_fifo);
 407         }
 408
 409         serial_write_fcr(s, val & 0xC9);
 410         serial_update_irq(s);
 411         break;
 412     case 3:
 413         {
 414             int break_enable;
 415             s->lcr = val;
 416             serial_update_parameters(s);
 417             break_enable = (val >> 6) & 1;
 418             if (break_enable != s->last_break_enable) {
 419                 s->last_break_enable = break_enable;
 420                 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 421                                &break_enable);
 422             }
 423         }
 424         break;
 425     case 4:
 426         {
 427             int flags;
 428             int old_mcr = s->mcr;
 429             s->mcr = val & 0x1f;
 430             if (val & UART_MCR_LOOP)
 431                 break;
 432
 433             if (s->poll_msl >= 0 && old_mcr != s->mcr) {
 434
 435                 qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
 436
 437                 flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
 438
 439                 if (val & UART_MCR_RTS)
 440                     flags |= CHR_TIOCM_RTS;
 441                 if (val & UART_MCR_DTR)
 442                     flags |= CHR_TIOCM_DTR;
 443
 444                 qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
 445                 /* Update the modem status after a one-character-send wait-time, since there may be a response
 446                    from the device/computer at the other end of the serial line */
 447                 timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time);
 448             }
 449         }
 450         break;
 451     case 5:
 452         break;
 453     case 6:
 454         break;
 455     case 7:
 456         s->scr = val;
 457         break;
 458     }
 459 }
 460
 461 static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
 462 {
 463     SerialState *s = opaque;
 464     uint32_t ret;
 465
 466     addr &= 7;
 467     switch(addr) {
 468     default:
 469     case 0:
 470         if (s->lcr & UART_LCR_DLAB) {
 471             ret = s->divider & 0xff;
 472         } else {
 473             if(s->fcr & UART_FCR_FE) {
 474                 ret = fifo8_is_empty(&s->recv_fifo) ?
 475                             0 : fifo8_pop(&s->recv_fifo);
 476                 if (s->recv_fifo.num == 0) {
 477                     s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 478                 } else {
 479                     timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4);
 480                 }
 481                 s->timeout_ipending = 0;
 482             } else {
 483                 ret = s->rbr;
 484                 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 485             }
 486             serial_update_irq(s);
 487             if (!(s->mcr & UART_MCR_LOOP)) {
 488                 /* in loopback mode, don't receive any data */
 489                 qemu_chr_accept_input(s->chr);
 490             }
 491         }
 492         break;
 493     case 1:
 494         if (s->lcr & UART_LCR_DLAB) {
 495             ret = (s->divider >> 8) & 0xff;
 496         } else {
 497             ret = s->ier;
 498         }
 499         break;
 500     case 2:
 501         ret = s->iir;
 502         if ((ret & UART_IIR_ID) == UART_IIR_THRI) {
 503             s->thr_ipending = 0;
 504             serial_update_irq(s);
 505         }
 506         break;
 507     case 3:
 508         ret = s->lcr;
 509         break;
 510     case 4:
 511         ret = s->mcr;
 512         break;
 513     case 5:
 514         ret = s->lsr;
 515         /* Clear break and overrun interrupts */
 516         if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
 517             s->lsr &= ~(UART_LSR_BI|UART_LSR_OE);
 518             serial_update_irq(s);
 519         }
 520         break;
 521     case 6:
 522         if (s->mcr & UART_MCR_LOOP) {
 523             /* in loopback, the modem output pins are connected to the
 524                inputs */
 525             ret = (s->mcr & 0x0c) << 4;
 526             ret |= (s->mcr & 0x02) << 3;
 527             ret |= (s->mcr & 0x01) << 5;
 528         } else {
 529             if (s->poll_msl >= 0)
 530                 serial_update_msl(s);
 531             ret = s->msr;
 532             /* Clear delta bits & msr int after read, if they were set */
 533             if (s->msr & UART_MSR_ANY_DELTA) {
 534                 s->msr &= 0xF0;
 535                 serial_update_irq(s);
 536             }
 537         }
 538         break;
 539     case 7:
 540         ret = s->scr;
 541         break;
 542     }
 543     DPRINTF("read addr=0x%" HWADDR_PRIx " val=0x%02x\n", addr, ret);
 544     return ret;
 545 }
 546
 547 static int serial_can_receive(SerialState *s)
 548 {
 549     if(s->fcr & UART_FCR_FE) {
 550         if (s->recv_fifo.num < UART_FIFO_LENGTH) {
 551             /*
 552              * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1
 553              * if above. If UART_FIFO_LENGTH - fifo.count is advertised the
 554              * effect will be to almost always fill the fifo completely before
 555              * the guest has a chance to respond, effectively overriding the ITL
 556              * that the guest has set.
 557              */
 558             return (s->recv_fifo.num <= s->recv_fifo_itl) ?
 559                         s->recv_fifo_itl - s->recv_fifo.num : 1;
 560         } else {
 561             return 0;
 562         }
 563     } else {
 564         return !(s->lsr & UART_LSR_DR);
 565     }
 566 }
 567
 568 static void serial_receive_break(SerialState *s)
 569 {
 570     s->rbr = 0;
 571     /* When the LSR_DR is set a null byte is pushed into the fifo */
 572     recv_fifo_put(s, '\0');
 573     s->lsr |= UART_LSR_BI | UART_LSR_DR;
 574     serial_update_irq(s);
 575 }
 576
 577 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
 578 static void fifo_timeout_int (void *opaque) {
 579     SerialState *s = opaque;
 580     if (s->recv_fifo.num) {
 581         s->timeout_ipending = 1;
 582         serial_update_irq(s);
 583     }
 584 }
 585
 586 static int serial_can_receive1(void *opaque)
 587 {
 588     SerialState *s = opaque;
 589     return serial_can_receive(s);
 590 }
 591
 592 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
 593 {
 594     SerialState *s = opaque;
 595
 596     if (s->wakeup) {
 597         qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER);
 598     }
 599     if(s->fcr & UART_FCR_FE) {
 600         int i;
 601         for (i = 0; i < size; i++) {
 602             recv_fifo_put(s, buf[i]);
 603         }
 604         s->lsr |= UART_LSR_DR;
 605         /* call the timeout receive callback in 4 char transmit time */
 606         timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4);
 607     } else {
 608         if (s->lsr & UART_LSR_DR)
 609             s->lsr |= UART_LSR_OE;
 610         s->rbr = buf[0];
 611         s->lsr |= UART_LSR_DR;
 612     }
 613     serial_update_irq(s);
 614 }
 615
 616 static void serial_event(void *opaque, int event)
 617 {
 618     SerialState *s = opaque;
 619     DPRINTF("event %x\n", event);
 620     if (event == CHR_EVENT_BREAK)
 621         serial_receive_break(s);
 622 }
 623
 624 static void serial_pre_save(void *opaque)
 625 {
 626     SerialState *s = opaque;
 627     s->fcr_vmstate = s->fcr;
 628 }
 629
 630 static int serial_pre_load(void *opaque)
 631 {
 632     SerialState *s = opaque;
 633     s->thr_ipending = -1;
 634     s->poll_msl = -1;
 635     return 0;
 636 }
 637
 638 static int serial_post_load(void *opaque, int version_id)
 639 {
 640     SerialState *s = opaque;
 641
 642     if (version_id < 3) {
 643         s->fcr_vmstate = 0;
 644     }
 645     if (s->thr_ipending == -1) {
 646         s->thr_ipending = ((s->iir & UART_IIR_ID) == UART_IIR_THRI);
 647     }
 648
 649     if (s->tsr_retry > 0) {
 650         /* tsr_retry > 0 implies LSR.TEMT = 0 (transmitter not empty).  */
 651         if (s->lsr & UART_LSR_TEMT) {
 652             error_report("inconsistent state in serial device "
 653                          "(tsr empty, tsr_retry=%d", s->tsr_retry);
 654             return -1;
 655         }
 656
 657         if (s->tsr_retry > MAX_XMIT_RETRY) {
 658             s->tsr_retry = MAX_XMIT_RETRY;
 659         }
 660
 661         assert(s->watch_tag == 0);
 662         s->watch_tag = qemu_chr_fe_add_watch(s->chr, G_IO_OUT|G_IO_HUP,
 663                                              serial_watch_cb, s);
 664     } else {
 665         /* tsr_retry == 0 implies LSR.TEMT = 1 (transmitter empty).  */
 666         if (!(s->lsr & UART_LSR_TEMT)) {
 667             error_report("inconsistent state in serial device "
 668                          "(tsr not empty, tsr_retry=0");
 669             return -1;
 670         }
 671     }
 672
 673     s->last_break_enable = (s->lcr >> 6) & 1;
 674     /* Initialize fcr via setter to perform essential side-effects */
 675     serial_write_fcr(s, s->fcr_vmstate);
 676     serial_update_parameters(s);
 677     return 0;
 678 }
 679
 680 static bool serial_thr_ipending_needed(void *opaque)
 681 {
 682     SerialState *s = opaque;
 683
 684     if (s->ier & UART_IER_THRI) {
 685         bool expected_value = ((s->iir & UART_IIR_ID) == UART_IIR_THRI);
 686         return s->thr_ipending != expected_value;
 687     } else {
 688         /* LSR.THRE will be sampled again when the interrupt is
 689          * enabled.  thr_ipending is not used in this case, do
 690          * not migrate it.
 691          */
 692         return false;
 693     }
 694 }
 695
 696 static const VMStateDescription vmstate_serial_thr_ipending = {
 697     .name = "serial/thr_ipending",
 698     .version_id = 1,
 699     .minimum_version_id = 1,
 700     .needed = serial_thr_ipending_needed,
 701     .fields = (VMStateField[]) {
 702         VMSTATE_INT32(thr_ipending, SerialState),
 703         VMSTATE_END_OF_LIST()
 704     }
 705 };
 706
 707 static bool serial_tsr_needed(void *opaque)
 708 {
 709     SerialState *s = (SerialState *)opaque;
 710     return s->tsr_retry != 0;
 711 }
 712
 713 static const VMStateDescription vmstate_serial_tsr = {
 714     .name = "serial/tsr",
 715     .version_id = 1,
 716     .minimum_version_id = 1,
 717     .needed = serial_tsr_needed,
 718     .fields = (VMStateField[]) {
 719         VMSTATE_UINT32(tsr_retry, SerialState),
 720         VMSTATE_UINT8(thr, SerialState),
 721         VMSTATE_UINT8(tsr, SerialState),
 722         VMSTATE_END_OF_LIST()
 723     }
 724 };
 725
 726 static bool serial_recv_fifo_needed(void *opaque)
 727 {
 728     SerialState *s = (SerialState *)opaque;
 729     return !fifo8_is_empty(&s->recv_fifo);
 730
 731 }
 732
 733 static const VMStateDescription vmstate_serial_recv_fifo = {
 734     .name = "serial/recv_fifo",
 735     .version_id = 1,
 736     .minimum_version_id = 1,
 737     .needed = serial_recv_fifo_needed,
 738     .fields = (VMStateField[]) {
 739         VMSTATE_STRUCT(recv_fifo, SerialState, 1, vmstate_fifo8, Fifo8),
 740         VMSTATE_END_OF_LIST()
 741     }
 742 };
 743
 744 static bool serial_xmit_fifo_needed(void *opaque)
 745 {
 746     SerialState *s = (SerialState *)opaque;
 747     return !fifo8_is_empty(&s->xmit_fifo);
 748 }
 749
 750 static const VMStateDescription vmstate_serial_xmit_fifo = {
 751     .name = "serial/xmit_fifo",
 752     .version_id = 1,
 753     .minimum_version_id = 1,
 754     .needed = serial_xmit_fifo_needed,
 755     .fields = (VMStateField[]) {
 756         VMSTATE_STRUCT(xmit_fifo, SerialState, 1, vmstate_fifo8, Fifo8),
 757         VMSTATE_END_OF_LIST()
 758     }
 759 };
 760
 761 static bool serial_fifo_timeout_timer_needed(void *opaque)
 762 {
 763     SerialState *s = (SerialState *)opaque;
 764     return timer_pending(s->fifo_timeout_timer);
 765 }
 766
 767 static const VMStateDescription vmstate_serial_fifo_timeout_timer = {
 768     .name = "serial/fifo_timeout_timer",
 769     .version_id = 1,
 770     .minimum_version_id = 1,
 771     .needed = serial_fifo_timeout_timer_needed,
 772     .fields = (VMStateField[]) {
 773         VMSTATE_TIMER_PTR(fifo_timeout_timer, SerialState),
 774         VMSTATE_END_OF_LIST()
 775     }
 776 };
 777
 778 static bool serial_timeout_ipending_needed(void *opaque)
 779 {
 780     SerialState *s = (SerialState *)opaque;
 781     return s->timeout_ipending != 0;
 782 }
 783
 784 static const VMStateDescription vmstate_serial_timeout_ipending = {
 785     .name = "serial/timeout_ipending",
 786     .version_id = 1,
 787     .minimum_version_id = 1,
 788     .needed = serial_timeout_ipending_needed,
 789     .fields = (VMStateField[]) {
 790         VMSTATE_INT32(timeout_ipending, SerialState),
 791         VMSTATE_END_OF_LIST()
 792     }
 793 };
 794
 795 static bool serial_poll_needed(void *opaque)
 796 {
 797     SerialState *s = (SerialState *)opaque;
 798     return s->poll_msl >= 0;
 799 }
 800
 801 static const VMStateDescription vmstate_serial_poll = {
 802     .name = "serial/poll",
 803     .version_id = 1,
 804     .needed = serial_poll_needed,
 805     .minimum_version_id = 1,
 806     .fields = (VMStateField[]) {
 807         VMSTATE_INT32(poll_msl, SerialState),
 808         VMSTATE_TIMER_PTR(modem_status_poll, SerialState),
 809         VMSTATE_END_OF_LIST()
 810     }
 811 };
 812
 813 const VMStateDescription vmstate_serial = {
 814     .name = "serial",
 815     .version_id = 3,
 816     .minimum_version_id = 2,
 817     .pre_save = serial_pre_save,
 818     .pre_load = serial_pre_load,
 819     .post_load = serial_post_load,
 820     .fields = (VMStateField[]) {
 821         VMSTATE_UINT16_V(divider, SerialState, 2),
 822         VMSTATE_UINT8(rbr, SerialState),
 823         VMSTATE_UINT8(ier, SerialState),
 824         VMSTATE_UINT8(iir, SerialState),
 825         VMSTATE_UINT8(lcr, SerialState),
 826         VMSTATE_UINT8(mcr, SerialState),
 827         VMSTATE_UINT8(lsr, SerialState),
 828         VMSTATE_UINT8(msr, SerialState),
 829         VMSTATE_UINT8(scr, SerialState),
 830         VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
 831         VMSTATE_END_OF_LIST()
 832     },
 833     .subsections = (const VMStateDescription*[]) {
 834         &vmstate_serial_thr_ipending,
 835         &vmstate_serial_tsr,
 836         &vmstate_serial_recv_fifo,
 837         &vmstate_serial_xmit_fifo,
 838         &vmstate_serial_fifo_timeout_timer,
 839         &vmstate_serial_timeout_ipending,
 840         &vmstate_serial_poll,
 841         NULL
 842     }
 843 };
 844
 845 static void serial_reset(void *opaque)
 846 {
 847     SerialState *s = opaque;
 848
 849     if (s->watch_tag > 0) {
 850         g_source_remove(s->watch_tag);
 851         s->watch_tag = 0;
 852     }
 853
 854     s->rbr = 0;
 855     s->ier = 0;
 856     s->iir = UART_IIR_NO_INT;
 857     s->lcr = 0;
 858     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 859     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
 860     /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */
 861     s->divider = 0x0C;
 862     s->mcr = UART_MCR_OUT2;
 863     s->scr = 0;
 864     s->tsr_retry = 0;
 865     s->char_transmit_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
 866     s->poll_msl = 0;
 867
 868     s->timeout_ipending = 0;
 869     timer_del(s->fifo_timeout_timer);
 870     timer_del(s->modem_status_poll);
 871
 872     fifo8_reset(&s->recv_fifo);
 873     fifo8_reset(&s->xmit_fifo);
 874
 875     s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 876
 877     s->thr_ipending = 0;
 878     s->last_break_enable = 0;
 879     qemu_irq_lower(s->irq);
 880
 881     serial_update_msl(s);
 882     s->msr &= ~UART_MSR_ANY_DELTA;
 883 }
 884
 885 void serial_realize_core(SerialState *s, Error **errp)
 886 {
 887     if (!s->chr) {
 888         error_setg(errp, "Can't create serial device, empty char device");
 889         return;
 890     }
 891
 892     s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s);
 893
 894     s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s);
 895     qemu_register_reset(serial_reset, s);
 896
 897     qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
 898                           serial_event, s);
 899     fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH);
 900     fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH);
 901     serial_reset(s);
 902 }
 903
 904 void serial_exit_core(SerialState *s)
 905 {
 906     qemu_chr_add_handlers(s->chr, NULL, NULL, NULL, NULL);
 907     qemu_unregister_reset(serial_reset, s);
 908 }
 909
 910 /* Change the main reference oscillator frequency. */
 911 void serial_set_frequency(SerialState *s, uint32_t frequency)
 912 {
 913     s->baudbase = frequency;
 914     serial_update_parameters(s);
 915 }
 916
 917 const MemoryRegionOps serial_io_ops = {
 918     .read = serial_ioport_read,
 919     .write = serial_ioport_write,
 920     .impl = {
 921         .min_access_size = 1,
 922         .max_access_size = 1,
 923     },
 924     .endianness = DEVICE_LITTLE_ENDIAN,
 925 };
 926
 927 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
 928                          CharDriverState *chr, MemoryRegion *system_io)
 929 {
 930     SerialState *s;
 931
 932     s = g_malloc0(sizeof(SerialState));
 933
 934     s->irq = irq;
 935     s->baudbase = baudbase;
 936     s->chr = chr;
 937     serial_realize_core(s, &error_fatal);
 938
 939     vmstate_register(NULL, base, &vmstate_serial, s);
 940
 941     memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8);
 942     memory_region_add_subregion(system_io, base, &s->io);
 943
 944     return s;
 945 }
 946
 947 /* Memory mapped interface */
 948 static uint64_t serial_mm_read(void *opaque, hwaddr addr,
 949                                unsigned size)
 950 {
 951     SerialState *s = opaque;
 952     return serial_ioport_read(s, addr >> s->it_shift, 1);
 953 }
 954
 955 static void serial_mm_write(void *opaque, hwaddr addr,
 956                             uint64_t value, unsigned size)
 957 {
 958     SerialState *s = opaque;
 959     value &= ~0u >> (32 - (size * 8));
 960     serial_ioport_write(s, addr >> s->it_shift, value, 1);
 961 }
 962
 963 static const MemoryRegionOps serial_mm_ops[3] = {
 964     [DEVICE_NATIVE_ENDIAN] = {
 965         .read = serial_mm_read,
 966         .write = serial_mm_write,
 967         .endianness = DEVICE_NATIVE_ENDIAN,
 968     },
 969     [DEVICE_LITTLE_ENDIAN] = {
 970         .read = serial_mm_read,
 971         .write = serial_mm_write,
 972         .endianness = DEVICE_LITTLE_ENDIAN,
 973     },
 974     [DEVICE_BIG_ENDIAN] = {
 975         .read = serial_mm_read,
 976         .write = serial_mm_write,
 977         .endianness = DEVICE_BIG_ENDIAN,
 978     },
 979 };
 980
 981 SerialState *serial_mm_init(MemoryRegion *address_space,
 982                             hwaddr base, int it_shift,
 983                             qemu_irq irq, int baudbase,
 984                             CharDriverState *chr, enum device_endian end)
 985 {
 986     SerialState *s;
 987
 988     s = g_malloc0(sizeof(SerialState));
 989
 990     s->it_shift = it_shift;
 991     s->irq = irq;
 992     s->baudbase = baudbase;
 993     s->chr = chr;
 994
 995     serial_realize_core(s, &error_fatal);
 996     vmstate_register(NULL, base, &vmstate_serial, s);
 997
 998     memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s,
 999                           "serial", 8 << it_shift);
1000     memory_region_add_subregion(address_space, base, &s->io);
1001     return s;
1002 }