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configure: Require at least spice-protocol-0.12.3
[qemu/ar7.git] / hw / ppc.c
blob8cfb84fa13fc73d1aa40c61194cbd8cfcaad33c8
1 /*
2 * QEMU generic PowerPC hardware System Emulator
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "ppc.h"
26 #include "qemu/timer.h"
27 #include "sysemu/sysemu.h"
28 #include "nvram.h"
29 #include "qemu/log.h"
30 #include "loader.h"
31 #include "sysemu/kvm.h"
32 #include "kvm_ppc.h"
33
34 //#define PPC_DEBUG_IRQ
35 //#define PPC_DEBUG_TB
36
37 #ifdef PPC_DEBUG_IRQ
38 # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
39 #else
40 # define LOG_IRQ(...) do { } while (0)
41 #endif
42
43
44 #ifdef PPC_DEBUG_TB
45 # define LOG_TB(...) qemu_log(__VA_ARGS__)
46 #else
47 # define LOG_TB(...) do { } while (0)
48 #endif
49
50 static void cpu_ppc_tb_stop (CPUPPCState *env);
51 static void cpu_ppc_tb_start (CPUPPCState *env);
52
53 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level)
54 {
55 CPUPPCState *env = &cpu->env;
56 unsigned int old_pending = env->pending_interrupts;
57
58 if (level) {
59 env->pending_interrupts |= 1 << n_IRQ;
60 cpu_interrupt(env, CPU_INTERRUPT_HARD);
61 } else {
62 env->pending_interrupts &= ~(1 << n_IRQ);
63 if (env->pending_interrupts == 0)
64 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
65 }
66
67 if (old_pending != env->pending_interrupts) {
68 #ifdef CONFIG_KVM
69 kvmppc_set_interrupt(cpu, n_IRQ, level);
70 #endif
71 }
72
73 LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
74 "req %08x\n", __func__, env, n_IRQ, level,
75 env->pending_interrupts, env->interrupt_request);
76 }
77
78 /* PowerPC 6xx / 7xx internal IRQ controller */
79 static void ppc6xx_set_irq(void *opaque, int pin, int level)
80 {
81 PowerPCCPU *cpu = opaque;
82 CPUPPCState *env = &cpu->env;
83 int cur_level;
84
85 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
86 env, pin, level);
87 cur_level = (env->irq_input_state >> pin) & 1;
88 /* Don't generate spurious events */
89 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
90 switch (pin) {
91 case PPC6xx_INPUT_TBEN:
92 /* Level sensitive - active high */
93 LOG_IRQ("%s: %s the time base\n",
94 __func__, level ? "start" : "stop");
95 if (level) {
96 cpu_ppc_tb_start(env);
97 } else {
98 cpu_ppc_tb_stop(env);
99 }
100 case PPC6xx_INPUT_INT:
101 /* Level sensitive - active high */
102 LOG_IRQ("%s: set the external IRQ state to %d\n",
103 __func__, level);
104 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
105 break;
106 case PPC6xx_INPUT_SMI:
107 /* Level sensitive - active high */
108 LOG_IRQ("%s: set the SMI IRQ state to %d\n",
109 __func__, level);
110 ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level);
111 break;
112 case PPC6xx_INPUT_MCP:
113 /* Negative edge sensitive */
114 /* XXX: TODO: actual reaction may depends on HID0 status
115 * 603/604/740/750: check HID0[EMCP]
116 */
117 if (cur_level == 1 && level == 0) {
118 LOG_IRQ("%s: raise machine check state\n",
119 __func__);
120 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
121 }
122 break;
123 case PPC6xx_INPUT_CKSTP_IN:
124 /* Level sensitive - active low */
125 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
126 /* XXX: Note that the only way to restart the CPU is to reset it */
127 if (level) {
128 LOG_IRQ("%s: stop the CPU\n", __func__);
129 env->halted = 1;
130 }
131 break;
132 case PPC6xx_INPUT_HRESET:
133 /* Level sensitive - active low */
134 if (level) {
135 LOG_IRQ("%s: reset the CPU\n", __func__);
136 cpu_interrupt(env, CPU_INTERRUPT_RESET);
137 }
138 break;
139 case PPC6xx_INPUT_SRESET:
140 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
141 __func__, level);
142 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
143 break;
144 default:
145 /* Unknown pin - do nothing */
146 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
147 return;
148 }
149 if (level)
150 env->irq_input_state |= 1 << pin;
151 else
152 env->irq_input_state &= ~(1 << pin);
153 }
154 }
155
156 void ppc6xx_irq_init(CPUPPCState *env)
157 {
158 PowerPCCPU *cpu = ppc_env_get_cpu(env);
159
160 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu,
161 PPC6xx_INPUT_NB);
162 }
163
164 #if defined(TARGET_PPC64)
165 /* PowerPC 970 internal IRQ controller */
166 static void ppc970_set_irq(void *opaque, int pin, int level)
167 {
168 PowerPCCPU *cpu = opaque;
169 CPUPPCState *env = &cpu->env;
170 int cur_level;
171
172 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
173 env, pin, level);
174 cur_level = (env->irq_input_state >> pin) & 1;
175 /* Don't generate spurious events */
176 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
177 switch (pin) {
178 case PPC970_INPUT_INT:
179 /* Level sensitive - active high */
180 LOG_IRQ("%s: set the external IRQ state to %d\n",
181 __func__, level);
182 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
183 break;
184 case PPC970_INPUT_THINT:
185 /* Level sensitive - active high */
186 LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__,
187 level);
188 ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level);
189 break;
190 case PPC970_INPUT_MCP:
191 /* Negative edge sensitive */
192 /* XXX: TODO: actual reaction may depends on HID0 status
193 * 603/604/740/750: check HID0[EMCP]
194 */
195 if (cur_level == 1 && level == 0) {
196 LOG_IRQ("%s: raise machine check state\n",
197 __func__);
198 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
199 }
200 break;
201 case PPC970_INPUT_CKSTP:
202 /* Level sensitive - active low */
203 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
204 if (level) {
205 LOG_IRQ("%s: stop the CPU\n", __func__);
206 env->halted = 1;
207 } else {
208 LOG_IRQ("%s: restart the CPU\n", __func__);
209 env->halted = 0;
210 qemu_cpu_kick(CPU(cpu));
211 }
212 break;
213 case PPC970_INPUT_HRESET:
214 /* Level sensitive - active low */
215 if (level) {
216 cpu_interrupt(env, CPU_INTERRUPT_RESET);
217 }
218 break;
219 case PPC970_INPUT_SRESET:
220 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
221 __func__, level);
222 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
223 break;
224 case PPC970_INPUT_TBEN:
225 LOG_IRQ("%s: set the TBEN state to %d\n", __func__,
226 level);
227 /* XXX: TODO */
228 break;
229 default:
230 /* Unknown pin - do nothing */
231 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
232 return;
233 }
234 if (level)
235 env->irq_input_state |= 1 << pin;
236 else
237 env->irq_input_state &= ~(1 << pin);
238 }
239 }
240
241 void ppc970_irq_init(CPUPPCState *env)
242 {
243 PowerPCCPU *cpu = ppc_env_get_cpu(env);
244
245 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu,
246 PPC970_INPUT_NB);
247 }
248
249 /* POWER7 internal IRQ controller */
250 static void power7_set_irq(void *opaque, int pin, int level)
251 {
252 PowerPCCPU *cpu = opaque;
253 CPUPPCState *env = &cpu->env;
254
255 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
256 env, pin, level);
257
258 switch (pin) {
259 case POWER7_INPUT_INT:
260 /* Level sensitive - active high */
261 LOG_IRQ("%s: set the external IRQ state to %d\n",
262 __func__, level);
263 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
264 break;
265 default:
266 /* Unknown pin - do nothing */
267 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
268 return;
269 }
270 if (level) {
271 env->irq_input_state |= 1 << pin;
272 } else {
273 env->irq_input_state &= ~(1 << pin);
274 }
275 }
276
277 void ppcPOWER7_irq_init(CPUPPCState *env)
278 {
279 PowerPCCPU *cpu = ppc_env_get_cpu(env);
280
281 env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu,
282 POWER7_INPUT_NB);
283 }
284 #endif /* defined(TARGET_PPC64) */
285
286 /* PowerPC 40x internal IRQ controller */
287 static void ppc40x_set_irq(void *opaque, int pin, int level)
288 {
289 PowerPCCPU *cpu = opaque;
290 CPUPPCState *env = &cpu->env;
291 int cur_level;
292
293 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
294 env, pin, level);
295 cur_level = (env->irq_input_state >> pin) & 1;
296 /* Don't generate spurious events */
297 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
298 switch (pin) {
299 case PPC40x_INPUT_RESET_SYS:
300 if (level) {
301 LOG_IRQ("%s: reset the PowerPC system\n",
302 __func__);
303 ppc40x_system_reset(cpu);
304 }
305 break;
306 case PPC40x_INPUT_RESET_CHIP:
307 if (level) {
308 LOG_IRQ("%s: reset the PowerPC chip\n", __func__);
309 ppc40x_chip_reset(cpu);
310 }
311 break;
312 case PPC40x_INPUT_RESET_CORE:
313 /* XXX: TODO: update DBSR[MRR] */
314 if (level) {
315 LOG_IRQ("%s: reset the PowerPC core\n", __func__);
316 ppc40x_core_reset(cpu);
317 }
318 break;
319 case PPC40x_INPUT_CINT:
320 /* Level sensitive - active high */
321 LOG_IRQ("%s: set the critical IRQ state to %d\n",
322 __func__, level);
323 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
324 break;
325 case PPC40x_INPUT_INT:
326 /* Level sensitive - active high */
327 LOG_IRQ("%s: set the external IRQ state to %d\n",
328 __func__, level);
329 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
330 break;
331 case PPC40x_INPUT_HALT:
332 /* Level sensitive - active low */
333 if (level) {
334 LOG_IRQ("%s: stop the CPU\n", __func__);
335 env->halted = 1;
336 } else {
337 LOG_IRQ("%s: restart the CPU\n", __func__);
338 env->halted = 0;
339 qemu_cpu_kick(CPU(cpu));
340 }
341 break;
342 case PPC40x_INPUT_DEBUG:
343 /* Level sensitive - active high */
344 LOG_IRQ("%s: set the debug pin state to %d\n",
345 __func__, level);
346 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
347 break;
348 default:
349 /* Unknown pin - do nothing */
350 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
351 return;
352 }
353 if (level)
354 env->irq_input_state |= 1 << pin;
355 else
356 env->irq_input_state &= ~(1 << pin);
357 }
358 }
359
360 void ppc40x_irq_init(CPUPPCState *env)
361 {
362 PowerPCCPU *cpu = ppc_env_get_cpu(env);
363
364 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
365 cpu, PPC40x_INPUT_NB);
366 }
367
368 /* PowerPC E500 internal IRQ controller */
369 static void ppce500_set_irq(void *opaque, int pin, int level)
370 {
371 PowerPCCPU *cpu = opaque;
372 CPUPPCState *env = &cpu->env;
373 int cur_level;
374
375 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
376 env, pin, level);
377 cur_level = (env->irq_input_state >> pin) & 1;
378 /* Don't generate spurious events */
379 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
380 switch (pin) {
381 case PPCE500_INPUT_MCK:
382 if (level) {
383 LOG_IRQ("%s: reset the PowerPC system\n",
384 __func__);
385 qemu_system_reset_request();
386 }
387 break;
388 case PPCE500_INPUT_RESET_CORE:
389 if (level) {
390 LOG_IRQ("%s: reset the PowerPC core\n", __func__);
391 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level);
392 }
393 break;
394 case PPCE500_INPUT_CINT:
395 /* Level sensitive - active high */
396 LOG_IRQ("%s: set the critical IRQ state to %d\n",
397 __func__, level);
398 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
399 break;
400 case PPCE500_INPUT_INT:
401 /* Level sensitive - active high */
402 LOG_IRQ("%s: set the core IRQ state to %d\n",
403 __func__, level);
404 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
405 break;
406 case PPCE500_INPUT_DEBUG:
407 /* Level sensitive - active high */
408 LOG_IRQ("%s: set the debug pin state to %d\n",
409 __func__, level);
410 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
411 break;
412 default:
413 /* Unknown pin - do nothing */
414 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
415 return;
416 }
417 if (level)
418 env->irq_input_state |= 1 << pin;
419 else
420 env->irq_input_state &= ~(1 << pin);
421 }
422 }
423
424 void ppce500_irq_init(CPUPPCState *env)
425 {
426 PowerPCCPU *cpu = ppc_env_get_cpu(env);
427
428 env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
429 cpu, PPCE500_INPUT_NB);
430 }
431
432 /* Enable or Disable the E500 EPR capability */
433 void ppce500_set_mpic_proxy(bool enabled)
434 {
435 CPUPPCState *env;
436
437 for (env = first_cpu; env != NULL; env = env->next_cpu) {
438 PowerPCCPU *cpu = ppc_env_get_cpu(env);
439 CPUState *cs = CPU(cpu);
440
441 env->mpic_proxy = enabled;
442 if (kvm_enabled()) {
443 kvmppc_set_mpic_proxy(POWERPC_CPU(cs), enabled);
444 }
445 }
446 }
447
448 /*****************************************************************************/
449 /* PowerPC time base and decrementer emulation */
450
451 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset)
452 {
453 /* TB time in tb periods */
454 return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset;
455 }
456
457 uint64_t cpu_ppc_load_tbl (CPUPPCState *env)
458 {
459 ppc_tb_t *tb_env = env->tb_env;
460 uint64_t tb;
461
462 if (kvm_enabled()) {
463 return env->spr[SPR_TBL];
464 }
465
466 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
467 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
468
469 return tb;
470 }
471
472 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env)
473 {
474 ppc_tb_t *tb_env = env->tb_env;
475 uint64_t tb;
476
477 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
478 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
479
480 return tb >> 32;
481 }
482
483 uint32_t cpu_ppc_load_tbu (CPUPPCState *env)
484 {
485 if (kvm_enabled()) {
486 return env->spr[SPR_TBU];
487 }
488
489 return _cpu_ppc_load_tbu(env);
490 }
491
492 static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk,
493 int64_t *tb_offsetp, uint64_t value)
494 {
495 *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec());
496 LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",
497 __func__, value, *tb_offsetp);
498 }
499
500 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value)
501 {
502 ppc_tb_t *tb_env = env->tb_env;
503 uint64_t tb;
504
505 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
506 tb &= 0xFFFFFFFF00000000ULL;
507 cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
508 &tb_env->tb_offset, tb | (uint64_t)value);
509 }
510
511 static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value)
512 {
513 ppc_tb_t *tb_env = env->tb_env;
514 uint64_t tb;
515
516 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
517 tb &= 0x00000000FFFFFFFFULL;
518 cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
519 &tb_env->tb_offset, ((uint64_t)value << 32) | tb);
520 }
521
522 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value)
523 {
524 _cpu_ppc_store_tbu(env, value);
525 }
526
527 uint64_t cpu_ppc_load_atbl (CPUPPCState *env)
528 {
529 ppc_tb_t *tb_env = env->tb_env;
530 uint64_t tb;
531
532 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
533 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
534
535 return tb;
536 }
537
538 uint32_t cpu_ppc_load_atbu (CPUPPCState *env)
539 {
540 ppc_tb_t *tb_env = env->tb_env;
541 uint64_t tb;
542
543 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
544 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
545
546 return tb >> 32;
547 }
548
549 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value)
550 {
551 ppc_tb_t *tb_env = env->tb_env;
552 uint64_t tb;
553
554 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
555 tb &= 0xFFFFFFFF00000000ULL;
556 cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
557 &tb_env->atb_offset, tb | (uint64_t)value);
558 }
559
560 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value)
561 {
562 ppc_tb_t *tb_env = env->tb_env;
563 uint64_t tb;
564
565 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
566 tb &= 0x00000000FFFFFFFFULL;
567 cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
568 &tb_env->atb_offset, ((uint64_t)value << 32) | tb);
569 }
570
571 static void cpu_ppc_tb_stop (CPUPPCState *env)
572 {
573 ppc_tb_t *tb_env = env->tb_env;
574 uint64_t tb, atb, vmclk;
575
576 /* If the time base is already frozen, do nothing */
577 if (tb_env->tb_freq != 0) {
578 vmclk = qemu_get_clock_ns(vm_clock);
579 /* Get the time base */
580 tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset);
581 /* Get the alternate time base */
582 atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset);
583 /* Store the time base value (ie compute the current offset) */
584 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
585 /* Store the alternate time base value (compute the current offset) */
586 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
587 /* Set the time base frequency to zero */
588 tb_env->tb_freq = 0;
589 /* Now, the time bases are frozen to tb_offset / atb_offset value */
590 }
591 }
592
593 static void cpu_ppc_tb_start (CPUPPCState *env)
594 {
595 ppc_tb_t *tb_env = env->tb_env;
596 uint64_t tb, atb, vmclk;
597
598 /* If the time base is not frozen, do nothing */
599 if (tb_env->tb_freq == 0) {
600 vmclk = qemu_get_clock_ns(vm_clock);
601 /* Get the time base from tb_offset */
602 tb = tb_env->tb_offset;
603 /* Get the alternate time base from atb_offset */
604 atb = tb_env->atb_offset;
605 /* Restore the tb frequency from the decrementer frequency */
606 tb_env->tb_freq = tb_env->decr_freq;
607 /* Store the time base value */
608 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
609 /* Store the alternate time base value */
610 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
611 }
612 }
613
614 static inline uint32_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next)
615 {
616 ppc_tb_t *tb_env = env->tb_env;
617 uint32_t decr;
618 int64_t diff;
619
620 diff = next - qemu_get_clock_ns(vm_clock);
621 if (diff >= 0) {
622 decr = muldiv64(diff, tb_env->decr_freq, get_ticks_per_sec());
623 } else if (tb_env->flags & PPC_TIMER_BOOKE) {
624 decr = 0;
625 } else {
626 decr = -muldiv64(-diff, tb_env->decr_freq, get_ticks_per_sec());
627 }
628 LOG_TB("%s: %08" PRIx32 "\n", __func__, decr);
629
630 return decr;
631 }
632
633 uint32_t cpu_ppc_load_decr (CPUPPCState *env)
634 {
635 ppc_tb_t *tb_env = env->tb_env;
636
637 if (kvm_enabled()) {
638 return env->spr[SPR_DECR];
639 }
640
641 return _cpu_ppc_load_decr(env, tb_env->decr_next);
642 }
643
644 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env)
645 {
646 ppc_tb_t *tb_env = env->tb_env;
647
648 return _cpu_ppc_load_decr(env, tb_env->hdecr_next);
649 }
650
651 uint64_t cpu_ppc_load_purr (CPUPPCState *env)
652 {
653 ppc_tb_t *tb_env = env->tb_env;
654 uint64_t diff;
655
656 diff = qemu_get_clock_ns(vm_clock) - tb_env->purr_start;
657
658 return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, get_ticks_per_sec());
659 }
660
661 /* When decrementer expires,
662 * all we need to do is generate or queue a CPU exception
663 */
664 static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu)
665 {
666 /* Raise it */
667 LOG_TB("raise decrementer exception\n");
668 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1);
669 }
670
671 static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu)
672 {
673 /* Raise it */
674 LOG_TB("raise decrementer exception\n");
675 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1);
676 }
677
678 static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp,
679 struct QEMUTimer *timer,
680 void (*raise_excp)(PowerPCCPU *),
681 uint32_t decr, uint32_t value,
682 int is_excp)
683 {
684 CPUPPCState *env = &cpu->env;
685 ppc_tb_t *tb_env = env->tb_env;
686 uint64_t now, next;
687
688 LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,
689 decr, value);
690
691 if (kvm_enabled()) {
692 /* KVM handles decrementer exceptions, we don't need our own timer */
693 return;
694 }
695
696 now = qemu_get_clock_ns(vm_clock);
697 next = now + muldiv64(value, get_ticks_per_sec(), tb_env->decr_freq);
698 if (is_excp) {
699 next += *nextp - now;
700 }
701 if (next == now) {
702 next++;
703 }
704 *nextp = next;
705 /* Adjust timer */
706 qemu_mod_timer(timer, next);
707
708 /* If we set a negative value and the decrementer was positive, raise an
709 * exception.
710 */
711 if ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED)
712 && (value & 0x80000000)
713 && !(decr & 0x80000000)) {
714 (*raise_excp)(cpu);
715 }
716 }
717
718 static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, uint32_t decr,
719 uint32_t value, int is_excp)
720 {
721 ppc_tb_t *tb_env = cpu->env.tb_env;
722
723 __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer,
724 &cpu_ppc_decr_excp, decr, value, is_excp);
725 }
726
727 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value)
728 {
729 PowerPCCPU *cpu = ppc_env_get_cpu(env);
730
731 _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value, 0);
732 }
733
734 static void cpu_ppc_decr_cb(void *opaque)
735 {
736 PowerPCCPU *cpu = opaque;
737
738 _cpu_ppc_store_decr(cpu, 0x00000000, 0xFFFFFFFF, 1);
739 }
740
741 static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, uint32_t hdecr,
742 uint32_t value, int is_excp)
743 {
744 ppc_tb_t *tb_env = cpu->env.tb_env;
745
746 if (tb_env->hdecr_timer != NULL) {
747 __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer,
748 &cpu_ppc_hdecr_excp, hdecr, value, is_excp);
749 }
750 }
751
752 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value)
753 {
754 PowerPCCPU *cpu = ppc_env_get_cpu(env);
755
756 _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value, 0);
757 }
758
759 static void cpu_ppc_hdecr_cb(void *opaque)
760 {
761 PowerPCCPU *cpu = opaque;
762
763 _cpu_ppc_store_hdecr(cpu, 0x00000000, 0xFFFFFFFF, 1);
764 }
765
766 static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_t value)
767 {
768 ppc_tb_t *tb_env = cpu->env.tb_env;
769
770 tb_env->purr_load = value;
771 tb_env->purr_start = qemu_get_clock_ns(vm_clock);
772 }
773
774 static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
775 {
776 CPUPPCState *env = opaque;
777 PowerPCCPU *cpu = ppc_env_get_cpu(env);
778 ppc_tb_t *tb_env = env->tb_env;
779
780 tb_env->tb_freq = freq;
781 tb_env->decr_freq = freq;
782 /* There is a bug in Linux 2.4 kernels:
783 * if a decrementer exception is pending when it enables msr_ee at startup,
784 * it's not ready to handle it...
785 */
786 _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 0);
787 _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 0);
788 cpu_ppc_store_purr(cpu, 0x0000000000000000ULL);
789 }
790
791 /* Set up (once) timebase frequency (in Hz) */
792 clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
793 {
794 PowerPCCPU *cpu = ppc_env_get_cpu(env);
795 ppc_tb_t *tb_env;
796
797 tb_env = g_malloc0(sizeof(ppc_tb_t));
798 env->tb_env = tb_env;
799 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
800 /* Create new timer */
801 tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &cpu_ppc_decr_cb, cpu);
802 if (0) {
803 /* XXX: find a suitable condition to enable the hypervisor decrementer
804 */
805 tb_env->hdecr_timer = qemu_new_timer_ns(vm_clock, &cpu_ppc_hdecr_cb,
806 cpu);
807 } else {
808 tb_env->hdecr_timer = NULL;
809 }
810 cpu_ppc_set_tb_clk(env, freq);
811
812 return &cpu_ppc_set_tb_clk;
813 }
814
815 /* Specific helpers for POWER & PowerPC 601 RTC */
816 #if 0
817 static clk_setup_cb cpu_ppc601_rtc_init (CPUPPCState *env)
818 {
819 return cpu_ppc_tb_init(env, 7812500);
820 }
821 #endif
822
823 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value)
824 {
825 _cpu_ppc_store_tbu(env, value);
826 }
827
828 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env)
829 {
830 return _cpu_ppc_load_tbu(env);
831 }
832
833 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value)
834 {
835 cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
836 }
837
838 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env)
839 {
840 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
841 }
842
843 /*****************************************************************************/
844 /* PowerPC 40x timers */
845
846 /* PIT, FIT & WDT */
847 typedef struct ppc40x_timer_t ppc40x_timer_t;
848 struct ppc40x_timer_t {
849 uint64_t pit_reload; /* PIT auto-reload value */
850 uint64_t fit_next; /* Tick for next FIT interrupt */
851 struct QEMUTimer *fit_timer;
852 uint64_t wdt_next; /* Tick for next WDT interrupt */
853 struct QEMUTimer *wdt_timer;
854
855 /* 405 have the PIT, 440 have a DECR. */
856 unsigned int decr_excp;
857 };
858
859 /* Fixed interval timer */
860 static void cpu_4xx_fit_cb (void *opaque)
861 {
862 PowerPCCPU *cpu;
863 CPUPPCState *env;
864 ppc_tb_t *tb_env;
865 ppc40x_timer_t *ppc40x_timer;
866 uint64_t now, next;
867
868 env = opaque;
869 cpu = ppc_env_get_cpu(env);
870 tb_env = env->tb_env;
871 ppc40x_timer = tb_env->opaque;
872 now = qemu_get_clock_ns(vm_clock);
873 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
874 case 0:
875 next = 1 << 9;
876 break;
877 case 1:
878 next = 1 << 13;
879 break;
880 case 2:
881 next = 1 << 17;
882 break;
883 case 3:
884 next = 1 << 21;
885 break;
886 default:
887 /* Cannot occur, but makes gcc happy */
888 return;
889 }
890 next = now + muldiv64(next, get_ticks_per_sec(), tb_env->tb_freq);
891 if (next == now)
892 next++;
893 qemu_mod_timer(ppc40x_timer->fit_timer, next);
894 env->spr[SPR_40x_TSR] |= 1 << 26;
895 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) {
896 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1);
897 }
898 LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
899 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
900 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
901 }
902
903 /* Programmable interval timer */
904 static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp)
905 {
906 ppc40x_timer_t *ppc40x_timer;
907 uint64_t now, next;
908
909 ppc40x_timer = tb_env->opaque;
910 if (ppc40x_timer->pit_reload <= 1 ||
911 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
912 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
913 /* Stop PIT */
914 LOG_TB("%s: stop PIT\n", __func__);
915 qemu_del_timer(tb_env->decr_timer);
916 } else {
917 LOG_TB("%s: start PIT %016" PRIx64 "\n",
918 __func__, ppc40x_timer->pit_reload);
919 now = qemu_get_clock_ns(vm_clock);
920 next = now + muldiv64(ppc40x_timer->pit_reload,
921 get_ticks_per_sec(), tb_env->decr_freq);
922 if (is_excp)
923 next += tb_env->decr_next - now;
924 if (next == now)
925 next++;
926 qemu_mod_timer(tb_env->decr_timer, next);
927 tb_env->decr_next = next;
928 }
929 }
930
931 static void cpu_4xx_pit_cb (void *opaque)
932 {
933 PowerPCCPU *cpu;
934 CPUPPCState *env;
935 ppc_tb_t *tb_env;
936 ppc40x_timer_t *ppc40x_timer;
937
938 env = opaque;
939 cpu = ppc_env_get_cpu(env);
940 tb_env = env->tb_env;
941 ppc40x_timer = tb_env->opaque;
942 env->spr[SPR_40x_TSR] |= 1 << 27;
943 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) {
944 ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1);
945 }
946 start_stop_pit(env, tb_env, 1);
947 LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " "
948 "%016" PRIx64 "\n", __func__,
949 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
950 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
951 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
952 ppc40x_timer->pit_reload);
953 }
954
955 /* Watchdog timer */
956 static void cpu_4xx_wdt_cb (void *opaque)
957 {
958 PowerPCCPU *cpu;
959 CPUPPCState *env;
960 ppc_tb_t *tb_env;
961 ppc40x_timer_t *ppc40x_timer;
962 uint64_t now, next;
963
964 env = opaque;
965 cpu = ppc_env_get_cpu(env);
966 tb_env = env->tb_env;
967 ppc40x_timer = tb_env->opaque;
968 now = qemu_get_clock_ns(vm_clock);
969 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
970 case 0:
971 next = 1 << 17;
972 break;
973 case 1:
974 next = 1 << 21;
975 break;
976 case 2:
977 next = 1 << 25;
978 break;
979 case 3:
980 next = 1 << 29;
981 break;
982 default:
983 /* Cannot occur, but makes gcc happy */
984 return;
985 }
986 next = now + muldiv64(next, get_ticks_per_sec(), tb_env->decr_freq);
987 if (next == now)
988 next++;
989 LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
990 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
991 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
992 case 0x0:
993 case 0x1:
994 qemu_mod_timer(ppc40x_timer->wdt_timer, next);
995 ppc40x_timer->wdt_next = next;
996 env->spr[SPR_40x_TSR] |= 1 << 31;
997 break;
998 case 0x2:
999 qemu_mod_timer(ppc40x_timer->wdt_timer, next);
1000 ppc40x_timer->wdt_next = next;
1001 env->spr[SPR_40x_TSR] |= 1 << 30;
1002 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) {
1003 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1);
1004 }
1005 break;
1006 case 0x3:
1007 env->spr[SPR_40x_TSR] &= ~0x30000000;
1008 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
1009 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
1010 case 0x0:
1011 /* No reset */
1012 break;
1013 case 0x1: /* Core reset */
1014 ppc40x_core_reset(cpu);
1015 break;
1016 case 0x2: /* Chip reset */
1017 ppc40x_chip_reset(cpu);
1018 break;
1019 case 0x3: /* System reset */
1020 ppc40x_system_reset(cpu);
1021 break;
1022 }
1023 }
1024 }
1025
1026 void store_40x_pit (CPUPPCState *env, target_ulong val)
1027 {
1028 ppc_tb_t *tb_env;
1029 ppc40x_timer_t *ppc40x_timer;
1030
1031 tb_env = env->tb_env;
1032 ppc40x_timer = tb_env->opaque;
1033 LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val);
1034 ppc40x_timer->pit_reload = val;
1035 start_stop_pit(env, tb_env, 0);
1036 }
1037
1038 target_ulong load_40x_pit (CPUPPCState *env)
1039 {
1040 return cpu_ppc_load_decr(env);
1041 }
1042
1043 static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq)
1044 {
1045 CPUPPCState *env = opaque;
1046 ppc_tb_t *tb_env = env->tb_env;
1047
1048 LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__,
1049 freq);
1050 tb_env->tb_freq = freq;
1051 tb_env->decr_freq = freq;
1052 /* XXX: we should also update all timers */
1053 }
1054
1055 clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
1056 unsigned int decr_excp)
1057 {
1058 ppc_tb_t *tb_env;
1059 ppc40x_timer_t *ppc40x_timer;
1060
1061 tb_env = g_malloc0(sizeof(ppc_tb_t));
1062 env->tb_env = tb_env;
1063 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
1064 ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t));
1065 tb_env->tb_freq = freq;
1066 tb_env->decr_freq = freq;
1067 tb_env->opaque = ppc40x_timer;
1068 LOG_TB("%s freq %" PRIu32 "\n", __func__, freq);
1069 if (ppc40x_timer != NULL) {
1070 /* We use decr timer for PIT */
1071 tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &cpu_4xx_pit_cb, env);
1072 ppc40x_timer->fit_timer =
1073 qemu_new_timer_ns(vm_clock, &cpu_4xx_fit_cb, env);
1074 ppc40x_timer->wdt_timer =
1075 qemu_new_timer_ns(vm_clock, &cpu_4xx_wdt_cb, env);
1076 ppc40x_timer->decr_excp = decr_excp;
1077 }
1078
1079 return &ppc_40x_set_tb_clk;
1080 }
1081
1082 /*****************************************************************************/
1083 /* Embedded PowerPC Device Control Registers */
1084 typedef struct ppc_dcrn_t ppc_dcrn_t;
1085 struct ppc_dcrn_t {
1086 dcr_read_cb dcr_read;
1087 dcr_write_cb dcr_write;
1088 void *opaque;
1089 };
1090
1091 /* XXX: on 460, DCR addresses are 32 bits wide,
1092 * using DCRIPR to get the 22 upper bits of the DCR address
1093 */
1094 #define DCRN_NB 1024
1095 struct ppc_dcr_t {
1096 ppc_dcrn_t dcrn[DCRN_NB];
1097 int (*read_error)(int dcrn);
1098 int (*write_error)(int dcrn);
1099 };
1100
1101 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1102 {
1103 ppc_dcrn_t *dcr;
1104
1105 if (dcrn < 0 || dcrn >= DCRN_NB)
1106 goto error;
1107 dcr = &dcr_env->dcrn[dcrn];
1108 if (dcr->dcr_read == NULL)
1109 goto error;
1110 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
1111
1112 return 0;
1113
1114 error:
1115 if (dcr_env->read_error != NULL)
1116 return (*dcr_env->read_error)(dcrn);
1117
1118 return -1;
1119 }
1120
1121 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1122 {
1123 ppc_dcrn_t *dcr;
1124
1125 if (dcrn < 0 || dcrn >= DCRN_NB)
1126 goto error;
1127 dcr = &dcr_env->dcrn[dcrn];
1128 if (dcr->dcr_write == NULL)
1129 goto error;
1130 (*dcr->dcr_write)(dcr->opaque, dcrn, val);
1131
1132 return 0;
1133
1134 error:
1135 if (dcr_env->write_error != NULL)
1136 return (*dcr_env->write_error)(dcrn);
1137
1138 return -1;
1139 }
1140
1141 int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
1142 dcr_read_cb dcr_read, dcr_write_cb dcr_write)
1143 {
1144 ppc_dcr_t *dcr_env;
1145 ppc_dcrn_t *dcr;
1146
1147 dcr_env = env->dcr_env;
1148 if (dcr_env == NULL)
1149 return -1;
1150 if (dcrn < 0 || dcrn >= DCRN_NB)
1151 return -1;
1152 dcr = &dcr_env->dcrn[dcrn];
1153 if (dcr->opaque != NULL ||
1154 dcr->dcr_read != NULL ||
1155 dcr->dcr_write != NULL)
1156 return -1;
1157 dcr->opaque = opaque;
1158 dcr->dcr_read = dcr_read;
1159 dcr->dcr_write = dcr_write;
1160
1161 return 0;
1162 }
1163
1164 int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn),
1165 int (*write_error)(int dcrn))
1166 {
1167 ppc_dcr_t *dcr_env;
1168
1169 dcr_env = g_malloc0(sizeof(ppc_dcr_t));
1170 dcr_env->read_error = read_error;
1171 dcr_env->write_error = write_error;
1172 env->dcr_env = dcr_env;
1173
1174 return 0;
1175 }
1176
1177 /*****************************************************************************/
1178 /* Debug port */
1179 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
1180 {
1181 addr &= 0xF;
1182 switch (addr) {
1183 case 0:
1184 printf("%c", val);
1185 break;
1186 case 1:
1187 printf("\n");
1188 fflush(stdout);
1189 break;
1190 case 2:
1191 printf("Set loglevel to %04" PRIx32 "\n", val);
1192 qemu_set_log(val | 0x100);
1193 break;
1194 }
1195 }
1196
1197 /*****************************************************************************/
1198 /* NVRAM helpers */
1199 static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr)
1200 {
1201 return (*nvram->read_fn)(nvram->opaque, addr);
1202 }
1203
1204 static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val)
1205 {
1206 (*nvram->write_fn)(nvram->opaque, addr, val);
1207 }
1208
1209 static void NVRAM_set_byte(nvram_t *nvram, uint32_t addr, uint8_t value)
1210 {
1211 nvram_write(nvram, addr, value);
1212 }
1213
1214 static uint8_t NVRAM_get_byte(nvram_t *nvram, uint32_t addr)
1215 {
1216 return nvram_read(nvram, addr);
1217 }
1218
1219 static void NVRAM_set_word(nvram_t *nvram, uint32_t addr, uint16_t value)
1220 {
1221 nvram_write(nvram, addr, value >> 8);
1222 nvram_write(nvram, addr + 1, value & 0xFF);
1223 }
1224
1225 static uint16_t NVRAM_get_word(nvram_t *nvram, uint32_t addr)
1226 {
1227 uint16_t tmp;
1228
1229 tmp = nvram_read(nvram, addr) << 8;
1230 tmp |= nvram_read(nvram, addr + 1);
1231
1232 return tmp;
1233 }
1234
1235 static void NVRAM_set_lword(nvram_t *nvram, uint32_t addr, uint32_t value)
1236 {
1237 nvram_write(nvram, addr, value >> 24);
1238 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
1239 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
1240 nvram_write(nvram, addr + 3, value & 0xFF);
1241 }
1242
1243 uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr)
1244 {
1245 uint32_t tmp;
1246
1247 tmp = nvram_read(nvram, addr) << 24;
1248 tmp |= nvram_read(nvram, addr + 1) << 16;
1249 tmp |= nvram_read(nvram, addr + 2) << 8;
1250 tmp |= nvram_read(nvram, addr + 3);
1251
1252 return tmp;
1253 }
1254
1255 static void NVRAM_set_string(nvram_t *nvram, uint32_t addr, const char *str,
1256 uint32_t max)
1257 {
1258 int i;
1259
1260 for (i = 0; i < max && str[i] != '\0'; i++) {
1261 nvram_write(nvram, addr + i, str[i]);
1262 }
1263 nvram_write(nvram, addr + i, str[i]);
1264 nvram_write(nvram, addr + max - 1, '\0');
1265 }
1266
1267 int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max)
1268 {
1269 int i;
1270
1271 memset(dst, 0, max);
1272 for (i = 0; i < max; i++) {
1273 dst[i] = NVRAM_get_byte(nvram, addr + i);
1274 if (dst[i] == '\0')
1275 break;
1276 }
1277
1278 return i;
1279 }
1280
1281 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
1282 {
1283 uint16_t tmp;
1284 uint16_t pd, pd1, pd2;
1285
1286 tmp = prev >> 8;
1287 pd = prev ^ value;
1288 pd1 = pd & 0x000F;
1289 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
1290 tmp ^= (pd1 << 3) | (pd1 << 8);
1291 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
1292
1293 return tmp;
1294 }
1295
1296 static uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count)
1297 {
1298 uint32_t i;
1299 uint16_t crc = 0xFFFF;
1300 int odd;
1301
1302 odd = count & 1;
1303 count &= ~1;
1304 for (i = 0; i != count; i++) {
1305 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
1306 }
1307 if (odd) {
1308 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
1309 }
1310
1311 return crc;
1312 }
1313
1314 #define CMDLINE_ADDR 0x017ff000
1315
1316 int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
1317 const char *arch,
1318 uint32_t RAM_size, int boot_device,
1319 uint32_t kernel_image, uint32_t kernel_size,
1320 const char *cmdline,
1321 uint32_t initrd_image, uint32_t initrd_size,
1322 uint32_t NVRAM_image,
1323 int width, int height, int depth)
1324 {
1325 uint16_t crc;
1326
1327 /* Set parameters for Open Hack'Ware BIOS */
1328 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
1329 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
1330 NVRAM_set_word(nvram, 0x14, NVRAM_size);
1331 NVRAM_set_string(nvram, 0x20, arch, 16);
1332 NVRAM_set_lword(nvram, 0x30, RAM_size);
1333 NVRAM_set_byte(nvram, 0x34, boot_device);
1334 NVRAM_set_lword(nvram, 0x38, kernel_image);
1335 NVRAM_set_lword(nvram, 0x3C, kernel_size);
1336 if (cmdline) {
1337 /* XXX: put the cmdline in NVRAM too ? */
1338 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, cmdline);
1339 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
1340 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
1341 } else {
1342 NVRAM_set_lword(nvram, 0x40, 0);
1343 NVRAM_set_lword(nvram, 0x44, 0);
1344 }
1345 NVRAM_set_lword(nvram, 0x48, initrd_image);
1346 NVRAM_set_lword(nvram, 0x4C, initrd_size);
1347 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
1348
1349 NVRAM_set_word(nvram, 0x54, width);
1350 NVRAM_set_word(nvram, 0x56, height);
1351 NVRAM_set_word(nvram, 0x58, depth);
1352 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
1353 NVRAM_set_word(nvram, 0xFC, crc);
1354
1355 return 0;
1356 }
AR7 emulation for QEMU