target/arm: Reset btype for direct branches
[qemu/ar7.git] / tests / fdc-test.c
blob88f1abfa10e256e16ad76184921d7dcfa84696cb
1 /*
2 * Floppy test cases.
4 * Copyright (c) 2012 Kevin Wolf <kwolf@redhat.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "qemu/osdep.h"
28 #include "libqtest.h"
29 #include "qapi/qmp/qdict.h"
30 #include "qemu-common.h"
32 /* TODO actually test the results and get rid of this */
33 #define qmp_discard_response(...) qobject_unref(qmp(__VA_ARGS__))
35 #define TEST_IMAGE_SIZE 1440 * 1024
37 #define FLOPPY_BASE 0x3f0
38 #define FLOPPY_IRQ 6
40 enum {
41 reg_sra = 0x0,
42 reg_srb = 0x1,
43 reg_dor = 0x2,
44 reg_msr = 0x4,
45 reg_dsr = 0x4,
46 reg_fifo = 0x5,
47 reg_dir = 0x7,
50 enum {
51 CMD_SENSE_INT = 0x08,
52 CMD_READ_ID = 0x0a,
53 CMD_SEEK = 0x0f,
54 CMD_VERIFY = 0x16,
55 CMD_READ = 0xe6,
56 CMD_RELATIVE_SEEK_OUT = 0x8f,
57 CMD_RELATIVE_SEEK_IN = 0xcf,
60 enum {
61 BUSY = 0x10,
62 NONDMA = 0x20,
63 RQM = 0x80,
64 DIO = 0x40,
66 DSKCHG = 0x80,
69 static char test_image[] = "/tmp/qtest.XXXXXX";
71 #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
72 #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
74 static uint8_t base = 0x70;
76 enum {
77 CMOS_FLOPPY = 0x10,
80 static void floppy_send(uint8_t byte)
82 uint8_t msr;
84 msr = inb(FLOPPY_BASE + reg_msr);
85 assert_bit_set(msr, RQM);
86 assert_bit_clear(msr, DIO);
88 outb(FLOPPY_BASE + reg_fifo, byte);
91 static uint8_t floppy_recv(void)
93 uint8_t msr;
95 msr = inb(FLOPPY_BASE + reg_msr);
96 assert_bit_set(msr, RQM | DIO);
98 return inb(FLOPPY_BASE + reg_fifo);
101 /* pcn: Present Cylinder Number */
102 static void ack_irq(uint8_t *pcn)
104 uint8_t ret;
106 g_assert(get_irq(FLOPPY_IRQ));
107 floppy_send(CMD_SENSE_INT);
108 floppy_recv();
110 ret = floppy_recv();
111 if (pcn != NULL) {
112 *pcn = ret;
115 g_assert(!get_irq(FLOPPY_IRQ));
118 static uint8_t send_read_command(uint8_t cmd)
120 uint8_t drive = 0;
121 uint8_t head = 0;
122 uint8_t cyl = 0;
123 uint8_t sect_addr = 1;
124 uint8_t sect_size = 2;
125 uint8_t eot = 1;
126 uint8_t gap = 0x1b;
127 uint8_t gpl = 0xff;
129 uint8_t msr = 0;
130 uint8_t st0;
132 uint8_t ret = 0;
134 floppy_send(cmd);
135 floppy_send(head << 2 | drive);
136 g_assert(!get_irq(FLOPPY_IRQ));
137 floppy_send(cyl);
138 floppy_send(head);
139 floppy_send(sect_addr);
140 floppy_send(sect_size);
141 floppy_send(eot);
142 floppy_send(gap);
143 floppy_send(gpl);
145 uint8_t i = 0;
146 uint8_t n = 2;
147 for (; i < n; i++) {
148 msr = inb(FLOPPY_BASE + reg_msr);
149 if (msr == 0xd0) {
150 break;
152 sleep(1);
155 if (i >= n) {
156 return 1;
159 st0 = floppy_recv();
160 if (st0 != 0x40) {
161 ret = 1;
164 floppy_recv();
165 floppy_recv();
166 floppy_recv();
167 floppy_recv();
168 floppy_recv();
169 floppy_recv();
171 return ret;
174 static uint8_t send_read_no_dma_command(int nb_sect, uint8_t expected_st0)
176 uint8_t drive = 0;
177 uint8_t head = 0;
178 uint8_t cyl = 0;
179 uint8_t sect_addr = 1;
180 uint8_t sect_size = 2;
181 uint8_t eot = nb_sect;
182 uint8_t gap = 0x1b;
183 uint8_t gpl = 0xff;
185 uint8_t msr = 0;
186 uint8_t st0;
188 uint8_t ret = 0;
190 floppy_send(CMD_READ);
191 floppy_send(head << 2 | drive);
192 g_assert(!get_irq(FLOPPY_IRQ));
193 floppy_send(cyl);
194 floppy_send(head);
195 floppy_send(sect_addr);
196 floppy_send(sect_size);
197 floppy_send(eot);
198 floppy_send(gap);
199 floppy_send(gpl);
201 uint16_t i = 0;
202 uint8_t n = 2;
203 for (; i < n; i++) {
204 msr = inb(FLOPPY_BASE + reg_msr);
205 if (msr == (BUSY | NONDMA | DIO | RQM)) {
206 break;
208 sleep(1);
211 if (i >= n) {
212 return 1;
215 /* Non-DMA mode */
216 for (i = 0; i < 512 * 2 * nb_sect; i++) {
217 msr = inb(FLOPPY_BASE + reg_msr);
218 assert_bit_set(msr, BUSY | RQM | DIO);
219 inb(FLOPPY_BASE + reg_fifo);
222 msr = inb(FLOPPY_BASE + reg_msr);
223 assert_bit_set(msr, BUSY | RQM | DIO);
224 g_assert(get_irq(FLOPPY_IRQ));
226 st0 = floppy_recv();
227 if (st0 != expected_st0) {
228 ret = 1;
231 floppy_recv();
232 floppy_recv();
233 floppy_recv();
234 floppy_recv();
235 floppy_recv();
236 g_assert(get_irq(FLOPPY_IRQ));
237 floppy_recv();
239 /* Check that we're back in command phase */
240 msr = inb(FLOPPY_BASE + reg_msr);
241 assert_bit_clear(msr, BUSY | DIO);
242 assert_bit_set(msr, RQM);
243 g_assert(!get_irq(FLOPPY_IRQ));
245 return ret;
248 static void send_seek(int cyl)
250 int drive = 0;
251 int head = 0;
253 floppy_send(CMD_SEEK);
254 floppy_send(head << 2 | drive);
255 g_assert(!get_irq(FLOPPY_IRQ));
256 floppy_send(cyl);
257 ack_irq(NULL);
260 static uint8_t cmos_read(uint8_t reg)
262 outb(base + 0, reg);
263 return inb(base + 1);
266 static void test_cmos(void)
268 uint8_t cmos;
270 cmos = cmos_read(CMOS_FLOPPY);
271 g_assert(cmos == 0x40 || cmos == 0x50);
274 static void test_no_media_on_start(void)
276 uint8_t dir;
278 /* Media changed bit must be set all time after start if there is
279 * no media in drive. */
280 dir = inb(FLOPPY_BASE + reg_dir);
281 assert_bit_set(dir, DSKCHG);
282 dir = inb(FLOPPY_BASE + reg_dir);
283 assert_bit_set(dir, DSKCHG);
284 send_seek(1);
285 dir = inb(FLOPPY_BASE + reg_dir);
286 assert_bit_set(dir, DSKCHG);
287 dir = inb(FLOPPY_BASE + reg_dir);
288 assert_bit_set(dir, DSKCHG);
291 static void test_read_without_media(void)
293 uint8_t ret;
295 ret = send_read_command(CMD_READ);
296 g_assert(ret == 0);
299 static void test_media_insert(void)
301 uint8_t dir;
303 /* Insert media in drive. DSKCHK should not be reset until a step pulse
304 * is sent. */
305 qmp_discard_response("{'execute':'blockdev-change-medium', 'arguments':{"
306 " 'id':'floppy0', 'filename': %s, 'format': 'raw' }}",
307 test_image);
309 dir = inb(FLOPPY_BASE + reg_dir);
310 assert_bit_set(dir, DSKCHG);
311 dir = inb(FLOPPY_BASE + reg_dir);
312 assert_bit_set(dir, DSKCHG);
314 send_seek(0);
315 dir = inb(FLOPPY_BASE + reg_dir);
316 assert_bit_set(dir, DSKCHG);
317 dir = inb(FLOPPY_BASE + reg_dir);
318 assert_bit_set(dir, DSKCHG);
320 /* Step to next track should clear DSKCHG bit. */
321 send_seek(1);
322 dir = inb(FLOPPY_BASE + reg_dir);
323 assert_bit_clear(dir, DSKCHG);
324 dir = inb(FLOPPY_BASE + reg_dir);
325 assert_bit_clear(dir, DSKCHG);
328 static void test_media_change(void)
330 uint8_t dir;
332 test_media_insert();
334 /* Eject the floppy and check that DSKCHG is set. Reading it out doesn't
335 * reset the bit. */
336 qmp_discard_response("{'execute':'eject', 'arguments':{"
337 " 'id':'floppy0' }}");
339 dir = inb(FLOPPY_BASE + reg_dir);
340 assert_bit_set(dir, DSKCHG);
341 dir = inb(FLOPPY_BASE + reg_dir);
342 assert_bit_set(dir, DSKCHG);
344 send_seek(0);
345 dir = inb(FLOPPY_BASE + reg_dir);
346 assert_bit_set(dir, DSKCHG);
347 dir = inb(FLOPPY_BASE + reg_dir);
348 assert_bit_set(dir, DSKCHG);
350 send_seek(1);
351 dir = inb(FLOPPY_BASE + reg_dir);
352 assert_bit_set(dir, DSKCHG);
353 dir = inb(FLOPPY_BASE + reg_dir);
354 assert_bit_set(dir, DSKCHG);
357 static void test_sense_interrupt(void)
359 int drive = 0;
360 int head = 0;
361 int cyl = 0;
362 int ret = 0;
364 floppy_send(CMD_SENSE_INT);
365 ret = floppy_recv();
366 g_assert(ret == 0x80);
368 floppy_send(CMD_SEEK);
369 floppy_send(head << 2 | drive);
370 g_assert(!get_irq(FLOPPY_IRQ));
371 floppy_send(cyl);
373 floppy_send(CMD_SENSE_INT);
374 ret = floppy_recv();
375 g_assert(ret == 0x20);
376 floppy_recv();
379 static void test_relative_seek(void)
381 uint8_t drive = 0;
382 uint8_t head = 0;
383 uint8_t cyl = 1;
384 uint8_t pcn;
386 /* Send seek to track 0 */
387 send_seek(0);
389 /* Send relative seek to increase track by 1 */
390 floppy_send(CMD_RELATIVE_SEEK_IN);
391 floppy_send(head << 2 | drive);
392 g_assert(!get_irq(FLOPPY_IRQ));
393 floppy_send(cyl);
395 ack_irq(&pcn);
396 g_assert(pcn == 1);
398 /* Send relative seek to decrease track by 1 */
399 floppy_send(CMD_RELATIVE_SEEK_OUT);
400 floppy_send(head << 2 | drive);
401 g_assert(!get_irq(FLOPPY_IRQ));
402 floppy_send(cyl);
404 ack_irq(&pcn);
405 g_assert(pcn == 0);
408 static void test_read_id(void)
410 uint8_t drive = 0;
411 uint8_t head = 0;
412 uint8_t cyl;
413 uint8_t st0;
414 uint8_t msr;
416 /* Seek to track 0 and check with READ ID */
417 send_seek(0);
419 floppy_send(CMD_READ_ID);
420 g_assert(!get_irq(FLOPPY_IRQ));
421 floppy_send(head << 2 | drive);
423 msr = inb(FLOPPY_BASE + reg_msr);
424 if (!get_irq(FLOPPY_IRQ)) {
425 assert_bit_set(msr, BUSY);
426 assert_bit_clear(msr, RQM);
429 while (!get_irq(FLOPPY_IRQ)) {
430 /* qemu involves a timer with READ ID... */
431 clock_step(1000000000LL / 50);
434 msr = inb(FLOPPY_BASE + reg_msr);
435 assert_bit_set(msr, BUSY | RQM | DIO);
437 st0 = floppy_recv();
438 floppy_recv();
439 floppy_recv();
440 cyl = floppy_recv();
441 head = floppy_recv();
442 floppy_recv();
443 g_assert(get_irq(FLOPPY_IRQ));
444 floppy_recv();
445 g_assert(!get_irq(FLOPPY_IRQ));
447 g_assert_cmpint(cyl, ==, 0);
448 g_assert_cmpint(head, ==, 0);
449 g_assert_cmpint(st0, ==, head << 2);
451 /* Seek to track 8 on head 1 and check with READ ID */
452 head = 1;
453 cyl = 8;
455 floppy_send(CMD_SEEK);
456 floppy_send(head << 2 | drive);
457 g_assert(!get_irq(FLOPPY_IRQ));
458 floppy_send(cyl);
459 g_assert(get_irq(FLOPPY_IRQ));
460 ack_irq(NULL);
462 floppy_send(CMD_READ_ID);
463 g_assert(!get_irq(FLOPPY_IRQ));
464 floppy_send(head << 2 | drive);
466 msr = inb(FLOPPY_BASE + reg_msr);
467 if (!get_irq(FLOPPY_IRQ)) {
468 assert_bit_set(msr, BUSY);
469 assert_bit_clear(msr, RQM);
472 while (!get_irq(FLOPPY_IRQ)) {
473 /* qemu involves a timer with READ ID... */
474 clock_step(1000000000LL / 50);
477 msr = inb(FLOPPY_BASE + reg_msr);
478 assert_bit_set(msr, BUSY | RQM | DIO);
480 st0 = floppy_recv();
481 floppy_recv();
482 floppy_recv();
483 cyl = floppy_recv();
484 head = floppy_recv();
485 floppy_recv();
486 g_assert(get_irq(FLOPPY_IRQ));
487 floppy_recv();
488 g_assert(!get_irq(FLOPPY_IRQ));
490 g_assert_cmpint(cyl, ==, 8);
491 g_assert_cmpint(head, ==, 1);
492 g_assert_cmpint(st0, ==, head << 2);
495 static void test_read_no_dma_1(void)
497 uint8_t ret;
499 outb(FLOPPY_BASE + reg_dor, inb(FLOPPY_BASE + reg_dor) & ~0x08);
500 send_seek(0);
501 ret = send_read_no_dma_command(1, 0x04);
502 g_assert(ret == 0);
505 static void test_read_no_dma_18(void)
507 uint8_t ret;
509 outb(FLOPPY_BASE + reg_dor, inb(FLOPPY_BASE + reg_dor) & ~0x08);
510 send_seek(0);
511 ret = send_read_no_dma_command(18, 0x04);
512 g_assert(ret == 0);
515 static void test_read_no_dma_19(void)
517 uint8_t ret;
519 outb(FLOPPY_BASE + reg_dor, inb(FLOPPY_BASE + reg_dor) & ~0x08);
520 send_seek(0);
521 ret = send_read_no_dma_command(19, 0x20);
522 g_assert(ret == 0);
525 static void test_verify(void)
527 uint8_t ret;
529 ret = send_read_command(CMD_VERIFY);
530 g_assert(ret == 0);
533 /* success if no crash or abort */
534 static void fuzz_registers(void)
536 unsigned int i;
538 for (i = 0; i < 1000; i++) {
539 uint8_t reg, val;
541 reg = (uint8_t)g_test_rand_int_range(0, 8);
542 val = (uint8_t)g_test_rand_int_range(0, 256);
544 outb(FLOPPY_BASE + reg, val);
545 inb(FLOPPY_BASE + reg);
549 int main(int argc, char **argv)
551 const char *arch = qtest_get_arch();
552 int fd;
553 int ret;
555 /* Check architecture */
556 if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
557 g_test_message("Skipping test for non-x86\n");
558 return 0;
561 /* Create a temporary raw image */
562 fd = mkstemp(test_image);
563 g_assert(fd >= 0);
564 ret = ftruncate(fd, TEST_IMAGE_SIZE);
565 g_assert(ret == 0);
566 close(fd);
568 /* Run the tests */
569 g_test_init(&argc, &argv, NULL);
571 qtest_start("-device floppy,id=floppy0");
572 qtest_irq_intercept_in(global_qtest, "ioapic");
573 qtest_add_func("/fdc/cmos", test_cmos);
574 qtest_add_func("/fdc/no_media_on_start", test_no_media_on_start);
575 qtest_add_func("/fdc/read_without_media", test_read_without_media);
576 qtest_add_func("/fdc/media_change", test_media_change);
577 qtest_add_func("/fdc/sense_interrupt", test_sense_interrupt);
578 qtest_add_func("/fdc/relative_seek", test_relative_seek);
579 qtest_add_func("/fdc/read_id", test_read_id);
580 qtest_add_func("/fdc/verify", test_verify);
581 qtest_add_func("/fdc/media_insert", test_media_insert);
582 qtest_add_func("/fdc/read_no_dma_1", test_read_no_dma_1);
583 qtest_add_func("/fdc/read_no_dma_18", test_read_no_dma_18);
584 qtest_add_func("/fdc/read_no_dma_19", test_read_no_dma_19);
585 qtest_add_func("/fdc/fuzz-registers", fuzz_registers);
587 ret = g_test_run();
589 /* Cleanup */
590 qtest_end();
591 unlink(test_image);
593 return ret;