spapr: Improved placement of PCI host bridges in guest memory map
[qemu/ar7.git] / target-mips / op_helper.c
blob7af4c2f08473d6f5e1f69cd514605030dcba952e
1 /*
2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "qemu/host-utils.h"
22 #include "exec/helper-proto.h"
23 #include "exec/exec-all.h"
24 #include "exec/cpu_ldst.h"
25 #include "sysemu/kvm.h"
27 /*****************************************************************************/
28 /* Exceptions processing helpers */
30 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
31 int error_code)
33 do_raise_exception_err(env, exception, error_code, 0);
36 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
38 do_raise_exception(env, exception, GETPC());
41 void helper_raise_exception_debug(CPUMIPSState *env)
43 do_raise_exception(env, EXCP_DEBUG, 0);
46 static void raise_exception(CPUMIPSState *env, uint32_t exception)
48 do_raise_exception(env, exception, 0);
51 #if defined(CONFIG_USER_ONLY)
52 #define HELPER_LD(name, insn, type) \
53 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
54 int mem_idx, uintptr_t retaddr) \
55 { \
56 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
58 #else
59 #define HELPER_LD(name, insn, type) \
60 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
61 int mem_idx, uintptr_t retaddr) \
62 { \
63 switch (mem_idx) \
64 { \
65 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
66 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
67 default: \
68 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
69 } \
71 #endif
72 HELPER_LD(lw, ldl, int32_t)
73 #if defined(TARGET_MIPS64)
74 HELPER_LD(ld, ldq, int64_t)
75 #endif
76 #undef HELPER_LD
78 #if defined(CONFIG_USER_ONLY)
79 #define HELPER_ST(name, insn, type) \
80 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
81 type val, int mem_idx, uintptr_t retaddr) \
82 { \
83 cpu_##insn##_data_ra(env, addr, val, retaddr); \
85 #else
86 #define HELPER_ST(name, insn, type) \
87 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
88 type val, int mem_idx, uintptr_t retaddr) \
89 { \
90 switch (mem_idx) \
91 { \
92 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
93 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
94 default: \
95 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
96 } \
98 #endif
99 HELPER_ST(sb, stb, uint8_t)
100 HELPER_ST(sw, stl, uint32_t)
101 #if defined(TARGET_MIPS64)
102 HELPER_ST(sd, stq, uint64_t)
103 #endif
104 #undef HELPER_ST
106 target_ulong helper_clo (target_ulong arg1)
108 return clo32(arg1);
111 target_ulong helper_clz (target_ulong arg1)
113 return clz32(arg1);
116 #if defined(TARGET_MIPS64)
117 target_ulong helper_dclo (target_ulong arg1)
119 return clo64(arg1);
122 target_ulong helper_dclz (target_ulong arg1)
124 return clz64(arg1);
126 #endif /* TARGET_MIPS64 */
128 /* 64 bits arithmetic for 32 bits hosts */
129 static inline uint64_t get_HILO(CPUMIPSState *env)
131 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
134 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
136 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
137 return env->active_tc.HI[0] = (int32_t)(HILO >> 32);
140 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
142 target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
143 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
144 return tmp;
147 /* Multiplication variants of the vr54xx. */
148 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
149 target_ulong arg2)
151 return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
152 (int64_t)(int32_t)arg2));
155 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
156 target_ulong arg2)
158 return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
159 (uint64_t)(uint32_t)arg2);
162 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
163 target_ulong arg2)
165 return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
166 (int64_t)(int32_t)arg2);
169 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
170 target_ulong arg2)
172 return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
173 (int64_t)(int32_t)arg2);
176 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
177 target_ulong arg2)
179 return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
180 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
183 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
184 target_ulong arg2)
186 return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
187 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
190 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
191 target_ulong arg2)
193 return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
194 (int64_t)(int32_t)arg2);
197 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
198 target_ulong arg2)
200 return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
201 (int64_t)(int32_t)arg2);
204 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
205 target_ulong arg2)
207 return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
208 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
211 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
212 target_ulong arg2)
214 return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
215 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
218 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
219 target_ulong arg2)
221 return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
224 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
225 target_ulong arg2)
227 return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
228 (uint64_t)(uint32_t)arg2);
231 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
232 target_ulong arg2)
234 return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
235 (int64_t)(int32_t)arg2);
238 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
239 target_ulong arg2)
241 return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
242 (uint64_t)(uint32_t)arg2);
245 static inline target_ulong bitswap(target_ulong v)
247 v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
248 ((v & (target_ulong)0x5555555555555555ULL) << 1);
249 v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
250 ((v & (target_ulong)0x3333333333333333ULL) << 2);
251 v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
252 ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
253 return v;
256 #ifdef TARGET_MIPS64
257 target_ulong helper_dbitswap(target_ulong rt)
259 return bitswap(rt);
261 #endif
263 target_ulong helper_bitswap(target_ulong rt)
265 return (int32_t)bitswap(rt);
268 #ifndef CONFIG_USER_ONLY
270 static inline hwaddr do_translate_address(CPUMIPSState *env,
271 target_ulong address,
272 int rw, uintptr_t retaddr)
274 hwaddr lladdr;
275 CPUState *cs = CPU(mips_env_get_cpu(env));
277 lladdr = cpu_mips_translate_address(env, address, rw);
279 if (lladdr == -1LL) {
280 cpu_loop_exit_restore(cs, retaddr);
281 } else {
282 return lladdr;
286 #define HELPER_LD_ATOMIC(name, insn, almask) \
287 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
289 if (arg & almask) { \
290 env->CP0_BadVAddr = arg; \
291 do_raise_exception(env, EXCP_AdEL, GETPC()); \
293 env->lladdr = do_translate_address(env, arg, 0, GETPC()); \
294 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
295 return env->llval; \
297 HELPER_LD_ATOMIC(ll, lw, 0x3)
298 #ifdef TARGET_MIPS64
299 HELPER_LD_ATOMIC(lld, ld, 0x7)
300 #endif
301 #undef HELPER_LD_ATOMIC
303 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
304 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
305 target_ulong arg2, int mem_idx) \
307 target_long tmp; \
309 if (arg2 & almask) { \
310 env->CP0_BadVAddr = arg2; \
311 do_raise_exception(env, EXCP_AdES, GETPC()); \
313 if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) { \
314 tmp = do_##ld_insn(env, arg2, mem_idx, GETPC()); \
315 if (tmp == env->llval) { \
316 do_##st_insn(env, arg2, arg1, mem_idx, GETPC()); \
317 return 1; \
320 return 0; \
322 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
323 #ifdef TARGET_MIPS64
324 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
325 #endif
326 #undef HELPER_ST_ATOMIC
327 #endif
329 #ifdef TARGET_WORDS_BIGENDIAN
330 #define GET_LMASK(v) ((v) & 3)
331 #define GET_OFFSET(addr, offset) (addr + (offset))
332 #else
333 #define GET_LMASK(v) (((v) & 3) ^ 3)
334 #define GET_OFFSET(addr, offset) (addr - (offset))
335 #endif
337 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
338 int mem_idx)
340 do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
342 if (GET_LMASK(arg2) <= 2) {
343 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx,
344 GETPC());
347 if (GET_LMASK(arg2) <= 1) {
348 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx,
349 GETPC());
352 if (GET_LMASK(arg2) == 0) {
353 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx,
354 GETPC());
358 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
359 int mem_idx)
361 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
363 if (GET_LMASK(arg2) >= 1) {
364 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
365 GETPC());
368 if (GET_LMASK(arg2) >= 2) {
369 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
370 GETPC());
373 if (GET_LMASK(arg2) == 3) {
374 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
375 GETPC());
379 #if defined(TARGET_MIPS64)
380 /* "half" load and stores. We must do the memory access inline,
381 or fault handling won't work. */
383 #ifdef TARGET_WORDS_BIGENDIAN
384 #define GET_LMASK64(v) ((v) & 7)
385 #else
386 #define GET_LMASK64(v) (((v) & 7) ^ 7)
387 #endif
389 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
390 int mem_idx)
392 do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
394 if (GET_LMASK64(arg2) <= 6) {
395 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx,
396 GETPC());
399 if (GET_LMASK64(arg2) <= 5) {
400 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx,
401 GETPC());
404 if (GET_LMASK64(arg2) <= 4) {
405 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx,
406 GETPC());
409 if (GET_LMASK64(arg2) <= 3) {
410 do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx,
411 GETPC());
414 if (GET_LMASK64(arg2) <= 2) {
415 do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx,
416 GETPC());
419 if (GET_LMASK64(arg2) <= 1) {
420 do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx,
421 GETPC());
424 if (GET_LMASK64(arg2) <= 0) {
425 do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx,
426 GETPC());
430 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
431 int mem_idx)
433 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
435 if (GET_LMASK64(arg2) >= 1) {
436 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
437 GETPC());
440 if (GET_LMASK64(arg2) >= 2) {
441 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
442 GETPC());
445 if (GET_LMASK64(arg2) >= 3) {
446 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
447 GETPC());
450 if (GET_LMASK64(arg2) >= 4) {
451 do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx,
452 GETPC());
455 if (GET_LMASK64(arg2) >= 5) {
456 do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx,
457 GETPC());
460 if (GET_LMASK64(arg2) >= 6) {
461 do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx,
462 GETPC());
465 if (GET_LMASK64(arg2) == 7) {
466 do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx,
467 GETPC());
470 #endif /* TARGET_MIPS64 */
472 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
474 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
475 uint32_t mem_idx)
477 target_ulong base_reglist = reglist & 0xf;
478 target_ulong do_r31 = reglist & 0x10;
480 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
481 target_ulong i;
483 for (i = 0; i < base_reglist; i++) {
484 env->active_tc.gpr[multiple_regs[i]] =
485 (target_long)do_lw(env, addr, mem_idx, GETPC());
486 addr += 4;
490 if (do_r31) {
491 env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx,
492 GETPC());
496 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
497 uint32_t mem_idx)
499 target_ulong base_reglist = reglist & 0xf;
500 target_ulong do_r31 = reglist & 0x10;
502 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
503 target_ulong i;
505 for (i = 0; i < base_reglist; i++) {
506 do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
507 GETPC());
508 addr += 4;
512 if (do_r31) {
513 do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
517 #if defined(TARGET_MIPS64)
518 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
519 uint32_t mem_idx)
521 target_ulong base_reglist = reglist & 0xf;
522 target_ulong do_r31 = reglist & 0x10;
524 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
525 target_ulong i;
527 for (i = 0; i < base_reglist; i++) {
528 env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx,
529 GETPC());
530 addr += 8;
534 if (do_r31) {
535 env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC());
539 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
540 uint32_t mem_idx)
542 target_ulong base_reglist = reglist & 0xf;
543 target_ulong do_r31 = reglist & 0x10;
545 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
546 target_ulong i;
548 for (i = 0; i < base_reglist; i++) {
549 do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
550 GETPC());
551 addr += 8;
555 if (do_r31) {
556 do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
559 #endif
561 #ifndef CONFIG_USER_ONLY
562 /* SMP helpers. */
563 static bool mips_vpe_is_wfi(MIPSCPU *c)
565 CPUState *cpu = CPU(c);
566 CPUMIPSState *env = &c->env;
568 /* If the VPE is halted but otherwise active, it means it's waiting for
569 an interrupt. */
570 return cpu->halted && mips_vpe_active(env);
573 static bool mips_vp_is_wfi(MIPSCPU *c)
575 CPUState *cpu = CPU(c);
576 CPUMIPSState *env = &c->env;
578 return cpu->halted && mips_vp_active(env);
581 static inline void mips_vpe_wake(MIPSCPU *c)
583 /* Don't set ->halted = 0 directly, let it be done via cpu_has_work
584 because there might be other conditions that state that c should
585 be sleeping. */
586 cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
589 static inline void mips_vpe_sleep(MIPSCPU *cpu)
591 CPUState *cs = CPU(cpu);
593 /* The VPE was shut off, really go to bed.
594 Reset any old _WAKE requests. */
595 cs->halted = 1;
596 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
599 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
601 CPUMIPSState *c = &cpu->env;
603 /* FIXME: TC reschedule. */
604 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
605 mips_vpe_wake(cpu);
609 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
611 CPUMIPSState *c = &cpu->env;
613 /* FIXME: TC reschedule. */
614 if (!mips_vpe_active(c)) {
615 mips_vpe_sleep(cpu);
620 * mips_cpu_map_tc:
621 * @env: CPU from which mapping is performed.
622 * @tc: Should point to an int with the value of the global TC index.
624 * This function will transform @tc into a local index within the
625 * returned #CPUMIPSState.
627 /* FIXME: This code assumes that all VPEs have the same number of TCs,
628 which depends on runtime setup. Can probably be fixed by
629 walking the list of CPUMIPSStates. */
630 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
632 MIPSCPU *cpu;
633 CPUState *cs;
634 CPUState *other_cs;
635 int vpe_idx;
636 int tc_idx = *tc;
638 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
639 /* Not allowed to address other CPUs. */
640 *tc = env->current_tc;
641 return env;
644 cs = CPU(mips_env_get_cpu(env));
645 vpe_idx = tc_idx / cs->nr_threads;
646 *tc = tc_idx % cs->nr_threads;
647 other_cs = qemu_get_cpu(vpe_idx);
648 if (other_cs == NULL) {
649 return env;
651 cpu = MIPS_CPU(other_cs);
652 return &cpu->env;
655 /* The per VPE CP0_Status register shares some fields with the per TC
656 CP0_TCStatus registers. These fields are wired to the same registers,
657 so changes to either of them should be reflected on both registers.
659 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
661 These helper call synchronizes the regs for a given cpu. */
663 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
664 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
665 int tc); */
667 /* Called for updates to CP0_TCStatus. */
668 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
669 target_ulong v)
671 uint32_t status;
672 uint32_t tcu, tmx, tasid, tksu;
673 uint32_t mask = ((1U << CP0St_CU3)
674 | (1 << CP0St_CU2)
675 | (1 << CP0St_CU1)
676 | (1 << CP0St_CU0)
677 | (1 << CP0St_MX)
678 | (3 << CP0St_KSU));
680 tcu = (v >> CP0TCSt_TCU0) & 0xf;
681 tmx = (v >> CP0TCSt_TMX) & 0x1;
682 tasid = v & cpu->CP0_EntryHi_ASID_mask;
683 tksu = (v >> CP0TCSt_TKSU) & 0x3;
685 status = tcu << CP0St_CU0;
686 status |= tmx << CP0St_MX;
687 status |= tksu << CP0St_KSU;
689 cpu->CP0_Status &= ~mask;
690 cpu->CP0_Status |= status;
692 /* Sync the TASID with EntryHi. */
693 cpu->CP0_EntryHi &= ~cpu->CP0_EntryHi_ASID_mask;
694 cpu->CP0_EntryHi |= tasid;
696 compute_hflags(cpu);
699 /* Called for updates to CP0_EntryHi. */
700 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
702 int32_t *tcst;
703 uint32_t asid, v = cpu->CP0_EntryHi;
705 asid = v & cpu->CP0_EntryHi_ASID_mask;
707 if (tc == cpu->current_tc) {
708 tcst = &cpu->active_tc.CP0_TCStatus;
709 } else {
710 tcst = &cpu->tcs[tc].CP0_TCStatus;
713 *tcst &= ~cpu->CP0_EntryHi_ASID_mask;
714 *tcst |= asid;
717 /* CP0 helpers */
718 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
720 return env->mvp->CP0_MVPControl;
723 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
725 return env->mvp->CP0_MVPConf0;
728 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
730 return env->mvp->CP0_MVPConf1;
733 target_ulong helper_mfc0_random(CPUMIPSState *env)
735 return (int32_t)cpu_mips_get_random(env);
738 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
740 return env->active_tc.CP0_TCStatus;
743 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
745 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
746 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
748 if (other_tc == other->current_tc)
749 return other->active_tc.CP0_TCStatus;
750 else
751 return other->tcs[other_tc].CP0_TCStatus;
754 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
756 return env->active_tc.CP0_TCBind;
759 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
761 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
762 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
764 if (other_tc == other->current_tc)
765 return other->active_tc.CP0_TCBind;
766 else
767 return other->tcs[other_tc].CP0_TCBind;
770 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
772 return env->active_tc.PC;
775 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
777 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
778 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
780 if (other_tc == other->current_tc)
781 return other->active_tc.PC;
782 else
783 return other->tcs[other_tc].PC;
786 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
788 return env->active_tc.CP0_TCHalt;
791 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
793 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
794 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
796 if (other_tc == other->current_tc)
797 return other->active_tc.CP0_TCHalt;
798 else
799 return other->tcs[other_tc].CP0_TCHalt;
802 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
804 return env->active_tc.CP0_TCContext;
807 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
809 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
810 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
812 if (other_tc == other->current_tc)
813 return other->active_tc.CP0_TCContext;
814 else
815 return other->tcs[other_tc].CP0_TCContext;
818 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
820 return env->active_tc.CP0_TCSchedule;
823 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
825 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
826 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
828 if (other_tc == other->current_tc)
829 return other->active_tc.CP0_TCSchedule;
830 else
831 return other->tcs[other_tc].CP0_TCSchedule;
834 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
836 return env->active_tc.CP0_TCScheFBack;
839 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
841 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
842 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
844 if (other_tc == other->current_tc)
845 return other->active_tc.CP0_TCScheFBack;
846 else
847 return other->tcs[other_tc].CP0_TCScheFBack;
850 target_ulong helper_mfc0_count(CPUMIPSState *env)
852 return (int32_t)cpu_mips_get_count(env);
855 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
857 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
858 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
860 return other->CP0_EntryHi;
863 target_ulong helper_mftc0_cause(CPUMIPSState *env)
865 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
866 int32_t tccause;
867 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
869 if (other_tc == other->current_tc) {
870 tccause = other->CP0_Cause;
871 } else {
872 tccause = other->CP0_Cause;
875 return tccause;
878 target_ulong helper_mftc0_status(CPUMIPSState *env)
880 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
881 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
883 return other->CP0_Status;
886 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
888 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
891 target_ulong helper_mfc0_maar(CPUMIPSState *env)
893 return (int32_t) env->CP0_MAAR[env->CP0_MAARI];
896 target_ulong helper_mfhc0_maar(CPUMIPSState *env)
898 return env->CP0_MAAR[env->CP0_MAARI] >> 32;
901 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
903 return (int32_t)env->CP0_WatchLo[sel];
906 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
908 return env->CP0_WatchHi[sel];
911 target_ulong helper_mfc0_debug(CPUMIPSState *env)
913 target_ulong t0 = env->CP0_Debug;
914 if (env->hflags & MIPS_HFLAG_DM)
915 t0 |= 1 << CP0DB_DM;
917 return t0;
920 target_ulong helper_mftc0_debug(CPUMIPSState *env)
922 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
923 int32_t tcstatus;
924 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
926 if (other_tc == other->current_tc)
927 tcstatus = other->active_tc.CP0_Debug_tcstatus;
928 else
929 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
931 /* XXX: Might be wrong, check with EJTAG spec. */
932 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
933 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
936 #if defined(TARGET_MIPS64)
937 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
939 return env->active_tc.PC;
942 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
944 return env->active_tc.CP0_TCHalt;
947 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
949 return env->active_tc.CP0_TCContext;
952 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
954 return env->active_tc.CP0_TCSchedule;
957 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
959 return env->active_tc.CP0_TCScheFBack;
962 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
964 return env->lladdr >> env->CP0_LLAddr_shift;
967 target_ulong helper_dmfc0_maar(CPUMIPSState *env)
969 return env->CP0_MAAR[env->CP0_MAARI];
972 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
974 return env->CP0_WatchLo[sel];
976 #endif /* TARGET_MIPS64 */
978 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
980 uint32_t index_p = env->CP0_Index & 0x80000000;
981 uint32_t tlb_index = arg1 & 0x7fffffff;
982 if (tlb_index < env->tlb->nb_tlb) {
983 if (env->insn_flags & ISA_MIPS32R6) {
984 index_p |= arg1 & 0x80000000;
986 env->CP0_Index = index_p | tlb_index;
990 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
992 uint32_t mask = 0;
993 uint32_t newval;
995 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
996 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
997 (1 << CP0MVPCo_EVP);
998 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
999 mask |= (1 << CP0MVPCo_STLB);
1000 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
1002 // TODO: Enable/disable shared TLB, enable/disable VPEs.
1004 env->mvp->CP0_MVPControl = newval;
1007 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1009 uint32_t mask;
1010 uint32_t newval;
1012 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1013 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1014 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
1016 /* Yield scheduler intercept not implemented. */
1017 /* Gating storage scheduler intercept not implemented. */
1019 // TODO: Enable/disable TCs.
1021 env->CP0_VPEControl = newval;
1024 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1026 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1027 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1028 uint32_t mask;
1029 uint32_t newval;
1031 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1032 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1033 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1035 /* TODO: Enable/disable TCs. */
1037 other->CP0_VPEControl = newval;
1040 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1042 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1043 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1044 /* FIXME: Mask away return zero on read bits. */
1045 return other->CP0_VPEControl;
1048 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1050 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1051 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1053 return other->CP0_VPEConf0;
1056 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1058 uint32_t mask = 0;
1059 uint32_t newval;
1061 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1062 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1063 mask |= (0xff << CP0VPEC0_XTC);
1064 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1066 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1068 // TODO: TC exclusive handling due to ERL/EXL.
1070 env->CP0_VPEConf0 = newval;
1073 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1075 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1076 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1077 uint32_t mask = 0;
1078 uint32_t newval;
1080 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1081 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1083 /* TODO: TC exclusive handling due to ERL/EXL. */
1084 other->CP0_VPEConf0 = newval;
1087 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1089 uint32_t mask = 0;
1090 uint32_t newval;
1092 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1093 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1094 (0xff << CP0VPEC1_NCP1);
1095 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1097 /* UDI not implemented. */
1098 /* CP2 not implemented. */
1100 // TODO: Handle FPU (CP1) binding.
1102 env->CP0_VPEConf1 = newval;
1105 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1107 /* Yield qualifier inputs not implemented. */
1108 env->CP0_YQMask = 0x00000000;
1111 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1113 env->CP0_VPEOpt = arg1 & 0x0000ffff;
1116 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1118 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1120 /* 1k pages not implemented */
1121 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1122 env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1123 | (rxi << (CP0EnLo_XI - 30));
1126 #if defined(TARGET_MIPS64)
1127 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1129 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1131 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1132 env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1134 #endif
1136 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1138 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1139 uint32_t newval;
1141 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1143 env->active_tc.CP0_TCStatus = newval;
1144 sync_c0_tcstatus(env, env->current_tc, newval);
1147 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1149 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1150 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1152 if (other_tc == other->current_tc)
1153 other->active_tc.CP0_TCStatus = arg1;
1154 else
1155 other->tcs[other_tc].CP0_TCStatus = arg1;
1156 sync_c0_tcstatus(other, other_tc, arg1);
1159 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1161 uint32_t mask = (1 << CP0TCBd_TBE);
1162 uint32_t newval;
1164 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1165 mask |= (1 << CP0TCBd_CurVPE);
1166 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1167 env->active_tc.CP0_TCBind = newval;
1170 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1172 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1173 uint32_t mask = (1 << CP0TCBd_TBE);
1174 uint32_t newval;
1175 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1177 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1178 mask |= (1 << CP0TCBd_CurVPE);
1179 if (other_tc == other->current_tc) {
1180 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1181 other->active_tc.CP0_TCBind = newval;
1182 } else {
1183 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1184 other->tcs[other_tc].CP0_TCBind = newval;
1188 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1190 env->active_tc.PC = arg1;
1191 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1192 env->lladdr = 0ULL;
1193 /* MIPS16 not implemented. */
1196 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1198 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1199 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1201 if (other_tc == other->current_tc) {
1202 other->active_tc.PC = arg1;
1203 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1204 other->lladdr = 0ULL;
1205 /* MIPS16 not implemented. */
1206 } else {
1207 other->tcs[other_tc].PC = arg1;
1208 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1209 other->lladdr = 0ULL;
1210 /* MIPS16 not implemented. */
1214 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1216 MIPSCPU *cpu = mips_env_get_cpu(env);
1218 env->active_tc.CP0_TCHalt = arg1 & 0x1;
1220 // TODO: Halt TC / Restart (if allocated+active) TC.
1221 if (env->active_tc.CP0_TCHalt & 1) {
1222 mips_tc_sleep(cpu, env->current_tc);
1223 } else {
1224 mips_tc_wake(cpu, env->current_tc);
1228 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1230 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1231 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1232 MIPSCPU *other_cpu = mips_env_get_cpu(other);
1234 // TODO: Halt TC / Restart (if allocated+active) TC.
1236 if (other_tc == other->current_tc)
1237 other->active_tc.CP0_TCHalt = arg1;
1238 else
1239 other->tcs[other_tc].CP0_TCHalt = arg1;
1241 if (arg1 & 1) {
1242 mips_tc_sleep(other_cpu, other_tc);
1243 } else {
1244 mips_tc_wake(other_cpu, other_tc);
1248 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1250 env->active_tc.CP0_TCContext = arg1;
1253 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1255 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1256 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1258 if (other_tc == other->current_tc)
1259 other->active_tc.CP0_TCContext = arg1;
1260 else
1261 other->tcs[other_tc].CP0_TCContext = arg1;
1264 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1266 env->active_tc.CP0_TCSchedule = arg1;
1269 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1271 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1272 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1274 if (other_tc == other->current_tc)
1275 other->active_tc.CP0_TCSchedule = arg1;
1276 else
1277 other->tcs[other_tc].CP0_TCSchedule = arg1;
1280 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1282 env->active_tc.CP0_TCScheFBack = arg1;
1285 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1287 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1288 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1290 if (other_tc == other->current_tc)
1291 other->active_tc.CP0_TCScheFBack = arg1;
1292 else
1293 other->tcs[other_tc].CP0_TCScheFBack = arg1;
1296 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1298 /* 1k pages not implemented */
1299 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1300 env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1301 | (rxi << (CP0EnLo_XI - 30));
1304 #if defined(TARGET_MIPS64)
1305 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1307 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1308 env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1310 #endif
1312 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1314 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1317 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1319 uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1320 if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1321 (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1322 mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1323 mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1324 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1328 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1330 /* SmartMIPS not implemented */
1331 /* 1k pages not implemented */
1332 env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1333 (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1334 compute_hflags(env);
1335 restore_pamask(env);
1338 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1340 if (env->insn_flags & ISA_MIPS32R6) {
1341 if (arg1 < env->tlb->nb_tlb) {
1342 env->CP0_Wired = arg1;
1344 } else {
1345 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1349 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1351 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1354 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1356 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1359 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1361 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1364 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1366 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1369 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1371 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1374 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1376 uint32_t mask = 0x0000000F;
1378 if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
1379 (env->insn_flags & ISA_MIPS32R6)) {
1380 mask |= (1 << 4);
1382 if (env->insn_flags & ISA_MIPS32R6) {
1383 mask |= (1 << 5);
1385 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1386 mask |= (1 << 29);
1388 if (arg1 & (1 << 29)) {
1389 env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1390 } else {
1391 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1395 env->CP0_HWREna = arg1 & mask;
1398 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1400 cpu_mips_store_count(env, arg1);
1403 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1405 target_ulong old, val, mask;
1406 mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask;
1407 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1408 mask |= 1 << CP0EnHi_EHINV;
1411 /* 1k pages not implemented */
1412 #if defined(TARGET_MIPS64)
1413 if (env->insn_flags & ISA_MIPS32R6) {
1414 int entryhi_r = extract64(arg1, 62, 2);
1415 int config0_at = extract32(env->CP0_Config0, 13, 2);
1416 bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1417 if ((entryhi_r == 2) ||
1418 (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1419 /* skip EntryHi.R field if new value is reserved */
1420 mask &= ~(0x3ull << 62);
1423 mask &= env->SEGMask;
1424 #endif
1425 old = env->CP0_EntryHi;
1426 val = (arg1 & mask) | (old & ~mask);
1427 env->CP0_EntryHi = val;
1428 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1429 sync_c0_entryhi(env, env->current_tc);
1431 /* If the ASID changes, flush qemu's TLB. */
1432 if ((old & env->CP0_EntryHi_ASID_mask) !=
1433 (val & env->CP0_EntryHi_ASID_mask)) {
1434 cpu_mips_tlb_flush(env, 1);
1438 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1440 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1441 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1443 other->CP0_EntryHi = arg1;
1444 sync_c0_entryhi(other, other_tc);
1447 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1449 cpu_mips_store_compare(env, arg1);
1452 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1454 MIPSCPU *cpu = mips_env_get_cpu(env);
1455 uint32_t val, old;
1457 old = env->CP0_Status;
1458 cpu_mips_store_status(env, arg1);
1459 val = env->CP0_Status;
1461 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1462 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1463 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1464 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1465 env->CP0_Cause);
1466 switch (env->hflags & MIPS_HFLAG_KSU) {
1467 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1468 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1469 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1470 default:
1471 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1472 break;
1477 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1479 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1480 uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1481 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1483 other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1484 sync_c0_status(env, other, other_tc);
1487 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1489 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1492 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1494 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1495 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1498 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1500 cpu_mips_store_cause(env, arg1);
1503 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1505 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1506 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1508 cpu_mips_store_cause(other, arg1);
1511 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1513 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1514 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1516 return other->CP0_EPC;
1519 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1521 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1522 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1524 return other->CP0_EBase;
1527 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1529 env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1532 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1534 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1535 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1536 other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1539 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1541 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1542 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1544 switch (idx) {
1545 case 0: return other->CP0_Config0;
1546 case 1: return other->CP0_Config1;
1547 case 2: return other->CP0_Config2;
1548 case 3: return other->CP0_Config3;
1549 /* 4 and 5 are reserved. */
1550 case 6: return other->CP0_Config6;
1551 case 7: return other->CP0_Config7;
1552 default:
1553 break;
1555 return 0;
1558 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1560 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1563 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1565 /* tertiary/secondary caches not implemented */
1566 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1569 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1571 if (env->insn_flags & ASE_MICROMIPS) {
1572 env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1573 (arg1 & (1 << CP0C3_ISA_ON_EXC));
1577 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1579 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1580 (arg1 & env->CP0_Config4_rw_bitmask);
1583 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1585 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1586 (arg1 & env->CP0_Config5_rw_bitmask);
1587 compute_hflags(env);
1590 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1592 target_long mask = env->CP0_LLAddr_rw_bitmask;
1593 arg1 = arg1 << env->CP0_LLAddr_shift;
1594 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1597 #define MTC0_MAAR_MASK(env) \
1598 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1600 void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1)
1602 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env);
1605 void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1)
1607 env->CP0_MAAR[env->CP0_MAARI] =
1608 (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) |
1609 (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL);
1612 void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1)
1614 int index = arg1 & 0x3f;
1615 if (index == 0x3f) {
1616 /* Software may write all ones to INDEX to determine the
1617 maximum value supported. */
1618 env->CP0_MAARI = MIPS_MAAR_MAX - 1;
1619 } else if (index < MIPS_MAAR_MAX) {
1620 env->CP0_MAARI = index;
1622 /* Other than the all ones, if the
1623 value written is not supported, then INDEX is unchanged
1624 from its previous value. */
1627 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1629 /* Watch exceptions for instructions, data loads, data stores
1630 not implemented. */
1631 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1634 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1636 int mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
1637 env->CP0_WatchHi[sel] = arg1 & mask;
1638 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1641 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1643 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1644 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1647 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1649 env->CP0_Framemask = arg1; /* XXX */
1652 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1654 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1655 if (arg1 & (1 << CP0DB_DM))
1656 env->hflags |= MIPS_HFLAG_DM;
1657 else
1658 env->hflags &= ~MIPS_HFLAG_DM;
1661 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1663 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1664 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1665 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1667 /* XXX: Might be wrong, check with EJTAG spec. */
1668 if (other_tc == other->current_tc)
1669 other->active_tc.CP0_Debug_tcstatus = val;
1670 else
1671 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1672 other->CP0_Debug = (other->CP0_Debug &
1673 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1674 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1677 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1679 env->CP0_Performance0 = arg1 & 0x000007ff;
1682 void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1)
1684 int32_t wst = arg1 & (1 << CP0EC_WST);
1685 int32_t spr = arg1 & (1 << CP0EC_SPR);
1686 int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0;
1688 env->CP0_ErrCtl = wst | spr | itc;
1690 if (itc && !wst && !spr) {
1691 env->hflags |= MIPS_HFLAG_ITC_CACHE;
1692 } else {
1693 env->hflags &= ~MIPS_HFLAG_ITC_CACHE;
1697 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1699 if (env->hflags & MIPS_HFLAG_ITC_CACHE) {
1700 /* If CACHE instruction is configured for ITC tags then make all
1701 CP0.TagLo bits writable. The actual write to ITC Configuration
1702 Tag will take care of the read-only bits. */
1703 env->CP0_TagLo = arg1;
1704 } else {
1705 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1709 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1711 env->CP0_DataLo = arg1; /* XXX */
1714 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1716 env->CP0_TagHi = arg1; /* XXX */
1719 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1721 env->CP0_DataHi = arg1; /* XXX */
1724 /* MIPS MT functions */
1725 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1727 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1728 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1730 if (other_tc == other->current_tc)
1731 return other->active_tc.gpr[sel];
1732 else
1733 return other->tcs[other_tc].gpr[sel];
1736 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1738 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1739 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1741 if (other_tc == other->current_tc)
1742 return other->active_tc.LO[sel];
1743 else
1744 return other->tcs[other_tc].LO[sel];
1747 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1749 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1750 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1752 if (other_tc == other->current_tc)
1753 return other->active_tc.HI[sel];
1754 else
1755 return other->tcs[other_tc].HI[sel];
1758 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1760 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1761 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1763 if (other_tc == other->current_tc)
1764 return other->active_tc.ACX[sel];
1765 else
1766 return other->tcs[other_tc].ACX[sel];
1769 target_ulong helper_mftdsp(CPUMIPSState *env)
1771 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1772 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1774 if (other_tc == other->current_tc)
1775 return other->active_tc.DSPControl;
1776 else
1777 return other->tcs[other_tc].DSPControl;
1780 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1782 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1783 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1785 if (other_tc == other->current_tc)
1786 other->active_tc.gpr[sel] = arg1;
1787 else
1788 other->tcs[other_tc].gpr[sel] = arg1;
1791 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1793 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1794 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1796 if (other_tc == other->current_tc)
1797 other->active_tc.LO[sel] = arg1;
1798 else
1799 other->tcs[other_tc].LO[sel] = arg1;
1802 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1804 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1805 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1807 if (other_tc == other->current_tc)
1808 other->active_tc.HI[sel] = arg1;
1809 else
1810 other->tcs[other_tc].HI[sel] = arg1;
1813 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1815 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1816 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1818 if (other_tc == other->current_tc)
1819 other->active_tc.ACX[sel] = arg1;
1820 else
1821 other->tcs[other_tc].ACX[sel] = arg1;
1824 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1826 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1827 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1829 if (other_tc == other->current_tc)
1830 other->active_tc.DSPControl = arg1;
1831 else
1832 other->tcs[other_tc].DSPControl = arg1;
1835 /* MIPS MT functions */
1836 target_ulong helper_dmt(void)
1838 // TODO
1839 return 0;
1842 target_ulong helper_emt(void)
1844 // TODO
1845 return 0;
1848 target_ulong helper_dvpe(CPUMIPSState *env)
1850 CPUState *other_cs = first_cpu;
1851 target_ulong prev = env->mvp->CP0_MVPControl;
1853 CPU_FOREACH(other_cs) {
1854 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1855 /* Turn off all VPEs except the one executing the dvpe. */
1856 if (&other_cpu->env != env) {
1857 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1858 mips_vpe_sleep(other_cpu);
1861 return prev;
1864 target_ulong helper_evpe(CPUMIPSState *env)
1866 CPUState *other_cs = first_cpu;
1867 target_ulong prev = env->mvp->CP0_MVPControl;
1869 CPU_FOREACH(other_cs) {
1870 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1872 if (&other_cpu->env != env
1873 /* If the VPE is WFI, don't disturb its sleep. */
1874 && !mips_vpe_is_wfi(other_cpu)) {
1875 /* Enable the VPE. */
1876 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1877 mips_vpe_wake(other_cpu); /* And wake it up. */
1880 return prev;
1882 #endif /* !CONFIG_USER_ONLY */
1884 void helper_fork(target_ulong arg1, target_ulong arg2)
1886 // arg1 = rt, arg2 = rs
1887 // TODO: store to TC register
1890 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1892 target_long arg1 = arg;
1894 if (arg1 < 0) {
1895 /* No scheduling policy implemented. */
1896 if (arg1 != -2) {
1897 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1898 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1899 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1900 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1901 do_raise_exception(env, EXCP_THREAD, GETPC());
1904 } else if (arg1 == 0) {
1905 if (0 /* TODO: TC underflow */) {
1906 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1907 do_raise_exception(env, EXCP_THREAD, GETPC());
1908 } else {
1909 // TODO: Deallocate TC
1911 } else if (arg1 > 0) {
1912 /* Yield qualifier inputs not implemented. */
1913 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1914 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1915 do_raise_exception(env, EXCP_THREAD, GETPC());
1917 return env->CP0_YQMask;
1920 /* R6 Multi-threading */
1921 #ifndef CONFIG_USER_ONLY
1922 target_ulong helper_dvp(CPUMIPSState *env)
1924 CPUState *other_cs = first_cpu;
1925 target_ulong prev = env->CP0_VPControl;
1927 if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
1928 CPU_FOREACH(other_cs) {
1929 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1930 /* Turn off all VPs except the one executing the dvp. */
1931 if (&other_cpu->env != env) {
1932 mips_vpe_sleep(other_cpu);
1935 env->CP0_VPControl |= (1 << CP0VPCtl_DIS);
1937 return prev;
1940 target_ulong helper_evp(CPUMIPSState *env)
1942 CPUState *other_cs = first_cpu;
1943 target_ulong prev = env->CP0_VPControl;
1945 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
1946 CPU_FOREACH(other_cs) {
1947 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1948 if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
1949 /* If the VP is WFI, don't disturb its sleep.
1950 * Otherwise, wake it up. */
1951 mips_vpe_wake(other_cpu);
1954 env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS);
1956 return prev;
1958 #endif /* !CONFIG_USER_ONLY */
1960 #ifndef CONFIG_USER_ONLY
1961 /* TLB management */
1962 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1964 /* Discard entries from env->tlb[first] onwards. */
1965 while (env->tlb->tlb_in_use > first) {
1966 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1970 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
1972 #if defined(TARGET_MIPS64)
1973 return extract64(entrylo, 6, 54);
1974 #else
1975 return extract64(entrylo, 6, 24) | /* PFN */
1976 (extract64(entrylo, 32, 32) << 24); /* PFNX */
1977 #endif
1980 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1982 r4k_tlb_t *tlb;
1984 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1985 tlb = &env->tlb->mmu.r4k.tlb[idx];
1986 if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
1987 tlb->EHINV = 1;
1988 return;
1990 tlb->EHINV = 0;
1991 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1992 #if defined(TARGET_MIPS64)
1993 tlb->VPN &= env->SEGMask;
1994 #endif
1995 tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
1996 tlb->PageMask = env->CP0_PageMask;
1997 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1998 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1999 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
2000 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
2001 tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
2002 tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
2003 tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;
2004 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
2005 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
2006 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
2007 tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
2008 tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
2009 tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;
2012 void r4k_helper_tlbinv(CPUMIPSState *env)
2014 int idx;
2015 r4k_tlb_t *tlb;
2016 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2018 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2019 tlb = &env->tlb->mmu.r4k.tlb[idx];
2020 if (!tlb->G && tlb->ASID == ASID) {
2021 tlb->EHINV = 1;
2024 cpu_mips_tlb_flush(env, 1);
2027 void r4k_helper_tlbinvf(CPUMIPSState *env)
2029 int idx;
2031 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2032 env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
2034 cpu_mips_tlb_flush(env, 1);
2037 void r4k_helper_tlbwi(CPUMIPSState *env)
2039 r4k_tlb_t *tlb;
2040 int idx;
2041 target_ulong VPN;
2042 uint16_t ASID;
2043 bool G, V0, D0, V1, D1;
2045 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2046 tlb = &env->tlb->mmu.r4k.tlb[idx];
2047 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2048 #if defined(TARGET_MIPS64)
2049 VPN &= env->SEGMask;
2050 #endif
2051 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2052 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2053 V0 = (env->CP0_EntryLo0 & 2) != 0;
2054 D0 = (env->CP0_EntryLo0 & 4) != 0;
2055 V1 = (env->CP0_EntryLo1 & 2) != 0;
2056 D1 = (env->CP0_EntryLo1 & 4) != 0;
2058 /* Discard cached TLB entries, unless tlbwi is just upgrading access
2059 permissions on the current entry. */
2060 if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
2061 (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
2062 (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
2063 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2066 r4k_invalidate_tlb(env, idx, 0);
2067 r4k_fill_tlb(env, idx);
2070 void r4k_helper_tlbwr(CPUMIPSState *env)
2072 int r = cpu_mips_get_random(env);
2074 r4k_invalidate_tlb(env, r, 1);
2075 r4k_fill_tlb(env, r);
2078 void r4k_helper_tlbp(CPUMIPSState *env)
2080 r4k_tlb_t *tlb;
2081 target_ulong mask;
2082 target_ulong tag;
2083 target_ulong VPN;
2084 uint16_t ASID;
2085 int i;
2087 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2088 for (i = 0; i < env->tlb->nb_tlb; i++) {
2089 tlb = &env->tlb->mmu.r4k.tlb[i];
2090 /* 1k pages are not supported. */
2091 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2092 tag = env->CP0_EntryHi & ~mask;
2093 VPN = tlb->VPN & ~mask;
2094 #if defined(TARGET_MIPS64)
2095 tag &= env->SEGMask;
2096 #endif
2097 /* Check ASID, virtual page number & size */
2098 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
2099 /* TLB match */
2100 env->CP0_Index = i;
2101 break;
2104 if (i == env->tlb->nb_tlb) {
2105 /* No match. Discard any shadow entries, if any of them match. */
2106 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
2107 tlb = &env->tlb->mmu.r4k.tlb[i];
2108 /* 1k pages are not supported. */
2109 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2110 tag = env->CP0_EntryHi & ~mask;
2111 VPN = tlb->VPN & ~mask;
2112 #if defined(TARGET_MIPS64)
2113 tag &= env->SEGMask;
2114 #endif
2115 /* Check ASID, virtual page number & size */
2116 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2117 r4k_mips_tlb_flush_extra (env, i);
2118 break;
2122 env->CP0_Index |= 0x80000000;
2126 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
2128 #if defined(TARGET_MIPS64)
2129 return tlb_pfn << 6;
2130 #else
2131 return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
2132 (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
2133 #endif
2136 void r4k_helper_tlbr(CPUMIPSState *env)
2138 r4k_tlb_t *tlb;
2139 uint16_t ASID;
2140 int idx;
2142 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2143 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2144 tlb = &env->tlb->mmu.r4k.tlb[idx];
2146 /* If this will change the current ASID, flush qemu's TLB. */
2147 if (ASID != tlb->ASID)
2148 cpu_mips_tlb_flush (env, 1);
2150 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2152 if (tlb->EHINV) {
2153 env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2154 env->CP0_PageMask = 0;
2155 env->CP0_EntryLo0 = 0;
2156 env->CP0_EntryLo1 = 0;
2157 } else {
2158 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2159 env->CP0_PageMask = tlb->PageMask;
2160 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2161 ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2162 ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2163 get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2164 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2165 ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2166 ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2167 get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2171 void helper_tlbwi(CPUMIPSState *env)
2173 env->tlb->helper_tlbwi(env);
2176 void helper_tlbwr(CPUMIPSState *env)
2178 env->tlb->helper_tlbwr(env);
2181 void helper_tlbp(CPUMIPSState *env)
2183 env->tlb->helper_tlbp(env);
2186 void helper_tlbr(CPUMIPSState *env)
2188 env->tlb->helper_tlbr(env);
2191 void helper_tlbinv(CPUMIPSState *env)
2193 env->tlb->helper_tlbinv(env);
2196 void helper_tlbinvf(CPUMIPSState *env)
2198 env->tlb->helper_tlbinvf(env);
2201 /* Specials */
2202 target_ulong helper_di(CPUMIPSState *env)
2204 target_ulong t0 = env->CP0_Status;
2206 env->CP0_Status = t0 & ~(1 << CP0St_IE);
2207 return t0;
2210 target_ulong helper_ei(CPUMIPSState *env)
2212 target_ulong t0 = env->CP0_Status;
2214 env->CP0_Status = t0 | (1 << CP0St_IE);
2215 return t0;
2218 static void debug_pre_eret(CPUMIPSState *env)
2220 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2221 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2222 env->active_tc.PC, env->CP0_EPC);
2223 if (env->CP0_Status & (1 << CP0St_ERL))
2224 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2225 if (env->hflags & MIPS_HFLAG_DM)
2226 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2227 qemu_log("\n");
2231 static void debug_post_eret(CPUMIPSState *env)
2233 MIPSCPU *cpu = mips_env_get_cpu(env);
2235 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2236 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2237 env->active_tc.PC, env->CP0_EPC);
2238 if (env->CP0_Status & (1 << CP0St_ERL))
2239 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2240 if (env->hflags & MIPS_HFLAG_DM)
2241 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2242 switch (env->hflags & MIPS_HFLAG_KSU) {
2243 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2244 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2245 case MIPS_HFLAG_KM: qemu_log("\n"); break;
2246 default:
2247 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2248 break;
2253 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2255 env->active_tc.PC = error_pc & ~(target_ulong)1;
2256 if (error_pc & 1) {
2257 env->hflags |= MIPS_HFLAG_M16;
2258 } else {
2259 env->hflags &= ~(MIPS_HFLAG_M16);
2263 static inline void exception_return(CPUMIPSState *env)
2265 debug_pre_eret(env);
2266 if (env->CP0_Status & (1 << CP0St_ERL)) {
2267 set_pc(env, env->CP0_ErrorEPC);
2268 env->CP0_Status &= ~(1 << CP0St_ERL);
2269 } else {
2270 set_pc(env, env->CP0_EPC);
2271 env->CP0_Status &= ~(1 << CP0St_EXL);
2273 compute_hflags(env);
2274 debug_post_eret(env);
2277 void helper_eret(CPUMIPSState *env)
2279 exception_return(env);
2280 env->lladdr = 1;
2283 void helper_eretnc(CPUMIPSState *env)
2285 exception_return(env);
2288 void helper_deret(CPUMIPSState *env)
2290 debug_pre_eret(env);
2291 set_pc(env, env->CP0_DEPC);
2293 env->hflags &= ~MIPS_HFLAG_DM;
2294 compute_hflags(env);
2295 debug_post_eret(env);
2297 #endif /* !CONFIG_USER_ONLY */
2299 static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc)
2301 if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
2302 return;
2304 do_raise_exception(env, EXCP_RI, pc);
2307 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2309 check_hwrena(env, 0, GETPC());
2310 return env->CP0_EBase & 0x3ff;
2313 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2315 check_hwrena(env, 1, GETPC());
2316 return env->SYNCI_Step;
2319 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2321 check_hwrena(env, 2, GETPC());
2322 #ifdef CONFIG_USER_ONLY
2323 return env->CP0_Count;
2324 #else
2325 return (int32_t)cpu_mips_get_count(env);
2326 #endif
2329 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2331 check_hwrena(env, 3, GETPC());
2332 return env->CCRes;
2335 target_ulong helper_rdhwr_performance(CPUMIPSState *env)
2337 check_hwrena(env, 4, GETPC());
2338 return env->CP0_Performance0;
2341 target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
2343 check_hwrena(env, 5, GETPC());
2344 return (env->CP0_Config5 >> CP0C5_XNP) & 1;
2347 void helper_pmon(CPUMIPSState *env, int function)
2349 function /= 2;
2350 switch (function) {
2351 case 2: /* TODO: char inbyte(int waitflag); */
2352 if (env->active_tc.gpr[4] == 0)
2353 env->active_tc.gpr[2] = -1;
2354 /* Fall through */
2355 case 11: /* TODO: char inbyte (void); */
2356 env->active_tc.gpr[2] = -1;
2357 break;
2358 case 3:
2359 case 12:
2360 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2361 break;
2362 case 17:
2363 break;
2364 case 158:
2366 unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2367 printf("%s", fmt);
2369 break;
2373 void helper_wait(CPUMIPSState *env)
2375 CPUState *cs = CPU(mips_env_get_cpu(env));
2377 cs->halted = 1;
2378 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2379 /* Last instruction in the block, PC was updated before
2380 - no need to recover PC and icount */
2381 raise_exception(env, EXCP_HLT);
2384 #if !defined(CONFIG_USER_ONLY)
2386 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2387 MMUAccessType access_type,
2388 int mmu_idx, uintptr_t retaddr)
2390 MIPSCPU *cpu = MIPS_CPU(cs);
2391 CPUMIPSState *env = &cpu->env;
2392 int error_code = 0;
2393 int excp;
2395 env->CP0_BadVAddr = addr;
2397 if (access_type == MMU_DATA_STORE) {
2398 excp = EXCP_AdES;
2399 } else {
2400 excp = EXCP_AdEL;
2401 if (access_type == MMU_INST_FETCH) {
2402 error_code |= EXCP_INST_NOTAVAIL;
2406 do_raise_exception_err(env, excp, error_code, retaddr);
2409 void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
2410 int mmu_idx, uintptr_t retaddr)
2412 int ret;
2414 ret = mips_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx);
2415 if (ret) {
2416 MIPSCPU *cpu = MIPS_CPU(cs);
2417 CPUMIPSState *env = &cpu->env;
2419 do_raise_exception_err(env, cs->exception_index,
2420 env->error_code, retaddr);
2424 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2425 bool is_write, bool is_exec, int unused,
2426 unsigned size)
2428 MIPSCPU *cpu = MIPS_CPU(cs);
2429 CPUMIPSState *env = &cpu->env;
2432 * Raising an exception with KVM enabled will crash because it won't be from
2433 * the main execution loop so the longjmp won't have a matching setjmp.
2434 * Until we can trigger a bus error exception through KVM lets just ignore
2435 * the access.
2437 if (kvm_enabled()) {
2438 return;
2441 if (is_exec) {
2442 raise_exception(env, EXCP_IBE);
2443 } else {
2444 raise_exception(env, EXCP_DBE);
2447 #endif /* !CONFIG_USER_ONLY */
2449 /* Complex FPU operations which may need stack space. */
2451 #define FLOAT_TWO32 make_float32(1 << 30)
2452 #define FLOAT_TWO64 make_float64(1ULL << 62)
2454 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2455 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2457 /* convert MIPS rounding mode in FCR31 to IEEE library */
2458 unsigned int ieee_rm[] = {
2459 float_round_nearest_even,
2460 float_round_to_zero,
2461 float_round_up,
2462 float_round_down
2465 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2467 target_ulong arg1 = 0;
2469 switch (reg) {
2470 case 0:
2471 arg1 = (int32_t)env->active_fpu.fcr0;
2472 break;
2473 case 1:
2474 /* UFR Support - Read Status FR */
2475 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2476 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2477 arg1 = (int32_t)
2478 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
2479 } else {
2480 do_raise_exception(env, EXCP_RI, GETPC());
2483 break;
2484 case 5:
2485 /* FRE Support - read Config5.FRE bit */
2486 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2487 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2488 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2489 } else {
2490 helper_raise_exception(env, EXCP_RI);
2493 break;
2494 case 25:
2495 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2496 break;
2497 case 26:
2498 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2499 break;
2500 case 28:
2501 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2502 break;
2503 default:
2504 arg1 = (int32_t)env->active_fpu.fcr31;
2505 break;
2508 return arg1;
2511 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2513 switch (fs) {
2514 case 1:
2515 /* UFR Alias - Reset Status FR */
2516 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2517 return;
2519 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2520 env->CP0_Status &= ~(1 << CP0St_FR);
2521 compute_hflags(env);
2522 } else {
2523 do_raise_exception(env, EXCP_RI, GETPC());
2525 break;
2526 case 4:
2527 /* UNFR Alias - Set Status FR */
2528 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2529 return;
2531 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2532 env->CP0_Status |= (1 << CP0St_FR);
2533 compute_hflags(env);
2534 } else {
2535 do_raise_exception(env, EXCP_RI, GETPC());
2537 break;
2538 case 5:
2539 /* FRE Support - clear Config5.FRE bit */
2540 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2541 return;
2543 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2544 env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2545 compute_hflags(env);
2546 } else {
2547 helper_raise_exception(env, EXCP_RI);
2549 break;
2550 case 6:
2551 /* FRE Support - set Config5.FRE bit */
2552 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2553 return;
2555 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2556 env->CP0_Config5 |= (1 << CP0C5_FRE);
2557 compute_hflags(env);
2558 } else {
2559 helper_raise_exception(env, EXCP_RI);
2561 break;
2562 case 25:
2563 if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2564 return;
2566 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2567 ((arg1 & 0x1) << 23);
2568 break;
2569 case 26:
2570 if (arg1 & 0x007c0000)
2571 return;
2572 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2573 break;
2574 case 28:
2575 if (arg1 & 0x007c0000)
2576 return;
2577 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2578 ((arg1 & 0x4) << 22);
2579 break;
2580 case 31:
2581 env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
2582 (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
2583 break;
2584 default:
2585 return;
2587 restore_fp_status(env);
2588 set_float_exception_flags(0, &env->active_fpu.fp_status);
2589 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2590 do_raise_exception(env, EXCP_FPE, GETPC());
2593 int ieee_ex_to_mips(int xcpt)
2595 int ret = 0;
2596 if (xcpt) {
2597 if (xcpt & float_flag_invalid) {
2598 ret |= FP_INVALID;
2600 if (xcpt & float_flag_overflow) {
2601 ret |= FP_OVERFLOW;
2603 if (xcpt & float_flag_underflow) {
2604 ret |= FP_UNDERFLOW;
2606 if (xcpt & float_flag_divbyzero) {
2607 ret |= FP_DIV0;
2609 if (xcpt & float_flag_inexact) {
2610 ret |= FP_INEXACT;
2613 return ret;
2616 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2618 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2620 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2622 if (tmp) {
2623 set_float_exception_flags(0, &env->active_fpu.fp_status);
2625 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2626 do_raise_exception(env, EXCP_FPE, pc);
2627 } else {
2628 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2633 /* Float support.
2634 Single precition routines have a "s" suffix, double precision a
2635 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2636 paired single lower "pl", paired single upper "pu". */
2638 /* unary operations, modifying fp status */
2639 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2641 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2642 update_fcr31(env, GETPC());
2643 return fdt0;
2646 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2648 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2649 update_fcr31(env, GETPC());
2650 return fst0;
2653 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2655 uint64_t fdt2;
2657 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2658 fdt2 = float64_maybe_silence_nan(fdt2, &env->active_fpu.fp_status);
2659 update_fcr31(env, GETPC());
2660 return fdt2;
2663 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2665 uint64_t fdt2;
2667 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2668 update_fcr31(env, GETPC());
2669 return fdt2;
2672 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2674 uint64_t fdt2;
2676 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2677 update_fcr31(env, GETPC());
2678 return fdt2;
2681 uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
2683 uint64_t dt2;
2685 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2686 if (get_float_exception_flags(&env->active_fpu.fp_status)
2687 & (float_flag_invalid | float_flag_overflow)) {
2688 dt2 = FP_TO_INT64_OVERFLOW;
2690 update_fcr31(env, GETPC());
2691 return dt2;
2694 uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
2696 uint64_t dt2;
2698 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2699 if (get_float_exception_flags(&env->active_fpu.fp_status)
2700 & (float_flag_invalid | float_flag_overflow)) {
2701 dt2 = FP_TO_INT64_OVERFLOW;
2703 update_fcr31(env, GETPC());
2704 return dt2;
2707 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2709 uint32_t fst2;
2710 uint32_t fsth2;
2712 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2713 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2714 update_fcr31(env, GETPC());
2715 return ((uint64_t)fsth2 << 32) | fst2;
2718 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2720 uint32_t wt2;
2721 uint32_t wth2;
2722 int excp, excph;
2724 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2725 excp = get_float_exception_flags(&env->active_fpu.fp_status);
2726 if (excp & (float_flag_overflow | float_flag_invalid)) {
2727 wt2 = FP_TO_INT32_OVERFLOW;
2730 set_float_exception_flags(0, &env->active_fpu.fp_status);
2731 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2732 excph = get_float_exception_flags(&env->active_fpu.fp_status);
2733 if (excph & (float_flag_overflow | float_flag_invalid)) {
2734 wth2 = FP_TO_INT32_OVERFLOW;
2737 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2738 update_fcr31(env, GETPC());
2740 return ((uint64_t)wth2 << 32) | wt2;
2743 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2745 uint32_t fst2;
2747 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2748 fst2 = float32_maybe_silence_nan(fst2, &env->active_fpu.fp_status);
2749 update_fcr31(env, GETPC());
2750 return fst2;
2753 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2755 uint32_t fst2;
2757 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2758 update_fcr31(env, GETPC());
2759 return fst2;
2762 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2764 uint32_t fst2;
2766 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2767 update_fcr31(env, GETPC());
2768 return fst2;
2771 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2773 uint32_t wt2;
2775 wt2 = wt0;
2776 update_fcr31(env, GETPC());
2777 return wt2;
2780 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2782 uint32_t wt2;
2784 wt2 = wth0;
2785 update_fcr31(env, GETPC());
2786 return wt2;
2789 uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
2791 uint32_t wt2;
2793 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2794 if (get_float_exception_flags(&env->active_fpu.fp_status)
2795 & (float_flag_invalid | float_flag_overflow)) {
2796 wt2 = FP_TO_INT32_OVERFLOW;
2798 update_fcr31(env, GETPC());
2799 return wt2;
2802 uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
2804 uint32_t wt2;
2806 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2807 if (get_float_exception_flags(&env->active_fpu.fp_status)
2808 & (float_flag_invalid | float_flag_overflow)) {
2809 wt2 = FP_TO_INT32_OVERFLOW;
2811 update_fcr31(env, GETPC());
2812 return wt2;
2815 uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0)
2817 uint64_t dt2;
2819 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2820 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2821 restore_rounding_mode(env);
2822 if (get_float_exception_flags(&env->active_fpu.fp_status)
2823 & (float_flag_invalid | float_flag_overflow)) {
2824 dt2 = FP_TO_INT64_OVERFLOW;
2826 update_fcr31(env, GETPC());
2827 return dt2;
2830 uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0)
2832 uint64_t dt2;
2834 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2835 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2836 restore_rounding_mode(env);
2837 if (get_float_exception_flags(&env->active_fpu.fp_status)
2838 & (float_flag_invalid | float_flag_overflow)) {
2839 dt2 = FP_TO_INT64_OVERFLOW;
2841 update_fcr31(env, GETPC());
2842 return dt2;
2845 uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0)
2847 uint32_t wt2;
2849 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2850 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2851 restore_rounding_mode(env);
2852 if (get_float_exception_flags(&env->active_fpu.fp_status)
2853 & (float_flag_invalid | float_flag_overflow)) {
2854 wt2 = FP_TO_INT32_OVERFLOW;
2856 update_fcr31(env, GETPC());
2857 return wt2;
2860 uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0)
2862 uint32_t wt2;
2864 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2865 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2866 restore_rounding_mode(env);
2867 if (get_float_exception_flags(&env->active_fpu.fp_status)
2868 & (float_flag_invalid | float_flag_overflow)) {
2869 wt2 = FP_TO_INT32_OVERFLOW;
2871 update_fcr31(env, GETPC());
2872 return wt2;
2875 uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0)
2877 uint64_t dt2;
2879 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2880 if (get_float_exception_flags(&env->active_fpu.fp_status)
2881 & (float_flag_invalid | float_flag_overflow)) {
2882 dt2 = FP_TO_INT64_OVERFLOW;
2884 update_fcr31(env, GETPC());
2885 return dt2;
2888 uint64_t helper_float_trunc_l_s(CPUMIPSState *env, uint32_t fst0)
2890 uint64_t dt2;
2892 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2893 if (get_float_exception_flags(&env->active_fpu.fp_status)
2894 & (float_flag_invalid | float_flag_overflow)) {
2895 dt2 = FP_TO_INT64_OVERFLOW;
2897 update_fcr31(env, GETPC());
2898 return dt2;
2901 uint32_t helper_float_trunc_w_d(CPUMIPSState *env, uint64_t fdt0)
2903 uint32_t wt2;
2905 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2906 if (get_float_exception_flags(&env->active_fpu.fp_status)
2907 & (float_flag_invalid | float_flag_overflow)) {
2908 wt2 = FP_TO_INT32_OVERFLOW;
2910 update_fcr31(env, GETPC());
2911 return wt2;
2914 uint32_t helper_float_trunc_w_s(CPUMIPSState *env, uint32_t fst0)
2916 uint32_t wt2;
2918 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2919 if (get_float_exception_flags(&env->active_fpu.fp_status)
2920 & (float_flag_invalid | float_flag_overflow)) {
2921 wt2 = FP_TO_INT32_OVERFLOW;
2923 update_fcr31(env, GETPC());
2924 return wt2;
2927 uint64_t helper_float_ceil_l_d(CPUMIPSState *env, uint64_t fdt0)
2929 uint64_t dt2;
2931 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2932 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2933 restore_rounding_mode(env);
2934 if (get_float_exception_flags(&env->active_fpu.fp_status)
2935 & (float_flag_invalid | float_flag_overflow)) {
2936 dt2 = FP_TO_INT64_OVERFLOW;
2938 update_fcr31(env, GETPC());
2939 return dt2;
2942 uint64_t helper_float_ceil_l_s(CPUMIPSState *env, uint32_t fst0)
2944 uint64_t dt2;
2946 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2947 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2948 restore_rounding_mode(env);
2949 if (get_float_exception_flags(&env->active_fpu.fp_status)
2950 & (float_flag_invalid | float_flag_overflow)) {
2951 dt2 = FP_TO_INT64_OVERFLOW;
2953 update_fcr31(env, GETPC());
2954 return dt2;
2957 uint32_t helper_float_ceil_w_d(CPUMIPSState *env, uint64_t fdt0)
2959 uint32_t wt2;
2961 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2962 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2963 restore_rounding_mode(env);
2964 if (get_float_exception_flags(&env->active_fpu.fp_status)
2965 & (float_flag_invalid | float_flag_overflow)) {
2966 wt2 = FP_TO_INT32_OVERFLOW;
2968 update_fcr31(env, GETPC());
2969 return wt2;
2972 uint32_t helper_float_ceil_w_s(CPUMIPSState *env, uint32_t fst0)
2974 uint32_t wt2;
2976 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2977 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2978 restore_rounding_mode(env);
2979 if (get_float_exception_flags(&env->active_fpu.fp_status)
2980 & (float_flag_invalid | float_flag_overflow)) {
2981 wt2 = FP_TO_INT32_OVERFLOW;
2983 update_fcr31(env, GETPC());
2984 return wt2;
2987 uint64_t helper_float_floor_l_d(CPUMIPSState *env, uint64_t fdt0)
2989 uint64_t dt2;
2991 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2992 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2993 restore_rounding_mode(env);
2994 if (get_float_exception_flags(&env->active_fpu.fp_status)
2995 & (float_flag_invalid | float_flag_overflow)) {
2996 dt2 = FP_TO_INT64_OVERFLOW;
2998 update_fcr31(env, GETPC());
2999 return dt2;
3002 uint64_t helper_float_floor_l_s(CPUMIPSState *env, uint32_t fst0)
3004 uint64_t dt2;
3006 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3007 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3008 restore_rounding_mode(env);
3009 if (get_float_exception_flags(&env->active_fpu.fp_status)
3010 & (float_flag_invalid | float_flag_overflow)) {
3011 dt2 = FP_TO_INT64_OVERFLOW;
3013 update_fcr31(env, GETPC());
3014 return dt2;
3017 uint32_t helper_float_floor_w_d(CPUMIPSState *env, uint64_t fdt0)
3019 uint32_t wt2;
3021 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3022 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3023 restore_rounding_mode(env);
3024 if (get_float_exception_flags(&env->active_fpu.fp_status)
3025 & (float_flag_invalid | float_flag_overflow)) {
3026 wt2 = FP_TO_INT32_OVERFLOW;
3028 update_fcr31(env, GETPC());
3029 return wt2;
3032 uint32_t helper_float_floor_w_s(CPUMIPSState *env, uint32_t fst0)
3034 uint32_t wt2;
3036 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3037 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3038 restore_rounding_mode(env);
3039 if (get_float_exception_flags(&env->active_fpu.fp_status)
3040 & (float_flag_invalid | float_flag_overflow)) {
3041 wt2 = FP_TO_INT32_OVERFLOW;
3043 update_fcr31(env, GETPC());
3044 return wt2;
3047 uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3049 uint64_t dt2;
3051 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3052 if (get_float_exception_flags(&env->active_fpu.fp_status)
3053 & float_flag_invalid) {
3054 if (float64_is_any_nan(fdt0)) {
3055 dt2 = 0;
3058 update_fcr31(env, GETPC());
3059 return dt2;
3062 uint64_t helper_float_cvt_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3064 uint64_t dt2;
3066 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3067 if (get_float_exception_flags(&env->active_fpu.fp_status)
3068 & float_flag_invalid) {
3069 if (float32_is_any_nan(fst0)) {
3070 dt2 = 0;
3073 update_fcr31(env, GETPC());
3074 return dt2;
3077 uint32_t helper_float_cvt_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3079 uint32_t wt2;
3081 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3082 if (get_float_exception_flags(&env->active_fpu.fp_status)
3083 & float_flag_invalid) {
3084 if (float64_is_any_nan(fdt0)) {
3085 wt2 = 0;
3088 update_fcr31(env, GETPC());
3089 return wt2;
3092 uint32_t helper_float_cvt_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3094 uint32_t wt2;
3096 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3097 if (get_float_exception_flags(&env->active_fpu.fp_status)
3098 & float_flag_invalid) {
3099 if (float32_is_any_nan(fst0)) {
3100 wt2 = 0;
3103 update_fcr31(env, GETPC());
3104 return wt2;
3107 uint64_t helper_float_round_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3109 uint64_t dt2;
3111 set_float_rounding_mode(float_round_nearest_even,
3112 &env->active_fpu.fp_status);
3113 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3114 restore_rounding_mode(env);
3115 if (get_float_exception_flags(&env->active_fpu.fp_status)
3116 & float_flag_invalid) {
3117 if (float64_is_any_nan(fdt0)) {
3118 dt2 = 0;
3121 update_fcr31(env, GETPC());
3122 return dt2;
3125 uint64_t helper_float_round_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3127 uint64_t dt2;
3129 set_float_rounding_mode(float_round_nearest_even,
3130 &env->active_fpu.fp_status);
3131 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3132 restore_rounding_mode(env);
3133 if (get_float_exception_flags(&env->active_fpu.fp_status)
3134 & float_flag_invalid) {
3135 if (float32_is_any_nan(fst0)) {
3136 dt2 = 0;
3139 update_fcr31(env, GETPC());
3140 return dt2;
3143 uint32_t helper_float_round_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3145 uint32_t wt2;
3147 set_float_rounding_mode(float_round_nearest_even,
3148 &env->active_fpu.fp_status);
3149 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3150 restore_rounding_mode(env);
3151 if (get_float_exception_flags(&env->active_fpu.fp_status)
3152 & float_flag_invalid) {
3153 if (float64_is_any_nan(fdt0)) {
3154 wt2 = 0;
3157 update_fcr31(env, GETPC());
3158 return wt2;
3161 uint32_t helper_float_round_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3163 uint32_t wt2;
3165 set_float_rounding_mode(float_round_nearest_even,
3166 &env->active_fpu.fp_status);
3167 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3168 restore_rounding_mode(env);
3169 if (get_float_exception_flags(&env->active_fpu.fp_status)
3170 & float_flag_invalid) {
3171 if (float32_is_any_nan(fst0)) {
3172 wt2 = 0;
3175 update_fcr31(env, GETPC());
3176 return wt2;
3179 uint64_t helper_float_trunc_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3181 uint64_t dt2;
3183 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
3184 if (get_float_exception_flags(&env->active_fpu.fp_status)
3185 & float_flag_invalid) {
3186 if (float64_is_any_nan(fdt0)) {
3187 dt2 = 0;
3190 update_fcr31(env, GETPC());
3191 return dt2;
3194 uint64_t helper_float_trunc_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3196 uint64_t dt2;
3198 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
3199 if (get_float_exception_flags(&env->active_fpu.fp_status)
3200 & float_flag_invalid) {
3201 if (float32_is_any_nan(fst0)) {
3202 dt2 = 0;
3205 update_fcr31(env, GETPC());
3206 return dt2;
3209 uint32_t helper_float_trunc_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3211 uint32_t wt2;
3213 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
3214 if (get_float_exception_flags(&env->active_fpu.fp_status)
3215 & float_flag_invalid) {
3216 if (float64_is_any_nan(fdt0)) {
3217 wt2 = 0;
3220 update_fcr31(env, GETPC());
3221 return wt2;
3224 uint32_t helper_float_trunc_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3226 uint32_t wt2;
3228 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
3229 if (get_float_exception_flags(&env->active_fpu.fp_status)
3230 & float_flag_invalid) {
3231 if (float32_is_any_nan(fst0)) {
3232 wt2 = 0;
3235 update_fcr31(env, GETPC());
3236 return wt2;
3239 uint64_t helper_float_ceil_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3241 uint64_t dt2;
3243 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3244 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3245 restore_rounding_mode(env);
3246 if (get_float_exception_flags(&env->active_fpu.fp_status)
3247 & float_flag_invalid) {
3248 if (float64_is_any_nan(fdt0)) {
3249 dt2 = 0;
3252 update_fcr31(env, GETPC());
3253 return dt2;
3256 uint64_t helper_float_ceil_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3258 uint64_t dt2;
3260 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3261 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3262 restore_rounding_mode(env);
3263 if (get_float_exception_flags(&env->active_fpu.fp_status)
3264 & float_flag_invalid) {
3265 if (float32_is_any_nan(fst0)) {
3266 dt2 = 0;
3269 update_fcr31(env, GETPC());
3270 return dt2;
3273 uint32_t helper_float_ceil_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3275 uint32_t wt2;
3277 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3278 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3279 restore_rounding_mode(env);
3280 if (get_float_exception_flags(&env->active_fpu.fp_status)
3281 & float_flag_invalid) {
3282 if (float64_is_any_nan(fdt0)) {
3283 wt2 = 0;
3286 update_fcr31(env, GETPC());
3287 return wt2;
3290 uint32_t helper_float_ceil_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3292 uint32_t wt2;
3294 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3295 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3296 restore_rounding_mode(env);
3297 if (get_float_exception_flags(&env->active_fpu.fp_status)
3298 & float_flag_invalid) {
3299 if (float32_is_any_nan(fst0)) {
3300 wt2 = 0;
3303 update_fcr31(env, GETPC());
3304 return wt2;
3307 uint64_t helper_float_floor_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3309 uint64_t dt2;
3311 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3312 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3313 restore_rounding_mode(env);
3314 if (get_float_exception_flags(&env->active_fpu.fp_status)
3315 & float_flag_invalid) {
3316 if (float64_is_any_nan(fdt0)) {
3317 dt2 = 0;
3320 update_fcr31(env, GETPC());
3321 return dt2;
3324 uint64_t helper_float_floor_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3326 uint64_t dt2;
3328 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3329 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3330 restore_rounding_mode(env);
3331 if (get_float_exception_flags(&env->active_fpu.fp_status)
3332 & float_flag_invalid) {
3333 if (float32_is_any_nan(fst0)) {
3334 dt2 = 0;
3337 update_fcr31(env, GETPC());
3338 return dt2;
3341 uint32_t helper_float_floor_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3343 uint32_t wt2;
3345 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3346 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3347 restore_rounding_mode(env);
3348 if (get_float_exception_flags(&env->active_fpu.fp_status)
3349 & float_flag_invalid) {
3350 if (float64_is_any_nan(fdt0)) {
3351 wt2 = 0;
3354 update_fcr31(env, GETPC());
3355 return wt2;
3358 uint32_t helper_float_floor_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3360 uint32_t wt2;
3362 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3363 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3364 restore_rounding_mode(env);
3365 if (get_float_exception_flags(&env->active_fpu.fp_status)
3366 & float_flag_invalid) {
3367 if (float32_is_any_nan(fst0)) {
3368 wt2 = 0;
3371 update_fcr31(env, GETPC());
3372 return wt2;
3375 /* unary operations, not modifying fp status */
3376 #define FLOAT_UNOP(name) \
3377 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
3379 return float64_ ## name(fdt0); \
3381 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
3383 return float32_ ## name(fst0); \
3385 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
3387 uint32_t wt0; \
3388 uint32_t wth0; \
3390 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
3391 wth0 = float32_ ## name(fdt0 >> 32); \
3392 return ((uint64_t)wth0 << 32) | wt0; \
3394 FLOAT_UNOP(abs)
3395 FLOAT_UNOP(chs)
3396 #undef FLOAT_UNOP
3398 /* MIPS specific unary operations */
3399 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
3401 uint64_t fdt2;
3403 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3404 update_fcr31(env, GETPC());
3405 return fdt2;
3408 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
3410 uint32_t fst2;
3412 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3413 update_fcr31(env, GETPC());
3414 return fst2;
3417 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
3419 uint64_t fdt2;
3421 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3422 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3423 update_fcr31(env, GETPC());
3424 return fdt2;
3427 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
3429 uint32_t fst2;
3431 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3432 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3433 update_fcr31(env, GETPC());
3434 return fst2;
3437 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
3439 uint64_t fdt2;
3441 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3442 update_fcr31(env, GETPC());
3443 return fdt2;
3446 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
3448 uint32_t fst2;
3450 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3451 update_fcr31(env, GETPC());
3452 return fst2;
3455 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
3457 uint32_t fst2;
3458 uint32_t fsth2;
3460 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3461 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
3462 update_fcr31(env, GETPC());
3463 return ((uint64_t)fsth2 << 32) | fst2;
3466 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3468 uint64_t fdt2;
3470 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3471 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3472 update_fcr31(env, GETPC());
3473 return fdt2;
3476 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3478 uint32_t fst2;
3480 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3481 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3482 update_fcr31(env, GETPC());
3483 return fst2;
3486 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3488 uint32_t fst2;
3489 uint32_t fsth2;
3491 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3492 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3493 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3494 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3495 update_fcr31(env, GETPC());
3496 return ((uint64_t)fsth2 << 32) | fst2;
3499 #define FLOAT_RINT(name, bits) \
3500 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3501 uint ## bits ## _t fs) \
3503 uint ## bits ## _t fdret; \
3505 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3506 update_fcr31(env, GETPC()); \
3507 return fdret; \
3510 FLOAT_RINT(rint_s, 32)
3511 FLOAT_RINT(rint_d, 64)
3512 #undef FLOAT_RINT
3514 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3515 #define FLOAT_CLASS_QUIET_NAN 0x002
3516 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3517 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3518 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3519 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3520 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3521 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3522 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3523 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3525 #define FLOAT_CLASS(name, bits) \
3526 uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \
3527 float_status *status) \
3529 if (float ## bits ## _is_signaling_nan(arg, status)) { \
3530 return FLOAT_CLASS_SIGNALING_NAN; \
3531 } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
3532 return FLOAT_CLASS_QUIET_NAN; \
3533 } else if (float ## bits ## _is_neg(arg)) { \
3534 if (float ## bits ## _is_infinity(arg)) { \
3535 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3536 } else if (float ## bits ## _is_zero(arg)) { \
3537 return FLOAT_CLASS_NEGATIVE_ZERO; \
3538 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3539 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3540 } else { \
3541 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3543 } else { \
3544 if (float ## bits ## _is_infinity(arg)) { \
3545 return FLOAT_CLASS_POSITIVE_INFINITY; \
3546 } else if (float ## bits ## _is_zero(arg)) { \
3547 return FLOAT_CLASS_POSITIVE_ZERO; \
3548 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3549 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3550 } else { \
3551 return FLOAT_CLASS_POSITIVE_NORMAL; \
3556 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3557 uint ## bits ## _t arg) \
3559 return float_ ## name(arg, &env->active_fpu.fp_status); \
3562 FLOAT_CLASS(class_s, 32)
3563 FLOAT_CLASS(class_d, 64)
3564 #undef FLOAT_CLASS
3566 /* binary operations */
3567 #define FLOAT_BINOP(name) \
3568 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3569 uint64_t fdt0, uint64_t fdt1) \
3571 uint64_t dt2; \
3573 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3574 update_fcr31(env, GETPC()); \
3575 return dt2; \
3578 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3579 uint32_t fst0, uint32_t fst1) \
3581 uint32_t wt2; \
3583 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3584 update_fcr31(env, GETPC()); \
3585 return wt2; \
3588 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3589 uint64_t fdt0, \
3590 uint64_t fdt1) \
3592 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3593 uint32_t fsth0 = fdt0 >> 32; \
3594 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3595 uint32_t fsth1 = fdt1 >> 32; \
3596 uint32_t wt2; \
3597 uint32_t wth2; \
3599 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3600 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3601 update_fcr31(env, GETPC()); \
3602 return ((uint64_t)wth2 << 32) | wt2; \
3605 FLOAT_BINOP(add)
3606 FLOAT_BINOP(sub)
3607 FLOAT_BINOP(mul)
3608 FLOAT_BINOP(div)
3609 #undef FLOAT_BINOP
3611 /* MIPS specific binary operations */
3612 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3614 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3615 fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3616 update_fcr31(env, GETPC());
3617 return fdt2;
3620 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3622 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3623 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3624 update_fcr31(env, GETPC());
3625 return fst2;
3628 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3630 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3631 uint32_t fsth0 = fdt0 >> 32;
3632 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3633 uint32_t fsth2 = fdt2 >> 32;
3635 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3636 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3637 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3638 fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3639 update_fcr31(env, GETPC());
3640 return ((uint64_t)fsth2 << 32) | fst2;
3643 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3645 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3646 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3647 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3648 update_fcr31(env, GETPC());
3649 return fdt2;
3652 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3654 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3655 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3656 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3657 update_fcr31(env, GETPC());
3658 return fst2;
3661 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3663 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3664 uint32_t fsth0 = fdt0 >> 32;
3665 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3666 uint32_t fsth2 = fdt2 >> 32;
3668 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3669 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3670 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3671 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3672 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3673 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3674 update_fcr31(env, GETPC());
3675 return ((uint64_t)fsth2 << 32) | fst2;
3678 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3680 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3681 uint32_t fsth0 = fdt0 >> 32;
3682 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3683 uint32_t fsth1 = fdt1 >> 32;
3684 uint32_t fst2;
3685 uint32_t fsth2;
3687 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3688 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3689 update_fcr31(env, GETPC());
3690 return ((uint64_t)fsth2 << 32) | fst2;
3693 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3695 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3696 uint32_t fsth0 = fdt0 >> 32;
3697 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3698 uint32_t fsth1 = fdt1 >> 32;
3699 uint32_t fst2;
3700 uint32_t fsth2;
3702 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3703 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3704 update_fcr31(env, GETPC());
3705 return ((uint64_t)fsth2 << 32) | fst2;
3708 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
3709 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3710 uint ## bits ## _t fs, \
3711 uint ## bits ## _t ft) \
3713 uint ## bits ## _t fdret; \
3715 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
3716 &env->active_fpu.fp_status); \
3717 update_fcr31(env, GETPC()); \
3718 return fdret; \
3721 FLOAT_MINMAX(max_s, 32, maxnum)
3722 FLOAT_MINMAX(max_d, 64, maxnum)
3723 FLOAT_MINMAX(maxa_s, 32, maxnummag)
3724 FLOAT_MINMAX(maxa_d, 64, maxnummag)
3726 FLOAT_MINMAX(min_s, 32, minnum)
3727 FLOAT_MINMAX(min_d, 64, minnum)
3728 FLOAT_MINMAX(mina_s, 32, minnummag)
3729 FLOAT_MINMAX(mina_d, 64, minnummag)
3730 #undef FLOAT_MINMAX
3732 /* ternary operations */
3733 #define UNFUSED_FMA(prefix, a, b, c, flags) \
3735 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
3736 if ((flags) & float_muladd_negate_c) { \
3737 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
3738 } else { \
3739 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
3741 if ((flags) & float_muladd_negate_result) { \
3742 a = prefix##_chs(a); \
3746 /* FMA based operations */
3747 #define FLOAT_FMA(name, type) \
3748 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3749 uint64_t fdt0, uint64_t fdt1, \
3750 uint64_t fdt2) \
3752 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
3753 update_fcr31(env, GETPC()); \
3754 return fdt0; \
3757 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3758 uint32_t fst0, uint32_t fst1, \
3759 uint32_t fst2) \
3761 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3762 update_fcr31(env, GETPC()); \
3763 return fst0; \
3766 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3767 uint64_t fdt0, uint64_t fdt1, \
3768 uint64_t fdt2) \
3770 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3771 uint32_t fsth0 = fdt0 >> 32; \
3772 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3773 uint32_t fsth1 = fdt1 >> 32; \
3774 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
3775 uint32_t fsth2 = fdt2 >> 32; \
3777 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3778 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
3779 update_fcr31(env, GETPC()); \
3780 return ((uint64_t)fsth0 << 32) | fst0; \
3782 FLOAT_FMA(madd, 0)
3783 FLOAT_FMA(msub, float_muladd_negate_c)
3784 FLOAT_FMA(nmadd, float_muladd_negate_result)
3785 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
3786 #undef FLOAT_FMA
3788 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
3789 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3790 uint ## bits ## _t fs, \
3791 uint ## bits ## _t ft, \
3792 uint ## bits ## _t fd) \
3794 uint ## bits ## _t fdret; \
3796 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
3797 &env->active_fpu.fp_status); \
3798 update_fcr31(env, GETPC()); \
3799 return fdret; \
3802 FLOAT_FMADDSUB(maddf_s, 32, 0)
3803 FLOAT_FMADDSUB(maddf_d, 64, 0)
3804 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
3805 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
3806 #undef FLOAT_FMADDSUB
3808 /* compare operations */
3809 #define FOP_COND_D(op, cond) \
3810 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3811 uint64_t fdt1, int cc) \
3813 int c; \
3814 c = cond; \
3815 update_fcr31(env, GETPC()); \
3816 if (c) \
3817 SET_FP_COND(cc, env->active_fpu); \
3818 else \
3819 CLEAR_FP_COND(cc, env->active_fpu); \
3821 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3822 uint64_t fdt1, int cc) \
3824 int c; \
3825 fdt0 = float64_abs(fdt0); \
3826 fdt1 = float64_abs(fdt1); \
3827 c = cond; \
3828 update_fcr31(env, GETPC()); \
3829 if (c) \
3830 SET_FP_COND(cc, env->active_fpu); \
3831 else \
3832 CLEAR_FP_COND(cc, env->active_fpu); \
3835 /* NOTE: the comma operator will make "cond" to eval to false,
3836 * but float64_unordered_quiet() is still called. */
3837 FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3838 FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3839 FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3840 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3841 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3842 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3843 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3844 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3845 /* NOTE: the comma operator will make "cond" to eval to false,
3846 * but float64_unordered() is still called. */
3847 FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3848 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3849 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3850 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3851 FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3852 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3853 FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3854 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3856 #define FOP_COND_S(op, cond) \
3857 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3858 uint32_t fst1, int cc) \
3860 int c; \
3861 c = cond; \
3862 update_fcr31(env, GETPC()); \
3863 if (c) \
3864 SET_FP_COND(cc, env->active_fpu); \
3865 else \
3866 CLEAR_FP_COND(cc, env->active_fpu); \
3868 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3869 uint32_t fst1, int cc) \
3871 int c; \
3872 fst0 = float32_abs(fst0); \
3873 fst1 = float32_abs(fst1); \
3874 c = cond; \
3875 update_fcr31(env, GETPC()); \
3876 if (c) \
3877 SET_FP_COND(cc, env->active_fpu); \
3878 else \
3879 CLEAR_FP_COND(cc, env->active_fpu); \
3882 /* NOTE: the comma operator will make "cond" to eval to false,
3883 * but float32_unordered_quiet() is still called. */
3884 FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3885 FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3886 FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3887 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3888 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3889 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3890 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3891 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3892 /* NOTE: the comma operator will make "cond" to eval to false,
3893 * but float32_unordered() is still called. */
3894 FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3895 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3896 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3897 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3898 FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3899 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3900 FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status))
3901 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3903 #define FOP_COND_PS(op, condl, condh) \
3904 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3905 uint64_t fdt1, int cc) \
3907 uint32_t fst0, fsth0, fst1, fsth1; \
3908 int ch, cl; \
3909 fst0 = fdt0 & 0XFFFFFFFF; \
3910 fsth0 = fdt0 >> 32; \
3911 fst1 = fdt1 & 0XFFFFFFFF; \
3912 fsth1 = fdt1 >> 32; \
3913 cl = condl; \
3914 ch = condh; \
3915 update_fcr31(env, GETPC()); \
3916 if (cl) \
3917 SET_FP_COND(cc, env->active_fpu); \
3918 else \
3919 CLEAR_FP_COND(cc, env->active_fpu); \
3920 if (ch) \
3921 SET_FP_COND(cc + 1, env->active_fpu); \
3922 else \
3923 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3925 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3926 uint64_t fdt1, int cc) \
3928 uint32_t fst0, fsth0, fst1, fsth1; \
3929 int ch, cl; \
3930 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
3931 fsth0 = float32_abs(fdt0 >> 32); \
3932 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3933 fsth1 = float32_abs(fdt1 >> 32); \
3934 cl = condl; \
3935 ch = condh; \
3936 update_fcr31(env, GETPC()); \
3937 if (cl) \
3938 SET_FP_COND(cc, env->active_fpu); \
3939 else \
3940 CLEAR_FP_COND(cc, env->active_fpu); \
3941 if (ch) \
3942 SET_FP_COND(cc + 1, env->active_fpu); \
3943 else \
3944 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3947 /* NOTE: the comma operator will make "cond" to eval to false,
3948 * but float32_unordered_quiet() is still called. */
3949 FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3950 (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3951 FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3952 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3953 FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3954 float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3955 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3956 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3957 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3958 float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3959 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3960 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3961 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3962 float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3963 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3964 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3965 /* NOTE: the comma operator will make "cond" to eval to false,
3966 * but float32_unordered() is still called. */
3967 FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3968 (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3969 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3970 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3971 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3972 float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3973 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3974 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3975 FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3976 float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3977 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3978 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3979 FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status),
3980 float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3981 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3982 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3984 /* R6 compare operations */
3985 #define FOP_CONDN_D(op, cond) \
3986 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
3987 uint64_t fdt1) \
3989 uint64_t c; \
3990 c = cond; \
3991 update_fcr31(env, GETPC()); \
3992 if (c) { \
3993 return -1; \
3994 } else { \
3995 return 0; \
3999 /* NOTE: the comma operator will make "cond" to eval to false,
4000 * but float64_unordered_quiet() is still called. */
4001 FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4002 FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
4003 FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4004 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4005 || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4006 FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4007 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4008 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4009 FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4010 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4011 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4012 /* NOTE: the comma operator will make "cond" to eval to false,
4013 * but float64_unordered() is still called. */
4014 FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4015 FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
4016 FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
4017 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4018 || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
4019 FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4020 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4021 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4022 FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4023 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4024 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4025 FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4026 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4027 FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4028 || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4029 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4030 FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4031 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4032 FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
4033 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4034 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4035 || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
4036 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4037 FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
4038 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4040 #define FOP_CONDN_S(op, cond) \
4041 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
4042 uint32_t fst1) \
4044 uint64_t c; \
4045 c = cond; \
4046 update_fcr31(env, GETPC()); \
4047 if (c) { \
4048 return -1; \
4049 } else { \
4050 return 0; \
4054 /* NOTE: the comma operator will make "cond" to eval to false,
4055 * but float32_unordered_quiet() is still called. */
4056 FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
4057 FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
4058 FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4059 FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4060 || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4061 FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4062 FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4063 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4064 FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4065 FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4066 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4067 /* NOTE: the comma operator will make "cond" to eval to false,
4068 * but float32_unordered() is still called. */
4069 FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
4070 FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
4071 FOP_CONDN_S(seq, (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
4072 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4073 || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
4074 FOP_CONDN_S(slt, (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4075 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4076 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4077 FOP_CONDN_S(sle, (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4078 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4079 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4080 FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
4081 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4082 FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4083 || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
4084 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4085 FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
4086 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4087 FOP_CONDN_S(sor, (float32_le(fst1, fst0, &env->active_fpu.fp_status)
4088 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4089 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4090 || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
4091 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4092 FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
4093 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4095 /* MSA */
4096 /* Data format min and max values */
4097 #define DF_BITS(df) (1 << ((df) + 3))
4099 /* Element-by-element access macros */
4100 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
4102 #if !defined(CONFIG_USER_ONLY)
4103 #define MEMOP_IDX(DF) \
4104 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
4105 cpu_mmu_index(env, false));
4106 #else
4107 #define MEMOP_IDX(DF)
4108 #endif
4110 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
4111 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4112 target_ulong addr) \
4114 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4115 wr_t wx; \
4116 int i; \
4117 MEMOP_IDX(DF) \
4118 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4119 wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
4121 memcpy(pwd, &wx, sizeof(wr_t)); \
4124 #if !defined(CONFIG_USER_ONLY)
4125 MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, oi, GETPC())
4126 MSA_LD_DF(DF_HALF, h, helper_ret_lduw_mmu, oi, GETPC())
4127 MSA_LD_DF(DF_WORD, w, helper_ret_ldul_mmu, oi, GETPC())
4128 MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu, oi, GETPC())
4129 #else
4130 MSA_LD_DF(DF_BYTE, b, cpu_ldub_data)
4131 MSA_LD_DF(DF_HALF, h, cpu_lduw_data)
4132 MSA_LD_DF(DF_WORD, w, cpu_ldl_data)
4133 MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
4134 #endif
4136 #define MSA_PAGESPAN(x) \
4137 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
4139 static inline void ensure_writable_pages(CPUMIPSState *env,
4140 target_ulong addr,
4141 int mmu_idx,
4142 uintptr_t retaddr)
4144 #if !defined(CONFIG_USER_ONLY)
4145 target_ulong page_addr;
4146 if (unlikely(MSA_PAGESPAN(addr))) {
4147 /* first page */
4148 probe_write(env, addr, mmu_idx, retaddr);
4149 /* second page */
4150 page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4151 probe_write(env, page_addr, mmu_idx, retaddr);
4153 #endif
4156 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
4157 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4158 target_ulong addr) \
4160 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4161 int mmu_idx = cpu_mmu_index(env, false); \
4162 int i; \
4163 MEMOP_IDX(DF) \
4164 ensure_writable_pages(env, addr, mmu_idx, GETPC()); \
4165 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4166 ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
4170 #if !defined(CONFIG_USER_ONLY)
4171 MSA_ST_DF(DF_BYTE, b, helper_ret_stb_mmu, oi, GETPC())
4172 MSA_ST_DF(DF_HALF, h, helper_ret_stw_mmu, oi, GETPC())
4173 MSA_ST_DF(DF_WORD, w, helper_ret_stl_mmu, oi, GETPC())
4174 MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETPC())
4175 #else
4176 MSA_ST_DF(DF_BYTE, b, cpu_stb_data)
4177 MSA_ST_DF(DF_HALF, h, cpu_stw_data)
4178 MSA_ST_DF(DF_WORD, w, cpu_stl_data)
4179 MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
4180 #endif
4182 void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
4184 #ifndef CONFIG_USER_ONLY
4185 target_ulong index = addr & 0x1fffffff;
4186 if (op == 9) {
4187 /* Index Store Tag */
4188 memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
4189 8, MEMTXATTRS_UNSPECIFIED);
4190 } else if (op == 5) {
4191 /* Index Load Tag */
4192 memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
4193 8, MEMTXATTRS_UNSPECIFIED);
4195 #endif