2 * ARM implementation of KVM hooks, 64 bit specific code
4 * Copyright Mian-M. Hamayun 2013, Virtual Open Systems
5 * Copyright Alex Bennée 2014, Linaro
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
12 #include "qemu/osdep.h"
13 #include <sys/ioctl.h>
14 #include <sys/ptrace.h>
16 #include <linux/elf.h>
17 #include <linux/kvm.h>
19 #include "qemu-common.h"
21 #include "qemu/timer.h"
22 #include "qemu/error-report.h"
23 #include "qemu/host-utils.h"
24 #include "exec/gdbstub.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/kvm.h"
28 #include "internals.h"
29 #include "hw/arm/arm.h"
31 static bool have_guest_debug
;
34 * Although the ARM implementation of hardware assisted debugging
35 * allows for different breakpoints per-core, the current GDB
36 * interface treats them as a global pool of registers (which seems to
37 * be the case for x86, ppc and s390). As a result we store one copy
38 * of registers which is used for all active cores.
40 * Write access is serialised by virtue of the GDB protocol which
41 * updates things. Read access (i.e. when the values are copied to the
42 * vCPU) is also gated by GDB's run control.
44 * This is not unreasonable as most of the time debugging kernels you
45 * never know which core will eventually execute your function.
53 /* The watchpoint registers can cover more area than the requested
54 * watchpoint so we need to store the additional information
55 * somewhere. We also need to supply a CPUWatchpoint to the GDB stub
56 * when the watchpoint is hit.
61 CPUWatchpoint details
;
64 /* Maximum and current break/watch point counts */
65 int max_hw_bps
, max_hw_wps
;
66 GArray
*hw_breakpoints
, *hw_watchpoints
;
68 #define cur_hw_wps (hw_watchpoints->len)
69 #define cur_hw_bps (hw_breakpoints->len)
70 #define get_hw_bp(i) (&g_array_index(hw_breakpoints, HWBreakpoint, i))
71 #define get_hw_wp(i) (&g_array_index(hw_watchpoints, HWWatchpoint, i))
74 * kvm_arm_init_debug() - check for guest debug capabilities
77 * kvm_check_extension returns the number of debug registers we have
78 * or 0 if we have none.
81 static void kvm_arm_init_debug(CPUState
*cs
)
83 have_guest_debug
= kvm_check_extension(cs
->kvm_state
,
84 KVM_CAP_SET_GUEST_DEBUG
);
86 max_hw_wps
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_GUEST_DEBUG_HW_WPS
);
87 hw_watchpoints
= g_array_sized_new(true, true,
88 sizeof(HWWatchpoint
), max_hw_wps
);
90 max_hw_bps
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_GUEST_DEBUG_HW_BPS
);
91 hw_breakpoints
= g_array_sized_new(true, true,
92 sizeof(HWBreakpoint
), max_hw_bps
);
97 * insert_hw_breakpoint()
98 * @addr: address of breakpoint
100 * See ARM ARM D2.9.1 for details but here we are only going to create
101 * simple un-linked breakpoints (i.e. we don't chain breakpoints
102 * together to match address and context or vmid). The hardware is
103 * capable of fancier matching but that will require exposing that
104 * fanciness to GDB's interface
106 * D7.3.2 DBGBCR<n>_EL1, Debug Breakpoint Control Registers
108 * 31 24 23 20 19 16 15 14 13 12 9 8 5 4 3 2 1 0
109 * +------+------+-------+-----+----+------+-----+------+-----+---+
110 * | RES0 | BT | LBN | SSC | HMC| RES0 | BAS | RES0 | PMC | E |
111 * +------+------+-------+-----+----+------+-----+------+-----+---+
113 * BT: Breakpoint type (0 = unlinked address match)
114 * LBN: Linked BP number (0 = unused)
115 * SSC/HMC/PMC: Security, Higher and Priv access control (Table D-12)
116 * BAS: Byte Address Select (RES1 for AArch64)
119 static int insert_hw_breakpoint(target_ulong addr
)
122 .bcr
= 0x1, /* BCR E=1, enable */
126 if (cur_hw_bps
>= max_hw_bps
) {
130 brk
.bcr
= deposit32(brk
.bcr
, 1, 2, 0x3); /* PMC = 11 */
131 brk
.bcr
= deposit32(brk
.bcr
, 5, 4, 0xf); /* BAS = RES1 */
133 g_array_append_val(hw_breakpoints
, brk
);
139 * delete_hw_breakpoint()
140 * @pc: address of breakpoint
142 * Delete a breakpoint and shuffle any above down
145 static int delete_hw_breakpoint(target_ulong pc
)
148 for (i
= 0; i
< hw_breakpoints
->len
; i
++) {
149 HWBreakpoint
*brk
= get_hw_bp(i
);
150 if (brk
->bvr
== pc
) {
151 g_array_remove_index(hw_breakpoints
, i
);
159 * insert_hw_watchpoint()
160 * @addr: address of watch point
162 * @type: type of watch point
164 * See ARM ARM D2.10. As with the breakpoints we can do some advanced
165 * stuff if we want to. The watch points can be linked with the break
166 * points above to make them context aware. However for simplicity
167 * currently we only deal with simple read/write watch points.
169 * D7.3.11 DBGWCR<n>_EL1, Debug Watchpoint Control Registers
171 * 31 29 28 24 23 21 20 19 16 15 14 13 12 5 4 3 2 1 0
172 * +------+-------+------+----+-----+-----+-----+-----+-----+-----+---+
173 * | RES0 | MASK | RES0 | WT | LBN | SSC | HMC | BAS | LSC | PAC | E |
174 * +------+-------+------+----+-----+-----+-----+-----+-----+-----+---+
176 * MASK: num bits addr mask (0=none,01/10=res,11=3 bits (8 bytes))
177 * WT: 0 - unlinked, 1 - linked (not currently used)
178 * LBN: Linked BP number (not currently used)
179 * SSC/HMC/PAC: Security, Higher and Priv access control (Table D2-11)
180 * BAS: Byte Address Select
181 * LSC: Load/Store control (01: load, 10: store, 11: both)
184 * The bottom 2 bits of the value register are masked. Therefore to
185 * break on any sizes smaller than an unaligned word you need to set
186 * MASK=0, BAS=bit per byte in question. For larger regions (^2) you
187 * need to ensure you mask the address as required and set BAS=0xff
190 static int insert_hw_watchpoint(target_ulong addr
,
191 target_ulong len
, int type
)
194 .wcr
= 1, /* E=1, enable */
195 .wvr
= addr
& (~0x7ULL
),
196 .details
= { .vaddr
= addr
, .len
= len
}
199 if (cur_hw_wps
>= max_hw_wps
) {
204 * HMC=0 SSC=0 PAC=3 will hit EL0 or EL1, any security state,
205 * valid whether EL3 is implemented or not
207 wp
.wcr
= deposit32(wp
.wcr
, 1, 2, 3);
210 case GDB_WATCHPOINT_READ
:
211 wp
.wcr
= deposit32(wp
.wcr
, 3, 2, 1);
212 wp
.details
.flags
= BP_MEM_READ
;
214 case GDB_WATCHPOINT_WRITE
:
215 wp
.wcr
= deposit32(wp
.wcr
, 3, 2, 2);
216 wp
.details
.flags
= BP_MEM_WRITE
;
218 case GDB_WATCHPOINT_ACCESS
:
219 wp
.wcr
= deposit32(wp
.wcr
, 3, 2, 3);
220 wp
.details
.flags
= BP_MEM_ACCESS
;
223 g_assert_not_reached();
227 /* we align the address and set the bits in BAS */
228 int off
= addr
& 0x7;
229 int bas
= (1 << len
) - 1;
231 wp
.wcr
= deposit32(wp
.wcr
, 5 + off
, 8 - off
, bas
);
233 /* For ranges above 8 bytes we need to be a power of 2 */
234 if (is_power_of_2(len
)) {
235 int bits
= ctz64(len
);
237 wp
.wvr
&= ~((1 << bits
) - 1);
238 wp
.wcr
= deposit32(wp
.wcr
, 24, 4, bits
);
239 wp
.wcr
= deposit32(wp
.wcr
, 5, 8, 0xff);
245 g_array_append_val(hw_watchpoints
, wp
);
250 static bool check_watchpoint_in_range(int i
, target_ulong addr
)
252 HWWatchpoint
*wp
= get_hw_wp(i
);
253 uint64_t addr_top
, addr_bottom
= wp
->wvr
;
254 int bas
= extract32(wp
->wcr
, 5, 8);
255 int mask
= extract32(wp
->wcr
, 24, 4);
258 addr_top
= addr_bottom
+ (1 << mask
);
260 /* BAS must be contiguous but can offset against the base
261 * address in DBGWVR */
262 addr_bottom
= addr_bottom
+ ctz32(bas
);
263 addr_top
= addr_bottom
+ clo32(bas
);
266 if (addr
>= addr_bottom
&& addr
<= addr_top
) {
274 * delete_hw_watchpoint()
275 * @addr: address of breakpoint
277 * Delete a breakpoint and shuffle any above down
280 static int delete_hw_watchpoint(target_ulong addr
,
281 target_ulong len
, int type
)
284 for (i
= 0; i
< cur_hw_wps
; i
++) {
285 if (check_watchpoint_in_range(i
, addr
)) {
286 g_array_remove_index(hw_watchpoints
, i
);
294 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
295 target_ulong len
, int type
)
298 case GDB_BREAKPOINT_HW
:
299 return insert_hw_breakpoint(addr
);
301 case GDB_WATCHPOINT_READ
:
302 case GDB_WATCHPOINT_WRITE
:
303 case GDB_WATCHPOINT_ACCESS
:
304 return insert_hw_watchpoint(addr
, len
, type
);
310 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
311 target_ulong len
, int type
)
314 case GDB_BREAKPOINT_HW
:
315 return delete_hw_breakpoint(addr
);
317 case GDB_WATCHPOINT_READ
:
318 case GDB_WATCHPOINT_WRITE
:
319 case GDB_WATCHPOINT_ACCESS
:
320 return delete_hw_watchpoint(addr
, len
, type
);
327 void kvm_arch_remove_all_hw_breakpoints(void)
329 if (cur_hw_wps
> 0) {
330 g_array_remove_range(hw_watchpoints
, 0, cur_hw_wps
);
332 if (cur_hw_bps
> 0) {
333 g_array_remove_range(hw_breakpoints
, 0, cur_hw_bps
);
337 void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch
*ptr
)
340 memset(ptr
, 0, sizeof(struct kvm_guest_debug_arch
));
342 for (i
= 0; i
< max_hw_wps
; i
++) {
343 HWWatchpoint
*wp
= get_hw_wp(i
);
344 ptr
->dbg_wcr
[i
] = wp
->wcr
;
345 ptr
->dbg_wvr
[i
] = wp
->wvr
;
347 for (i
= 0; i
< max_hw_bps
; i
++) {
348 HWBreakpoint
*bp
= get_hw_bp(i
);
349 ptr
->dbg_bcr
[i
] = bp
->bcr
;
350 ptr
->dbg_bvr
[i
] = bp
->bvr
;
354 bool kvm_arm_hw_debug_active(CPUState
*cs
)
356 return ((cur_hw_wps
> 0) || (cur_hw_bps
> 0));
359 static bool find_hw_breakpoint(CPUState
*cpu
, target_ulong pc
)
363 for (i
= 0; i
< cur_hw_bps
; i
++) {
364 HWBreakpoint
*bp
= get_hw_bp(i
);
372 static CPUWatchpoint
*find_hw_watchpoint(CPUState
*cpu
, target_ulong addr
)
376 for (i
= 0; i
< cur_hw_wps
; i
++) {
377 if (check_watchpoint_in_range(i
, addr
)) {
378 return &get_hw_wp(i
)->details
;
384 static bool kvm_arm_pmu_set_attr(CPUState
*cs
, struct kvm_device_attr
*attr
)
388 err
= kvm_vcpu_ioctl(cs
, KVM_HAS_DEVICE_ATTR
, attr
);
390 error_report("PMU: KVM_HAS_DEVICE_ATTR: %s", strerror(-err
));
394 err
= kvm_vcpu_ioctl(cs
, KVM_SET_DEVICE_ATTR
, attr
);
396 error_report("PMU: KVM_SET_DEVICE_ATTR: %s", strerror(-err
));
403 void kvm_arm_pmu_init(CPUState
*cs
)
405 struct kvm_device_attr attr
= {
406 .group
= KVM_ARM_VCPU_PMU_V3_CTRL
,
407 .attr
= KVM_ARM_VCPU_PMU_V3_INIT
,
410 if (!ARM_CPU(cs
)->has_pmu
) {
413 if (!kvm_arm_pmu_set_attr(cs
, &attr
)) {
414 error_report("failed to init PMU");
419 void kvm_arm_pmu_set_irq(CPUState
*cs
, int irq
)
421 struct kvm_device_attr attr
= {
422 .group
= KVM_ARM_VCPU_PMU_V3_CTRL
,
423 .addr
= (intptr_t)&irq
,
424 .attr
= KVM_ARM_VCPU_PMU_V3_IRQ
,
427 if (!ARM_CPU(cs
)->has_pmu
) {
430 if (!kvm_arm_pmu_set_attr(cs
, &attr
)) {
431 error_report("failed to set irq for PMU");
436 static inline void set_feature(uint64_t *features
, int feature
)
438 *features
|= 1ULL << feature
;
441 static inline void unset_feature(uint64_t *features
, int feature
)
443 *features
&= ~(1ULL << feature
);
446 bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures
*ahcf
)
448 /* Identify the feature bits corresponding to the host CPU, and
449 * fill out the ARMHostCPUClass fields accordingly. To do this
450 * we have to create a scratch VM, create a single CPU inside it,
451 * and then query that CPU for the relevant ID registers.
452 * For AArch64 we currently don't care about ID registers at
453 * all; we just want to know the CPU type.
456 uint64_t features
= 0;
457 /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
458 * we know these will only support creating one kind of guest CPU,
459 * which is its preferred CPU type. Fortunately these old kernels
460 * support only a very limited number of CPUs.
462 static const uint32_t cpus_to_try
[] = {
463 KVM_ARM_TARGET_AEM_V8
,
464 KVM_ARM_TARGET_FOUNDATION_V8
,
465 KVM_ARM_TARGET_CORTEX_A57
,
466 QEMU_KVM_ARM_TARGET_NONE
468 struct kvm_vcpu_init init
;
470 if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try
, fdarray
, &init
)) {
474 ahcf
->target
= init
.target
;
475 ahcf
->dtb_compatible
= "arm,arm-v8";
477 kvm_arm_destroy_scratch_host_vcpu(fdarray
);
479 /* We can assume any KVM supporting CPU is at least a v8
480 * with VFPv4+Neon; this in turn implies most of the other
483 set_feature(&features
, ARM_FEATURE_V8
);
484 set_feature(&features
, ARM_FEATURE_VFP4
);
485 set_feature(&features
, ARM_FEATURE_NEON
);
486 set_feature(&features
, ARM_FEATURE_AARCH64
);
487 set_feature(&features
, ARM_FEATURE_PMU
);
489 ahcf
->features
= features
;
494 #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
496 int kvm_arch_init_vcpu(CPUState
*cs
)
500 ARMCPU
*cpu
= ARM_CPU(cs
);
501 CPUARMState
*env
= &cpu
->env
;
503 if (cpu
->kvm_target
== QEMU_KVM_ARM_TARGET_NONE
||
504 !object_dynamic_cast(OBJECT(cpu
), TYPE_AARCH64_CPU
)) {
505 fprintf(stderr
, "KVM is not supported for this guest CPU type\n");
509 /* Determine init features for this CPU */
510 memset(cpu
->kvm_init_features
, 0, sizeof(cpu
->kvm_init_features
));
511 if (cpu
->start_powered_off
) {
512 cpu
->kvm_init_features
[0] |= 1 << KVM_ARM_VCPU_POWER_OFF
;
514 if (kvm_check_extension(cs
->kvm_state
, KVM_CAP_ARM_PSCI_0_2
)) {
515 cpu
->psci_version
= 2;
516 cpu
->kvm_init_features
[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2
;
518 if (!arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
519 cpu
->kvm_init_features
[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT
;
521 if (!kvm_check_extension(cs
->kvm_state
, KVM_CAP_ARM_PMU_V3
)) {
522 cpu
->has_pmu
= false;
525 cpu
->kvm_init_features
[0] |= 1 << KVM_ARM_VCPU_PMU_V3
;
527 unset_feature(&env
->features
, ARM_FEATURE_PMU
);
530 /* Do KVM_ARM_VCPU_INIT ioctl */
531 ret
= kvm_arm_vcpu_init(cs
);
537 * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
538 * Currently KVM has its own idea about MPIDR assignment, so we
539 * override our defaults with what we get from KVM.
541 ret
= kvm_get_one_reg(cs
, ARM64_SYS_REG(ARM_CPU_ID_MPIDR
), &mpidr
);
545 cpu
->mp_affinity
= mpidr
& ARM64_AFFINITY_MASK
;
547 kvm_arm_init_debug(cs
);
549 return kvm_arm_init_cpreg_list(cpu
);
552 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx
)
554 /* Return true if the regidx is a register we should synchronize
555 * via the cpreg_tuples array (ie is not a core reg we sync by
556 * hand in kvm_arch_get/put_registers())
558 switch (regidx
& KVM_REG_ARM_COPROC_MASK
) {
559 case KVM_REG_ARM_CORE
:
566 typedef struct CPRegStateLevel
{
571 /* All system registers not listed in the following table are assumed to be
572 * of the level KVM_PUT_RUNTIME_STATE. If a register should be written less
573 * often, you must add it to this table with a state of either
574 * KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE.
576 static const CPRegStateLevel non_runtime_cpregs
[] = {
577 { KVM_REG_ARM_TIMER_CNT
, KVM_PUT_FULL_STATE
},
580 int kvm_arm_cpreg_level(uint64_t regidx
)
584 for (i
= 0; i
< ARRAY_SIZE(non_runtime_cpregs
); i
++) {
585 const CPRegStateLevel
*l
= &non_runtime_cpregs
[i
];
586 if (l
->regidx
== regidx
) {
591 return KVM_PUT_RUNTIME_STATE
;
594 #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
595 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
597 #define AARCH64_SIMD_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \
598 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
600 #define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \
601 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
603 int kvm_arch_put_registers(CPUState
*cs
, int level
)
605 struct kvm_one_reg reg
;
612 ARMCPU
*cpu
= ARM_CPU(cs
);
613 CPUARMState
*env
= &cpu
->env
;
615 /* If we are in AArch32 mode then we need to copy the AArch32 regs to the
616 * AArch64 registers before pushing them out to 64-bit KVM.
619 aarch64_sync_32_to_64(env
);
622 for (i
= 0; i
< 31; i
++) {
623 reg
.id
= AARCH64_CORE_REG(regs
.regs
[i
]);
624 reg
.addr
= (uintptr_t) &env
->xregs
[i
];
625 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
631 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
632 * QEMU side we keep the current SP in xregs[31] as well.
634 aarch64_save_sp(env
, 1);
636 reg
.id
= AARCH64_CORE_REG(regs
.sp
);
637 reg
.addr
= (uintptr_t) &env
->sp_el
[0];
638 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
643 reg
.id
= AARCH64_CORE_REG(sp_el1
);
644 reg
.addr
= (uintptr_t) &env
->sp_el
[1];
645 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
650 /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */
652 val
= pstate_read(env
);
654 val
= cpsr_read(env
);
656 reg
.id
= AARCH64_CORE_REG(regs
.pstate
);
657 reg
.addr
= (uintptr_t) &val
;
658 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
663 reg
.id
= AARCH64_CORE_REG(regs
.pc
);
664 reg
.addr
= (uintptr_t) &env
->pc
;
665 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
670 reg
.id
= AARCH64_CORE_REG(elr_el1
);
671 reg
.addr
= (uintptr_t) &env
->elr_el
[1];
672 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
677 /* Saved Program State Registers
679 * Before we restore from the banked_spsr[] array we need to
680 * ensure that any modifications to env->spsr are correctly
681 * reflected in the banks.
683 el
= arm_current_el(env
);
684 if (el
> 0 && !is_a64(env
)) {
685 i
= bank_number(env
->uncached_cpsr
& CPSR_M
);
686 env
->banked_spsr
[i
] = env
->spsr
;
689 /* KVM 0-4 map to QEMU banks 1-5 */
690 for (i
= 0; i
< KVM_NR_SPSR
; i
++) {
691 reg
.id
= AARCH64_CORE_REG(spsr
[i
]);
692 reg
.addr
= (uintptr_t) &env
->banked_spsr
[i
+ 1];
693 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
699 /* Advanced SIMD and FP registers. */
700 for (i
= 0; i
< 32; i
++) {
701 uint64_t *q
= aa64_vfp_qreg(env
, i
);
702 #ifdef HOST_WORDS_BIGENDIAN
703 uint64_t fp_val
[2] = { q
[1], q
[0] };
704 reg
.addr
= (uintptr_t)fp_val
;
706 reg
.addr
= (uintptr_t)q
;
708 reg
.id
= AARCH64_SIMD_CORE_REG(fp_regs
.vregs
[i
]);
709 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
715 reg
.addr
= (uintptr_t)(&fpr
);
716 fpr
= vfp_get_fpsr(env
);
717 reg
.id
= AARCH64_SIMD_CTRL_REG(fp_regs
.fpsr
);
718 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
723 fpr
= vfp_get_fpcr(env
);
724 reg
.id
= AARCH64_SIMD_CTRL_REG(fp_regs
.fpcr
);
725 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
730 if (!write_list_to_kvmstate(cpu
, level
)) {
734 kvm_arm_sync_mpstate_to_kvm(cpu
);
739 int kvm_arch_get_registers(CPUState
*cs
)
741 struct kvm_one_reg reg
;
748 ARMCPU
*cpu
= ARM_CPU(cs
);
749 CPUARMState
*env
= &cpu
->env
;
751 for (i
= 0; i
< 31; i
++) {
752 reg
.id
= AARCH64_CORE_REG(regs
.regs
[i
]);
753 reg
.addr
= (uintptr_t) &env
->xregs
[i
];
754 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
760 reg
.id
= AARCH64_CORE_REG(regs
.sp
);
761 reg
.addr
= (uintptr_t) &env
->sp_el
[0];
762 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
767 reg
.id
= AARCH64_CORE_REG(sp_el1
);
768 reg
.addr
= (uintptr_t) &env
->sp_el
[1];
769 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
774 reg
.id
= AARCH64_CORE_REG(regs
.pstate
);
775 reg
.addr
= (uintptr_t) &val
;
776 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
781 env
->aarch64
= ((val
& PSTATE_nRW
) == 0);
783 pstate_write(env
, val
);
785 cpsr_write(env
, val
, 0xffffffff, CPSRWriteRaw
);
788 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
789 * QEMU side we keep the current SP in xregs[31] as well.
791 aarch64_restore_sp(env
, 1);
793 reg
.id
= AARCH64_CORE_REG(regs
.pc
);
794 reg
.addr
= (uintptr_t) &env
->pc
;
795 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
800 /* If we are in AArch32 mode then we need to sync the AArch32 regs with the
801 * incoming AArch64 regs received from 64-bit KVM.
802 * We must perform this after all of the registers have been acquired from
806 aarch64_sync_64_to_32(env
);
809 reg
.id
= AARCH64_CORE_REG(elr_el1
);
810 reg
.addr
= (uintptr_t) &env
->elr_el
[1];
811 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
816 /* Fetch the SPSR registers
818 * KVM SPSRs 0-4 map to QEMU banks 1-5
820 for (i
= 0; i
< KVM_NR_SPSR
; i
++) {
821 reg
.id
= AARCH64_CORE_REG(spsr
[i
]);
822 reg
.addr
= (uintptr_t) &env
->banked_spsr
[i
+ 1];
823 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
829 el
= arm_current_el(env
);
830 if (el
> 0 && !is_a64(env
)) {
831 i
= bank_number(env
->uncached_cpsr
& CPSR_M
);
832 env
->spsr
= env
->banked_spsr
[i
];
835 /* Advanced SIMD and FP registers */
836 for (i
= 0; i
< 32; i
++) {
837 uint64_t *q
= aa64_vfp_qreg(env
, i
);
838 reg
.id
= AARCH64_SIMD_CORE_REG(fp_regs
.vregs
[i
]);
839 reg
.addr
= (uintptr_t)q
;
840 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
844 #ifdef HOST_WORDS_BIGENDIAN
846 t
= q
[0], q
[0] = q
[1], q
[1] = t
;
851 reg
.addr
= (uintptr_t)(&fpr
);
852 reg
.id
= AARCH64_SIMD_CTRL_REG(fp_regs
.fpsr
);
853 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
857 vfp_set_fpsr(env
, fpr
);
859 reg
.id
= AARCH64_SIMD_CTRL_REG(fp_regs
.fpcr
);
860 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
864 vfp_set_fpcr(env
, fpr
);
866 if (!write_kvmstate_to_list(cpu
)) {
869 /* Note that it's OK to have registers which aren't in CPUState,
870 * so we can ignore a failure return here.
872 write_list_to_cpustate(cpu
);
874 kvm_arm_sync_mpstate_to_qemu(cpu
);
876 /* TODO: other registers */
880 /* C6.6.29 BRK instruction */
881 static const uint32_t brk_insn
= 0xd4200000;
883 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
885 if (have_guest_debug
) {
886 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 4, 0) ||
887 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&brk_insn
, 4, 1)) {
892 error_report("guest debug not supported on this kernel");
897 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
901 if (have_guest_debug
) {
902 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&brk
, 4, 0) ||
904 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 4, 1)) {
909 error_report("guest debug not supported on this kernel");
914 /* See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register
916 * To minimise translating between kernel and user-space the kernel
917 * ABI just provides user-space with the full exception syndrome
918 * register value to be decoded in QEMU.
921 bool kvm_arm_handle_debug(CPUState
*cs
, struct kvm_debug_exit_arch
*debug_exit
)
923 int hsr_ec
= debug_exit
->hsr
>> ARM_EL_EC_SHIFT
;
924 ARMCPU
*cpu
= ARM_CPU(cs
);
925 CPUClass
*cc
= CPU_GET_CLASS(cs
);
926 CPUARMState
*env
= &cpu
->env
;
928 /* Ensure PC is synchronised */
929 kvm_cpu_synchronize_state(cs
);
932 case EC_SOFTWARESTEP
:
933 if (cs
->singlestep_enabled
) {
937 * The kernel should have suppressed the guest's ability to
938 * single step at this point so something has gone wrong.
940 error_report("%s: guest single-step while debugging unsupported"
941 " (%"PRIx64
", %"PRIx32
")",
942 __func__
, env
->pc
, debug_exit
->hsr
);
947 if (kvm_find_sw_breakpoint(cs
, env
->pc
)) {
952 if (find_hw_breakpoint(cs
, env
->pc
)) {
958 CPUWatchpoint
*wp
= find_hw_watchpoint(cs
, debug_exit
->far
);
960 cs
->watchpoint_hit
= wp
;
966 error_report("%s: unhandled debug exit (%"PRIx32
", %"PRIx64
")",
967 __func__
, debug_exit
->hsr
, env
->pc
);
970 /* If we are not handling the debug exception it must belong to
971 * the guest. Let's re-use the existing TCG interrupt code to set
972 * everything up properly.
974 cs
->exception_index
= EXCP_BKPT
;
975 env
->exception
.syndrome
= debug_exit
->hsr
;
976 env
->exception
.vaddress
= debug_exit
->far
;
977 cc
->do_interrupt(cs
);