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HEAD
hw/dma: Implement a Xilinx CSU DMA model
[qemu/ar7.git]
/
tests
/
tcg
/
lm32
/
test_muli.S
blob
d6dd4a0f7ecc64d7ef2207a327cbe46ba6b060e5
1
.include "macros.inc"
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3
start
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test_name MULI_1
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mvi r1, 0
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muli r3, r1, 0
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check_r3 0
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test_name MULI_2
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mvi r1, 1
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muli r3, r1, 0
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check_r3 0
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test_name MULI_3
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mvi r1, 0
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muli r3, r1, 1
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check_r3 0
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test_name MULI_4
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mvi r1, 1
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muli r3, r1, 1
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check_r3 1
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test_name MULI_5
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mvi r1, 2
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muli r3, r1, -1
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check_r3 -2
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test_name MULI_6
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mvi r1, -2
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muli r3, r1, -1
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check_r3 2
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test_name MULI_7
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mvi r1, 0x1234
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muli r3, r1, 0x789
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check_r3 0x8929d4
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test_name MULI_8
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mvi r3, 4
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muli r3, r3, 4
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check_r3 16
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end