hw/dma: Implement a Xilinx CSU DMA model
[qemu/ar7.git] / scripts / tracetool / backend / syslog.py
blob5a3a00fe310ae721d2292e4a6a0620551f9036f5
1 # -*- coding: utf-8 -*-
3 """
4 Syslog built-in backend.
5 """
7 __author__ = "Paul Durrant <paul.durrant@citrix.com>"
8 __copyright__ = "Copyright 2016, Citrix Systems Inc."
9 __license__ = "GPL version 2 or (at your option) any later version"
11 __maintainer__ = "Stefan Hajnoczi"
12 __email__ = "stefanha@redhat.com"
15 from tracetool import out
18 PUBLIC = True
21 def generate_h_begin(events, group):
22 out('#include <syslog.h>',
23 '')
26 def generate_h(event, group):
27 argnames = ", ".join(event.args.names())
28 if len(event.args) > 0:
29 argnames = ", " + argnames
31 if "vcpu" in event.properties:
32 # already checked on the generic format code
33 cond = "true"
34 else:
35 cond = "trace_event_get_state(%s)" % ("TRACE_" + event.name.upper())
37 out(' if (%(cond)s) {',
38 '#line %(event_lineno)d "%(event_filename)s"',
39 ' syslog(LOG_INFO, "%(name)s " %(fmt)s %(argnames)s);',
40 '#line %(out_next_lineno)d "%(out_filename)s"',
41 ' }',
42 cond=cond,
43 event_lineno=event.lineno,
44 event_filename=event.filename,
45 name=event.name,
46 fmt=event.fmt.rstrip("\n"),
47 argnames=argnames)
50 def generate_h_backend_dstate(event, group):
51 out(' trace_event_get_state_dynamic_by_id(%(event_id)s) || \\',
52 event_id="TRACE_" + event.name.upper())