4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
26 #include "translate.h"
27 #include "internals.h"
28 #include "qemu/host-utils.h"
30 #include "exec/semihost.h"
31 #include "exec/gen-icount.h"
33 #include "exec/helper-proto.h"
34 #include "exec/helper-gen.h"
37 #include "trace-tcg.h"
39 static TCGv_i64 cpu_X
[32];
40 static TCGv_i64 cpu_pc
;
42 /* Load/store exclusive handling */
43 static TCGv_i64 cpu_exclusive_high
;
44 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
);
46 static const char *regnames
[] = {
47 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
48 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
49 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
50 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
54 A64_SHIFT_TYPE_LSL
= 0,
55 A64_SHIFT_TYPE_LSR
= 1,
56 A64_SHIFT_TYPE_ASR
= 2,
57 A64_SHIFT_TYPE_ROR
= 3
60 /* Table based decoder typedefs - used when the relevant bits for decode
61 * are too awkwardly scattered across the instruction (eg SIMD).
63 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
65 typedef struct AArch64DecodeTable
{
68 AArch64DecodeFn
*disas_fn
;
71 /* Function prototype for gen_ functions for calling Neon helpers */
72 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
73 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
74 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
75 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
76 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
77 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
78 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
79 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
80 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
81 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
82 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
83 typedef void CryptoTwoOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
);
84 typedef void CryptoThreeOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
, TCGv_i32
);
86 /* initialize TCG globals. */
87 void a64_translate_init(void)
91 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
92 offsetof(CPUARMState
, pc
),
94 for (i
= 0; i
< 32; i
++) {
95 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, xregs
[i
]),
100 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
101 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
104 static inline int get_a64_user_mem_index(DisasContext
*s
)
106 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
107 * if EL1, access as if EL0; otherwise access at current EL
111 switch (s
->mmu_idx
) {
112 case ARMMMUIdx_S12NSE1
:
113 useridx
= ARMMMUIdx_S12NSE0
;
115 case ARMMMUIdx_S1SE1
:
116 useridx
= ARMMMUIdx_S1SE0
;
119 g_assert_not_reached();
121 useridx
= s
->mmu_idx
;
124 return arm_to_core_mmu_idx(useridx
);
127 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
128 fprintf_function cpu_fprintf
, int flags
)
130 ARMCPU
*cpu
= ARM_CPU(cs
);
131 CPUARMState
*env
= &cpu
->env
;
132 uint32_t psr
= pstate_read(env
);
134 int el
= arm_current_el(env
);
135 const char *ns_status
;
137 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
138 env
->pc
, env
->xregs
[31]);
139 for (i
= 0; i
< 31; i
++) {
140 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
142 cpu_fprintf(f
, "\n");
148 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
149 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
154 cpu_fprintf(f
, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
156 psr
& PSTATE_N
? 'N' : '-',
157 psr
& PSTATE_Z
? 'Z' : '-',
158 psr
& PSTATE_C
? 'C' : '-',
159 psr
& PSTATE_V
? 'V' : '-',
162 psr
& PSTATE_SP
? 'h' : 't');
164 if (flags
& CPU_DUMP_FPU
) {
166 for (i
= 0; i
< numvfpregs
; i
+= 2) {
167 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
168 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
169 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
171 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
172 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
173 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
176 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
177 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
181 void gen_a64_set_pc_im(uint64_t val
)
183 tcg_gen_movi_i64(cpu_pc
, val
);
186 /* Load the PC from a generic TCG variable.
188 * If address tagging is enabled via the TCR TBI bits, then loading
189 * an address into the PC will clear out any tag in the it:
190 * + for EL2 and EL3 there is only one TBI bit, and if it is set
191 * then the address is zero-extended, clearing bits [63:56]
192 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
193 * and TBI1 controls addressses with bit 55 == 1.
194 * If the appropriate TBI bit is set for the address then
195 * the address is sign-extended from bit 55 into bits [63:56]
197 * We can avoid doing this for relative-branches, because the
198 * PC + offset can never overflow into the tag bits (assuming
199 * that virtual addresses are less than 56 bits wide, as they
200 * are currently), but we must handle it for branch-to-register.
202 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
205 if (s
->current_el
<= 1) {
206 /* Test if NEITHER or BOTH TBI values are set. If so, no need to
207 * examine bit 55 of address, can just generate code.
208 * If mixed, then test via generated code
210 if (s
->tbi0
&& s
->tbi1
) {
211 TCGv_i64 tmp_reg
= tcg_temp_new_i64();
212 /* Both bits set, sign extension from bit 55 into [63:56] will
215 tcg_gen_shli_i64(tmp_reg
, src
, 8);
216 tcg_gen_sari_i64(cpu_pc
, tmp_reg
, 8);
217 tcg_temp_free_i64(tmp_reg
);
218 } else if (!s
->tbi0
&& !s
->tbi1
) {
219 /* Neither bit set, just load it as-is */
220 tcg_gen_mov_i64(cpu_pc
, src
);
222 TCGv_i64 tcg_tmpval
= tcg_temp_new_i64();
223 TCGv_i64 tcg_bit55
= tcg_temp_new_i64();
224 TCGv_i64 tcg_zero
= tcg_const_i64(0);
226 tcg_gen_andi_i64(tcg_bit55
, src
, (1ull << 55));
229 /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
230 tcg_gen_andi_i64(tcg_tmpval
, src
,
231 0x00FFFFFFFFFFFFFFull
);
232 tcg_gen_movcond_i64(TCG_COND_EQ
, cpu_pc
, tcg_bit55
, tcg_zero
,
235 /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
236 tcg_gen_ori_i64(tcg_tmpval
, src
,
237 0xFF00000000000000ull
);
238 tcg_gen_movcond_i64(TCG_COND_NE
, cpu_pc
, tcg_bit55
, tcg_zero
,
241 tcg_temp_free_i64(tcg_zero
);
242 tcg_temp_free_i64(tcg_bit55
);
243 tcg_temp_free_i64(tcg_tmpval
);
245 } else { /* EL > 1 */
247 /* Force tag byte to all zero */
248 tcg_gen_andi_i64(cpu_pc
, src
, 0x00FFFFFFFFFFFFFFull
);
250 /* Load unmodified address */
251 tcg_gen_mov_i64(cpu_pc
, src
);
256 typedef struct DisasCompare64
{
261 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
265 arm_test_cc(&c32
, cc
);
267 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
268 * properly. The NE/EQ comparisons are also fine with this choice. */
269 c64
->cond
= c32
.cond
;
270 c64
->value
= tcg_temp_new_i64();
271 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
276 static void a64_free_cc(DisasCompare64
*c64
)
278 tcg_temp_free_i64(c64
->value
);
281 static void gen_exception_internal(int excp
)
283 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
285 assert(excp_is_internal(excp
));
286 gen_helper_exception_internal(cpu_env
, tcg_excp
);
287 tcg_temp_free_i32(tcg_excp
);
290 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
292 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
293 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
294 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
296 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
298 tcg_temp_free_i32(tcg_el
);
299 tcg_temp_free_i32(tcg_syn
);
300 tcg_temp_free_i32(tcg_excp
);
303 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
305 gen_a64_set_pc_im(s
->pc
- offset
);
306 gen_exception_internal(excp
);
307 s
->base
.is_jmp
= DISAS_NORETURN
;
310 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
311 uint32_t syndrome
, uint32_t target_el
)
313 gen_a64_set_pc_im(s
->pc
- offset
);
314 gen_exception(excp
, syndrome
, target_el
);
315 s
->base
.is_jmp
= DISAS_NORETURN
;
318 static void gen_ss_advance(DisasContext
*s
)
320 /* If the singlestep state is Active-not-pending, advance to
325 gen_helper_clear_pstate_ss(cpu_env
);
329 static void gen_step_complete_exception(DisasContext
*s
)
331 /* We just completed step of an insn. Move from Active-not-pending
332 * to Active-pending, and then also take the swstep exception.
333 * This corresponds to making the (IMPDEF) choice to prioritize
334 * swstep exceptions over asynchronous exceptions taken to an exception
335 * level where debug is disabled. This choice has the advantage that
336 * we do not need to maintain internal state corresponding to the
337 * ISV/EX syndrome bits between completion of the step and generation
338 * of the exception, and our syndrome information is always correct.
341 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
342 default_exception_el(s
));
343 s
->base
.is_jmp
= DISAS_NORETURN
;
346 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
348 /* No direct tb linking with singlestep (either QEMU's or the ARM
349 * debug architecture kind) or deterministic io
351 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
352 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
356 #ifndef CONFIG_USER_ONLY
357 /* Only link tbs from inside the same guest page */
358 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
366 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
368 TranslationBlock
*tb
;
371 if (use_goto_tb(s
, n
, dest
)) {
373 gen_a64_set_pc_im(dest
);
374 tcg_gen_exit_tb((intptr_t)tb
+ n
);
375 s
->base
.is_jmp
= DISAS_NORETURN
;
377 gen_a64_set_pc_im(dest
);
379 gen_step_complete_exception(s
);
380 } else if (s
->base
.singlestep_enabled
) {
381 gen_exception_internal(EXCP_DEBUG
);
383 tcg_gen_lookup_and_goto_ptr();
384 s
->base
.is_jmp
= DISAS_NORETURN
;
389 static void unallocated_encoding(DisasContext
*s
)
391 /* Unallocated and reserved encodings are uncategorized */
392 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
393 default_exception_el(s
));
396 #define unsupported_encoding(s, insn) \
398 qemu_log_mask(LOG_UNIMP, \
399 "%s:%d: unsupported instruction encoding 0x%08x " \
400 "at pc=%016" PRIx64 "\n", \
401 __FILE__, __LINE__, insn, s->pc - 4); \
402 unallocated_encoding(s); \
405 static void init_tmp_a64_array(DisasContext
*s
)
407 #ifdef CONFIG_DEBUG_TCG
408 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
410 s
->tmp_a64_count
= 0;
413 static void free_tmp_a64(DisasContext
*s
)
416 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
417 tcg_temp_free_i64(s
->tmp_a64
[i
]);
419 init_tmp_a64_array(s
);
422 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
424 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
425 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
428 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
430 TCGv_i64 t
= new_tmp_a64(s
);
431 tcg_gen_movi_i64(t
, 0);
436 * Register access functions
438 * These functions are used for directly accessing a register in where
439 * changes to the final register value are likely to be made. If you
440 * need to use a register for temporary calculation (e.g. index type
441 * operations) use the read_* form.
443 * B1.2.1 Register mappings
445 * In instruction register encoding 31 can refer to ZR (zero register) or
446 * the SP (stack pointer) depending on context. In QEMU's case we map SP
447 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
448 * This is the point of the _sp forms.
450 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
453 return new_tmp_a64_zero(s
);
459 /* register access for when 31 == SP */
460 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
465 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
466 * representing the register contents. This TCGv is an auto-freed
467 * temporary so it need not be explicitly freed, and may be modified.
469 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
471 TCGv_i64 v
= new_tmp_a64(s
);
474 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
476 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
479 tcg_gen_movi_i64(v
, 0);
484 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
486 TCGv_i64 v
= new_tmp_a64(s
);
488 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
490 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
495 /* We should have at some point before trying to access an FP register
496 * done the necessary access check, so assert that
497 * (a) we did the check and
498 * (b) we didn't then just plough ahead anyway if it failed.
499 * Print the instruction pattern in the abort message so we can figure
500 * out what we need to fix if a user encounters this problem in the wild.
502 static inline void assert_fp_access_checked(DisasContext
*s
)
504 #ifdef CONFIG_DEBUG_TCG
505 if (unlikely(!s
->fp_access_checked
|| s
->fp_excp_el
)) {
506 fprintf(stderr
, "target-arm: FP access check missing for "
507 "instruction 0x%08x\n", s
->insn
);
513 /* Return the offset into CPUARMState of an element of specified
514 * size, 'element' places in from the least significant end of
515 * the FP/vector register Qn.
517 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
518 int element
, TCGMemOp size
)
521 #ifdef HOST_WORDS_BIGENDIAN
522 /* This is complicated slightly because vfp.regs[2n] is
523 * still the low half and vfp.regs[2n+1] the high half
524 * of the 128 bit vector, even on big endian systems.
525 * Calculate the offset assuming a fully bigendian 128 bits,
526 * then XOR to account for the order of the two 64 bit halves.
528 offs
+= (16 - ((element
+ 1) * (1 << size
)));
531 offs
+= element
* (1 << size
);
533 offs
+= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
534 assert_fp_access_checked(s
);
538 /* Return the offset into CPUARMState of a slice (from
539 * the least significant end) of FP register Qn (ie
541 * (Note that this is not the same mapping as for A32; see cpu.h)
543 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
545 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
546 #ifdef HOST_WORDS_BIGENDIAN
547 offs
+= (8 - (1 << size
));
549 assert_fp_access_checked(s
);
553 /* Offset of the high half of the 128 bit vector Qn */
554 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
556 assert_fp_access_checked(s
);
557 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
560 /* Convenience accessors for reading and writing single and double
561 * FP registers. Writing clears the upper parts of the associated
562 * 128 bit vector register, as required by the architecture.
563 * Note that unlike the GP register accessors, the values returned
564 * by the read functions must be manually freed.
566 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
568 TCGv_i64 v
= tcg_temp_new_i64();
570 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
574 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
576 TCGv_i32 v
= tcg_temp_new_i32();
578 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
582 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
584 TCGv_i64 tcg_zero
= tcg_const_i64(0);
586 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
587 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(s
, reg
));
588 tcg_temp_free_i64(tcg_zero
);
591 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
593 TCGv_i64 tmp
= tcg_temp_new_i64();
595 tcg_gen_extu_i32_i64(tmp
, v
);
596 write_fp_dreg(s
, reg
, tmp
);
597 tcg_temp_free_i64(tmp
);
600 static TCGv_ptr
get_fpstatus_ptr(void)
602 TCGv_ptr statusptr
= tcg_temp_new_ptr();
605 /* In A64 all instructions (both FP and Neon) use the FPCR;
606 * there is no equivalent of the A32 Neon "standard FPSCR value"
607 * and all operations use vfp.fp_status.
609 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
610 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
614 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
615 * than the 32 bit equivalent.
617 static inline void gen_set_NZ64(TCGv_i64 result
)
619 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
620 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
623 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
624 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
627 gen_set_NZ64(result
);
629 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
630 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
632 tcg_gen_movi_i32(cpu_CF
, 0);
633 tcg_gen_movi_i32(cpu_VF
, 0);
636 /* dest = T0 + T1; compute C, N, V and Z flags */
637 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
640 TCGv_i64 result
, flag
, tmp
;
641 result
= tcg_temp_new_i64();
642 flag
= tcg_temp_new_i64();
643 tmp
= tcg_temp_new_i64();
645 tcg_gen_movi_i64(tmp
, 0);
646 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
648 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
650 gen_set_NZ64(result
);
652 tcg_gen_xor_i64(flag
, result
, t0
);
653 tcg_gen_xor_i64(tmp
, t0
, t1
);
654 tcg_gen_andc_i64(flag
, flag
, tmp
);
655 tcg_temp_free_i64(tmp
);
656 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
658 tcg_gen_mov_i64(dest
, result
);
659 tcg_temp_free_i64(result
);
660 tcg_temp_free_i64(flag
);
662 /* 32 bit arithmetic */
663 TCGv_i32 t0_32
= tcg_temp_new_i32();
664 TCGv_i32 t1_32
= tcg_temp_new_i32();
665 TCGv_i32 tmp
= tcg_temp_new_i32();
667 tcg_gen_movi_i32(tmp
, 0);
668 tcg_gen_extrl_i64_i32(t0_32
, t0
);
669 tcg_gen_extrl_i64_i32(t1_32
, t1
);
670 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
671 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
672 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
673 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
674 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
675 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
677 tcg_temp_free_i32(tmp
);
678 tcg_temp_free_i32(t0_32
);
679 tcg_temp_free_i32(t1_32
);
683 /* dest = T0 - T1; compute C, N, V and Z flags */
684 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
687 /* 64 bit arithmetic */
688 TCGv_i64 result
, flag
, tmp
;
690 result
= tcg_temp_new_i64();
691 flag
= tcg_temp_new_i64();
692 tcg_gen_sub_i64(result
, t0
, t1
);
694 gen_set_NZ64(result
);
696 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
697 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
699 tcg_gen_xor_i64(flag
, result
, t0
);
700 tmp
= tcg_temp_new_i64();
701 tcg_gen_xor_i64(tmp
, t0
, t1
);
702 tcg_gen_and_i64(flag
, flag
, tmp
);
703 tcg_temp_free_i64(tmp
);
704 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
705 tcg_gen_mov_i64(dest
, result
);
706 tcg_temp_free_i64(flag
);
707 tcg_temp_free_i64(result
);
709 /* 32 bit arithmetic */
710 TCGv_i32 t0_32
= tcg_temp_new_i32();
711 TCGv_i32 t1_32
= tcg_temp_new_i32();
714 tcg_gen_extrl_i64_i32(t0_32
, t0
);
715 tcg_gen_extrl_i64_i32(t1_32
, t1
);
716 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
717 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
718 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
719 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
720 tmp
= tcg_temp_new_i32();
721 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
722 tcg_temp_free_i32(t0_32
);
723 tcg_temp_free_i32(t1_32
);
724 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
725 tcg_temp_free_i32(tmp
);
726 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
730 /* dest = T0 + T1 + CF; do not compute flags. */
731 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
733 TCGv_i64 flag
= tcg_temp_new_i64();
734 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
735 tcg_gen_add_i64(dest
, t0
, t1
);
736 tcg_gen_add_i64(dest
, dest
, flag
);
737 tcg_temp_free_i64(flag
);
740 tcg_gen_ext32u_i64(dest
, dest
);
744 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
745 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
748 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
749 result
= tcg_temp_new_i64();
750 cf_64
= tcg_temp_new_i64();
751 vf_64
= tcg_temp_new_i64();
752 tmp
= tcg_const_i64(0);
754 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
755 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
756 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
757 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
758 gen_set_NZ64(result
);
760 tcg_gen_xor_i64(vf_64
, result
, t0
);
761 tcg_gen_xor_i64(tmp
, t0
, t1
);
762 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
763 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
765 tcg_gen_mov_i64(dest
, result
);
767 tcg_temp_free_i64(tmp
);
768 tcg_temp_free_i64(vf_64
);
769 tcg_temp_free_i64(cf_64
);
770 tcg_temp_free_i64(result
);
772 TCGv_i32 t0_32
, t1_32
, tmp
;
773 t0_32
= tcg_temp_new_i32();
774 t1_32
= tcg_temp_new_i32();
775 tmp
= tcg_const_i32(0);
777 tcg_gen_extrl_i64_i32(t0_32
, t0
);
778 tcg_gen_extrl_i64_i32(t1_32
, t1
);
779 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
780 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
782 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
783 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
784 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
785 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
786 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
788 tcg_temp_free_i32(tmp
);
789 tcg_temp_free_i32(t1_32
);
790 tcg_temp_free_i32(t0_32
);
795 * Load/Store generators
799 * Store from GPR register to memory.
801 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
802 TCGv_i64 tcg_addr
, int size
, int memidx
,
804 unsigned int iss_srt
,
805 bool iss_sf
, bool iss_ar
)
808 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
813 syn
= syn_data_abort_with_iss(0,
819 0, 0, 0, 0, 0, false);
820 disas_set_insn_syndrome(s
, syn
);
824 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
825 TCGv_i64 tcg_addr
, int size
,
827 unsigned int iss_srt
,
828 bool iss_sf
, bool iss_ar
)
830 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
831 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
835 * Load from memory to GPR register
837 static void do_gpr_ld_memidx(DisasContext
*s
,
838 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
839 int size
, bool is_signed
,
840 bool extend
, int memidx
,
841 bool iss_valid
, unsigned int iss_srt
,
842 bool iss_sf
, bool iss_ar
)
844 TCGMemOp memop
= s
->be_data
+ size
;
852 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
854 if (extend
&& is_signed
) {
856 tcg_gen_ext32u_i64(dest
, dest
);
862 syn
= syn_data_abort_with_iss(0,
868 0, 0, 0, 0, 0, false);
869 disas_set_insn_syndrome(s
, syn
);
873 static void do_gpr_ld(DisasContext
*s
,
874 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
875 int size
, bool is_signed
, bool extend
,
876 bool iss_valid
, unsigned int iss_srt
,
877 bool iss_sf
, bool iss_ar
)
879 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
881 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
885 * Store from FP register to memory
887 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
889 /* This writes the bottom N bits of a 128 bit wide vector to memory */
890 TCGv_i64 tmp
= tcg_temp_new_i64();
891 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
893 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
896 bool be
= s
->be_data
== MO_BE
;
897 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
899 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
900 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
902 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
903 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
905 tcg_temp_free_i64(tcg_hiaddr
);
908 tcg_temp_free_i64(tmp
);
912 * Load from memory to FP register
914 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
916 /* This always zero-extends and writes to a full 128 bit wide vector */
917 TCGv_i64 tmplo
= tcg_temp_new_i64();
921 TCGMemOp memop
= s
->be_data
+ size
;
922 tmphi
= tcg_const_i64(0);
923 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
925 bool be
= s
->be_data
== MO_BE
;
928 tmphi
= tcg_temp_new_i64();
929 tcg_hiaddr
= tcg_temp_new_i64();
931 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
932 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
934 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
936 tcg_temp_free_i64(tcg_hiaddr
);
939 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
940 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
942 tcg_temp_free_i64(tmplo
);
943 tcg_temp_free_i64(tmphi
);
947 * Vector load/store helpers.
949 * The principal difference between this and a FP load is that we don't
950 * zero extend as we are filling a partial chunk of the vector register.
951 * These functions don't support 128 bit loads/stores, which would be
952 * normal load/store operations.
954 * The _i32 versions are useful when operating on 32 bit quantities
955 * (eg for floating point single or using Neon helper functions).
958 /* Get value of an element within a vector register */
959 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
960 int element
, TCGMemOp memop
)
962 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
965 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
968 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
971 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
974 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
977 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
980 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
984 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
987 g_assert_not_reached();
991 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
992 int element
, TCGMemOp memop
)
994 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
997 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1000 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1003 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1006 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1010 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1013 g_assert_not_reached();
1017 /* Set value of an element within a vector register */
1018 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1019 int element
, TCGMemOp memop
)
1021 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1024 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1027 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1030 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1033 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1036 g_assert_not_reached();
1040 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1041 int destidx
, int element
, TCGMemOp memop
)
1043 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1046 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1049 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1052 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1055 g_assert_not_reached();
1059 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
1060 * vector ops all need to do this).
1062 static void clear_vec_high(DisasContext
*s
, int rd
)
1064 TCGv_i64 tcg_zero
= tcg_const_i64(0);
1066 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
1067 tcg_temp_free_i64(tcg_zero
);
1070 /* Store from vector register to memory */
1071 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1072 TCGv_i64 tcg_addr
, int size
)
1074 TCGMemOp memop
= s
->be_data
+ size
;
1075 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1077 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1078 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1080 tcg_temp_free_i64(tcg_tmp
);
1083 /* Load from memory to vector register */
1084 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1085 TCGv_i64 tcg_addr
, int size
)
1087 TCGMemOp memop
= s
->be_data
+ size
;
1088 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1090 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1091 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1093 tcg_temp_free_i64(tcg_tmp
);
1096 /* Check that FP/Neon access is enabled. If it is, return
1097 * true. If not, emit code to generate an appropriate exception,
1098 * and return false; the caller should not emit any code for
1099 * the instruction. Note that this check must happen after all
1100 * unallocated-encoding checks (otherwise the syndrome information
1101 * for the resulting exception will be incorrect).
1103 static inline bool fp_access_check(DisasContext
*s
)
1105 assert(!s
->fp_access_checked
);
1106 s
->fp_access_checked
= true;
1108 if (!s
->fp_excp_el
) {
1112 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1118 * This utility function is for doing register extension with an
1119 * optional shift. You will likely want to pass a temporary for the
1120 * destination register. See DecodeRegExtend() in the ARM ARM.
1122 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1123 int option
, unsigned int shift
)
1125 int extsize
= extract32(option
, 0, 2);
1126 bool is_signed
= extract32(option
, 2, 1);
1131 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1134 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1137 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1140 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1146 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1149 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1152 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1155 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1161 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1165 static inline void gen_check_sp_alignment(DisasContext
*s
)
1167 /* The AArch64 architecture mandates that (if enabled via PSTATE
1168 * or SCTLR bits) there is a check that SP is 16-aligned on every
1169 * SP-relative load or store (with an exception generated if it is not).
1170 * In line with general QEMU practice regarding misaligned accesses,
1171 * we omit these checks for the sake of guest program performance.
1172 * This function is provided as a hook so we can more easily add these
1173 * checks in future (possibly as a "favour catching guest program bugs
1174 * over speed" user selectable option).
1179 * This provides a simple table based table lookup decoder. It is
1180 * intended to be used when the relevant bits for decode are too
1181 * awkwardly placed and switch/if based logic would be confusing and
1182 * deeply nested. Since it's a linear search through the table, tables
1183 * should be kept small.
1185 * It returns the first handler where insn & mask == pattern, or
1186 * NULL if there is no match.
1187 * The table is terminated by an empty mask (i.e. 0)
1189 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1192 const AArch64DecodeTable
*tptr
= table
;
1194 while (tptr
->mask
) {
1195 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1196 return tptr
->disas_fn
;
1204 * The instruction disassembly implemented here matches
1205 * the instruction encoding classifications in chapter C4
1206 * of the ARM Architecture Reference Manual (DDI0487B_a);
1207 * classification names and decode diagrams here should generally
1208 * match up with those in the manual.
1211 /* Unconditional branch (immediate)
1213 * +----+-----------+-------------------------------------+
1214 * | op | 0 0 1 0 1 | imm26 |
1215 * +----+-----------+-------------------------------------+
1217 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1219 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1221 if (insn
& (1U << 31)) {
1222 /* BL Branch with link */
1223 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1226 /* B Branch / BL Branch with link */
1227 gen_goto_tb(s
, 0, addr
);
1230 /* Compare and branch (immediate)
1231 * 31 30 25 24 23 5 4 0
1232 * +----+-------------+----+---------------------+--------+
1233 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1234 * +----+-------------+----+---------------------+--------+
1236 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1238 unsigned int sf
, op
, rt
;
1240 TCGLabel
*label_match
;
1243 sf
= extract32(insn
, 31, 1);
1244 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1245 rt
= extract32(insn
, 0, 5);
1246 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1248 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1249 label_match
= gen_new_label();
1251 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1252 tcg_cmp
, 0, label_match
);
1254 gen_goto_tb(s
, 0, s
->pc
);
1255 gen_set_label(label_match
);
1256 gen_goto_tb(s
, 1, addr
);
1259 /* Test and branch (immediate)
1260 * 31 30 25 24 23 19 18 5 4 0
1261 * +----+-------------+----+-------+-------------+------+
1262 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1263 * +----+-------------+----+-------+-------------+------+
1265 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1267 unsigned int bit_pos
, op
, rt
;
1269 TCGLabel
*label_match
;
1272 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1273 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1274 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1275 rt
= extract32(insn
, 0, 5);
1277 tcg_cmp
= tcg_temp_new_i64();
1278 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1279 label_match
= gen_new_label();
1280 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1281 tcg_cmp
, 0, label_match
);
1282 tcg_temp_free_i64(tcg_cmp
);
1283 gen_goto_tb(s
, 0, s
->pc
);
1284 gen_set_label(label_match
);
1285 gen_goto_tb(s
, 1, addr
);
1288 /* Conditional branch (immediate)
1289 * 31 25 24 23 5 4 3 0
1290 * +---------------+----+---------------------+----+------+
1291 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1292 * +---------------+----+---------------------+----+------+
1294 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1299 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1300 unallocated_encoding(s
);
1303 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1304 cond
= extract32(insn
, 0, 4);
1307 /* genuinely conditional branches */
1308 TCGLabel
*label_match
= gen_new_label();
1309 arm_gen_test_cc(cond
, label_match
);
1310 gen_goto_tb(s
, 0, s
->pc
);
1311 gen_set_label(label_match
);
1312 gen_goto_tb(s
, 1, addr
);
1314 /* 0xe and 0xf are both "always" conditions */
1315 gen_goto_tb(s
, 0, addr
);
1319 /* HINT instruction group, including various allocated HINTs */
1320 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1321 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1323 unsigned int selector
= crm
<< 3 | op2
;
1326 unallocated_encoding(s
);
1334 s
->base
.is_jmp
= DISAS_WFI
;
1336 /* When running in MTTCG we don't generate jumps to the yield and
1337 * WFE helpers as it won't affect the scheduling of other vCPUs.
1338 * If we wanted to more completely model WFE/SEV so we don't busy
1339 * spin unnecessarily we would need to do something more involved.
1342 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1343 s
->base
.is_jmp
= DISAS_YIELD
;
1347 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1348 s
->base
.is_jmp
= DISAS_WFE
;
1353 /* we treat all as NOP at least for now */
1356 /* default specified as NOP equivalent */
1361 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1363 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1366 /* CLREX, DSB, DMB, ISB */
1367 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1368 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1373 unallocated_encoding(s
);
1384 case 1: /* MBReqTypes_Reads */
1385 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1387 case 2: /* MBReqTypes_Writes */
1388 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1390 default: /* MBReqTypes_All */
1391 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1397 /* We need to break the TB after this insn to execute
1398 * a self-modified code correctly and also to take
1399 * any pending interrupts immediately.
1401 gen_goto_tb(s
, 0, s
->pc
);
1404 unallocated_encoding(s
);
1409 /* MSR (immediate) - move immediate to processor state field */
1410 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1411 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1413 int op
= op1
<< 3 | op2
;
1415 case 0x05: /* SPSel */
1416 if (s
->current_el
== 0) {
1417 unallocated_encoding(s
);
1421 case 0x1e: /* DAIFSet */
1422 case 0x1f: /* DAIFClear */
1424 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1425 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1426 gen_a64_set_pc_im(s
->pc
- 4);
1427 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1428 tcg_temp_free_i32(tcg_imm
);
1429 tcg_temp_free_i32(tcg_op
);
1430 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1431 gen_a64_set_pc_im(s
->pc
);
1432 s
->base
.is_jmp
= (op
== 0x1f ? DISAS_EXIT
: DISAS_JUMP
);
1436 unallocated_encoding(s
);
1441 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1443 TCGv_i32 tmp
= tcg_temp_new_i32();
1444 TCGv_i32 nzcv
= tcg_temp_new_i32();
1446 /* build bit 31, N */
1447 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1448 /* build bit 30, Z */
1449 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1450 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1451 /* build bit 29, C */
1452 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1453 /* build bit 28, V */
1454 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1455 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1456 /* generate result */
1457 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1459 tcg_temp_free_i32(nzcv
);
1460 tcg_temp_free_i32(tmp
);
1463 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1466 TCGv_i32 nzcv
= tcg_temp_new_i32();
1468 /* take NZCV from R[t] */
1469 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1472 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1474 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1475 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1477 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1478 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1480 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1481 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1482 tcg_temp_free_i32(nzcv
);
1485 /* MRS - move from system register
1486 * MSR (register) - move to system register
1489 * These are all essentially the same insn in 'read' and 'write'
1490 * versions, with varying op0 fields.
1492 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1493 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1494 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1496 const ARMCPRegInfo
*ri
;
1499 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1500 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1501 crn
, crm
, op0
, op1
, op2
));
1504 /* Unknown register; this might be a guest error or a QEMU
1505 * unimplemented feature.
1507 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1508 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1509 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1510 unallocated_encoding(s
);
1514 /* Check access permissions */
1515 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1516 unallocated_encoding(s
);
1521 /* Emit code to perform further access permissions checks at
1522 * runtime; this may result in an exception.
1525 TCGv_i32 tcg_syn
, tcg_isread
;
1528 gen_a64_set_pc_im(s
->pc
- 4);
1529 tmpptr
= tcg_const_ptr(ri
);
1530 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1531 tcg_syn
= tcg_const_i32(syndrome
);
1532 tcg_isread
= tcg_const_i32(isread
);
1533 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1534 tcg_temp_free_ptr(tmpptr
);
1535 tcg_temp_free_i32(tcg_syn
);
1536 tcg_temp_free_i32(tcg_isread
);
1539 /* Handle special cases first */
1540 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1544 tcg_rt
= cpu_reg(s
, rt
);
1546 gen_get_nzcv(tcg_rt
);
1548 gen_set_nzcv(tcg_rt
);
1551 case ARM_CP_CURRENTEL
:
1552 /* Reads as current EL value from pstate, which is
1553 * guaranteed to be constant by the tb flags.
1555 tcg_rt
= cpu_reg(s
, rt
);
1556 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1559 /* Writes clear the aligned block of memory which rt points into. */
1560 tcg_rt
= cpu_reg(s
, rt
);
1561 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1567 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1571 tcg_rt
= cpu_reg(s
, rt
);
1574 if (ri
->type
& ARM_CP_CONST
) {
1575 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1576 } else if (ri
->readfn
) {
1578 tmpptr
= tcg_const_ptr(ri
);
1579 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1580 tcg_temp_free_ptr(tmpptr
);
1582 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1585 if (ri
->type
& ARM_CP_CONST
) {
1586 /* If not forbidden by access permissions, treat as WI */
1588 } else if (ri
->writefn
) {
1590 tmpptr
= tcg_const_ptr(ri
);
1591 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1592 tcg_temp_free_ptr(tmpptr
);
1594 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1598 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1599 /* I/O operations must end the TB here (whether read or write) */
1601 s
->base
.is_jmp
= DISAS_UPDATE
;
1602 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1603 /* We default to ending the TB on a coprocessor register write,
1604 * but allow this to be suppressed by the register definition
1605 * (usually only necessary to work around guest bugs).
1607 s
->base
.is_jmp
= DISAS_UPDATE
;
1612 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1613 * +---------------------+---+-----+-----+-------+-------+-----+------+
1614 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1615 * +---------------------+---+-----+-----+-------+-------+-----+------+
1617 static void disas_system(DisasContext
*s
, uint32_t insn
)
1619 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1620 l
= extract32(insn
, 21, 1);
1621 op0
= extract32(insn
, 19, 2);
1622 op1
= extract32(insn
, 16, 3);
1623 crn
= extract32(insn
, 12, 4);
1624 crm
= extract32(insn
, 8, 4);
1625 op2
= extract32(insn
, 5, 3);
1626 rt
= extract32(insn
, 0, 5);
1629 if (l
|| rt
!= 31) {
1630 unallocated_encoding(s
);
1634 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1635 handle_hint(s
, insn
, op1
, op2
, crm
);
1637 case 3: /* CLREX, DSB, DMB, ISB */
1638 handle_sync(s
, insn
, op1
, op2
, crm
);
1640 case 4: /* MSR (immediate) */
1641 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1644 unallocated_encoding(s
);
1649 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1652 /* Exception generation
1654 * 31 24 23 21 20 5 4 2 1 0
1655 * +-----------------+-----+------------------------+-----+----+
1656 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1657 * +-----------------------+------------------------+----------+
1659 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1661 int opc
= extract32(insn
, 21, 3);
1662 int op2_ll
= extract32(insn
, 0, 5);
1663 int imm16
= extract32(insn
, 5, 16);
1668 /* For SVC, HVC and SMC we advance the single-step state
1669 * machine before taking the exception. This is architecturally
1670 * mandated, to ensure that single-stepping a system call
1671 * instruction works properly.
1676 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1677 default_exception_el(s
));
1680 if (s
->current_el
== 0) {
1681 unallocated_encoding(s
);
1684 /* The pre HVC helper handles cases when HVC gets trapped
1685 * as an undefined insn by runtime configuration.
1687 gen_a64_set_pc_im(s
->pc
- 4);
1688 gen_helper_pre_hvc(cpu_env
);
1690 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1693 if (s
->current_el
== 0) {
1694 unallocated_encoding(s
);
1697 gen_a64_set_pc_im(s
->pc
- 4);
1698 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1699 gen_helper_pre_smc(cpu_env
, tmp
);
1700 tcg_temp_free_i32(tmp
);
1702 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1705 unallocated_encoding(s
);
1711 unallocated_encoding(s
);
1715 gen_exception_insn(s
, 4, EXCP_BKPT
, syn_aa64_bkpt(imm16
),
1716 default_exception_el(s
));
1720 unallocated_encoding(s
);
1723 /* HLT. This has two purposes.
1724 * Architecturally, it is an external halting debug instruction.
1725 * Since QEMU doesn't implement external debug, we treat this as
1726 * it is required for halting debug disabled: it will UNDEF.
1727 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1729 if (semihosting_enabled() && imm16
== 0xf000) {
1730 #ifndef CONFIG_USER_ONLY
1731 /* In system mode, don't allow userspace access to semihosting,
1732 * to provide some semblance of security (and for consistency
1733 * with our 32-bit semihosting).
1735 if (s
->current_el
== 0) {
1736 unsupported_encoding(s
, insn
);
1740 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1742 unsupported_encoding(s
, insn
);
1746 if (op2_ll
< 1 || op2_ll
> 3) {
1747 unallocated_encoding(s
);
1750 /* DCPS1, DCPS2, DCPS3 */
1751 unsupported_encoding(s
, insn
);
1754 unallocated_encoding(s
);
1759 /* Unconditional branch (register)
1760 * 31 25 24 21 20 16 15 10 9 5 4 0
1761 * +---------------+-------+-------+-------+------+-------+
1762 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1763 * +---------------+-------+-------+-------+------+-------+
1765 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1767 unsigned int opc
, op2
, op3
, rn
, op4
;
1769 opc
= extract32(insn
, 21, 4);
1770 op2
= extract32(insn
, 16, 5);
1771 op3
= extract32(insn
, 10, 6);
1772 rn
= extract32(insn
, 5, 5);
1773 op4
= extract32(insn
, 0, 5);
1775 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1776 unallocated_encoding(s
);
1784 gen_a64_set_pc(s
, cpu_reg(s
, rn
));
1785 /* BLR also needs to load return address */
1787 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1791 if (s
->current_el
== 0) {
1792 unallocated_encoding(s
);
1795 gen_helper_exception_return(cpu_env
);
1796 /* Must exit loop to check un-masked IRQs */
1797 s
->base
.is_jmp
= DISAS_EXIT
;
1801 unallocated_encoding(s
);
1803 unsupported_encoding(s
, insn
);
1807 unallocated_encoding(s
);
1811 s
->base
.is_jmp
= DISAS_JUMP
;
1814 /* Branches, exception generating and system instructions */
1815 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1817 switch (extract32(insn
, 25, 7)) {
1818 case 0x0a: case 0x0b:
1819 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1820 disas_uncond_b_imm(s
, insn
);
1822 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1823 disas_comp_b_imm(s
, insn
);
1825 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1826 disas_test_b_imm(s
, insn
);
1828 case 0x2a: /* Conditional branch (immediate) */
1829 disas_cond_b_imm(s
, insn
);
1831 case 0x6a: /* Exception generation / System */
1832 if (insn
& (1 << 24)) {
1833 disas_system(s
, insn
);
1838 case 0x6b: /* Unconditional branch (register) */
1839 disas_uncond_b_reg(s
, insn
);
1842 unallocated_encoding(s
);
1848 * Load/Store exclusive instructions are implemented by remembering
1849 * the value/address loaded, and seeing if these are the same
1850 * when the store is performed. This is not actually the architecturally
1851 * mandated semantics, but it works for typical guest code sequences
1852 * and avoids having to monitor regular stores.
1854 * The store exclusive uses the atomic cmpxchg primitives to avoid
1855 * races in multi-threaded linux-user and when MTTCG softmmu is
1858 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1859 TCGv_i64 addr
, int size
, bool is_pair
)
1861 int idx
= get_mem_index(s
);
1862 TCGMemOp memop
= s
->be_data
;
1864 g_assert(size
<= 3);
1866 g_assert(size
>= 2);
1868 /* The pair must be single-copy atomic for the doubleword. */
1869 memop
|= MO_64
| MO_ALIGN
;
1870 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
1871 if (s
->be_data
== MO_LE
) {
1872 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
1873 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
1875 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
1876 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
1879 /* The pair must be single-copy atomic for *each* doubleword, not
1880 the entire quadword, however it must be quadword aligned. */
1882 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
1883 memop
| MO_ALIGN_16
);
1885 TCGv_i64 addr2
= tcg_temp_new_i64();
1886 tcg_gen_addi_i64(addr2
, addr
, 8);
1887 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
1888 tcg_temp_free_i64(addr2
);
1890 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
1891 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
1894 memop
|= size
| MO_ALIGN
;
1895 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
1896 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
1898 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1901 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1902 TCGv_i64 addr
, int size
, int is_pair
)
1904 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1905 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1908 * [addr + datasize] = {Rt2};
1914 * env->exclusive_addr = -1;
1916 TCGLabel
*fail_label
= gen_new_label();
1917 TCGLabel
*done_label
= gen_new_label();
1920 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1922 tmp
= tcg_temp_new_i64();
1925 if (s
->be_data
== MO_LE
) {
1926 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
1928 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
1930 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
1931 cpu_exclusive_val
, tmp
,
1933 MO_64
| MO_ALIGN
| s
->be_data
);
1934 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
1935 } else if (s
->be_data
== MO_LE
) {
1936 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
1937 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
1942 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
1943 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
1946 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
1947 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
1952 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
1953 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
1957 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
1958 cpu_reg(s
, rt
), get_mem_index(s
),
1959 size
| MO_ALIGN
| s
->be_data
);
1960 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
1962 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
1963 tcg_temp_free_i64(tmp
);
1964 tcg_gen_br(done_label
);
1966 gen_set_label(fail_label
);
1967 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1968 gen_set_label(done_label
);
1969 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1972 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
1973 * from the ARMv8 specs for LDR (Shared decode for all encodings).
1975 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
1977 int opc0
= extract32(opc
, 0, 1);
1981 regsize
= opc0
? 32 : 64;
1983 regsize
= size
== 3 ? 64 : 32;
1985 return regsize
== 64;
1988 /* Load/store exclusive
1990 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1991 * +-----+-------------+----+---+----+------+----+-------+------+------+
1992 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1993 * +-----+-------------+----+---+----+------+----+-------+------+------+
1995 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1996 * L: 0 -> store, 1 -> load
1997 * o2: 0 -> exclusive, 1 -> not
1998 * o1: 0 -> single register, 1 -> register pair
1999 * o0: 1 -> load-acquire/store-release, 0 -> not
2001 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2003 int rt
= extract32(insn
, 0, 5);
2004 int rn
= extract32(insn
, 5, 5);
2005 int rt2
= extract32(insn
, 10, 5);
2006 int is_lasr
= extract32(insn
, 15, 1);
2007 int rs
= extract32(insn
, 16, 5);
2008 int is_pair
= extract32(insn
, 21, 1);
2009 int is_store
= !extract32(insn
, 22, 1);
2010 int is_excl
= !extract32(insn
, 23, 1);
2011 int size
= extract32(insn
, 30, 2);
2014 if ((!is_excl
&& !is_pair
&& !is_lasr
) ||
2015 (!is_excl
&& is_pair
) ||
2016 (is_pair
&& size
< 2)) {
2017 unallocated_encoding(s
);
2022 gen_check_sp_alignment(s
);
2024 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2026 /* Note that since TCG is single threaded load-acquire/store-release
2027 * semantics require no extra if (is_lasr) { ... } handling.
2033 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
2035 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2039 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2041 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
2044 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2045 bool iss_sf
= disas_ldst_compute_iss_sf(size
, false, 0);
2047 /* Generate ISS for non-exclusive accesses including LASR. */
2050 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2052 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2053 true, rt
, iss_sf
, is_lasr
);
2055 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false,
2056 true, rt
, iss_sf
, is_lasr
);
2058 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2065 * Load register (literal)
2067 * 31 30 29 27 26 25 24 23 5 4 0
2068 * +-----+-------+---+-----+-------------------+-------+
2069 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2070 * +-----+-------+---+-----+-------------------+-------+
2072 * V: 1 -> vector (simd/fp)
2073 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2074 * 10-> 32 bit signed, 11 -> prefetch
2075 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2077 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2079 int rt
= extract32(insn
, 0, 5);
2080 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2081 bool is_vector
= extract32(insn
, 26, 1);
2082 int opc
= extract32(insn
, 30, 2);
2083 bool is_signed
= false;
2085 TCGv_i64 tcg_rt
, tcg_addr
;
2089 unallocated_encoding(s
);
2093 if (!fp_access_check(s
)) {
2098 /* PRFM (literal) : prefetch */
2101 size
= 2 + extract32(opc
, 0, 1);
2102 is_signed
= extract32(opc
, 1, 1);
2105 tcg_rt
= cpu_reg(s
, rt
);
2107 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2109 do_fp_ld(s
, rt
, tcg_addr
, size
);
2111 /* Only unsigned 32bit loads target 32bit registers. */
2112 bool iss_sf
= opc
!= 0;
2114 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2115 true, rt
, iss_sf
, false);
2117 tcg_temp_free_i64(tcg_addr
);
2121 * LDNP (Load Pair - non-temporal hint)
2122 * LDP (Load Pair - non vector)
2123 * LDPSW (Load Pair Signed Word - non vector)
2124 * STNP (Store Pair - non-temporal hint)
2125 * STP (Store Pair - non vector)
2126 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2127 * LDP (Load Pair of SIMD&FP)
2128 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2129 * STP (Store Pair of SIMD&FP)
2131 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2132 * +-----+-------+---+---+-------+---+-----------------------------+
2133 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2134 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2136 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2138 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2139 * V: 0 -> GPR, 1 -> Vector
2140 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2141 * 10 -> signed offset, 11 -> pre-index
2142 * L: 0 -> Store 1 -> Load
2144 * Rt, Rt2 = GPR or SIMD registers to be stored
2145 * Rn = general purpose register containing address
2146 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2148 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2150 int rt
= extract32(insn
, 0, 5);
2151 int rn
= extract32(insn
, 5, 5);
2152 int rt2
= extract32(insn
, 10, 5);
2153 uint64_t offset
= sextract64(insn
, 15, 7);
2154 int index
= extract32(insn
, 23, 2);
2155 bool is_vector
= extract32(insn
, 26, 1);
2156 bool is_load
= extract32(insn
, 22, 1);
2157 int opc
= extract32(insn
, 30, 2);
2159 bool is_signed
= false;
2160 bool postindex
= false;
2163 TCGv_i64 tcg_addr
; /* calculated address */
2167 unallocated_encoding(s
);
2174 size
= 2 + extract32(opc
, 1, 1);
2175 is_signed
= extract32(opc
, 0, 1);
2176 if (!is_load
&& is_signed
) {
2177 unallocated_encoding(s
);
2183 case 1: /* post-index */
2188 /* signed offset with "non-temporal" hint. Since we don't emulate
2189 * caches we don't care about hints to the cache system about
2190 * data access patterns, and handle this identically to plain
2194 /* There is no non-temporal-hint version of LDPSW */
2195 unallocated_encoding(s
);
2200 case 2: /* signed offset, rn not updated */
2203 case 3: /* pre-index */
2209 if (is_vector
&& !fp_access_check(s
)) {
2216 gen_check_sp_alignment(s
);
2219 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2222 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2227 do_fp_ld(s
, rt
, tcg_addr
, size
);
2229 do_fp_st(s
, rt
, tcg_addr
, size
);
2231 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2233 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2235 do_fp_st(s
, rt2
, tcg_addr
, size
);
2238 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2239 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2242 TCGv_i64 tmp
= tcg_temp_new_i64();
2244 /* Do not modify tcg_rt before recognizing any exception
2245 * from the second load.
2247 do_gpr_ld(s
, tmp
, tcg_addr
, size
, is_signed
, false,
2248 false, 0, false, false);
2249 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2250 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false,
2251 false, 0, false, false);
2253 tcg_gen_mov_i64(tcg_rt
, tmp
);
2254 tcg_temp_free_i64(tmp
);
2256 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2257 false, 0, false, false);
2258 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2259 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
,
2260 false, 0, false, false);
2266 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2268 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2270 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2275 * Load/store (immediate post-indexed)
2276 * Load/store (immediate pre-indexed)
2277 * Load/store (unscaled immediate)
2279 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2280 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2281 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2282 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2284 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2286 * V = 0 -> non-vector
2287 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2288 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2290 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2296 int rn
= extract32(insn
, 5, 5);
2297 int imm9
= sextract32(insn
, 12, 9);
2298 int idx
= extract32(insn
, 10, 2);
2299 bool is_signed
= false;
2300 bool is_store
= false;
2301 bool is_extended
= false;
2302 bool is_unpriv
= (idx
== 2);
2303 bool iss_valid
= !is_vector
;
2310 size
|= (opc
& 2) << 1;
2311 if (size
> 4 || is_unpriv
) {
2312 unallocated_encoding(s
);
2315 is_store
= ((opc
& 1) == 0);
2316 if (!fp_access_check(s
)) {
2320 if (size
== 3 && opc
== 2) {
2321 /* PRFM - prefetch */
2323 unallocated_encoding(s
);
2328 if (opc
== 3 && size
> 1) {
2329 unallocated_encoding(s
);
2332 is_store
= (opc
== 0);
2333 is_signed
= extract32(opc
, 1, 1);
2334 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2352 g_assert_not_reached();
2356 gen_check_sp_alignment(s
);
2358 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2361 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2366 do_fp_st(s
, rt
, tcg_addr
, size
);
2368 do_fp_ld(s
, rt
, tcg_addr
, size
);
2371 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2372 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2373 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2376 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
,
2377 iss_valid
, rt
, iss_sf
, false);
2379 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2380 is_signed
, is_extended
, memidx
,
2381 iss_valid
, rt
, iss_sf
, false);
2386 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2388 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2390 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2395 * Load/store (register offset)
2397 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2398 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2399 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2400 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2403 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2404 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2406 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2407 * opc<0>: 0 -> store, 1 -> load
2408 * V: 1 -> vector/simd
2409 * opt: extend encoding (see DecodeRegExtend)
2410 * S: if S=1 then scale (essentially index by sizeof(size))
2411 * Rt: register to transfer into/out of
2412 * Rn: address register or SP for base
2413 * Rm: offset register or ZR for offset
2415 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2421 int rn
= extract32(insn
, 5, 5);
2422 int shift
= extract32(insn
, 12, 1);
2423 int rm
= extract32(insn
, 16, 5);
2424 int opt
= extract32(insn
, 13, 3);
2425 bool is_signed
= false;
2426 bool is_store
= false;
2427 bool is_extended
= false;
2432 if (extract32(opt
, 1, 1) == 0) {
2433 unallocated_encoding(s
);
2438 size
|= (opc
& 2) << 1;
2440 unallocated_encoding(s
);
2443 is_store
= !extract32(opc
, 0, 1);
2444 if (!fp_access_check(s
)) {
2448 if (size
== 3 && opc
== 2) {
2449 /* PRFM - prefetch */
2452 if (opc
== 3 && size
> 1) {
2453 unallocated_encoding(s
);
2456 is_store
= (opc
== 0);
2457 is_signed
= extract32(opc
, 1, 1);
2458 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2462 gen_check_sp_alignment(s
);
2464 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2466 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2467 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2469 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2473 do_fp_st(s
, rt
, tcg_addr
, size
);
2475 do_fp_ld(s
, rt
, tcg_addr
, size
);
2478 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2479 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2481 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2482 true, rt
, iss_sf
, false);
2484 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
,
2485 is_signed
, is_extended
,
2486 true, rt
, iss_sf
, false);
2492 * Load/store (unsigned immediate)
2494 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2495 * +----+-------+---+-----+-----+------------+-------+------+
2496 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2497 * +----+-------+---+-----+-----+------------+-------+------+
2500 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2501 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2503 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2504 * opc<0>: 0 -> store, 1 -> load
2505 * Rn: base address register (inc SP)
2506 * Rt: target register
2508 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
2514 int rn
= extract32(insn
, 5, 5);
2515 unsigned int imm12
= extract32(insn
, 10, 12);
2516 unsigned int offset
;
2521 bool is_signed
= false;
2522 bool is_extended
= false;
2525 size
|= (opc
& 2) << 1;
2527 unallocated_encoding(s
);
2530 is_store
= !extract32(opc
, 0, 1);
2531 if (!fp_access_check(s
)) {
2535 if (size
== 3 && opc
== 2) {
2536 /* PRFM - prefetch */
2539 if (opc
== 3 && size
> 1) {
2540 unallocated_encoding(s
);
2543 is_store
= (opc
== 0);
2544 is_signed
= extract32(opc
, 1, 1);
2545 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2549 gen_check_sp_alignment(s
);
2551 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2552 offset
= imm12
<< size
;
2553 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2557 do_fp_st(s
, rt
, tcg_addr
, size
);
2559 do_fp_ld(s
, rt
, tcg_addr
, size
);
2562 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2563 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2565 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2566 true, rt
, iss_sf
, false);
2568 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
,
2569 true, rt
, iss_sf
, false);
2574 /* Load/store register (all forms) */
2575 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2577 int rt
= extract32(insn
, 0, 5);
2578 int opc
= extract32(insn
, 22, 2);
2579 bool is_vector
= extract32(insn
, 26, 1);
2580 int size
= extract32(insn
, 30, 2);
2582 switch (extract32(insn
, 24, 2)) {
2584 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2585 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
2587 /* Load/store register (unscaled immediate)
2588 * Load/store immediate pre/post-indexed
2589 * Load/store register unprivileged
2591 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
2595 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
2598 unallocated_encoding(s
);
2603 /* AdvSIMD load/store multiple structures
2605 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2606 * +---+---+---------------+---+-------------+--------+------+------+------+
2607 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2608 * +---+---+---------------+---+-------------+--------+------+------+------+
2610 * AdvSIMD load/store multiple structures (post-indexed)
2612 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2613 * +---+---+---------------+---+---+---------+--------+------+------+------+
2614 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2615 * +---+---+---------------+---+---+---------+--------+------+------+------+
2617 * Rt: first (or only) SIMD&FP register to be transferred
2618 * Rn: base address or SP
2619 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2621 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2623 int rt
= extract32(insn
, 0, 5);
2624 int rn
= extract32(insn
, 5, 5);
2625 int size
= extract32(insn
, 10, 2);
2626 int opcode
= extract32(insn
, 12, 4);
2627 bool is_store
= !extract32(insn
, 22, 1);
2628 bool is_postidx
= extract32(insn
, 23, 1);
2629 bool is_q
= extract32(insn
, 30, 1);
2630 TCGv_i64 tcg_addr
, tcg_rn
;
2632 int ebytes
= 1 << size
;
2633 int elements
= (is_q
? 128 : 64) / (8 << size
);
2634 int rpt
; /* num iterations */
2635 int selem
; /* structure elements */
2638 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2639 unallocated_encoding(s
);
2643 /* From the shared decode logic */
2674 unallocated_encoding(s
);
2678 if (size
== 3 && !is_q
&& selem
!= 1) {
2680 unallocated_encoding(s
);
2684 if (!fp_access_check(s
)) {
2689 gen_check_sp_alignment(s
);
2692 tcg_rn
= cpu_reg_sp(s
, rn
);
2693 tcg_addr
= tcg_temp_new_i64();
2694 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2696 for (r
= 0; r
< rpt
; r
++) {
2698 for (e
= 0; e
< elements
; e
++) {
2699 int tt
= (rt
+ r
) % 32;
2701 for (xs
= 0; xs
< selem
; xs
++) {
2703 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2705 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2707 /* For non-quad operations, setting a slice of the low
2708 * 64 bits of the register clears the high 64 bits (in
2709 * the ARM ARM pseudocode this is implicit in the fact
2710 * that 'rval' is a 64 bit wide variable). We optimize
2711 * by noticing that we only need to do this the first
2712 * time we touch a register.
2714 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2715 clear_vec_high(s
, tt
);
2718 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2725 int rm
= extract32(insn
, 16, 5);
2727 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2729 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2732 tcg_temp_free_i64(tcg_addr
);
2735 /* AdvSIMD load/store single structure
2737 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2738 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2739 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2740 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2742 * AdvSIMD load/store single structure (post-indexed)
2744 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2745 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2746 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2747 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2749 * Rt: first (or only) SIMD&FP register to be transferred
2750 * Rn: base address or SP
2751 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2752 * index = encoded in Q:S:size dependent on size
2754 * lane_size = encoded in R, opc
2755 * transfer width = encoded in opc, S, size
2757 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2759 int rt
= extract32(insn
, 0, 5);
2760 int rn
= extract32(insn
, 5, 5);
2761 int size
= extract32(insn
, 10, 2);
2762 int S
= extract32(insn
, 12, 1);
2763 int opc
= extract32(insn
, 13, 3);
2764 int R
= extract32(insn
, 21, 1);
2765 int is_load
= extract32(insn
, 22, 1);
2766 int is_postidx
= extract32(insn
, 23, 1);
2767 int is_q
= extract32(insn
, 30, 1);
2769 int scale
= extract32(opc
, 1, 2);
2770 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2771 bool replicate
= false;
2772 int index
= is_q
<< 3 | S
<< 2 | size
;
2774 TCGv_i64 tcg_addr
, tcg_rn
;
2778 if (!is_load
|| S
) {
2779 unallocated_encoding(s
);
2788 if (extract32(size
, 0, 1)) {
2789 unallocated_encoding(s
);
2795 if (extract32(size
, 1, 1)) {
2796 unallocated_encoding(s
);
2799 if (!extract32(size
, 0, 1)) {
2803 unallocated_encoding(s
);
2811 g_assert_not_reached();
2814 if (!fp_access_check(s
)) {
2818 ebytes
= 1 << scale
;
2821 gen_check_sp_alignment(s
);
2824 tcg_rn
= cpu_reg_sp(s
, rn
);
2825 tcg_addr
= tcg_temp_new_i64();
2826 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2828 for (xs
= 0; xs
< selem
; xs
++) {
2830 /* Load and replicate to all elements */
2832 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2834 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2835 get_mem_index(s
), s
->be_data
+ scale
);
2838 mulconst
= 0x0101010101010101ULL
;
2841 mulconst
= 0x0001000100010001ULL
;
2844 mulconst
= 0x0000000100000001ULL
;
2850 g_assert_not_reached();
2853 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2855 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2857 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2859 clear_vec_high(s
, rt
);
2861 tcg_temp_free_i64(tcg_tmp
);
2863 /* Load/store one element per register */
2865 do_vec_ld(s
, rt
, index
, tcg_addr
, scale
);
2867 do_vec_st(s
, rt
, index
, tcg_addr
, scale
);
2870 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2875 int rm
= extract32(insn
, 16, 5);
2877 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2879 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2882 tcg_temp_free_i64(tcg_addr
);
2885 /* Loads and stores */
2886 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2888 switch (extract32(insn
, 24, 6)) {
2889 case 0x08: /* Load/store exclusive */
2890 disas_ldst_excl(s
, insn
);
2892 case 0x18: case 0x1c: /* Load register (literal) */
2893 disas_ld_lit(s
, insn
);
2895 case 0x28: case 0x29:
2896 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2897 disas_ldst_pair(s
, insn
);
2899 case 0x38: case 0x39:
2900 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2901 disas_ldst_reg(s
, insn
);
2903 case 0x0c: /* AdvSIMD load/store multiple structures */
2904 disas_ldst_multiple_struct(s
, insn
);
2906 case 0x0d: /* AdvSIMD load/store single structure */
2907 disas_ldst_single_struct(s
, insn
);
2910 unallocated_encoding(s
);
2915 /* PC-rel. addressing
2916 * 31 30 29 28 24 23 5 4 0
2917 * +----+-------+-----------+-------------------+------+
2918 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2919 * +----+-------+-----------+-------------------+------+
2921 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2923 unsigned int page
, rd
;
2927 page
= extract32(insn
, 31, 1);
2928 /* SignExtend(immhi:immlo) -> offset */
2929 offset
= sextract64(insn
, 5, 19);
2930 offset
= offset
<< 2 | extract32(insn
, 29, 2);
2931 rd
= extract32(insn
, 0, 5);
2935 /* ADRP (page based) */
2940 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2944 * Add/subtract (immediate)
2946 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2947 * +--+--+--+-----------+-----+-------------+-----+-----+
2948 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2949 * +--+--+--+-----------+-----+-------------+-----+-----+
2951 * sf: 0 -> 32bit, 1 -> 64bit
2952 * op: 0 -> add , 1 -> sub
2954 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2956 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2958 int rd
= extract32(insn
, 0, 5);
2959 int rn
= extract32(insn
, 5, 5);
2960 uint64_t imm
= extract32(insn
, 10, 12);
2961 int shift
= extract32(insn
, 22, 2);
2962 bool setflags
= extract32(insn
, 29, 1);
2963 bool sub_op
= extract32(insn
, 30, 1);
2964 bool is_64bit
= extract32(insn
, 31, 1);
2966 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2967 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2968 TCGv_i64 tcg_result
;
2977 unallocated_encoding(s
);
2981 tcg_result
= tcg_temp_new_i64();
2984 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2986 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2989 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2991 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2993 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2995 tcg_temp_free_i64(tcg_imm
);
2999 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3001 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3004 tcg_temp_free_i64(tcg_result
);
3007 /* The input should be a value in the bottom e bits (with higher
3008 * bits zero); returns that value replicated into every element
3009 * of size e in a 64 bit integer.
3011 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3021 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3022 static inline uint64_t bitmask64(unsigned int length
)
3024 assert(length
> 0 && length
<= 64);
3025 return ~0ULL >> (64 - length
);
3028 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3029 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3030 * value (ie should cause a guest UNDEF exception), and true if they are
3031 * valid, in which case the decoded bit pattern is written to result.
3033 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3034 unsigned int imms
, unsigned int immr
)
3037 unsigned e
, levels
, s
, r
;
3040 assert(immn
< 2 && imms
< 64 && immr
< 64);
3042 /* The bit patterns we create here are 64 bit patterns which
3043 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3044 * 64 bits each. Each element contains the same value: a run
3045 * of between 1 and e-1 non-zero bits, rotated within the
3046 * element by between 0 and e-1 bits.
3048 * The element size and run length are encoded into immn (1 bit)
3049 * and imms (6 bits) as follows:
3050 * 64 bit elements: immn = 1, imms = <length of run - 1>
3051 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3052 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3053 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3054 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3055 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3056 * Notice that immn = 0, imms = 11111x is the only combination
3057 * not covered by one of the above options; this is reserved.
3058 * Further, <length of run - 1> all-ones is a reserved pattern.
3060 * In all cases the rotation is by immr % e (and immr is 6 bits).
3063 /* First determine the element size */
3064 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3066 /* This is the immn == 0, imms == 0x11111x case */
3076 /* <length of run - 1> mustn't be all-ones. */
3080 /* Create the value of one element: s+1 set bits rotated
3081 * by r within the element (which is e bits wide)...
3083 mask
= bitmask64(s
+ 1);
3085 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3086 mask
&= bitmask64(e
);
3088 /* ...then replicate the element over the whole 64 bit value */
3089 mask
= bitfield_replicate(mask
, e
);
3094 /* Logical (immediate)
3095 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3096 * +----+-----+-------------+---+------+------+------+------+
3097 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3098 * +----+-----+-------------+---+------+------+------+------+
3100 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3102 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3103 TCGv_i64 tcg_rd
, tcg_rn
;
3105 bool is_and
= false;
3107 sf
= extract32(insn
, 31, 1);
3108 opc
= extract32(insn
, 29, 2);
3109 is_n
= extract32(insn
, 22, 1);
3110 immr
= extract32(insn
, 16, 6);
3111 imms
= extract32(insn
, 10, 6);
3112 rn
= extract32(insn
, 5, 5);
3113 rd
= extract32(insn
, 0, 5);
3116 unallocated_encoding(s
);
3120 if (opc
== 0x3) { /* ANDS */
3121 tcg_rd
= cpu_reg(s
, rd
);
3123 tcg_rd
= cpu_reg_sp(s
, rd
);
3125 tcg_rn
= cpu_reg(s
, rn
);
3127 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3128 /* some immediate field values are reserved */
3129 unallocated_encoding(s
);
3134 wmask
&= 0xffffffff;
3138 case 0x3: /* ANDS */
3140 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3144 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3147 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3150 assert(FALSE
); /* must handle all above */
3154 if (!sf
&& !is_and
) {
3155 /* zero extend final result; we know we can skip this for AND
3156 * since the immediate had the high 32 bits clear.
3158 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3161 if (opc
== 3) { /* ANDS */
3162 gen_logic_CC(sf
, tcg_rd
);
3167 * Move wide (immediate)
3169 * 31 30 29 28 23 22 21 20 5 4 0
3170 * +--+-----+-------------+-----+----------------+------+
3171 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3172 * +--+-----+-------------+-----+----------------+------+
3174 * sf: 0 -> 32 bit, 1 -> 64 bit
3175 * opc: 00 -> N, 10 -> Z, 11 -> K
3176 * hw: shift/16 (0,16, and sf only 32, 48)
3178 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3180 int rd
= extract32(insn
, 0, 5);
3181 uint64_t imm
= extract32(insn
, 5, 16);
3182 int sf
= extract32(insn
, 31, 1);
3183 int opc
= extract32(insn
, 29, 2);
3184 int pos
= extract32(insn
, 21, 2) << 4;
3185 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3188 if (!sf
&& (pos
>= 32)) {
3189 unallocated_encoding(s
);
3203 tcg_gen_movi_i64(tcg_rd
, imm
);
3206 tcg_imm
= tcg_const_i64(imm
);
3207 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3208 tcg_temp_free_i64(tcg_imm
);
3210 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3214 unallocated_encoding(s
);
3220 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3221 * +----+-----+-------------+---+------+------+------+------+
3222 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3223 * +----+-----+-------------+---+------+------+------+------+
3225 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3227 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3228 TCGv_i64 tcg_rd
, tcg_tmp
;
3230 sf
= extract32(insn
, 31, 1);
3231 opc
= extract32(insn
, 29, 2);
3232 n
= extract32(insn
, 22, 1);
3233 ri
= extract32(insn
, 16, 6);
3234 si
= extract32(insn
, 10, 6);
3235 rn
= extract32(insn
, 5, 5);
3236 rd
= extract32(insn
, 0, 5);
3237 bitsize
= sf
? 64 : 32;
3239 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3240 unallocated_encoding(s
);
3244 tcg_rd
= cpu_reg(s
, rd
);
3246 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3247 to be smaller than bitsize, we'll never reference data outside the
3248 low 32-bits anyway. */
3249 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3251 /* Recognize simple(r) extractions. */
3253 /* Wd<s-r:0> = Wn<s:r> */
3254 len
= (si
- ri
) + 1;
3255 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3256 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3258 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3259 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3262 /* opc == 1, BXFIL fall through to deposit */
3263 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
3266 /* Handle the ri > si case with a deposit
3267 * Wd<32+s-r,32-r> = Wn<s:0>
3270 pos
= (bitsize
- ri
) & (bitsize
- 1);
3273 if (opc
== 0 && len
< ri
) {
3274 /* SBFM: sign extend the destination field from len to fill
3275 the balance of the word. Let the deposit below insert all
3276 of those sign bits. */
3277 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3281 if (opc
== 1) { /* BFM, BXFIL */
3282 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3284 /* SBFM or UBFM: We start with zero, and we haven't modified
3285 any bits outside bitsize, therefore the zero-extension
3286 below is unneeded. */
3287 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3292 if (!sf
) { /* zero extend final result */
3293 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3298 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3299 * +----+------+-------------+---+----+------+--------+------+------+
3300 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3301 * +----+------+-------------+---+----+------+--------+------+------+
3303 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3305 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3307 sf
= extract32(insn
, 31, 1);
3308 n
= extract32(insn
, 22, 1);
3309 rm
= extract32(insn
, 16, 5);
3310 imm
= extract32(insn
, 10, 6);
3311 rn
= extract32(insn
, 5, 5);
3312 rd
= extract32(insn
, 0, 5);
3313 op21
= extract32(insn
, 29, 2);
3314 op0
= extract32(insn
, 21, 1);
3315 bitsize
= sf
? 64 : 32;
3317 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3318 unallocated_encoding(s
);
3320 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3322 tcg_rd
= cpu_reg(s
, rd
);
3324 if (unlikely(imm
== 0)) {
3325 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3326 * so an extract from bit 0 is a special case.
3329 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3331 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3333 } else if (rm
== rn
) { /* ROR */
3334 tcg_rm
= cpu_reg(s
, rm
);
3336 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
3338 TCGv_i32 tmp
= tcg_temp_new_i32();
3339 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
3340 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
3341 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
3342 tcg_temp_free_i32(tmp
);
3345 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3346 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3347 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3348 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3349 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3351 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3357 /* Data processing - immediate */
3358 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3360 switch (extract32(insn
, 23, 6)) {
3361 case 0x20: case 0x21: /* PC-rel. addressing */
3362 disas_pc_rel_adr(s
, insn
);
3364 case 0x22: case 0x23: /* Add/subtract (immediate) */
3365 disas_add_sub_imm(s
, insn
);
3367 case 0x24: /* Logical (immediate) */
3368 disas_logic_imm(s
, insn
);
3370 case 0x25: /* Move wide (immediate) */
3371 disas_movw_imm(s
, insn
);
3373 case 0x26: /* Bitfield */
3374 disas_bitfield(s
, insn
);
3376 case 0x27: /* Extract */
3377 disas_extract(s
, insn
);
3380 unallocated_encoding(s
);
3385 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3386 * Note that it is the caller's responsibility to ensure that the
3387 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3388 * mandated semantics for out of range shifts.
3390 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3391 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3393 switch (shift_type
) {
3394 case A64_SHIFT_TYPE_LSL
:
3395 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3397 case A64_SHIFT_TYPE_LSR
:
3398 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3400 case A64_SHIFT_TYPE_ASR
:
3402 tcg_gen_ext32s_i64(dst
, src
);
3404 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3406 case A64_SHIFT_TYPE_ROR
:
3408 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3411 t0
= tcg_temp_new_i32();
3412 t1
= tcg_temp_new_i32();
3413 tcg_gen_extrl_i64_i32(t0
, src
);
3414 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
3415 tcg_gen_rotr_i32(t0
, t0
, t1
);
3416 tcg_gen_extu_i32_i64(dst
, t0
);
3417 tcg_temp_free_i32(t0
);
3418 tcg_temp_free_i32(t1
);
3422 assert(FALSE
); /* all shift types should be handled */
3426 if (!sf
) { /* zero extend final result */
3427 tcg_gen_ext32u_i64(dst
, dst
);
3431 /* Shift a TCGv src by immediate, put result in dst.
3432 * The shift amount must be in range (this should always be true as the
3433 * relevant instructions will UNDEF on bad shift immediates).
3435 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3436 enum a64_shift_type shift_type
, unsigned int shift_i
)
3438 assert(shift_i
< (sf
? 64 : 32));
3441 tcg_gen_mov_i64(dst
, src
);
3443 TCGv_i64 shift_const
;
3445 shift_const
= tcg_const_i64(shift_i
);
3446 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3447 tcg_temp_free_i64(shift_const
);
3451 /* Logical (shifted register)
3452 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3453 * +----+-----+-----------+-------+---+------+--------+------+------+
3454 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3455 * +----+-----+-----------+-------+---+------+--------+------+------+
3457 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3459 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3460 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3462 sf
= extract32(insn
, 31, 1);
3463 opc
= extract32(insn
, 29, 2);
3464 shift_type
= extract32(insn
, 22, 2);
3465 invert
= extract32(insn
, 21, 1);
3466 rm
= extract32(insn
, 16, 5);
3467 shift_amount
= extract32(insn
, 10, 6);
3468 rn
= extract32(insn
, 5, 5);
3469 rd
= extract32(insn
, 0, 5);
3471 if (!sf
&& (shift_amount
& (1 << 5))) {
3472 unallocated_encoding(s
);
3476 tcg_rd
= cpu_reg(s
, rd
);
3478 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3479 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3480 * register-register MOV and MVN, so it is worth special casing.
3482 tcg_rm
= cpu_reg(s
, rm
);
3484 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3486 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3490 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3492 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3498 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3501 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3504 tcg_rn
= cpu_reg(s
, rn
);
3506 switch (opc
| (invert
<< 2)) {
3509 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3512 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3515 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3519 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3522 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3525 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3533 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3537 gen_logic_CC(sf
, tcg_rd
);
3542 * Add/subtract (extended register)
3544 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3545 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3546 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3547 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3549 * sf: 0 -> 32bit, 1 -> 64bit
3550 * op: 0 -> add , 1 -> sub
3553 * option: extension type (see DecodeRegExtend)
3554 * imm3: optional shift to Rm
3556 * Rd = Rn + LSL(extend(Rm), amount)
3558 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3560 int rd
= extract32(insn
, 0, 5);
3561 int rn
= extract32(insn
, 5, 5);
3562 int imm3
= extract32(insn
, 10, 3);
3563 int option
= extract32(insn
, 13, 3);
3564 int rm
= extract32(insn
, 16, 5);
3565 bool setflags
= extract32(insn
, 29, 1);
3566 bool sub_op
= extract32(insn
, 30, 1);
3567 bool sf
= extract32(insn
, 31, 1);
3569 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3571 TCGv_i64 tcg_result
;
3574 unallocated_encoding(s
);
3578 /* non-flag setting ops may use SP */
3580 tcg_rd
= cpu_reg_sp(s
, rd
);
3582 tcg_rd
= cpu_reg(s
, rd
);
3584 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3586 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3587 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3589 tcg_result
= tcg_temp_new_i64();
3593 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3595 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3599 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3601 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3606 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3608 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3611 tcg_temp_free_i64(tcg_result
);
3615 * Add/subtract (shifted register)
3617 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3618 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3619 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3620 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3622 * sf: 0 -> 32bit, 1 -> 64bit
3623 * op: 0 -> add , 1 -> sub
3625 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3626 * imm6: Shift amount to apply to Rm before the add/sub
3628 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3630 int rd
= extract32(insn
, 0, 5);
3631 int rn
= extract32(insn
, 5, 5);
3632 int imm6
= extract32(insn
, 10, 6);
3633 int rm
= extract32(insn
, 16, 5);
3634 int shift_type
= extract32(insn
, 22, 2);
3635 bool setflags
= extract32(insn
, 29, 1);
3636 bool sub_op
= extract32(insn
, 30, 1);
3637 bool sf
= extract32(insn
, 31, 1);
3639 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3640 TCGv_i64 tcg_rn
, tcg_rm
;
3641 TCGv_i64 tcg_result
;
3643 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3644 unallocated_encoding(s
);
3648 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3649 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3651 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3653 tcg_result
= tcg_temp_new_i64();
3657 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3659 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3663 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3665 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3670 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3672 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3675 tcg_temp_free_i64(tcg_result
);
3678 /* Data-processing (3 source)
3680 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3681 * +--+------+-----------+------+------+----+------+------+------+
3682 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3683 * +--+------+-----------+------+------+----+------+------+------+
3685 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3687 int rd
= extract32(insn
, 0, 5);
3688 int rn
= extract32(insn
, 5, 5);
3689 int ra
= extract32(insn
, 10, 5);
3690 int rm
= extract32(insn
, 16, 5);
3691 int op_id
= (extract32(insn
, 29, 3) << 4) |
3692 (extract32(insn
, 21, 3) << 1) |
3693 extract32(insn
, 15, 1);
3694 bool sf
= extract32(insn
, 31, 1);
3695 bool is_sub
= extract32(op_id
, 0, 1);
3696 bool is_high
= extract32(op_id
, 2, 1);
3697 bool is_signed
= false;
3702 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3704 case 0x42: /* SMADDL */
3705 case 0x43: /* SMSUBL */
3706 case 0x44: /* SMULH */
3709 case 0x0: /* MADD (32bit) */
3710 case 0x1: /* MSUB (32bit) */
3711 case 0x40: /* MADD (64bit) */
3712 case 0x41: /* MSUB (64bit) */
3713 case 0x4a: /* UMADDL */
3714 case 0x4b: /* UMSUBL */
3715 case 0x4c: /* UMULH */
3718 unallocated_encoding(s
);
3723 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3724 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3725 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3726 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3729 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3731 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3734 tcg_temp_free_i64(low_bits
);
3738 tcg_op1
= tcg_temp_new_i64();
3739 tcg_op2
= tcg_temp_new_i64();
3740 tcg_tmp
= tcg_temp_new_i64();
3743 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3744 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3747 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3748 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3750 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3751 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3755 if (ra
== 31 && !is_sub
) {
3756 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3757 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3759 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3761 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3763 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3768 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3771 tcg_temp_free_i64(tcg_op1
);
3772 tcg_temp_free_i64(tcg_op2
);
3773 tcg_temp_free_i64(tcg_tmp
);
3776 /* Add/subtract (with carry)
3777 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3778 * +--+--+--+------------------------+------+---------+------+-----+
3779 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3780 * +--+--+--+------------------------+------+---------+------+-----+
3784 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3786 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3787 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3789 if (extract32(insn
, 10, 6) != 0) {
3790 unallocated_encoding(s
);
3794 sf
= extract32(insn
, 31, 1);
3795 op
= extract32(insn
, 30, 1);
3796 setflags
= extract32(insn
, 29, 1);
3797 rm
= extract32(insn
, 16, 5);
3798 rn
= extract32(insn
, 5, 5);
3799 rd
= extract32(insn
, 0, 5);
3801 tcg_rd
= cpu_reg(s
, rd
);
3802 tcg_rn
= cpu_reg(s
, rn
);
3805 tcg_y
= new_tmp_a64(s
);
3806 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3808 tcg_y
= cpu_reg(s
, rm
);
3812 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3814 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3818 /* Conditional compare (immediate / register)
3819 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3820 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3821 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3822 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3825 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3827 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3828 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
3829 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3832 if (!extract32(insn
, 29, 1)) {
3833 unallocated_encoding(s
);
3836 if (insn
& (1 << 10 | 1 << 4)) {
3837 unallocated_encoding(s
);
3840 sf
= extract32(insn
, 31, 1);
3841 op
= extract32(insn
, 30, 1);
3842 is_imm
= extract32(insn
, 11, 1);
3843 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3844 cond
= extract32(insn
, 12, 4);
3845 rn
= extract32(insn
, 5, 5);
3846 nzcv
= extract32(insn
, 0, 4);
3848 /* Set T0 = !COND. */
3849 tcg_t0
= tcg_temp_new_i32();
3850 arm_test_cc(&c
, cond
);
3851 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
3854 /* Load the arguments for the new comparison. */
3856 tcg_y
= new_tmp_a64(s
);
3857 tcg_gen_movi_i64(tcg_y
, y
);
3859 tcg_y
= cpu_reg(s
, y
);
3861 tcg_rn
= cpu_reg(s
, rn
);
3863 /* Set the flags for the new comparison. */
3864 tcg_tmp
= tcg_temp_new_i64();
3866 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3868 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3870 tcg_temp_free_i64(tcg_tmp
);
3872 /* If COND was false, force the flags to #nzcv. Compute two masks
3873 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
3874 * For tcg hosts that support ANDC, we can make do with just T1.
3875 * In either case, allow the tcg optimizer to delete any unused mask.
3877 tcg_t1
= tcg_temp_new_i32();
3878 tcg_t2
= tcg_temp_new_i32();
3879 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
3880 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
3882 if (nzcv
& 8) { /* N */
3883 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3885 if (TCG_TARGET_HAS_andc_i32
) {
3886 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3888 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
3891 if (nzcv
& 4) { /* Z */
3892 if (TCG_TARGET_HAS_andc_i32
) {
3893 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
3895 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
3898 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
3900 if (nzcv
& 2) { /* C */
3901 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
3903 if (TCG_TARGET_HAS_andc_i32
) {
3904 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
3906 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
3909 if (nzcv
& 1) { /* V */
3910 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3912 if (TCG_TARGET_HAS_andc_i32
) {
3913 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3915 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
3918 tcg_temp_free_i32(tcg_t0
);
3919 tcg_temp_free_i32(tcg_t1
);
3920 tcg_temp_free_i32(tcg_t2
);
3923 /* Conditional select
3924 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3925 * +----+----+---+-----------------+------+------+-----+------+------+
3926 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3927 * +----+----+---+-----------------+------+------+-----+------+------+
3929 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3931 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3932 TCGv_i64 tcg_rd
, zero
;
3935 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3936 /* S == 1 or op2<1> == 1 */
3937 unallocated_encoding(s
);
3940 sf
= extract32(insn
, 31, 1);
3941 else_inv
= extract32(insn
, 30, 1);
3942 rm
= extract32(insn
, 16, 5);
3943 cond
= extract32(insn
, 12, 4);
3944 else_inc
= extract32(insn
, 10, 1);
3945 rn
= extract32(insn
, 5, 5);
3946 rd
= extract32(insn
, 0, 5);
3948 tcg_rd
= cpu_reg(s
, rd
);
3950 a64_test_cc(&c
, cond
);
3951 zero
= tcg_const_i64(0);
3953 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
3955 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
3957 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
3960 TCGv_i64 t_true
= cpu_reg(s
, rn
);
3961 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
3962 if (else_inv
&& else_inc
) {
3963 tcg_gen_neg_i64(t_false
, t_false
);
3964 } else if (else_inv
) {
3965 tcg_gen_not_i64(t_false
, t_false
);
3966 } else if (else_inc
) {
3967 tcg_gen_addi_i64(t_false
, t_false
, 1);
3969 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
3972 tcg_temp_free_i64(zero
);
3976 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3980 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3981 unsigned int rn
, unsigned int rd
)
3983 TCGv_i64 tcg_rd
, tcg_rn
;
3984 tcg_rd
= cpu_reg(s
, rd
);
3985 tcg_rn
= cpu_reg(s
, rn
);
3988 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
3990 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3991 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3992 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
3993 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3994 tcg_temp_free_i32(tcg_tmp32
);
3998 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3999 unsigned int rn
, unsigned int rd
)
4001 TCGv_i64 tcg_rd
, tcg_rn
;
4002 tcg_rd
= cpu_reg(s
, rd
);
4003 tcg_rn
= cpu_reg(s
, rn
);
4006 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4008 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4009 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4010 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4011 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4012 tcg_temp_free_i32(tcg_tmp32
);
4016 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4017 unsigned int rn
, unsigned int rd
)
4019 TCGv_i64 tcg_rd
, tcg_rn
;
4020 tcg_rd
= cpu_reg(s
, rd
);
4021 tcg_rn
= cpu_reg(s
, rn
);
4024 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4026 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4027 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4028 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4029 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4030 tcg_temp_free_i32(tcg_tmp32
);
4034 /* REV with sf==1, opcode==3 ("REV64") */
4035 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4036 unsigned int rn
, unsigned int rd
)
4039 unallocated_encoding(s
);
4042 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4045 /* REV with sf==0, opcode==2
4046 * REV32 (sf==1, opcode==2)
4048 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4049 unsigned int rn
, unsigned int rd
)
4051 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4054 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4055 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4057 /* bswap32_i64 requires zero high word */
4058 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4059 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4060 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4061 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4062 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4064 tcg_temp_free_i64(tcg_tmp
);
4066 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4067 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4071 /* REV16 (opcode==1) */
4072 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4073 unsigned int rn
, unsigned int rd
)
4075 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4076 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4077 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4078 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4080 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4081 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4082 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4083 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4084 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4086 tcg_temp_free_i64(mask
);
4087 tcg_temp_free_i64(tcg_tmp
);
4090 /* Data-processing (1 source)
4091 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4092 * +----+---+---+-----------------+---------+--------+------+------+
4093 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4094 * +----+---+---+-----------------+---------+--------+------+------+
4096 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4098 unsigned int sf
, opcode
, rn
, rd
;
4100 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
4101 unallocated_encoding(s
);
4105 sf
= extract32(insn
, 31, 1);
4106 opcode
= extract32(insn
, 10, 6);
4107 rn
= extract32(insn
, 5, 5);
4108 rd
= extract32(insn
, 0, 5);
4112 handle_rbit(s
, sf
, rn
, rd
);
4115 handle_rev16(s
, sf
, rn
, rd
);
4118 handle_rev32(s
, sf
, rn
, rd
);
4121 handle_rev64(s
, sf
, rn
, rd
);
4124 handle_clz(s
, sf
, rn
, rd
);
4127 handle_cls(s
, sf
, rn
, rd
);
4132 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
4133 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4135 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
4136 tcg_rd
= cpu_reg(s
, rd
);
4138 if (!sf
&& is_signed
) {
4139 tcg_n
= new_tmp_a64(s
);
4140 tcg_m
= new_tmp_a64(s
);
4141 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
4142 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
4144 tcg_n
= read_cpu_reg(s
, rn
, sf
);
4145 tcg_m
= read_cpu_reg(s
, rm
, sf
);
4149 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
4151 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
4154 if (!sf
) { /* zero extend final result */
4155 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4159 /* LSLV, LSRV, ASRV, RORV */
4160 static void handle_shift_reg(DisasContext
*s
,
4161 enum a64_shift_type shift_type
, unsigned int sf
,
4162 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4164 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
4165 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4166 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4168 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
4169 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
4170 tcg_temp_free_i64(tcg_shift
);
4173 /* CRC32[BHWX], CRC32C[BHWX] */
4174 static void handle_crc32(DisasContext
*s
,
4175 unsigned int sf
, unsigned int sz
, bool crc32c
,
4176 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4178 TCGv_i64 tcg_acc
, tcg_val
;
4181 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)
4182 || (sf
== 1 && sz
!= 3)
4183 || (sf
== 0 && sz
== 3)) {
4184 unallocated_encoding(s
);
4189 tcg_val
= cpu_reg(s
, rm
);
4203 g_assert_not_reached();
4205 tcg_val
= new_tmp_a64(s
);
4206 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
4209 tcg_acc
= cpu_reg(s
, rn
);
4210 tcg_bytes
= tcg_const_i32(1 << sz
);
4213 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4215 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4218 tcg_temp_free_i32(tcg_bytes
);
4221 /* Data-processing (2 source)
4222 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4223 * +----+---+---+-----------------+------+--------+------+------+
4224 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4225 * +----+---+---+-----------------+------+--------+------+------+
4227 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
4229 unsigned int sf
, rm
, opcode
, rn
, rd
;
4230 sf
= extract32(insn
, 31, 1);
4231 rm
= extract32(insn
, 16, 5);
4232 opcode
= extract32(insn
, 10, 6);
4233 rn
= extract32(insn
, 5, 5);
4234 rd
= extract32(insn
, 0, 5);
4236 if (extract32(insn
, 29, 1)) {
4237 unallocated_encoding(s
);
4243 handle_div(s
, false, sf
, rm
, rn
, rd
);
4246 handle_div(s
, true, sf
, rm
, rn
, rd
);
4249 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
4252 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
4255 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
4258 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
4267 case 23: /* CRC32 */
4269 int sz
= extract32(opcode
, 0, 2);
4270 bool crc32c
= extract32(opcode
, 2, 1);
4271 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
4275 unallocated_encoding(s
);
4280 /* Data processing - register */
4281 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
4283 switch (extract32(insn
, 24, 5)) {
4284 case 0x0a: /* Logical (shifted register) */
4285 disas_logic_reg(s
, insn
);
4287 case 0x0b: /* Add/subtract */
4288 if (insn
& (1 << 21)) { /* (extended register) */
4289 disas_add_sub_ext_reg(s
, insn
);
4291 disas_add_sub_reg(s
, insn
);
4294 case 0x1b: /* Data-processing (3 source) */
4295 disas_data_proc_3src(s
, insn
);
4298 switch (extract32(insn
, 21, 3)) {
4299 case 0x0: /* Add/subtract (with carry) */
4300 disas_adc_sbc(s
, insn
);
4302 case 0x2: /* Conditional compare */
4303 disas_cc(s
, insn
); /* both imm and reg forms */
4305 case 0x4: /* Conditional select */
4306 disas_cond_select(s
, insn
);
4308 case 0x6: /* Data-processing */
4309 if (insn
& (1 << 30)) { /* (1 source) */
4310 disas_data_proc_1src(s
, insn
);
4311 } else { /* (2 source) */
4312 disas_data_proc_2src(s
, insn
);
4316 unallocated_encoding(s
);
4321 unallocated_encoding(s
);
4326 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
4327 unsigned int rn
, unsigned int rm
,
4328 bool cmp_with_zero
, bool signal_all_nans
)
4330 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4331 TCGv_ptr fpst
= get_fpstatus_ptr();
4334 TCGv_i64 tcg_vn
, tcg_vm
;
4336 tcg_vn
= read_fp_dreg(s
, rn
);
4337 if (cmp_with_zero
) {
4338 tcg_vm
= tcg_const_i64(0);
4340 tcg_vm
= read_fp_dreg(s
, rm
);
4342 if (signal_all_nans
) {
4343 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4345 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4347 tcg_temp_free_i64(tcg_vn
);
4348 tcg_temp_free_i64(tcg_vm
);
4350 TCGv_i32 tcg_vn
, tcg_vm
;
4352 tcg_vn
= read_fp_sreg(s
, rn
);
4353 if (cmp_with_zero
) {
4354 tcg_vm
= tcg_const_i32(0);
4356 tcg_vm
= read_fp_sreg(s
, rm
);
4358 if (signal_all_nans
) {
4359 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4361 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4363 tcg_temp_free_i32(tcg_vn
);
4364 tcg_temp_free_i32(tcg_vm
);
4367 tcg_temp_free_ptr(fpst
);
4369 gen_set_nzcv(tcg_flags
);
4371 tcg_temp_free_i64(tcg_flags
);
4374 /* Floating point compare
4375 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4376 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4377 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4378 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4380 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4382 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4384 mos
= extract32(insn
, 29, 3);
4385 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4386 rm
= extract32(insn
, 16, 5);
4387 op
= extract32(insn
, 14, 2);
4388 rn
= extract32(insn
, 5, 5);
4389 opc
= extract32(insn
, 3, 2);
4390 op2r
= extract32(insn
, 0, 3);
4392 if (mos
|| op
|| op2r
|| type
> 1) {
4393 unallocated_encoding(s
);
4397 if (!fp_access_check(s
)) {
4401 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
4404 /* Floating point conditional compare
4405 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4406 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4407 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4408 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4410 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4412 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4414 TCGLabel
*label_continue
= NULL
;
4416 mos
= extract32(insn
, 29, 3);
4417 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4418 rm
= extract32(insn
, 16, 5);
4419 cond
= extract32(insn
, 12, 4);
4420 rn
= extract32(insn
, 5, 5);
4421 op
= extract32(insn
, 4, 1);
4422 nzcv
= extract32(insn
, 0, 4);
4424 if (mos
|| type
> 1) {
4425 unallocated_encoding(s
);
4429 if (!fp_access_check(s
)) {
4433 if (cond
< 0x0e) { /* not always */
4434 TCGLabel
*label_match
= gen_new_label();
4435 label_continue
= gen_new_label();
4436 arm_gen_test_cc(cond
, label_match
);
4438 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4439 gen_set_nzcv(tcg_flags
);
4440 tcg_temp_free_i64(tcg_flags
);
4441 tcg_gen_br(label_continue
);
4442 gen_set_label(label_match
);
4445 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
4448 gen_set_label(label_continue
);
4452 /* Floating point conditional select
4453 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4454 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4455 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4456 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4458 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4460 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4461 TCGv_i64 t_true
, t_false
, t_zero
;
4464 mos
= extract32(insn
, 29, 3);
4465 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4466 rm
= extract32(insn
, 16, 5);
4467 cond
= extract32(insn
, 12, 4);
4468 rn
= extract32(insn
, 5, 5);
4469 rd
= extract32(insn
, 0, 5);
4471 if (mos
|| type
> 1) {
4472 unallocated_encoding(s
);
4476 if (!fp_access_check(s
)) {
4480 /* Zero extend sreg inputs to 64 bits now. */
4481 t_true
= tcg_temp_new_i64();
4482 t_false
= tcg_temp_new_i64();
4483 read_vec_element(s
, t_true
, rn
, 0, type
? MO_64
: MO_32
);
4484 read_vec_element(s
, t_false
, rm
, 0, type
? MO_64
: MO_32
);
4486 a64_test_cc(&c
, cond
);
4487 t_zero
= tcg_const_i64(0);
4488 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
4489 tcg_temp_free_i64(t_zero
);
4490 tcg_temp_free_i64(t_false
);
4493 /* Note that sregs write back zeros to the high bits,
4494 and we've already done the zero-extension. */
4495 write_fp_dreg(s
, rd
, t_true
);
4496 tcg_temp_free_i64(t_true
);
4499 /* Floating-point data-processing (1 source) - single precision */
4500 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
4506 fpst
= get_fpstatus_ptr();
4507 tcg_op
= read_fp_sreg(s
, rn
);
4508 tcg_res
= tcg_temp_new_i32();
4511 case 0x0: /* FMOV */
4512 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4514 case 0x1: /* FABS */
4515 gen_helper_vfp_abss(tcg_res
, tcg_op
);
4517 case 0x2: /* FNEG */
4518 gen_helper_vfp_negs(tcg_res
, tcg_op
);
4520 case 0x3: /* FSQRT */
4521 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
4523 case 0x8: /* FRINTN */
4524 case 0x9: /* FRINTP */
4525 case 0xa: /* FRINTM */
4526 case 0xb: /* FRINTZ */
4527 case 0xc: /* FRINTA */
4529 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4531 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4532 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4534 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4535 tcg_temp_free_i32(tcg_rmode
);
4538 case 0xe: /* FRINTX */
4539 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
4541 case 0xf: /* FRINTI */
4542 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4548 write_fp_sreg(s
, rd
, tcg_res
);
4550 tcg_temp_free_ptr(fpst
);
4551 tcg_temp_free_i32(tcg_op
);
4552 tcg_temp_free_i32(tcg_res
);
4555 /* Floating-point data-processing (1 source) - double precision */
4556 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4562 fpst
= get_fpstatus_ptr();
4563 tcg_op
= read_fp_dreg(s
, rn
);
4564 tcg_res
= tcg_temp_new_i64();
4567 case 0x0: /* FMOV */
4568 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4570 case 0x1: /* FABS */
4571 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4573 case 0x2: /* FNEG */
4574 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4576 case 0x3: /* FSQRT */
4577 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4579 case 0x8: /* FRINTN */
4580 case 0x9: /* FRINTP */
4581 case 0xa: /* FRINTM */
4582 case 0xb: /* FRINTZ */
4583 case 0xc: /* FRINTA */
4585 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4587 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4588 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4590 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4591 tcg_temp_free_i32(tcg_rmode
);
4594 case 0xe: /* FRINTX */
4595 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4597 case 0xf: /* FRINTI */
4598 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4604 write_fp_dreg(s
, rd
, tcg_res
);
4606 tcg_temp_free_ptr(fpst
);
4607 tcg_temp_free_i64(tcg_op
);
4608 tcg_temp_free_i64(tcg_res
);
4611 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4612 int rd
, int rn
, int dtype
, int ntype
)
4617 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4619 /* Single to double */
4620 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4621 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4622 write_fp_dreg(s
, rd
, tcg_rd
);
4623 tcg_temp_free_i64(tcg_rd
);
4625 /* Single to half */
4626 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4627 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4628 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4629 write_fp_sreg(s
, rd
, tcg_rd
);
4630 tcg_temp_free_i32(tcg_rd
);
4632 tcg_temp_free_i32(tcg_rn
);
4637 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4638 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4640 /* Double to single */
4641 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4643 /* Double to half */
4644 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4645 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4647 write_fp_sreg(s
, rd
, tcg_rd
);
4648 tcg_temp_free_i32(tcg_rd
);
4649 tcg_temp_free_i64(tcg_rn
);
4654 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4655 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4657 /* Half to single */
4658 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4659 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4660 write_fp_sreg(s
, rd
, tcg_rd
);
4661 tcg_temp_free_i32(tcg_rd
);
4663 /* Half to double */
4664 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4665 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4666 write_fp_dreg(s
, rd
, tcg_rd
);
4667 tcg_temp_free_i64(tcg_rd
);
4669 tcg_temp_free_i32(tcg_rn
);
4677 /* Floating point data-processing (1 source)
4678 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4679 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4680 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4681 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4683 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4685 int type
= extract32(insn
, 22, 2);
4686 int opcode
= extract32(insn
, 15, 6);
4687 int rn
= extract32(insn
, 5, 5);
4688 int rd
= extract32(insn
, 0, 5);
4691 case 0x4: case 0x5: case 0x7:
4693 /* FCVT between half, single and double precision */
4694 int dtype
= extract32(opcode
, 0, 2);
4695 if (type
== 2 || dtype
== type
) {
4696 unallocated_encoding(s
);
4699 if (!fp_access_check(s
)) {
4703 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4709 /* 32-to-32 and 64-to-64 ops */
4712 if (!fp_access_check(s
)) {
4716 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4719 if (!fp_access_check(s
)) {
4723 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4726 unallocated_encoding(s
);
4730 unallocated_encoding(s
);
4735 /* Floating-point data-processing (2 source) - single precision */
4736 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4737 int rd
, int rn
, int rm
)
4744 tcg_res
= tcg_temp_new_i32();
4745 fpst
= get_fpstatus_ptr();
4746 tcg_op1
= read_fp_sreg(s
, rn
);
4747 tcg_op2
= read_fp_sreg(s
, rm
);
4750 case 0x0: /* FMUL */
4751 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4753 case 0x1: /* FDIV */
4754 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4756 case 0x2: /* FADD */
4757 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4759 case 0x3: /* FSUB */
4760 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4762 case 0x4: /* FMAX */
4763 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4765 case 0x5: /* FMIN */
4766 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4768 case 0x6: /* FMAXNM */
4769 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4771 case 0x7: /* FMINNM */
4772 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4774 case 0x8: /* FNMUL */
4775 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4776 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4780 write_fp_sreg(s
, rd
, tcg_res
);
4782 tcg_temp_free_ptr(fpst
);
4783 tcg_temp_free_i32(tcg_op1
);
4784 tcg_temp_free_i32(tcg_op2
);
4785 tcg_temp_free_i32(tcg_res
);
4788 /* Floating-point data-processing (2 source) - double precision */
4789 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4790 int rd
, int rn
, int rm
)
4797 tcg_res
= tcg_temp_new_i64();
4798 fpst
= get_fpstatus_ptr();
4799 tcg_op1
= read_fp_dreg(s
, rn
);
4800 tcg_op2
= read_fp_dreg(s
, rm
);
4803 case 0x0: /* FMUL */
4804 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4806 case 0x1: /* FDIV */
4807 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4809 case 0x2: /* FADD */
4810 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4812 case 0x3: /* FSUB */
4813 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4815 case 0x4: /* FMAX */
4816 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4818 case 0x5: /* FMIN */
4819 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4821 case 0x6: /* FMAXNM */
4822 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4824 case 0x7: /* FMINNM */
4825 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4827 case 0x8: /* FNMUL */
4828 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4829 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4833 write_fp_dreg(s
, rd
, tcg_res
);
4835 tcg_temp_free_ptr(fpst
);
4836 tcg_temp_free_i64(tcg_op1
);
4837 tcg_temp_free_i64(tcg_op2
);
4838 tcg_temp_free_i64(tcg_res
);
4841 /* Floating point data-processing (2 source)
4842 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4843 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4844 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4845 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4847 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4849 int type
= extract32(insn
, 22, 2);
4850 int rd
= extract32(insn
, 0, 5);
4851 int rn
= extract32(insn
, 5, 5);
4852 int rm
= extract32(insn
, 16, 5);
4853 int opcode
= extract32(insn
, 12, 4);
4856 unallocated_encoding(s
);
4862 if (!fp_access_check(s
)) {
4865 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4868 if (!fp_access_check(s
)) {
4871 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4874 unallocated_encoding(s
);
4878 /* Floating-point data-processing (3 source) - single precision */
4879 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4880 int rd
, int rn
, int rm
, int ra
)
4882 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4883 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4884 TCGv_ptr fpst
= get_fpstatus_ptr();
4886 tcg_op1
= read_fp_sreg(s
, rn
);
4887 tcg_op2
= read_fp_sreg(s
, rm
);
4888 tcg_op3
= read_fp_sreg(s
, ra
);
4890 /* These are fused multiply-add, and must be done as one
4891 * floating point operation with no rounding between the
4892 * multiplication and addition steps.
4893 * NB that doing the negations here as separate steps is
4894 * correct : an input NaN should come out with its sign bit
4895 * flipped if it is a negated-input.
4898 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4902 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4905 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4907 write_fp_sreg(s
, rd
, tcg_res
);
4909 tcg_temp_free_ptr(fpst
);
4910 tcg_temp_free_i32(tcg_op1
);
4911 tcg_temp_free_i32(tcg_op2
);
4912 tcg_temp_free_i32(tcg_op3
);
4913 tcg_temp_free_i32(tcg_res
);
4916 /* Floating-point data-processing (3 source) - double precision */
4917 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4918 int rd
, int rn
, int rm
, int ra
)
4920 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4921 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4922 TCGv_ptr fpst
= get_fpstatus_ptr();
4924 tcg_op1
= read_fp_dreg(s
, rn
);
4925 tcg_op2
= read_fp_dreg(s
, rm
);
4926 tcg_op3
= read_fp_dreg(s
, ra
);
4928 /* These are fused multiply-add, and must be done as one
4929 * floating point operation with no rounding between the
4930 * multiplication and addition steps.
4931 * NB that doing the negations here as separate steps is
4932 * correct : an input NaN should come out with its sign bit
4933 * flipped if it is a negated-input.
4936 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4940 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4943 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4945 write_fp_dreg(s
, rd
, tcg_res
);
4947 tcg_temp_free_ptr(fpst
);
4948 tcg_temp_free_i64(tcg_op1
);
4949 tcg_temp_free_i64(tcg_op2
);
4950 tcg_temp_free_i64(tcg_op3
);
4951 tcg_temp_free_i64(tcg_res
);
4954 /* Floating point data-processing (3 source)
4955 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4956 * +---+---+---+-----------+------+----+------+----+------+------+------+
4957 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4958 * +---+---+---+-----------+------+----+------+----+------+------+------+
4960 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4962 int type
= extract32(insn
, 22, 2);
4963 int rd
= extract32(insn
, 0, 5);
4964 int rn
= extract32(insn
, 5, 5);
4965 int ra
= extract32(insn
, 10, 5);
4966 int rm
= extract32(insn
, 16, 5);
4967 bool o0
= extract32(insn
, 15, 1);
4968 bool o1
= extract32(insn
, 21, 1);
4972 if (!fp_access_check(s
)) {
4975 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4978 if (!fp_access_check(s
)) {
4981 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4984 unallocated_encoding(s
);
4988 /* Floating point immediate
4989 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4990 * +---+---+---+-----------+------+---+------------+-------+------+------+
4991 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4992 * +---+---+---+-----------+------+---+------------+-------+------+------+
4994 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
4996 int rd
= extract32(insn
, 0, 5);
4997 int imm8
= extract32(insn
, 13, 8);
4998 int is_double
= extract32(insn
, 22, 2);
5002 if (is_double
> 1) {
5003 unallocated_encoding(s
);
5007 if (!fp_access_check(s
)) {
5011 /* The imm8 encodes the sign bit, enough bits to represent
5012 * an exponent in the range 01....1xx to 10....0xx,
5013 * and the most significant 4 bits of the mantissa; see
5014 * VFPExpandImm() in the v8 ARM ARM.
5017 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5018 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
5019 extract32(imm8
, 0, 6);
5022 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5023 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
5024 (extract32(imm8
, 0, 6) << 3);
5028 tcg_res
= tcg_const_i64(imm
);
5029 write_fp_dreg(s
, rd
, tcg_res
);
5030 tcg_temp_free_i64(tcg_res
);
5033 /* Handle floating point <=> fixed point conversions. Note that we can
5034 * also deal with fp <=> integer conversions as a special case (scale == 64)
5035 * OPTME: consider handling that special case specially or at least skipping
5036 * the call to scalbn in the helpers for zero shifts.
5038 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
5039 bool itof
, int rmode
, int scale
, int sf
, int type
)
5041 bool is_signed
= !(opcode
& 1);
5042 bool is_double
= type
;
5043 TCGv_ptr tcg_fpstatus
;
5046 tcg_fpstatus
= get_fpstatus_ptr();
5048 tcg_shift
= tcg_const_i32(64 - scale
);
5051 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
5053 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
5056 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
5058 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
5061 tcg_int
= tcg_extend
;
5065 TCGv_i64 tcg_double
= tcg_temp_new_i64();
5067 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
5068 tcg_shift
, tcg_fpstatus
);
5070 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
5071 tcg_shift
, tcg_fpstatus
);
5073 write_fp_dreg(s
, rd
, tcg_double
);
5074 tcg_temp_free_i64(tcg_double
);
5076 TCGv_i32 tcg_single
= tcg_temp_new_i32();
5078 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
5079 tcg_shift
, tcg_fpstatus
);
5081 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
5082 tcg_shift
, tcg_fpstatus
);
5084 write_fp_sreg(s
, rd
, tcg_single
);
5085 tcg_temp_free_i32(tcg_single
);
5088 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
5091 if (extract32(opcode
, 2, 1)) {
5092 /* There are too many rounding modes to all fit into rmode,
5093 * so FCVTA[US] is a special case.
5095 rmode
= FPROUNDING_TIEAWAY
;
5098 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
5100 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5103 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
5106 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
5107 tcg_shift
, tcg_fpstatus
);
5109 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
5110 tcg_shift
, tcg_fpstatus
);
5114 gen_helper_vfp_tould(tcg_int
, tcg_double
,
5115 tcg_shift
, tcg_fpstatus
);
5117 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
5118 tcg_shift
, tcg_fpstatus
);
5121 tcg_temp_free_i64(tcg_double
);
5123 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
5126 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
5127 tcg_shift
, tcg_fpstatus
);
5129 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
5130 tcg_shift
, tcg_fpstatus
);
5133 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5135 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
5136 tcg_shift
, tcg_fpstatus
);
5138 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
5139 tcg_shift
, tcg_fpstatus
);
5141 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5142 tcg_temp_free_i32(tcg_dest
);
5144 tcg_temp_free_i32(tcg_single
);
5147 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5148 tcg_temp_free_i32(tcg_rmode
);
5151 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
5155 tcg_temp_free_ptr(tcg_fpstatus
);
5156 tcg_temp_free_i32(tcg_shift
);
5159 /* Floating point <-> fixed point conversions
5160 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5161 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5162 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
5163 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5165 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
5167 int rd
= extract32(insn
, 0, 5);
5168 int rn
= extract32(insn
, 5, 5);
5169 int scale
= extract32(insn
, 10, 6);
5170 int opcode
= extract32(insn
, 16, 3);
5171 int rmode
= extract32(insn
, 19, 2);
5172 int type
= extract32(insn
, 22, 2);
5173 bool sbit
= extract32(insn
, 29, 1);
5174 bool sf
= extract32(insn
, 31, 1);
5177 if (sbit
|| (type
> 1)
5178 || (!sf
&& scale
< 32)) {
5179 unallocated_encoding(s
);
5183 switch ((rmode
<< 3) | opcode
) {
5184 case 0x2: /* SCVTF */
5185 case 0x3: /* UCVTF */
5188 case 0x18: /* FCVTZS */
5189 case 0x19: /* FCVTZU */
5193 unallocated_encoding(s
);
5197 if (!fp_access_check(s
)) {
5201 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
5204 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
5206 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5207 * without conversion.
5211 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5217 TCGv_i64 tmp
= tcg_temp_new_i64();
5218 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
5219 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5220 tcg_gen_movi_i64(tmp
, 0);
5221 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5222 tcg_temp_free_i64(tmp
);
5228 TCGv_i64 tmp
= tcg_const_i64(0);
5229 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5230 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5231 tcg_temp_free_i64(tmp
);
5235 /* 64 bit to top half. */
5236 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5240 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5245 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
5249 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
5252 /* 64 bits from top half */
5253 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
5259 /* Floating point <-> integer conversions
5260 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5261 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5262 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
5263 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5265 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
5267 int rd
= extract32(insn
, 0, 5);
5268 int rn
= extract32(insn
, 5, 5);
5269 int opcode
= extract32(insn
, 16, 3);
5270 int rmode
= extract32(insn
, 19, 2);
5271 int type
= extract32(insn
, 22, 2);
5272 bool sbit
= extract32(insn
, 29, 1);
5273 bool sf
= extract32(insn
, 31, 1);
5276 unallocated_encoding(s
);
5282 bool itof
= opcode
& 1;
5285 unallocated_encoding(s
);
5289 switch (sf
<< 3 | type
<< 1 | rmode
) {
5290 case 0x0: /* 32 bit */
5291 case 0xa: /* 64 bit */
5292 case 0xd: /* 64 bit to top half of quad */
5295 /* all other sf/type/rmode combinations are invalid */
5296 unallocated_encoding(s
);
5300 if (!fp_access_check(s
)) {
5303 handle_fmov(s
, rd
, rn
, type
, itof
);
5305 /* actual FP conversions */
5306 bool itof
= extract32(opcode
, 1, 1);
5308 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
5309 unallocated_encoding(s
);
5313 if (!fp_access_check(s
)) {
5316 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
5320 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
5321 * 31 30 29 28 25 24 0
5322 * +---+---+---+---------+-----------------------------+
5323 * | | 0 | | 1 1 1 1 | |
5324 * +---+---+---+---------+-----------------------------+
5326 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
5328 if (extract32(insn
, 24, 1)) {
5329 /* Floating point data-processing (3 source) */
5330 disas_fp_3src(s
, insn
);
5331 } else if (extract32(insn
, 21, 1) == 0) {
5332 /* Floating point to fixed point conversions */
5333 disas_fp_fixed_conv(s
, insn
);
5335 switch (extract32(insn
, 10, 2)) {
5337 /* Floating point conditional compare */
5338 disas_fp_ccomp(s
, insn
);
5341 /* Floating point data-processing (2 source) */
5342 disas_fp_2src(s
, insn
);
5345 /* Floating point conditional select */
5346 disas_fp_csel(s
, insn
);
5349 switch (ctz32(extract32(insn
, 12, 4))) {
5350 case 0: /* [15:12] == xxx1 */
5351 /* Floating point immediate */
5352 disas_fp_imm(s
, insn
);
5354 case 1: /* [15:12] == xx10 */
5355 /* Floating point compare */
5356 disas_fp_compare(s
, insn
);
5358 case 2: /* [15:12] == x100 */
5359 /* Floating point data-processing (1 source) */
5360 disas_fp_1src(s
, insn
);
5362 case 3: /* [15:12] == 1000 */
5363 unallocated_encoding(s
);
5365 default: /* [15:12] == 0000 */
5366 /* Floating point <-> integer conversions */
5367 disas_fp_int_conv(s
, insn
);
5375 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
5378 /* Extract 64 bits from the middle of two concatenated 64 bit
5379 * vector register slices left:right. The extracted bits start
5380 * at 'pos' bits into the right (least significant) side.
5381 * We return the result in tcg_right, and guarantee not to
5384 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5385 assert(pos
> 0 && pos
< 64);
5387 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
5388 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
5389 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
5391 tcg_temp_free_i64(tcg_tmp
);
5395 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
5396 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5397 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
5398 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5400 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
5402 int is_q
= extract32(insn
, 30, 1);
5403 int op2
= extract32(insn
, 22, 2);
5404 int imm4
= extract32(insn
, 11, 4);
5405 int rm
= extract32(insn
, 16, 5);
5406 int rn
= extract32(insn
, 5, 5);
5407 int rd
= extract32(insn
, 0, 5);
5408 int pos
= imm4
<< 3;
5409 TCGv_i64 tcg_resl
, tcg_resh
;
5411 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
5412 unallocated_encoding(s
);
5416 if (!fp_access_check(s
)) {
5420 tcg_resh
= tcg_temp_new_i64();
5421 tcg_resl
= tcg_temp_new_i64();
5423 /* Vd gets bits starting at pos bits into Vm:Vn. This is
5424 * either extracting 128 bits from a 128:128 concatenation, or
5425 * extracting 64 bits from a 64:64 concatenation.
5428 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
5430 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
5431 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5433 tcg_gen_movi_i64(tcg_resh
, 0);
5440 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
5441 EltPosns
*elt
= eltposns
;
5448 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
5450 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
5453 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5454 tcg_hh
= tcg_temp_new_i64();
5455 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
5456 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
5457 tcg_temp_free_i64(tcg_hh
);
5461 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5462 tcg_temp_free_i64(tcg_resl
);
5463 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5464 tcg_temp_free_i64(tcg_resh
);
5468 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5469 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5470 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5471 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5473 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
5475 int op2
= extract32(insn
, 22, 2);
5476 int is_q
= extract32(insn
, 30, 1);
5477 int rm
= extract32(insn
, 16, 5);
5478 int rn
= extract32(insn
, 5, 5);
5479 int rd
= extract32(insn
, 0, 5);
5480 int is_tblx
= extract32(insn
, 12, 1);
5481 int len
= extract32(insn
, 13, 2);
5482 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
5483 TCGv_i32 tcg_regno
, tcg_numregs
;
5486 unallocated_encoding(s
);
5490 if (!fp_access_check(s
)) {
5494 /* This does a table lookup: for every byte element in the input
5495 * we index into a table formed from up to four vector registers,
5496 * and then the output is the result of the lookups. Our helper
5497 * function does the lookup operation for a single 64 bit part of
5500 tcg_resl
= tcg_temp_new_i64();
5501 tcg_resh
= tcg_temp_new_i64();
5504 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5506 tcg_gen_movi_i64(tcg_resl
, 0);
5508 if (is_tblx
&& is_q
) {
5509 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5511 tcg_gen_movi_i64(tcg_resh
, 0);
5514 tcg_idx
= tcg_temp_new_i64();
5515 tcg_regno
= tcg_const_i32(rn
);
5516 tcg_numregs
= tcg_const_i32(len
+ 1);
5517 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
5518 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
5519 tcg_regno
, tcg_numregs
);
5521 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
5522 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
5523 tcg_regno
, tcg_numregs
);
5525 tcg_temp_free_i64(tcg_idx
);
5526 tcg_temp_free_i32(tcg_regno
);
5527 tcg_temp_free_i32(tcg_numregs
);
5529 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5530 tcg_temp_free_i64(tcg_resl
);
5531 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5532 tcg_temp_free_i64(tcg_resh
);
5536 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5537 * +---+---+-------------+------+---+------+---+------------------+------+
5538 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5539 * +---+---+-------------+------+---+------+---+------------------+------+
5541 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
5543 int rd
= extract32(insn
, 0, 5);
5544 int rn
= extract32(insn
, 5, 5);
5545 int rm
= extract32(insn
, 16, 5);
5546 int size
= extract32(insn
, 22, 2);
5547 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5548 * bit 2 indicates 1 vs 2 variant of the insn.
5550 int opcode
= extract32(insn
, 12, 2);
5551 bool part
= extract32(insn
, 14, 1);
5552 bool is_q
= extract32(insn
, 30, 1);
5553 int esize
= 8 << size
;
5555 int datasize
= is_q
? 128 : 64;
5556 int elements
= datasize
/ esize
;
5557 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
5559 if (opcode
== 0 || (size
== 3 && !is_q
)) {
5560 unallocated_encoding(s
);
5564 if (!fp_access_check(s
)) {
5568 tcg_resl
= tcg_const_i64(0);
5569 tcg_resh
= tcg_const_i64(0);
5570 tcg_res
= tcg_temp_new_i64();
5572 for (i
= 0; i
< elements
; i
++) {
5574 case 1: /* UZP1/2 */
5576 int midpoint
= elements
/ 2;
5578 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
5580 read_vec_element(s
, tcg_res
, rm
,
5581 2 * (i
- midpoint
) + part
, size
);
5585 case 2: /* TRN1/2 */
5587 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
5589 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
5592 case 3: /* ZIP1/2 */
5594 int base
= part
* elements
/ 2;
5596 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
5598 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5603 g_assert_not_reached();
5608 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5609 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5611 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5612 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5616 tcg_temp_free_i64(tcg_res
);
5618 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5619 tcg_temp_free_i64(tcg_resl
);
5620 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5621 tcg_temp_free_i64(tcg_resh
);
5624 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5625 int opc
, bool is_min
, TCGv_ptr fpst
)
5627 /* Helper function for disas_simd_across_lanes: do a single precision
5628 * min/max operation on the specified two inputs,
5629 * and return the result in tcg_elt1.
5633 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5635 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5640 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5642 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5647 /* AdvSIMD across lanes
5648 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5649 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5650 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5651 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5653 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5655 int rd
= extract32(insn
, 0, 5);
5656 int rn
= extract32(insn
, 5, 5);
5657 int size
= extract32(insn
, 22, 2);
5658 int opcode
= extract32(insn
, 12, 5);
5659 bool is_q
= extract32(insn
, 30, 1);
5660 bool is_u
= extract32(insn
, 29, 1);
5662 bool is_min
= false;
5666 TCGv_i64 tcg_res
, tcg_elt
;
5669 case 0x1b: /* ADDV */
5671 unallocated_encoding(s
);
5675 case 0x3: /* SADDLV, UADDLV */
5676 case 0xa: /* SMAXV, UMAXV */
5677 case 0x1a: /* SMINV, UMINV */
5678 if (size
== 3 || (size
== 2 && !is_q
)) {
5679 unallocated_encoding(s
);
5683 case 0xc: /* FMAXNMV, FMINNMV */
5684 case 0xf: /* FMAXV, FMINV */
5685 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5686 unallocated_encoding(s
);
5689 /* Bit 1 of size field encodes min vs max, and actual size is always
5690 * 32 bits: adjust the size variable so following code can rely on it
5692 is_min
= extract32(size
, 1, 1);
5697 unallocated_encoding(s
);
5701 if (!fp_access_check(s
)) {
5706 elements
= (is_q
? 128 : 64) / esize
;
5708 tcg_res
= tcg_temp_new_i64();
5709 tcg_elt
= tcg_temp_new_i64();
5711 /* These instructions operate across all lanes of a vector
5712 * to produce a single result. We can guarantee that a 64
5713 * bit intermediate is sufficient:
5714 * + for [US]ADDLV the maximum element size is 32 bits, and
5715 * the result type is 64 bits
5716 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5717 * same as the element size, which is 32 bits at most
5718 * For the integer operations we can choose to work at 64
5719 * or 32 bits and truncate at the end; for simplicity
5720 * we use 64 bits always. The floating point
5721 * ops do require 32 bit intermediates, though.
5724 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5726 for (i
= 1; i
< elements
; i
++) {
5727 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5730 case 0x03: /* SADDLV / UADDLV */
5731 case 0x1b: /* ADDV */
5732 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5734 case 0x0a: /* SMAXV / UMAXV */
5735 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5737 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5739 case 0x1a: /* SMINV / UMINV */
5740 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5742 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5746 g_assert_not_reached();
5751 /* Floating point ops which work on 32 bit (single) intermediates.
5752 * Note that correct NaN propagation requires that we do these
5753 * operations in exactly the order specified by the pseudocode.
5755 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5756 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5757 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5758 TCGv_ptr fpst
= get_fpstatus_ptr();
5760 assert(esize
== 32);
5761 assert(elements
== 4);
5763 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5764 tcg_gen_extrl_i64_i32(tcg_elt1
, tcg_elt
);
5765 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5766 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5768 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5770 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5771 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5772 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5773 tcg_gen_extrl_i64_i32(tcg_elt3
, tcg_elt
);
5775 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5777 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5779 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5780 tcg_temp_free_i32(tcg_elt1
);
5781 tcg_temp_free_i32(tcg_elt2
);
5782 tcg_temp_free_i32(tcg_elt3
);
5783 tcg_temp_free_ptr(fpst
);
5786 tcg_temp_free_i64(tcg_elt
);
5788 /* Now truncate the result to the width required for the final output */
5789 if (opcode
== 0x03) {
5790 /* SADDLV, UADDLV: result is 2*esize */
5796 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5799 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5802 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5807 g_assert_not_reached();
5810 write_fp_dreg(s
, rd
, tcg_res
);
5811 tcg_temp_free_i64(tcg_res
);
5814 /* DUP (Element, Vector)
5816 * 31 30 29 21 20 16 15 10 9 5 4 0
5817 * +---+---+-------------------+--------+-------------+------+------+
5818 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5819 * +---+---+-------------------+--------+-------------+------+------+
5821 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5823 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5826 int size
= ctz32(imm5
);
5827 int esize
= 8 << size
;
5828 int elements
= (is_q
? 128 : 64) / esize
;
5832 if (size
> 3 || (size
== 3 && !is_q
)) {
5833 unallocated_encoding(s
);
5837 if (!fp_access_check(s
)) {
5841 index
= imm5
>> (size
+ 1);
5843 tmp
= tcg_temp_new_i64();
5844 read_vec_element(s
, tmp
, rn
, index
, size
);
5846 for (i
= 0; i
< elements
; i
++) {
5847 write_vec_element(s
, tmp
, rd
, i
, size
);
5851 clear_vec_high(s
, rd
);
5854 tcg_temp_free_i64(tmp
);
5857 /* DUP (element, scalar)
5858 * 31 21 20 16 15 10 9 5 4 0
5859 * +-----------------------+--------+-------------+------+------+
5860 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5861 * +-----------------------+--------+-------------+------+------+
5863 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5866 int size
= ctz32(imm5
);
5871 unallocated_encoding(s
);
5875 if (!fp_access_check(s
)) {
5879 index
= imm5
>> (size
+ 1);
5881 /* This instruction just extracts the specified element and
5882 * zero-extends it into the bottom of the destination register.
5884 tmp
= tcg_temp_new_i64();
5885 read_vec_element(s
, tmp
, rn
, index
, size
);
5886 write_fp_dreg(s
, rd
, tmp
);
5887 tcg_temp_free_i64(tmp
);
5892 * 31 30 29 21 20 16 15 10 9 5 4 0
5893 * +---+---+-------------------+--------+-------------+------+------+
5894 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5895 * +---+---+-------------------+--------+-------------+------+------+
5897 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5899 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5902 int size
= ctz32(imm5
);
5903 int esize
= 8 << size
;
5904 int elements
= (is_q
? 128 : 64)/esize
;
5907 if (size
> 3 || ((size
== 3) && !is_q
)) {
5908 unallocated_encoding(s
);
5912 if (!fp_access_check(s
)) {
5916 for (i
= 0; i
< elements
; i
++) {
5917 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5920 clear_vec_high(s
, rd
);
5926 * 31 21 20 16 15 14 11 10 9 5 4 0
5927 * +-----------------------+--------+------------+---+------+------+
5928 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5929 * +-----------------------+--------+------------+---+------+------+
5931 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5932 * index: encoded in imm5<4:size+1>
5934 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5937 int size
= ctz32(imm5
);
5938 int src_index
, dst_index
;
5942 unallocated_encoding(s
);
5946 if (!fp_access_check(s
)) {
5950 dst_index
= extract32(imm5
, 1+size
, 5);
5951 src_index
= extract32(imm4
, size
, 4);
5953 tmp
= tcg_temp_new_i64();
5955 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5956 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5958 tcg_temp_free_i64(tmp
);
5964 * 31 21 20 16 15 10 9 5 4 0
5965 * +-----------------------+--------+-------------+------+------+
5966 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5967 * +-----------------------+--------+-------------+------+------+
5969 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5970 * index: encoded in imm5<4:size+1>
5972 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5974 int size
= ctz32(imm5
);
5978 unallocated_encoding(s
);
5982 if (!fp_access_check(s
)) {
5986 idx
= extract32(imm5
, 1 + size
, 4 - size
);
5987 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
5994 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5995 * +---+---+-------------------+--------+-------------+------+------+
5996 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5997 * +---+---+-------------------+--------+-------------+------+------+
5999 * U: unsigned when set
6000 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6002 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
6003 int rn
, int rd
, int imm5
)
6005 int size
= ctz32(imm5
);
6009 /* Check for UnallocatedEncodings */
6011 if (size
> 2 || (size
== 2 && !is_q
)) {
6012 unallocated_encoding(s
);
6017 || (size
< 3 && is_q
)
6018 || (size
== 3 && !is_q
)) {
6019 unallocated_encoding(s
);
6024 if (!fp_access_check(s
)) {
6028 element
= extract32(imm5
, 1+size
, 4);
6030 tcg_rd
= cpu_reg(s
, rd
);
6031 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
6032 if (is_signed
&& !is_q
) {
6033 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
6038 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6039 * +---+---+----+-----------------+------+---+------+---+------+------+
6040 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6041 * +---+---+----+-----------------+------+---+------+---+------+------+
6043 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
6045 int rd
= extract32(insn
, 0, 5);
6046 int rn
= extract32(insn
, 5, 5);
6047 int imm4
= extract32(insn
, 11, 4);
6048 int op
= extract32(insn
, 29, 1);
6049 int is_q
= extract32(insn
, 30, 1);
6050 int imm5
= extract32(insn
, 16, 5);
6055 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
6057 unallocated_encoding(s
);
6062 /* DUP (element - vector) */
6063 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
6067 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
6072 handle_simd_insg(s
, rd
, rn
, imm5
);
6074 unallocated_encoding(s
);
6079 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
6080 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
6083 unallocated_encoding(s
);
6089 /* AdvSIMD modified immediate
6090 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
6091 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6092 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
6093 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6095 * There are a number of operations that can be carried out here:
6096 * MOVI - move (shifted) imm into register
6097 * MVNI - move inverted (shifted) imm into register
6098 * ORR - bitwise OR of (shifted) imm with register
6099 * BIC - bitwise clear of (shifted) imm with register
6101 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
6103 int rd
= extract32(insn
, 0, 5);
6104 int cmode
= extract32(insn
, 12, 4);
6105 int cmode_3_1
= extract32(cmode
, 1, 3);
6106 int cmode_0
= extract32(cmode
, 0, 1);
6107 int o2
= extract32(insn
, 11, 1);
6108 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
6109 bool is_neg
= extract32(insn
, 29, 1);
6110 bool is_q
= extract32(insn
, 30, 1);
6112 TCGv_i64 tcg_rd
, tcg_imm
;
6115 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
6116 unallocated_encoding(s
);
6120 if (!fp_access_check(s
)) {
6124 /* See AdvSIMDExpandImm() in ARM ARM */
6125 switch (cmode_3_1
) {
6126 case 0: /* Replicate(Zeros(24):imm8, 2) */
6127 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
6128 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
6129 case 3: /* Replicate(imm8:Zeros(24), 2) */
6131 int shift
= cmode_3_1
* 8;
6132 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
6135 case 4: /* Replicate(Zeros(8):imm8, 4) */
6136 case 5: /* Replicate(imm8:Zeros(8), 4) */
6138 int shift
= (cmode_3_1
& 0x1) * 8;
6139 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
6144 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
6145 imm
= (abcdefgh
<< 16) | 0xffff;
6147 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
6148 imm
= (abcdefgh
<< 8) | 0xff;
6150 imm
= bitfield_replicate(imm
, 32);
6153 if (!cmode_0
&& !is_neg
) {
6154 imm
= bitfield_replicate(abcdefgh
, 8);
6155 } else if (!cmode_0
&& is_neg
) {
6158 for (i
= 0; i
< 8; i
++) {
6159 if ((abcdefgh
) & (1 << i
)) {
6160 imm
|= 0xffULL
<< (i
* 8);
6163 } else if (cmode_0
) {
6165 imm
= (abcdefgh
& 0x3f) << 48;
6166 if (abcdefgh
& 0x80) {
6167 imm
|= 0x8000000000000000ULL
;
6169 if (abcdefgh
& 0x40) {
6170 imm
|= 0x3fc0000000000000ULL
;
6172 imm
|= 0x4000000000000000ULL
;
6175 imm
= (abcdefgh
& 0x3f) << 19;
6176 if (abcdefgh
& 0x80) {
6179 if (abcdefgh
& 0x40) {
6190 if (cmode_3_1
!= 7 && is_neg
) {
6194 tcg_imm
= tcg_const_i64(imm
);
6195 tcg_rd
= new_tmp_a64(s
);
6197 for (i
= 0; i
< 2; i
++) {
6198 int foffs
= i
? fp_reg_hi_offset(s
, rd
) : fp_reg_offset(s
, rd
, MO_64
);
6200 if (i
== 1 && !is_q
) {
6201 /* non-quad ops clear high half of vector */
6202 tcg_gen_movi_i64(tcg_rd
, 0);
6203 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
6204 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
6207 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6210 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6214 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
6216 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
6219 tcg_temp_free_i64(tcg_imm
);
6222 /* AdvSIMD scalar copy
6223 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6224 * +-----+----+-----------------+------+---+------+---+------+------+
6225 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6226 * +-----+----+-----------------+------+---+------+---+------+------+
6228 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
6230 int rd
= extract32(insn
, 0, 5);
6231 int rn
= extract32(insn
, 5, 5);
6232 int imm4
= extract32(insn
, 11, 4);
6233 int imm5
= extract32(insn
, 16, 5);
6234 int op
= extract32(insn
, 29, 1);
6236 if (op
!= 0 || imm4
!= 0) {
6237 unallocated_encoding(s
);
6241 /* DUP (element, scalar) */
6242 handle_simd_dupes(s
, rd
, rn
, imm5
);
6245 /* AdvSIMD scalar pairwise
6246 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6247 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6248 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6249 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6251 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
6253 int u
= extract32(insn
, 29, 1);
6254 int size
= extract32(insn
, 22, 2);
6255 int opcode
= extract32(insn
, 12, 5);
6256 int rn
= extract32(insn
, 5, 5);
6257 int rd
= extract32(insn
, 0, 5);
6260 /* For some ops (the FP ones), size[1] is part of the encoding.
6261 * For ADDP strictly it is not but size[1] is always 1 for valid
6264 opcode
|= (extract32(size
, 1, 1) << 5);
6267 case 0x3b: /* ADDP */
6268 if (u
|| size
!= 3) {
6269 unallocated_encoding(s
);
6272 if (!fp_access_check(s
)) {
6278 case 0xc: /* FMAXNMP */
6279 case 0xd: /* FADDP */
6280 case 0xf: /* FMAXP */
6281 case 0x2c: /* FMINNMP */
6282 case 0x2f: /* FMINP */
6283 /* FP op, size[0] is 32 or 64 bit */
6285 unallocated_encoding(s
);
6288 if (!fp_access_check(s
)) {
6292 size
= extract32(size
, 0, 1) ? 3 : 2;
6293 fpst
= get_fpstatus_ptr();
6296 unallocated_encoding(s
);
6301 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6302 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6303 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6305 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
6306 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
6309 case 0x3b: /* ADDP */
6310 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
6312 case 0xc: /* FMAXNMP */
6313 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6315 case 0xd: /* FADDP */
6316 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6318 case 0xf: /* FMAXP */
6319 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6321 case 0x2c: /* FMINNMP */
6322 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6324 case 0x2f: /* FMINP */
6325 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6328 g_assert_not_reached();
6331 write_fp_dreg(s
, rd
, tcg_res
);
6333 tcg_temp_free_i64(tcg_op1
);
6334 tcg_temp_free_i64(tcg_op2
);
6335 tcg_temp_free_i64(tcg_res
);
6337 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6338 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6339 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6341 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
6342 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
6345 case 0xc: /* FMAXNMP */
6346 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6348 case 0xd: /* FADDP */
6349 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6351 case 0xf: /* FMAXP */
6352 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6354 case 0x2c: /* FMINNMP */
6355 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6357 case 0x2f: /* FMINP */
6358 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6361 g_assert_not_reached();
6364 write_fp_sreg(s
, rd
, tcg_res
);
6366 tcg_temp_free_i32(tcg_op1
);
6367 tcg_temp_free_i32(tcg_op2
);
6368 tcg_temp_free_i32(tcg_res
);
6372 tcg_temp_free_ptr(fpst
);
6377 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
6379 * This code is handles the common shifting code and is used by both
6380 * the vector and scalar code.
6382 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6383 TCGv_i64 tcg_rnd
, bool accumulate
,
6384 bool is_u
, int size
, int shift
)
6386 bool extended_result
= false;
6387 bool round
= tcg_rnd
!= NULL
;
6389 TCGv_i64 tcg_src_hi
;
6391 if (round
&& size
== 3) {
6392 extended_result
= true;
6393 ext_lshift
= 64 - shift
;
6394 tcg_src_hi
= tcg_temp_new_i64();
6395 } else if (shift
== 64) {
6396 if (!accumulate
&& is_u
) {
6397 /* result is zero */
6398 tcg_gen_movi_i64(tcg_res
, 0);
6403 /* Deal with the rounding step */
6405 if (extended_result
) {
6406 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6408 /* take care of sign extending tcg_res */
6409 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
6410 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6411 tcg_src
, tcg_src_hi
,
6414 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6418 tcg_temp_free_i64(tcg_zero
);
6420 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
6424 /* Now do the shift right */
6425 if (round
&& extended_result
) {
6426 /* extended case, >64 bit precision required */
6427 if (ext_lshift
== 0) {
6428 /* special case, only high bits matter */
6429 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
6431 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6432 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
6433 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
6438 /* essentially shifting in 64 zeros */
6439 tcg_gen_movi_i64(tcg_src
, 0);
6441 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6445 /* effectively extending the sign-bit */
6446 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
6448 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
6454 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
6456 tcg_gen_mov_i64(tcg_res
, tcg_src
);
6459 if (extended_result
) {
6460 tcg_temp_free_i64(tcg_src_hi
);
6464 /* Common SHL/SLI - Shift left with an optional insert */
6465 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6466 bool insert
, int shift
)
6468 if (insert
) { /* SLI */
6469 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
6471 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
6475 /* SRI: shift right with insert */
6476 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6477 int size
, int shift
)
6479 int esize
= 8 << size
;
6481 /* shift count same as element size is valid but does nothing;
6482 * special case to avoid potential shift by 64.
6484 if (shift
!= esize
) {
6485 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6486 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
6490 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6491 static void handle_scalar_simd_shri(DisasContext
*s
,
6492 bool is_u
, int immh
, int immb
,
6493 int opcode
, int rn
, int rd
)
6496 int immhb
= immh
<< 3 | immb
;
6497 int shift
= 2 * (8 << size
) - immhb
;
6498 bool accumulate
= false;
6500 bool insert
= false;
6505 if (!extract32(immh
, 3, 1)) {
6506 unallocated_encoding(s
);
6510 if (!fp_access_check(s
)) {
6515 case 0x02: /* SSRA / USRA (accumulate) */
6518 case 0x04: /* SRSHR / URSHR (rounding) */
6521 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6522 accumulate
= round
= true;
6524 case 0x08: /* SRI */
6530 uint64_t round_const
= 1ULL << (shift
- 1);
6531 tcg_round
= tcg_const_i64(round_const
);
6536 tcg_rn
= read_fp_dreg(s
, rn
);
6537 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6540 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
6542 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6543 accumulate
, is_u
, size
, shift
);
6546 write_fp_dreg(s
, rd
, tcg_rd
);
6548 tcg_temp_free_i64(tcg_rn
);
6549 tcg_temp_free_i64(tcg_rd
);
6551 tcg_temp_free_i64(tcg_round
);
6555 /* SHL/SLI - Scalar shift left */
6556 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
6557 int immh
, int immb
, int opcode
,
6560 int size
= 32 - clz32(immh
) - 1;
6561 int immhb
= immh
<< 3 | immb
;
6562 int shift
= immhb
- (8 << size
);
6563 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6564 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6566 if (!extract32(immh
, 3, 1)) {
6567 unallocated_encoding(s
);
6571 if (!fp_access_check(s
)) {
6575 tcg_rn
= read_fp_dreg(s
, rn
);
6576 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6578 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6580 write_fp_dreg(s
, rd
, tcg_rd
);
6582 tcg_temp_free_i64(tcg_rn
);
6583 tcg_temp_free_i64(tcg_rd
);
6586 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6587 * (signed/unsigned) narrowing */
6588 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
6589 bool is_u_shift
, bool is_u_narrow
,
6590 int immh
, int immb
, int opcode
,
6593 int immhb
= immh
<< 3 | immb
;
6594 int size
= 32 - clz32(immh
) - 1;
6595 int esize
= 8 << size
;
6596 int shift
= (2 * esize
) - immhb
;
6597 int elements
= is_scalar
? 1 : (64 / esize
);
6598 bool round
= extract32(opcode
, 0, 1);
6599 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
6600 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
6601 TCGv_i32 tcg_rd_narrowed
;
6604 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
6605 { gen_helper_neon_narrow_sat_s8
,
6606 gen_helper_neon_unarrow_sat8
},
6607 { gen_helper_neon_narrow_sat_s16
,
6608 gen_helper_neon_unarrow_sat16
},
6609 { gen_helper_neon_narrow_sat_s32
,
6610 gen_helper_neon_unarrow_sat32
},
6613 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
6614 gen_helper_neon_narrow_sat_u8
,
6615 gen_helper_neon_narrow_sat_u16
,
6616 gen_helper_neon_narrow_sat_u32
,
6619 NeonGenNarrowEnvFn
*narrowfn
;
6625 if (extract32(immh
, 3, 1)) {
6626 unallocated_encoding(s
);
6630 if (!fp_access_check(s
)) {
6635 narrowfn
= unsigned_narrow_fns
[size
];
6637 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
6640 tcg_rn
= tcg_temp_new_i64();
6641 tcg_rd
= tcg_temp_new_i64();
6642 tcg_rd_narrowed
= tcg_temp_new_i32();
6643 tcg_final
= tcg_const_i64(0);
6646 uint64_t round_const
= 1ULL << (shift
- 1);
6647 tcg_round
= tcg_const_i64(round_const
);
6652 for (i
= 0; i
< elements
; i
++) {
6653 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
6654 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6655 false, is_u_shift
, size
+1, shift
);
6656 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6657 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6658 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6662 clear_vec_high(s
, rd
);
6663 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6665 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6669 tcg_temp_free_i64(tcg_round
);
6671 tcg_temp_free_i64(tcg_rn
);
6672 tcg_temp_free_i64(tcg_rd
);
6673 tcg_temp_free_i32(tcg_rd_narrowed
);
6674 tcg_temp_free_i64(tcg_final
);
6678 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6679 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6680 bool src_unsigned
, bool dst_unsigned
,
6681 int immh
, int immb
, int rn
, int rd
)
6683 int immhb
= immh
<< 3 | immb
;
6684 int size
= 32 - clz32(immh
) - 1;
6685 int shift
= immhb
- (8 << size
);
6689 assert(!(scalar
&& is_q
));
6692 if (!is_q
&& extract32(immh
, 3, 1)) {
6693 unallocated_encoding(s
);
6697 /* Since we use the variable-shift helpers we must
6698 * replicate the shift count into each element of
6699 * the tcg_shift value.
6703 shift
|= shift
<< 8;
6706 shift
|= shift
<< 16;
6712 g_assert_not_reached();
6716 if (!fp_access_check(s
)) {
6721 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6722 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6723 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6724 { NULL
, gen_helper_neon_qshl_u64
},
6726 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6727 int maxpass
= is_q
? 2 : 1;
6729 for (pass
= 0; pass
< maxpass
; pass
++) {
6730 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6732 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6733 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6734 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6736 tcg_temp_free_i64(tcg_op
);
6738 tcg_temp_free_i64(tcg_shift
);
6741 clear_vec_high(s
, rd
);
6744 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6745 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6747 { gen_helper_neon_qshl_s8
,
6748 gen_helper_neon_qshl_s16
,
6749 gen_helper_neon_qshl_s32
},
6750 { gen_helper_neon_qshlu_s8
,
6751 gen_helper_neon_qshlu_s16
,
6752 gen_helper_neon_qshlu_s32
}
6754 { NULL
, NULL
, NULL
},
6755 { gen_helper_neon_qshl_u8
,
6756 gen_helper_neon_qshl_u16
,
6757 gen_helper_neon_qshl_u32
}
6760 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6761 TCGMemOp memop
= scalar
? size
: MO_32
;
6762 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6764 for (pass
= 0; pass
< maxpass
; pass
++) {
6765 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6767 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6768 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6772 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6775 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6780 g_assert_not_reached();
6782 write_fp_sreg(s
, rd
, tcg_op
);
6784 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6787 tcg_temp_free_i32(tcg_op
);
6789 tcg_temp_free_i32(tcg_shift
);
6791 if (!is_q
&& !scalar
) {
6792 clear_vec_high(s
, rd
);
6797 /* Common vector code for handling integer to FP conversion */
6798 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6799 int elements
, int is_signed
,
6800 int fracbits
, int size
)
6802 bool is_double
= size
== 3 ? true : false;
6803 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6804 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6805 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6806 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6809 for (pass
= 0; pass
< elements
; pass
++) {
6810 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6813 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6815 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6816 tcg_shift
, tcg_fpst
);
6818 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6819 tcg_shift
, tcg_fpst
);
6821 if (elements
== 1) {
6822 write_fp_dreg(s
, rd
, tcg_double
);
6824 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6826 tcg_temp_free_i64(tcg_double
);
6828 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6830 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6831 tcg_shift
, tcg_fpst
);
6833 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6834 tcg_shift
, tcg_fpst
);
6836 if (elements
== 1) {
6837 write_fp_sreg(s
, rd
, tcg_single
);
6839 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6841 tcg_temp_free_i32(tcg_single
);
6845 if (!is_double
&& elements
== 2) {
6846 clear_vec_high(s
, rd
);
6849 tcg_temp_free_i64(tcg_int
);
6850 tcg_temp_free_ptr(tcg_fpst
);
6851 tcg_temp_free_i32(tcg_shift
);
6854 /* UCVTF/SCVTF - Integer to FP conversion */
6855 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6856 bool is_q
, bool is_u
,
6857 int immh
, int immb
, int opcode
,
6860 bool is_double
= extract32(immh
, 3, 1);
6861 int size
= is_double
? MO_64
: MO_32
;
6863 int immhb
= immh
<< 3 | immb
;
6864 int fracbits
= (is_double
? 128 : 64) - immhb
;
6866 if (!extract32(immh
, 2, 2)) {
6867 unallocated_encoding(s
);
6874 elements
= is_double
? 2 : is_q
? 4 : 2;
6875 if (is_double
&& !is_q
) {
6876 unallocated_encoding(s
);
6881 if (!fp_access_check(s
)) {
6885 /* immh == 0 would be a failure of the decode logic */
6888 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6891 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6892 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6893 bool is_q
, bool is_u
,
6894 int immh
, int immb
, int rn
, int rd
)
6896 bool is_double
= extract32(immh
, 3, 1);
6897 int immhb
= immh
<< 3 | immb
;
6898 int fracbits
= (is_double
? 128 : 64) - immhb
;
6900 TCGv_ptr tcg_fpstatus
;
6901 TCGv_i32 tcg_rmode
, tcg_shift
;
6903 if (!extract32(immh
, 2, 2)) {
6904 unallocated_encoding(s
);
6908 if (!is_scalar
&& !is_q
&& is_double
) {
6909 unallocated_encoding(s
);
6913 if (!fp_access_check(s
)) {
6917 assert(!(is_scalar
&& is_q
));
6919 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6920 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6921 tcg_fpstatus
= get_fpstatus_ptr();
6922 tcg_shift
= tcg_const_i32(fracbits
);
6925 int maxpass
= is_scalar
? 1 : 2;
6927 for (pass
= 0; pass
< maxpass
; pass
++) {
6928 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6930 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6932 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6934 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6936 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6937 tcg_temp_free_i64(tcg_op
);
6940 clear_vec_high(s
, rd
);
6943 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6944 for (pass
= 0; pass
< maxpass
; pass
++) {
6945 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6947 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6949 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6951 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6954 write_fp_sreg(s
, rd
, tcg_op
);
6956 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6958 tcg_temp_free_i32(tcg_op
);
6960 if (!is_q
&& !is_scalar
) {
6961 clear_vec_high(s
, rd
);
6965 tcg_temp_free_ptr(tcg_fpstatus
);
6966 tcg_temp_free_i32(tcg_shift
);
6967 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6968 tcg_temp_free_i32(tcg_rmode
);
6971 /* AdvSIMD scalar shift by immediate
6972 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6973 * +-----+---+-------------+------+------+--------+---+------+------+
6974 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6975 * +-----+---+-------------+------+------+--------+---+------+------+
6977 * This is the scalar version so it works on a fixed sized registers
6979 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6981 int rd
= extract32(insn
, 0, 5);
6982 int rn
= extract32(insn
, 5, 5);
6983 int opcode
= extract32(insn
, 11, 5);
6984 int immb
= extract32(insn
, 16, 3);
6985 int immh
= extract32(insn
, 19, 4);
6986 bool is_u
= extract32(insn
, 29, 1);
6989 unallocated_encoding(s
);
6994 case 0x08: /* SRI */
6996 unallocated_encoding(s
);
7000 case 0x00: /* SSHR / USHR */
7001 case 0x02: /* SSRA / USRA */
7002 case 0x04: /* SRSHR / URSHR */
7003 case 0x06: /* SRSRA / URSRA */
7004 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7006 case 0x0a: /* SHL / SLI */
7007 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7009 case 0x1c: /* SCVTF, UCVTF */
7010 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
7013 case 0x10: /* SQSHRUN, SQSHRUN2 */
7014 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
7016 unallocated_encoding(s
);
7019 handle_vec_simd_sqshrn(s
, true, false, false, true,
7020 immh
, immb
, opcode
, rn
, rd
);
7022 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
7023 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
7024 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
7025 immh
, immb
, opcode
, rn
, rd
);
7027 case 0xc: /* SQSHLU */
7029 unallocated_encoding(s
);
7032 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
7034 case 0xe: /* SQSHL, UQSHL */
7035 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
7037 case 0x1f: /* FCVTZS, FCVTZU */
7038 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
7041 unallocated_encoding(s
);
7046 /* AdvSIMD scalar three different
7047 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
7048 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7049 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
7050 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7052 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
7054 bool is_u
= extract32(insn
, 29, 1);
7055 int size
= extract32(insn
, 22, 2);
7056 int opcode
= extract32(insn
, 12, 4);
7057 int rm
= extract32(insn
, 16, 5);
7058 int rn
= extract32(insn
, 5, 5);
7059 int rd
= extract32(insn
, 0, 5);
7062 unallocated_encoding(s
);
7067 case 0x9: /* SQDMLAL, SQDMLAL2 */
7068 case 0xb: /* SQDMLSL, SQDMLSL2 */
7069 case 0xd: /* SQDMULL, SQDMULL2 */
7070 if (size
== 0 || size
== 3) {
7071 unallocated_encoding(s
);
7076 unallocated_encoding(s
);
7080 if (!fp_access_check(s
)) {
7085 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7086 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7087 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7089 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
7090 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
7092 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
7093 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7096 case 0xd: /* SQDMULL, SQDMULL2 */
7098 case 0xb: /* SQDMLSL, SQDMLSL2 */
7099 tcg_gen_neg_i64(tcg_res
, tcg_res
);
7101 case 0x9: /* SQDMLAL, SQDMLAL2 */
7102 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
7103 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
7107 g_assert_not_reached();
7110 write_fp_dreg(s
, rd
, tcg_res
);
7112 tcg_temp_free_i64(tcg_op1
);
7113 tcg_temp_free_i64(tcg_op2
);
7114 tcg_temp_free_i64(tcg_res
);
7116 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7117 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7118 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7120 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
7121 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
7123 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
7124 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7127 case 0xd: /* SQDMULL, SQDMULL2 */
7129 case 0xb: /* SQDMLSL, SQDMLSL2 */
7130 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
7132 case 0x9: /* SQDMLAL, SQDMLAL2 */
7134 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
7135 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
7136 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
7138 tcg_temp_free_i64(tcg_op3
);
7142 g_assert_not_reached();
7145 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7146 write_fp_dreg(s
, rd
, tcg_res
);
7148 tcg_temp_free_i32(tcg_op1
);
7149 tcg_temp_free_i32(tcg_op2
);
7150 tcg_temp_free_i64(tcg_res
);
7154 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
7155 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
7157 /* Handle 64x64->64 opcodes which are shared between the scalar
7158 * and vector 3-same groups. We cover every opcode where size == 3
7159 * is valid in either the three-reg-same (integer, not pairwise)
7160 * or scalar-three-reg-same groups. (Some opcodes are not yet
7166 case 0x1: /* SQADD */
7168 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7170 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7173 case 0x5: /* SQSUB */
7175 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7177 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7180 case 0x6: /* CMGT, CMHI */
7181 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
7182 * We implement this using setcond (test) and then negating.
7184 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
7186 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
7187 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7189 case 0x7: /* CMGE, CMHS */
7190 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
7192 case 0x11: /* CMTST, CMEQ */
7197 /* CMTST : test is "if (X & Y != 0)". */
7198 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7199 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
7200 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7202 case 0x8: /* SSHL, USHL */
7204 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7206 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7209 case 0x9: /* SQSHL, UQSHL */
7211 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7213 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7216 case 0xa: /* SRSHL, URSHL */
7218 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7220 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7223 case 0xb: /* SQRSHL, UQRSHL */
7225 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7227 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7230 case 0x10: /* ADD, SUB */
7232 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7234 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7238 g_assert_not_reached();
7242 /* Handle the 3-same-operands float operations; shared by the scalar
7243 * and vector encodings. The caller must filter out any encodings
7244 * not allocated for the encoding it is dealing with.
7246 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
7247 int fpopcode
, int rd
, int rn
, int rm
)
7250 TCGv_ptr fpst
= get_fpstatus_ptr();
7252 for (pass
= 0; pass
< elements
; pass
++) {
7255 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7256 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7257 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7259 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7260 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
7263 case 0x39: /* FMLS */
7264 /* As usual for ARM, separate negation for fused multiply-add */
7265 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
7267 case 0x19: /* FMLA */
7268 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7269 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
7272 case 0x18: /* FMAXNM */
7273 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7275 case 0x1a: /* FADD */
7276 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7278 case 0x1b: /* FMULX */
7279 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7281 case 0x1c: /* FCMEQ */
7282 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7284 case 0x1e: /* FMAX */
7285 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7287 case 0x1f: /* FRECPS */
7288 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7290 case 0x38: /* FMINNM */
7291 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7293 case 0x3a: /* FSUB */
7294 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7296 case 0x3e: /* FMIN */
7297 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7299 case 0x3f: /* FRSQRTS */
7300 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7302 case 0x5b: /* FMUL */
7303 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7305 case 0x5c: /* FCMGE */
7306 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7308 case 0x5d: /* FACGE */
7309 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7311 case 0x5f: /* FDIV */
7312 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7314 case 0x7a: /* FABD */
7315 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7316 gen_helper_vfp_absd(tcg_res
, tcg_res
);
7318 case 0x7c: /* FCMGT */
7319 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7321 case 0x7d: /* FACGT */
7322 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7325 g_assert_not_reached();
7328 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7330 tcg_temp_free_i64(tcg_res
);
7331 tcg_temp_free_i64(tcg_op1
);
7332 tcg_temp_free_i64(tcg_op2
);
7335 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7336 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7337 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7339 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
7340 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
7343 case 0x39: /* FMLS */
7344 /* As usual for ARM, separate negation for fused multiply-add */
7345 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
7347 case 0x19: /* FMLA */
7348 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7349 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
7352 case 0x1a: /* FADD */
7353 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7355 case 0x1b: /* FMULX */
7356 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7358 case 0x1c: /* FCMEQ */
7359 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7361 case 0x1e: /* FMAX */
7362 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7364 case 0x1f: /* FRECPS */
7365 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7367 case 0x18: /* FMAXNM */
7368 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7370 case 0x38: /* FMINNM */
7371 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7373 case 0x3a: /* FSUB */
7374 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7376 case 0x3e: /* FMIN */
7377 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7379 case 0x3f: /* FRSQRTS */
7380 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7382 case 0x5b: /* FMUL */
7383 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7385 case 0x5c: /* FCMGE */
7386 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7388 case 0x5d: /* FACGE */
7389 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7391 case 0x5f: /* FDIV */
7392 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7394 case 0x7a: /* FABD */
7395 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7396 gen_helper_vfp_abss(tcg_res
, tcg_res
);
7398 case 0x7c: /* FCMGT */
7399 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7401 case 0x7d: /* FACGT */
7402 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7405 g_assert_not_reached();
7408 if (elements
== 1) {
7409 /* scalar single so clear high part */
7410 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7412 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
7413 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
7414 tcg_temp_free_i64(tcg_tmp
);
7416 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7419 tcg_temp_free_i32(tcg_res
);
7420 tcg_temp_free_i32(tcg_op1
);
7421 tcg_temp_free_i32(tcg_op2
);
7425 tcg_temp_free_ptr(fpst
);
7427 if ((elements
<< size
) < 4) {
7428 /* scalar, or non-quad vector op */
7429 clear_vec_high(s
, rd
);
7433 /* AdvSIMD scalar three same
7434 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7435 * +-----+---+-----------+------+---+------+--------+---+------+------+
7436 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7437 * +-----+---+-----------+------+---+------+--------+---+------+------+
7439 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
7441 int rd
= extract32(insn
, 0, 5);
7442 int rn
= extract32(insn
, 5, 5);
7443 int opcode
= extract32(insn
, 11, 5);
7444 int rm
= extract32(insn
, 16, 5);
7445 int size
= extract32(insn
, 22, 2);
7446 bool u
= extract32(insn
, 29, 1);
7449 if (opcode
>= 0x18) {
7450 /* Floating point: U, size[1] and opcode indicate operation */
7451 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
7453 case 0x1b: /* FMULX */
7454 case 0x1f: /* FRECPS */
7455 case 0x3f: /* FRSQRTS */
7456 case 0x5d: /* FACGE */
7457 case 0x7d: /* FACGT */
7458 case 0x1c: /* FCMEQ */
7459 case 0x5c: /* FCMGE */
7460 case 0x7c: /* FCMGT */
7461 case 0x7a: /* FABD */
7464 unallocated_encoding(s
);
7468 if (!fp_access_check(s
)) {
7472 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
7477 case 0x1: /* SQADD, UQADD */
7478 case 0x5: /* SQSUB, UQSUB */
7479 case 0x9: /* SQSHL, UQSHL */
7480 case 0xb: /* SQRSHL, UQRSHL */
7482 case 0x8: /* SSHL, USHL */
7483 case 0xa: /* SRSHL, URSHL */
7484 case 0x6: /* CMGT, CMHI */
7485 case 0x7: /* CMGE, CMHS */
7486 case 0x11: /* CMTST, CMEQ */
7487 case 0x10: /* ADD, SUB (vector) */
7489 unallocated_encoding(s
);
7493 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7494 if (size
!= 1 && size
!= 2) {
7495 unallocated_encoding(s
);
7500 unallocated_encoding(s
);
7504 if (!fp_access_check(s
)) {
7508 tcg_rd
= tcg_temp_new_i64();
7511 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7512 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
7514 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
7515 tcg_temp_free_i64(tcg_rn
);
7516 tcg_temp_free_i64(tcg_rm
);
7518 /* Do a single operation on the lowest element in the vector.
7519 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7520 * no side effects for all these operations.
7521 * OPTME: special-purpose helpers would avoid doing some
7522 * unnecessary work in the helper for the 8 and 16 bit cases.
7524 NeonGenTwoOpEnvFn
*genenvfn
;
7525 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7526 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
7527 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
7529 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7530 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
7533 case 0x1: /* SQADD, UQADD */
7535 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7536 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7537 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7538 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7540 genenvfn
= fns
[size
][u
];
7543 case 0x5: /* SQSUB, UQSUB */
7545 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7546 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7547 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7548 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7550 genenvfn
= fns
[size
][u
];
7553 case 0x9: /* SQSHL, UQSHL */
7555 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7556 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7557 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7558 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7560 genenvfn
= fns
[size
][u
];
7563 case 0xb: /* SQRSHL, UQRSHL */
7565 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7566 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7567 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7568 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7570 genenvfn
= fns
[size
][u
];
7573 case 0x16: /* SQDMULH, SQRDMULH */
7575 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7576 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7577 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7579 assert(size
== 1 || size
== 2);
7580 genenvfn
= fns
[size
- 1][u
];
7584 g_assert_not_reached();
7587 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
7588 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
7589 tcg_temp_free_i32(tcg_rd32
);
7590 tcg_temp_free_i32(tcg_rn
);
7591 tcg_temp_free_i32(tcg_rm
);
7594 write_fp_dreg(s
, rd
, tcg_rd
);
7596 tcg_temp_free_i64(tcg_rd
);
7599 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
7600 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
7601 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
7603 /* Handle 64->64 opcodes which are shared between the scalar and
7604 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7605 * is valid in either group and also the double-precision fp ops.
7606 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7612 case 0x4: /* CLS, CLZ */
7614 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
7616 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
7620 /* This opcode is shared with CNT and RBIT but we have earlier
7621 * enforced that size == 3 if and only if this is the NOT insn.
7623 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
7625 case 0x7: /* SQABS, SQNEG */
7627 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
7629 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
7632 case 0xa: /* CMLT */
7633 /* 64 bit integer comparison against zero, result is
7634 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7639 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
7640 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7642 case 0x8: /* CMGT, CMGE */
7643 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
7645 case 0x9: /* CMEQ, CMLE */
7646 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
7648 case 0xb: /* ABS, NEG */
7650 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7652 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7653 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7654 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
7656 tcg_temp_free_i64(tcg_zero
);
7659 case 0x2f: /* FABS */
7660 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
7662 case 0x6f: /* FNEG */
7663 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
7665 case 0x7f: /* FSQRT */
7666 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
7668 case 0x1a: /* FCVTNS */
7669 case 0x1b: /* FCVTMS */
7670 case 0x1c: /* FCVTAS */
7671 case 0x3a: /* FCVTPS */
7672 case 0x3b: /* FCVTZS */
7674 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7675 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7676 tcg_temp_free_i32(tcg_shift
);
7679 case 0x5a: /* FCVTNU */
7680 case 0x5b: /* FCVTMU */
7681 case 0x5c: /* FCVTAU */
7682 case 0x7a: /* FCVTPU */
7683 case 0x7b: /* FCVTZU */
7685 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7686 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7687 tcg_temp_free_i32(tcg_shift
);
7690 case 0x18: /* FRINTN */
7691 case 0x19: /* FRINTM */
7692 case 0x38: /* FRINTP */
7693 case 0x39: /* FRINTZ */
7694 case 0x58: /* FRINTA */
7695 case 0x79: /* FRINTI */
7696 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7698 case 0x59: /* FRINTX */
7699 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7702 g_assert_not_reached();
7706 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7707 bool is_scalar
, bool is_u
, bool is_q
,
7708 int size
, int rn
, int rd
)
7710 bool is_double
= (size
== 3);
7713 if (!fp_access_check(s
)) {
7717 fpst
= get_fpstatus_ptr();
7720 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7721 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7722 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7723 NeonGenTwoDoubleOPFn
*genfn
;
7728 case 0x2e: /* FCMLT (zero) */
7731 case 0x2c: /* FCMGT (zero) */
7732 genfn
= gen_helper_neon_cgt_f64
;
7734 case 0x2d: /* FCMEQ (zero) */
7735 genfn
= gen_helper_neon_ceq_f64
;
7737 case 0x6d: /* FCMLE (zero) */
7740 case 0x6c: /* FCMGE (zero) */
7741 genfn
= gen_helper_neon_cge_f64
;
7744 g_assert_not_reached();
7747 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7748 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7750 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7752 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7754 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7757 clear_vec_high(s
, rd
);
7760 tcg_temp_free_i64(tcg_res
);
7761 tcg_temp_free_i64(tcg_zero
);
7762 tcg_temp_free_i64(tcg_op
);
7764 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7765 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7766 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7767 NeonGenTwoSingleOPFn
*genfn
;
7769 int pass
, maxpasses
;
7772 case 0x2e: /* FCMLT (zero) */
7775 case 0x2c: /* FCMGT (zero) */
7776 genfn
= gen_helper_neon_cgt_f32
;
7778 case 0x2d: /* FCMEQ (zero) */
7779 genfn
= gen_helper_neon_ceq_f32
;
7781 case 0x6d: /* FCMLE (zero) */
7784 case 0x6c: /* FCMGE (zero) */
7785 genfn
= gen_helper_neon_cge_f32
;
7788 g_assert_not_reached();
7794 maxpasses
= is_q
? 4 : 2;
7797 for (pass
= 0; pass
< maxpasses
; pass
++) {
7798 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7800 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7802 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7805 write_fp_sreg(s
, rd
, tcg_res
);
7807 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7810 tcg_temp_free_i32(tcg_res
);
7811 tcg_temp_free_i32(tcg_zero
);
7812 tcg_temp_free_i32(tcg_op
);
7813 if (!is_q
&& !is_scalar
) {
7814 clear_vec_high(s
, rd
);
7818 tcg_temp_free_ptr(fpst
);
7821 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7822 bool is_scalar
, bool is_u
, bool is_q
,
7823 int size
, int rn
, int rd
)
7825 bool is_double
= (size
== 3);
7826 TCGv_ptr fpst
= get_fpstatus_ptr();
7829 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7830 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7833 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7834 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7836 case 0x3d: /* FRECPE */
7837 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7839 case 0x3f: /* FRECPX */
7840 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7842 case 0x7d: /* FRSQRTE */
7843 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7846 g_assert_not_reached();
7848 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7851 clear_vec_high(s
, rd
);
7854 tcg_temp_free_i64(tcg_res
);
7855 tcg_temp_free_i64(tcg_op
);
7857 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7858 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7859 int pass
, maxpasses
;
7864 maxpasses
= is_q
? 4 : 2;
7867 for (pass
= 0; pass
< maxpasses
; pass
++) {
7868 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7871 case 0x3c: /* URECPE */
7872 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7874 case 0x3d: /* FRECPE */
7875 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7877 case 0x3f: /* FRECPX */
7878 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7880 case 0x7d: /* FRSQRTE */
7881 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7884 g_assert_not_reached();
7888 write_fp_sreg(s
, rd
, tcg_res
);
7890 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7893 tcg_temp_free_i32(tcg_res
);
7894 tcg_temp_free_i32(tcg_op
);
7895 if (!is_q
&& !is_scalar
) {
7896 clear_vec_high(s
, rd
);
7899 tcg_temp_free_ptr(fpst
);
7902 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7903 int opcode
, bool u
, bool is_q
,
7904 int size
, int rn
, int rd
)
7906 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7907 * in the source becomes a size element in the destination).
7910 TCGv_i32 tcg_res
[2];
7911 int destelt
= is_q
? 2 : 0;
7912 int passes
= scalar
? 1 : 2;
7915 tcg_res
[1] = tcg_const_i32(0);
7918 for (pass
= 0; pass
< passes
; pass
++) {
7919 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7920 NeonGenNarrowFn
*genfn
= NULL
;
7921 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7924 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7926 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7928 tcg_res
[pass
] = tcg_temp_new_i32();
7931 case 0x12: /* XTN, SQXTUN */
7933 static NeonGenNarrowFn
* const xtnfns
[3] = {
7934 gen_helper_neon_narrow_u8
,
7935 gen_helper_neon_narrow_u16
,
7936 tcg_gen_extrl_i64_i32
,
7938 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7939 gen_helper_neon_unarrow_sat8
,
7940 gen_helper_neon_unarrow_sat16
,
7941 gen_helper_neon_unarrow_sat32
,
7944 genenvfn
= sqxtunfns
[size
];
7946 genfn
= xtnfns
[size
];
7950 case 0x14: /* SQXTN, UQXTN */
7952 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
7953 { gen_helper_neon_narrow_sat_s8
,
7954 gen_helper_neon_narrow_sat_u8
},
7955 { gen_helper_neon_narrow_sat_s16
,
7956 gen_helper_neon_narrow_sat_u16
},
7957 { gen_helper_neon_narrow_sat_s32
,
7958 gen_helper_neon_narrow_sat_u32
},
7960 genenvfn
= fns
[size
][u
];
7963 case 0x16: /* FCVTN, FCVTN2 */
7964 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7966 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
7968 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
7969 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
7970 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
7971 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
7972 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
7973 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
7974 tcg_temp_free_i32(tcg_lo
);
7975 tcg_temp_free_i32(tcg_hi
);
7978 case 0x56: /* FCVTXN, FCVTXN2 */
7979 /* 64 bit to 32 bit float conversion
7980 * with von Neumann rounding (round to odd)
7983 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
7986 g_assert_not_reached();
7990 genfn(tcg_res
[pass
], tcg_op
);
7991 } else if (genenvfn
) {
7992 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
7995 tcg_temp_free_i64(tcg_op
);
7998 for (pass
= 0; pass
< 2; pass
++) {
7999 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
8000 tcg_temp_free_i32(tcg_res
[pass
]);
8003 clear_vec_high(s
, rd
);
8007 /* Remaining saturating accumulating ops */
8008 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
8009 bool is_q
, int size
, int rn
, int rd
)
8011 bool is_double
= (size
== 3);
8014 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
8015 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
8018 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
8019 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
8020 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
8022 if (is_u
) { /* USQADD */
8023 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8024 } else { /* SUQADD */
8025 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8027 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
8030 clear_vec_high(s
, rd
);
8033 tcg_temp_free_i64(tcg_rd
);
8034 tcg_temp_free_i64(tcg_rn
);
8036 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8037 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8038 int pass
, maxpasses
;
8043 maxpasses
= is_q
? 4 : 2;
8046 for (pass
= 0; pass
< maxpasses
; pass
++) {
8048 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
8049 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
8051 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
8052 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8055 if (is_u
) { /* USQADD */
8058 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8061 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8064 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8067 g_assert_not_reached();
8069 } else { /* SUQADD */
8072 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8075 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8078 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8081 g_assert_not_reached();
8086 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8087 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
8088 tcg_temp_free_i64(tcg_zero
);
8090 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8094 clear_vec_high(s
, rd
);
8097 tcg_temp_free_i32(tcg_rd
);
8098 tcg_temp_free_i32(tcg_rn
);
8102 /* AdvSIMD scalar two reg misc
8103 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8104 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8105 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
8106 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8108 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
8110 int rd
= extract32(insn
, 0, 5);
8111 int rn
= extract32(insn
, 5, 5);
8112 int opcode
= extract32(insn
, 12, 5);
8113 int size
= extract32(insn
, 22, 2);
8114 bool u
= extract32(insn
, 29, 1);
8115 bool is_fcvt
= false;
8118 TCGv_ptr tcg_fpstatus
;
8121 case 0x3: /* USQADD / SUQADD*/
8122 if (!fp_access_check(s
)) {
8125 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
8127 case 0x7: /* SQABS / SQNEG */
8129 case 0xa: /* CMLT */
8131 unallocated_encoding(s
);
8135 case 0x8: /* CMGT, CMGE */
8136 case 0x9: /* CMEQ, CMLE */
8137 case 0xb: /* ABS, NEG */
8139 unallocated_encoding(s
);
8143 case 0x12: /* SQXTUN */
8145 unallocated_encoding(s
);
8149 case 0x14: /* SQXTN, UQXTN */
8151 unallocated_encoding(s
);
8154 if (!fp_access_check(s
)) {
8157 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
8162 /* Floating point: U, size[1] and opcode indicate operation;
8163 * size[0] indicates single or double precision.
8165 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
8166 size
= extract32(size
, 0, 1) ? 3 : 2;
8168 case 0x2c: /* FCMGT (zero) */
8169 case 0x2d: /* FCMEQ (zero) */
8170 case 0x2e: /* FCMLT (zero) */
8171 case 0x6c: /* FCMGE (zero) */
8172 case 0x6d: /* FCMLE (zero) */
8173 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
8175 case 0x1d: /* SCVTF */
8176 case 0x5d: /* UCVTF */
8178 bool is_signed
= (opcode
== 0x1d);
8179 if (!fp_access_check(s
)) {
8182 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
8185 case 0x3d: /* FRECPE */
8186 case 0x3f: /* FRECPX */
8187 case 0x7d: /* FRSQRTE */
8188 if (!fp_access_check(s
)) {
8191 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
8193 case 0x1a: /* FCVTNS */
8194 case 0x1b: /* FCVTMS */
8195 case 0x3a: /* FCVTPS */
8196 case 0x3b: /* FCVTZS */
8197 case 0x5a: /* FCVTNU */
8198 case 0x5b: /* FCVTMU */
8199 case 0x7a: /* FCVTPU */
8200 case 0x7b: /* FCVTZU */
8202 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
8204 case 0x1c: /* FCVTAS */
8205 case 0x5c: /* FCVTAU */
8206 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
8208 rmode
= FPROUNDING_TIEAWAY
;
8210 case 0x56: /* FCVTXN, FCVTXN2 */
8212 unallocated_encoding(s
);
8215 if (!fp_access_check(s
)) {
8218 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
8221 unallocated_encoding(s
);
8226 unallocated_encoding(s
);
8230 if (!fp_access_check(s
)) {
8235 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
8236 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8237 tcg_fpstatus
= get_fpstatus_ptr();
8240 tcg_fpstatus
= NULL
;
8244 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8245 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
8247 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
8248 write_fp_dreg(s
, rd
, tcg_rd
);
8249 tcg_temp_free_i64(tcg_rd
);
8250 tcg_temp_free_i64(tcg_rn
);
8252 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8253 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8255 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8258 case 0x7: /* SQABS, SQNEG */
8260 NeonGenOneOpEnvFn
*genfn
;
8261 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
8262 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
8263 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
8264 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
8266 genfn
= fns
[size
][u
];
8267 genfn(tcg_rd
, cpu_env
, tcg_rn
);
8270 case 0x1a: /* FCVTNS */
8271 case 0x1b: /* FCVTMS */
8272 case 0x1c: /* FCVTAS */
8273 case 0x3a: /* FCVTPS */
8274 case 0x3b: /* FCVTZS */
8276 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8277 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8278 tcg_temp_free_i32(tcg_shift
);
8281 case 0x5a: /* FCVTNU */
8282 case 0x5b: /* FCVTMU */
8283 case 0x5c: /* FCVTAU */
8284 case 0x7a: /* FCVTPU */
8285 case 0x7b: /* FCVTZU */
8287 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8288 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8289 tcg_temp_free_i32(tcg_shift
);
8293 g_assert_not_reached();
8296 write_fp_sreg(s
, rd
, tcg_rd
);
8297 tcg_temp_free_i32(tcg_rd
);
8298 tcg_temp_free_i32(tcg_rn
);
8302 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8303 tcg_temp_free_i32(tcg_rmode
);
8304 tcg_temp_free_ptr(tcg_fpstatus
);
8308 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
8309 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
8310 int immh
, int immb
, int opcode
, int rn
, int rd
)
8312 int size
= 32 - clz32(immh
) - 1;
8313 int immhb
= immh
<< 3 | immb
;
8314 int shift
= 2 * (8 << size
) - immhb
;
8315 bool accumulate
= false;
8317 bool insert
= false;
8318 int dsize
= is_q
? 128 : 64;
8319 int esize
= 8 << size
;
8320 int elements
= dsize
/esize
;
8321 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
8322 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8323 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8327 if (extract32(immh
, 3, 1) && !is_q
) {
8328 unallocated_encoding(s
);
8332 if (size
> 3 && !is_q
) {
8333 unallocated_encoding(s
);
8337 if (!fp_access_check(s
)) {
8342 case 0x02: /* SSRA / USRA (accumulate) */
8345 case 0x04: /* SRSHR / URSHR (rounding) */
8348 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8349 accumulate
= round
= true;
8351 case 0x08: /* SRI */
8357 uint64_t round_const
= 1ULL << (shift
- 1);
8358 tcg_round
= tcg_const_i64(round_const
);
8363 for (i
= 0; i
< elements
; i
++) {
8364 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
8365 if (accumulate
|| insert
) {
8366 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
8370 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
8372 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8373 accumulate
, is_u
, size
, shift
);
8376 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8380 clear_vec_high(s
, rd
);
8384 tcg_temp_free_i64(tcg_round
);
8388 /* SHL/SLI - Vector shift left */
8389 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
8390 int immh
, int immb
, int opcode
, int rn
, int rd
)
8392 int size
= 32 - clz32(immh
) - 1;
8393 int immhb
= immh
<< 3 | immb
;
8394 int shift
= immhb
- (8 << size
);
8395 int dsize
= is_q
? 128 : 64;
8396 int esize
= 8 << size
;
8397 int elements
= dsize
/esize
;
8398 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8399 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8402 if (extract32(immh
, 3, 1) && !is_q
) {
8403 unallocated_encoding(s
);
8407 if (size
> 3 && !is_q
) {
8408 unallocated_encoding(s
);
8412 if (!fp_access_check(s
)) {
8416 for (i
= 0; i
< elements
; i
++) {
8417 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8419 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
8422 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
8424 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8428 clear_vec_high(s
, rd
);
8432 /* USHLL/SHLL - Vector shift left with widening */
8433 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
8434 int immh
, int immb
, int opcode
, int rn
, int rd
)
8436 int size
= 32 - clz32(immh
) - 1;
8437 int immhb
= immh
<< 3 | immb
;
8438 int shift
= immhb
- (8 << size
);
8440 int esize
= 8 << size
;
8441 int elements
= dsize
/esize
;
8442 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8443 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8447 unallocated_encoding(s
);
8451 if (!fp_access_check(s
)) {
8455 /* For the LL variants the store is larger than the load,
8456 * so if rd == rn we would overwrite parts of our input.
8457 * So load everything right now and use shifts in the main loop.
8459 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
8461 for (i
= 0; i
< elements
; i
++) {
8462 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
8463 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
8464 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
8465 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
8469 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8470 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
8471 int immh
, int immb
, int opcode
, int rn
, int rd
)
8473 int immhb
= immh
<< 3 | immb
;
8474 int size
= 32 - clz32(immh
) - 1;
8476 int esize
= 8 << size
;
8477 int elements
= dsize
/esize
;
8478 int shift
= (2 * esize
) - immhb
;
8479 bool round
= extract32(opcode
, 0, 1);
8480 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
8484 if (extract32(immh
, 3, 1)) {
8485 unallocated_encoding(s
);
8489 if (!fp_access_check(s
)) {
8493 tcg_rn
= tcg_temp_new_i64();
8494 tcg_rd
= tcg_temp_new_i64();
8495 tcg_final
= tcg_temp_new_i64();
8496 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
8499 uint64_t round_const
= 1ULL << (shift
- 1);
8500 tcg_round
= tcg_const_i64(round_const
);
8505 for (i
= 0; i
< elements
; i
++) {
8506 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
8507 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8508 false, true, size
+1, shift
);
8510 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8514 clear_vec_high(s
, rd
);
8515 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8517 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8521 tcg_temp_free_i64(tcg_round
);
8523 tcg_temp_free_i64(tcg_rn
);
8524 tcg_temp_free_i64(tcg_rd
);
8525 tcg_temp_free_i64(tcg_final
);
8530 /* AdvSIMD shift by immediate
8531 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8532 * +---+---+---+-------------+------+------+--------+---+------+------+
8533 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8534 * +---+---+---+-------------+------+------+--------+---+------+------+
8536 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
8538 int rd
= extract32(insn
, 0, 5);
8539 int rn
= extract32(insn
, 5, 5);
8540 int opcode
= extract32(insn
, 11, 5);
8541 int immb
= extract32(insn
, 16, 3);
8542 int immh
= extract32(insn
, 19, 4);
8543 bool is_u
= extract32(insn
, 29, 1);
8544 bool is_q
= extract32(insn
, 30, 1);
8547 case 0x08: /* SRI */
8549 unallocated_encoding(s
);
8553 case 0x00: /* SSHR / USHR */
8554 case 0x02: /* SSRA / USRA (accumulate) */
8555 case 0x04: /* SRSHR / URSHR (rounding) */
8556 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8557 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8559 case 0x0a: /* SHL / SLI */
8560 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8562 case 0x10: /* SHRN */
8563 case 0x11: /* RSHRN / SQRSHRUN */
8565 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
8568 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
8571 case 0x12: /* SQSHRN / UQSHRN */
8572 case 0x13: /* SQRSHRN / UQRSHRN */
8573 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
8576 case 0x14: /* SSHLL / USHLL */
8577 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8579 case 0x1c: /* SCVTF / UCVTF */
8580 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
8583 case 0xc: /* SQSHLU */
8585 unallocated_encoding(s
);
8588 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
8590 case 0xe: /* SQSHL, UQSHL */
8591 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
8593 case 0x1f: /* FCVTZS/ FCVTZU */
8594 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
8597 unallocated_encoding(s
);
8602 /* Generate code to do a "long" addition or subtraction, ie one done in
8603 * TCGv_i64 on vector lanes twice the width specified by size.
8605 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
8606 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
8608 static NeonGenTwo64OpFn
* const fns
[3][2] = {
8609 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
8610 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
8611 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
8613 NeonGenTwo64OpFn
*genfn
;
8616 genfn
= fns
[size
][is_sub
];
8617 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8620 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
8621 int opcode
, int rd
, int rn
, int rm
)
8623 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8624 TCGv_i64 tcg_res
[2];
8627 tcg_res
[0] = tcg_temp_new_i64();
8628 tcg_res
[1] = tcg_temp_new_i64();
8630 /* Does this op do an adding accumulate, a subtracting accumulate,
8631 * or no accumulate at all?
8649 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8650 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8653 /* size == 2 means two 32x32->64 operations; this is worth special
8654 * casing because we can generally handle it inline.
8657 for (pass
= 0; pass
< 2; pass
++) {
8658 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8659 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8660 TCGv_i64 tcg_passres
;
8661 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
8663 int elt
= pass
+ is_q
* 2;
8665 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
8666 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
8669 tcg_passres
= tcg_res
[pass
];
8671 tcg_passres
= tcg_temp_new_i64();
8675 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8676 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8678 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8679 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8681 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8682 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8684 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
8685 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
8687 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
8688 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
8689 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
8691 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
8692 tcg_temp_free_i64(tcg_tmp1
);
8693 tcg_temp_free_i64(tcg_tmp2
);
8696 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8697 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8698 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8699 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8701 case 9: /* SQDMLAL, SQDMLAL2 */
8702 case 11: /* SQDMLSL, SQDMLSL2 */
8703 case 13: /* SQDMULL, SQDMULL2 */
8704 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8705 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8706 tcg_passres
, tcg_passres
);
8709 g_assert_not_reached();
8712 if (opcode
== 9 || opcode
== 11) {
8713 /* saturating accumulate ops */
8715 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8717 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8718 tcg_res
[pass
], tcg_passres
);
8719 } else if (accop
> 0) {
8720 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8721 } else if (accop
< 0) {
8722 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8726 tcg_temp_free_i64(tcg_passres
);
8729 tcg_temp_free_i64(tcg_op1
);
8730 tcg_temp_free_i64(tcg_op2
);
8733 /* size 0 or 1, generally helper functions */
8734 for (pass
= 0; pass
< 2; pass
++) {
8735 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8736 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8737 TCGv_i64 tcg_passres
;
8738 int elt
= pass
+ is_q
* 2;
8740 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
8741 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
8744 tcg_passres
= tcg_res
[pass
];
8746 tcg_passres
= tcg_temp_new_i64();
8750 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8751 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8753 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
8754 static NeonGenWidenFn
* const widenfns
[2][2] = {
8755 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8756 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8758 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8760 widenfn(tcg_op2_64
, tcg_op2
);
8761 widenfn(tcg_passres
, tcg_op1
);
8762 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
8763 tcg_passres
, tcg_op2_64
);
8764 tcg_temp_free_i64(tcg_op2_64
);
8767 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8768 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8771 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8773 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8777 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
8779 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
8783 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8784 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8785 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8788 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
8790 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
8794 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8796 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8800 case 9: /* SQDMLAL, SQDMLAL2 */
8801 case 11: /* SQDMLSL, SQDMLSL2 */
8802 case 13: /* SQDMULL, SQDMULL2 */
8804 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8805 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8806 tcg_passres
, tcg_passres
);
8808 case 14: /* PMULL */
8810 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
8813 g_assert_not_reached();
8815 tcg_temp_free_i32(tcg_op1
);
8816 tcg_temp_free_i32(tcg_op2
);
8819 if (opcode
== 9 || opcode
== 11) {
8820 /* saturating accumulate ops */
8822 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8824 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8828 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
8829 tcg_res
[pass
], tcg_passres
);
8831 tcg_temp_free_i64(tcg_passres
);
8836 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8837 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8838 tcg_temp_free_i64(tcg_res
[0]);
8839 tcg_temp_free_i64(tcg_res
[1]);
8842 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8843 int opcode
, int rd
, int rn
, int rm
)
8845 TCGv_i64 tcg_res
[2];
8846 int part
= is_q
? 2 : 0;
8849 for (pass
= 0; pass
< 2; pass
++) {
8850 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8851 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8852 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8853 static NeonGenWidenFn
* const widenfns
[3][2] = {
8854 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8855 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8856 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8858 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8860 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8861 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8862 widenfn(tcg_op2_wide
, tcg_op2
);
8863 tcg_temp_free_i32(tcg_op2
);
8864 tcg_res
[pass
] = tcg_temp_new_i64();
8865 gen_neon_addl(size
, (opcode
== 3),
8866 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8867 tcg_temp_free_i64(tcg_op1
);
8868 tcg_temp_free_i64(tcg_op2_wide
);
8871 for (pass
= 0; pass
< 2; pass
++) {
8872 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8873 tcg_temp_free_i64(tcg_res
[pass
]);
8877 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8879 tcg_gen_addi_i64(in
, in
, 1U << 31);
8880 tcg_gen_extrh_i64_i32(res
, in
);
8883 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8884 int opcode
, int rd
, int rn
, int rm
)
8886 TCGv_i32 tcg_res
[2];
8887 int part
= is_q
? 2 : 0;
8890 for (pass
= 0; pass
< 2; pass
++) {
8891 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8892 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8893 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8894 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8895 { gen_helper_neon_narrow_high_u8
,
8896 gen_helper_neon_narrow_round_high_u8
},
8897 { gen_helper_neon_narrow_high_u16
,
8898 gen_helper_neon_narrow_round_high_u16
},
8899 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
8901 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8903 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8904 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8906 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8908 tcg_temp_free_i64(tcg_op1
);
8909 tcg_temp_free_i64(tcg_op2
);
8911 tcg_res
[pass
] = tcg_temp_new_i32();
8912 gennarrow(tcg_res
[pass
], tcg_wideres
);
8913 tcg_temp_free_i64(tcg_wideres
);
8916 for (pass
= 0; pass
< 2; pass
++) {
8917 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8918 tcg_temp_free_i32(tcg_res
[pass
]);
8921 clear_vec_high(s
, rd
);
8925 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8927 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8928 * is the only three-reg-diff instruction which produces a
8929 * 128-bit wide result from a single operation. However since
8930 * it's possible to calculate the two halves more or less
8931 * separately we just use two helper calls.
8933 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8934 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8935 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8937 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8938 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8939 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8940 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8941 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8942 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8944 tcg_temp_free_i64(tcg_op1
);
8945 tcg_temp_free_i64(tcg_op2
);
8946 tcg_temp_free_i64(tcg_res
);
8949 /* AdvSIMD three different
8950 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8951 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8952 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8953 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8955 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8957 /* Instructions in this group fall into three basic classes
8958 * (in each case with the operation working on each element in
8959 * the input vectors):
8960 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8962 * (2) wide 64 x 128 -> 128
8963 * (3) narrowing 128 x 128 -> 64
8964 * Here we do initial decode, catch unallocated cases and
8965 * dispatch to separate functions for each class.
8967 int is_q
= extract32(insn
, 30, 1);
8968 int is_u
= extract32(insn
, 29, 1);
8969 int size
= extract32(insn
, 22, 2);
8970 int opcode
= extract32(insn
, 12, 4);
8971 int rm
= extract32(insn
, 16, 5);
8972 int rn
= extract32(insn
, 5, 5);
8973 int rd
= extract32(insn
, 0, 5);
8976 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8977 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8978 /* 64 x 128 -> 128 */
8980 unallocated_encoding(s
);
8983 if (!fp_access_check(s
)) {
8986 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8988 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
8989 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
8990 /* 128 x 128 -> 64 */
8992 unallocated_encoding(s
);
8995 if (!fp_access_check(s
)) {
8998 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
9000 case 14: /* PMULL, PMULL2 */
9001 if (is_u
|| size
== 1 || size
== 2) {
9002 unallocated_encoding(s
);
9006 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
9007 unallocated_encoding(s
);
9010 if (!fp_access_check(s
)) {
9013 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
9017 case 9: /* SQDMLAL, SQDMLAL2 */
9018 case 11: /* SQDMLSL, SQDMLSL2 */
9019 case 13: /* SQDMULL, SQDMULL2 */
9020 if (is_u
|| size
== 0) {
9021 unallocated_encoding(s
);
9025 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
9026 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
9027 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
9028 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
9029 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
9030 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
9031 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
9032 /* 64 x 64 -> 128 */
9034 unallocated_encoding(s
);
9038 if (!fp_access_check(s
)) {
9042 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
9045 /* opcode 15 not allocated */
9046 unallocated_encoding(s
);
9051 /* Logic op (opcode == 3) subgroup of C3.6.16. */
9052 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
9054 int rd
= extract32(insn
, 0, 5);
9055 int rn
= extract32(insn
, 5, 5);
9056 int rm
= extract32(insn
, 16, 5);
9057 int size
= extract32(insn
, 22, 2);
9058 bool is_u
= extract32(insn
, 29, 1);
9059 bool is_q
= extract32(insn
, 30, 1);
9060 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
9063 if (!fp_access_check(s
)) {
9067 tcg_op1
= tcg_temp_new_i64();
9068 tcg_op2
= tcg_temp_new_i64();
9069 tcg_res
[0] = tcg_temp_new_i64();
9070 tcg_res
[1] = tcg_temp_new_i64();
9072 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
9073 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9074 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9079 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9082 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9085 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9088 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9093 /* B* ops need res loaded to operate on */
9094 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9099 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9101 case 1: /* BSL bitwise select */
9102 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9103 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9104 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
9106 case 2: /* BIT, bitwise insert if true */
9107 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9108 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9109 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9111 case 3: /* BIF, bitwise insert if false */
9112 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9113 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9114 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9120 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
9122 tcg_gen_movi_i64(tcg_res
[1], 0);
9124 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
9126 tcg_temp_free_i64(tcg_op1
);
9127 tcg_temp_free_i64(tcg_op2
);
9128 tcg_temp_free_i64(tcg_res
[0]);
9129 tcg_temp_free_i64(tcg_res
[1]);
9132 /* Helper functions for 32 bit comparisons */
9133 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9135 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
9138 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9140 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
9143 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9145 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
9148 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9150 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
9153 /* Pairwise op subgroup of C3.6.16.
9155 * This is called directly or via the handle_3same_float for float pairwise
9156 * operations where the opcode and size are calculated differently.
9158 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
9159 int size
, int rn
, int rm
, int rd
)
9164 /* Floating point operations need fpst */
9165 if (opcode
>= 0x58) {
9166 fpst
= get_fpstatus_ptr();
9171 if (!fp_access_check(s
)) {
9175 /* These operations work on the concatenated rm:rn, with each pair of
9176 * adjacent elements being operated on to produce an element in the result.
9179 TCGv_i64 tcg_res
[2];
9181 for (pass
= 0; pass
< 2; pass
++) {
9182 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9183 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9184 int passreg
= (pass
== 0) ? rn
: rm
;
9186 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
9187 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
9188 tcg_res
[pass
] = tcg_temp_new_i64();
9191 case 0x17: /* ADDP */
9192 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9194 case 0x58: /* FMAXNMP */
9195 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9197 case 0x5a: /* FADDP */
9198 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9200 case 0x5e: /* FMAXP */
9201 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9203 case 0x78: /* FMINNMP */
9204 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9206 case 0x7e: /* FMINP */
9207 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9210 g_assert_not_reached();
9213 tcg_temp_free_i64(tcg_op1
);
9214 tcg_temp_free_i64(tcg_op2
);
9217 for (pass
= 0; pass
< 2; pass
++) {
9218 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9219 tcg_temp_free_i64(tcg_res
[pass
]);
9222 int maxpass
= is_q
? 4 : 2;
9223 TCGv_i32 tcg_res
[4];
9225 for (pass
= 0; pass
< maxpass
; pass
++) {
9226 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9227 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9228 NeonGenTwoOpFn
*genfn
= NULL
;
9229 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
9230 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
9232 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
9233 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
9234 tcg_res
[pass
] = tcg_temp_new_i32();
9237 case 0x17: /* ADDP */
9239 static NeonGenTwoOpFn
* const fns
[3] = {
9240 gen_helper_neon_padd_u8
,
9241 gen_helper_neon_padd_u16
,
9247 case 0x14: /* SMAXP, UMAXP */
9249 static NeonGenTwoOpFn
* const fns
[3][2] = {
9250 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
9251 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
9252 { gen_max_s32
, gen_max_u32
},
9254 genfn
= fns
[size
][u
];
9257 case 0x15: /* SMINP, UMINP */
9259 static NeonGenTwoOpFn
* const fns
[3][2] = {
9260 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
9261 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
9262 { gen_min_s32
, gen_min_u32
},
9264 genfn
= fns
[size
][u
];
9267 /* The FP operations are all on single floats (32 bit) */
9268 case 0x58: /* FMAXNMP */
9269 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9271 case 0x5a: /* FADDP */
9272 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9274 case 0x5e: /* FMAXP */
9275 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9277 case 0x78: /* FMINNMP */
9278 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9280 case 0x7e: /* FMINP */
9281 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9284 g_assert_not_reached();
9287 /* FP ops called directly, otherwise call now */
9289 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9292 tcg_temp_free_i32(tcg_op1
);
9293 tcg_temp_free_i32(tcg_op2
);
9296 for (pass
= 0; pass
< maxpass
; pass
++) {
9297 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9298 tcg_temp_free_i32(tcg_res
[pass
]);
9301 clear_vec_high(s
, rd
);
9306 tcg_temp_free_ptr(fpst
);
9310 /* Floating point op subgroup of C3.6.16. */
9311 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
9313 /* For floating point ops, the U, size[1] and opcode bits
9314 * together indicate the operation. size[0] indicates single
9317 int fpopcode
= extract32(insn
, 11, 5)
9318 | (extract32(insn
, 23, 1) << 5)
9319 | (extract32(insn
, 29, 1) << 6);
9320 int is_q
= extract32(insn
, 30, 1);
9321 int size
= extract32(insn
, 22, 1);
9322 int rm
= extract32(insn
, 16, 5);
9323 int rn
= extract32(insn
, 5, 5);
9324 int rd
= extract32(insn
, 0, 5);
9326 int datasize
= is_q
? 128 : 64;
9327 int esize
= 32 << size
;
9328 int elements
= datasize
/ esize
;
9330 if (size
== 1 && !is_q
) {
9331 unallocated_encoding(s
);
9336 case 0x58: /* FMAXNMP */
9337 case 0x5a: /* FADDP */
9338 case 0x5e: /* FMAXP */
9339 case 0x78: /* FMINNMP */
9340 case 0x7e: /* FMINP */
9341 if (size
&& !is_q
) {
9342 unallocated_encoding(s
);
9345 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
9348 case 0x1b: /* FMULX */
9349 case 0x1f: /* FRECPS */
9350 case 0x3f: /* FRSQRTS */
9351 case 0x5d: /* FACGE */
9352 case 0x7d: /* FACGT */
9353 case 0x19: /* FMLA */
9354 case 0x39: /* FMLS */
9355 case 0x18: /* FMAXNM */
9356 case 0x1a: /* FADD */
9357 case 0x1c: /* FCMEQ */
9358 case 0x1e: /* FMAX */
9359 case 0x38: /* FMINNM */
9360 case 0x3a: /* FSUB */
9361 case 0x3e: /* FMIN */
9362 case 0x5b: /* FMUL */
9363 case 0x5c: /* FCMGE */
9364 case 0x5f: /* FDIV */
9365 case 0x7a: /* FABD */
9366 case 0x7c: /* FCMGT */
9367 if (!fp_access_check(s
)) {
9371 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
9374 unallocated_encoding(s
);
9379 /* Integer op subgroup of C3.6.16. */
9380 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
9382 int is_q
= extract32(insn
, 30, 1);
9383 int u
= extract32(insn
, 29, 1);
9384 int size
= extract32(insn
, 22, 2);
9385 int opcode
= extract32(insn
, 11, 5);
9386 int rm
= extract32(insn
, 16, 5);
9387 int rn
= extract32(insn
, 5, 5);
9388 int rd
= extract32(insn
, 0, 5);
9392 case 0x13: /* MUL, PMUL */
9393 if (u
&& size
!= 0) {
9394 unallocated_encoding(s
);
9398 case 0x0: /* SHADD, UHADD */
9399 case 0x2: /* SRHADD, URHADD */
9400 case 0x4: /* SHSUB, UHSUB */
9401 case 0xc: /* SMAX, UMAX */
9402 case 0xd: /* SMIN, UMIN */
9403 case 0xe: /* SABD, UABD */
9404 case 0xf: /* SABA, UABA */
9405 case 0x12: /* MLA, MLS */
9407 unallocated_encoding(s
);
9411 case 0x16: /* SQDMULH, SQRDMULH */
9412 if (size
== 0 || size
== 3) {
9413 unallocated_encoding(s
);
9418 if (size
== 3 && !is_q
) {
9419 unallocated_encoding(s
);
9425 if (!fp_access_check(s
)) {
9431 for (pass
= 0; pass
< 2; pass
++) {
9432 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9433 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9434 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9436 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9437 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9439 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
9441 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9443 tcg_temp_free_i64(tcg_res
);
9444 tcg_temp_free_i64(tcg_op1
);
9445 tcg_temp_free_i64(tcg_op2
);
9448 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9449 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9450 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9451 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9452 NeonGenTwoOpFn
*genfn
= NULL
;
9453 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
9455 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9456 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9459 case 0x0: /* SHADD, UHADD */
9461 static NeonGenTwoOpFn
* const fns
[3][2] = {
9462 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
9463 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
9464 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
9466 genfn
= fns
[size
][u
];
9469 case 0x1: /* SQADD, UQADD */
9471 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9472 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9473 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9474 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9476 genenvfn
= fns
[size
][u
];
9479 case 0x2: /* SRHADD, URHADD */
9481 static NeonGenTwoOpFn
* const fns
[3][2] = {
9482 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
9483 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
9484 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
9486 genfn
= fns
[size
][u
];
9489 case 0x4: /* SHSUB, UHSUB */
9491 static NeonGenTwoOpFn
* const fns
[3][2] = {
9492 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
9493 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
9494 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
9496 genfn
= fns
[size
][u
];
9499 case 0x5: /* SQSUB, UQSUB */
9501 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9502 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9503 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9504 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9506 genenvfn
= fns
[size
][u
];
9509 case 0x6: /* CMGT, CMHI */
9511 static NeonGenTwoOpFn
* const fns
[3][2] = {
9512 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
9513 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
9514 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
9516 genfn
= fns
[size
][u
];
9519 case 0x7: /* CMGE, CMHS */
9521 static NeonGenTwoOpFn
* const fns
[3][2] = {
9522 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
9523 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
9524 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
9526 genfn
= fns
[size
][u
];
9529 case 0x8: /* SSHL, USHL */
9531 static NeonGenTwoOpFn
* const fns
[3][2] = {
9532 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
9533 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
9534 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
9536 genfn
= fns
[size
][u
];
9539 case 0x9: /* SQSHL, UQSHL */
9541 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9542 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9543 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9544 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9546 genenvfn
= fns
[size
][u
];
9549 case 0xa: /* SRSHL, URSHL */
9551 static NeonGenTwoOpFn
* const fns
[3][2] = {
9552 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
9553 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
9554 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
9556 genfn
= fns
[size
][u
];
9559 case 0xb: /* SQRSHL, UQRSHL */
9561 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9562 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9563 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9564 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9566 genenvfn
= fns
[size
][u
];
9569 case 0xc: /* SMAX, UMAX */
9571 static NeonGenTwoOpFn
* const fns
[3][2] = {
9572 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
9573 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
9574 { gen_max_s32
, gen_max_u32
},
9576 genfn
= fns
[size
][u
];
9580 case 0xd: /* SMIN, UMIN */
9582 static NeonGenTwoOpFn
* const fns
[3][2] = {
9583 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
9584 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
9585 { gen_min_s32
, gen_min_u32
},
9587 genfn
= fns
[size
][u
];
9590 case 0xe: /* SABD, UABD */
9591 case 0xf: /* SABA, UABA */
9593 static NeonGenTwoOpFn
* const fns
[3][2] = {
9594 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
9595 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
9596 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
9598 genfn
= fns
[size
][u
];
9601 case 0x10: /* ADD, SUB */
9603 static NeonGenTwoOpFn
* const fns
[3][2] = {
9604 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9605 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9606 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9608 genfn
= fns
[size
][u
];
9611 case 0x11: /* CMTST, CMEQ */
9613 static NeonGenTwoOpFn
* const fns
[3][2] = {
9614 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
9615 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
9616 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
9618 genfn
= fns
[size
][u
];
9621 case 0x13: /* MUL, PMUL */
9625 genfn
= gen_helper_neon_mul_p8
;
9628 /* fall through : MUL */
9629 case 0x12: /* MLA, MLS */
9631 static NeonGenTwoOpFn
* const fns
[3] = {
9632 gen_helper_neon_mul_u8
,
9633 gen_helper_neon_mul_u16
,
9639 case 0x16: /* SQDMULH, SQRDMULH */
9641 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9642 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9643 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9645 assert(size
== 1 || size
== 2);
9646 genenvfn
= fns
[size
- 1][u
];
9650 g_assert_not_reached();
9654 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
9656 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9659 if (opcode
== 0xf || opcode
== 0x12) {
9660 /* SABA, UABA, MLA, MLS: accumulating ops */
9661 static NeonGenTwoOpFn
* const fns
[3][2] = {
9662 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9663 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9664 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9666 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
9668 genfn
= fns
[size
][is_sub
];
9669 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
9670 genfn(tcg_res
, tcg_op1
, tcg_res
);
9673 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9675 tcg_temp_free_i32(tcg_res
);
9676 tcg_temp_free_i32(tcg_op1
);
9677 tcg_temp_free_i32(tcg_op2
);
9682 clear_vec_high(s
, rd
);
9686 /* AdvSIMD three same
9687 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9688 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9689 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9690 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9692 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
9694 int opcode
= extract32(insn
, 11, 5);
9697 case 0x3: /* logic ops */
9698 disas_simd_3same_logic(s
, insn
);
9700 case 0x17: /* ADDP */
9701 case 0x14: /* SMAXP, UMAXP */
9702 case 0x15: /* SMINP, UMINP */
9704 /* Pairwise operations */
9705 int is_q
= extract32(insn
, 30, 1);
9706 int u
= extract32(insn
, 29, 1);
9707 int size
= extract32(insn
, 22, 2);
9708 int rm
= extract32(insn
, 16, 5);
9709 int rn
= extract32(insn
, 5, 5);
9710 int rd
= extract32(insn
, 0, 5);
9711 if (opcode
== 0x17) {
9712 if (u
|| (size
== 3 && !is_q
)) {
9713 unallocated_encoding(s
);
9718 unallocated_encoding(s
);
9722 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
9726 /* floating point ops, sz[1] and U are part of opcode */
9727 disas_simd_3same_float(s
, insn
);
9730 disas_simd_3same_int(s
, insn
);
9735 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
9736 int size
, int rn
, int rd
)
9738 /* Handle 2-reg-misc ops which are widening (so each size element
9739 * in the source becomes a 2*size element in the destination.
9740 * The only instruction like this is FCVTL.
9745 /* 32 -> 64 bit fp conversion */
9746 TCGv_i64 tcg_res
[2];
9747 int srcelt
= is_q
? 2 : 0;
9749 for (pass
= 0; pass
< 2; pass
++) {
9750 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9751 tcg_res
[pass
] = tcg_temp_new_i64();
9753 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
9754 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
9755 tcg_temp_free_i32(tcg_op
);
9757 for (pass
= 0; pass
< 2; pass
++) {
9758 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9759 tcg_temp_free_i64(tcg_res
[pass
]);
9762 /* 16 -> 32 bit fp conversion */
9763 int srcelt
= is_q
? 4 : 0;
9764 TCGv_i32 tcg_res
[4];
9766 for (pass
= 0; pass
< 4; pass
++) {
9767 tcg_res
[pass
] = tcg_temp_new_i32();
9769 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
9770 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
9773 for (pass
= 0; pass
< 4; pass
++) {
9774 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9775 tcg_temp_free_i32(tcg_res
[pass
]);
9780 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
9781 bool is_q
, int size
, int rn
, int rd
)
9783 int op
= (opcode
<< 1) | u
;
9784 int opsz
= op
+ size
;
9785 int grp_size
= 3 - opsz
;
9786 int dsize
= is_q
? 128 : 64;
9790 unallocated_encoding(s
);
9794 if (!fp_access_check(s
)) {
9799 /* Special case bytes, use bswap op on each group of elements */
9800 int groups
= dsize
/ (8 << grp_size
);
9802 for (i
= 0; i
< groups
; i
++) {
9803 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9805 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
9808 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
9811 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
9814 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
9817 g_assert_not_reached();
9819 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
9820 tcg_temp_free_i64(tcg_tmp
);
9823 clear_vec_high(s
, rd
);
9826 int revmask
= (1 << grp_size
) - 1;
9827 int esize
= 8 << size
;
9828 int elements
= dsize
/ esize
;
9829 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9830 TCGv_i64 tcg_rd
= tcg_const_i64(0);
9831 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
9833 for (i
= 0; i
< elements
; i
++) {
9834 int e_rev
= (i
& 0xf) ^ revmask
;
9835 int off
= e_rev
* esize
;
9836 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
9838 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
9839 tcg_rn
, off
- 64, esize
);
9841 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
9844 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
9845 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
9847 tcg_temp_free_i64(tcg_rd_hi
);
9848 tcg_temp_free_i64(tcg_rd
);
9849 tcg_temp_free_i64(tcg_rn
);
9853 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
9854 bool is_q
, int size
, int rn
, int rd
)
9856 /* Implement the pairwise operations from 2-misc:
9857 * SADDLP, UADDLP, SADALP, UADALP.
9858 * These all add pairs of elements in the input to produce a
9859 * double-width result element in the output (possibly accumulating).
9861 bool accum
= (opcode
== 0x6);
9862 int maxpass
= is_q
? 2 : 1;
9864 TCGv_i64 tcg_res
[2];
9867 /* 32 + 32 -> 64 op */
9868 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9870 for (pass
= 0; pass
< maxpass
; pass
++) {
9871 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9872 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9874 tcg_res
[pass
] = tcg_temp_new_i64();
9876 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9877 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9878 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9880 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9881 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9884 tcg_temp_free_i64(tcg_op1
);
9885 tcg_temp_free_i64(tcg_op2
);
9888 for (pass
= 0; pass
< maxpass
; pass
++) {
9889 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9890 NeonGenOneOpFn
*genfn
;
9891 static NeonGenOneOpFn
* const fns
[2][2] = {
9892 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9893 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9896 genfn
= fns
[size
][u
];
9898 tcg_res
[pass
] = tcg_temp_new_i64();
9900 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9901 genfn(tcg_res
[pass
], tcg_op
);
9904 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9906 gen_helper_neon_addl_u16(tcg_res
[pass
],
9907 tcg_res
[pass
], tcg_op
);
9909 gen_helper_neon_addl_u32(tcg_res
[pass
],
9910 tcg_res
[pass
], tcg_op
);
9913 tcg_temp_free_i64(tcg_op
);
9917 tcg_res
[1] = tcg_const_i64(0);
9919 for (pass
= 0; pass
< 2; pass
++) {
9920 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9921 tcg_temp_free_i64(tcg_res
[pass
]);
9925 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
9927 /* Implement SHLL and SHLL2 */
9929 int part
= is_q
? 2 : 0;
9930 TCGv_i64 tcg_res
[2];
9932 for (pass
= 0; pass
< 2; pass
++) {
9933 static NeonGenWidenFn
* const widenfns
[3] = {
9934 gen_helper_neon_widen_u8
,
9935 gen_helper_neon_widen_u16
,
9936 tcg_gen_extu_i32_i64
,
9938 NeonGenWidenFn
*widenfn
= widenfns
[size
];
9939 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9941 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
9942 tcg_res
[pass
] = tcg_temp_new_i64();
9943 widenfn(tcg_res
[pass
], tcg_op
);
9944 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
9946 tcg_temp_free_i32(tcg_op
);
9949 for (pass
= 0; pass
< 2; pass
++) {
9950 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9951 tcg_temp_free_i64(tcg_res
[pass
]);
9955 /* AdvSIMD two reg misc
9956 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9957 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9958 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9959 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9961 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9963 int size
= extract32(insn
, 22, 2);
9964 int opcode
= extract32(insn
, 12, 5);
9965 bool u
= extract32(insn
, 29, 1);
9966 bool is_q
= extract32(insn
, 30, 1);
9967 int rn
= extract32(insn
, 5, 5);
9968 int rd
= extract32(insn
, 0, 5);
9969 bool need_fpstatus
= false;
9970 bool need_rmode
= false;
9973 TCGv_ptr tcg_fpstatus
;
9976 case 0x0: /* REV64, REV32 */
9977 case 0x1: /* REV16 */
9978 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9980 case 0x5: /* CNT, NOT, RBIT */
9981 if (u
&& size
== 0) {
9982 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
9985 } else if (u
&& size
== 1) {
9988 } else if (!u
&& size
== 0) {
9992 unallocated_encoding(s
);
9994 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
9995 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
9997 unallocated_encoding(s
);
10000 if (!fp_access_check(s
)) {
10004 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
10006 case 0x4: /* CLS, CLZ */
10008 unallocated_encoding(s
);
10012 case 0x2: /* SADDLP, UADDLP */
10013 case 0x6: /* SADALP, UADALP */
10015 unallocated_encoding(s
);
10018 if (!fp_access_check(s
)) {
10021 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
10023 case 0x13: /* SHLL, SHLL2 */
10024 if (u
== 0 || size
== 3) {
10025 unallocated_encoding(s
);
10028 if (!fp_access_check(s
)) {
10031 handle_shll(s
, is_q
, size
, rn
, rd
);
10033 case 0xa: /* CMLT */
10035 unallocated_encoding(s
);
10039 case 0x8: /* CMGT, CMGE */
10040 case 0x9: /* CMEQ, CMLE */
10041 case 0xb: /* ABS, NEG */
10042 if (size
== 3 && !is_q
) {
10043 unallocated_encoding(s
);
10047 case 0x3: /* SUQADD, USQADD */
10048 if (size
== 3 && !is_q
) {
10049 unallocated_encoding(s
);
10052 if (!fp_access_check(s
)) {
10055 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
10057 case 0x7: /* SQABS, SQNEG */
10058 if (size
== 3 && !is_q
) {
10059 unallocated_encoding(s
);
10064 case 0x16 ... 0x1d:
10067 /* Floating point: U, size[1] and opcode indicate operation;
10068 * size[0] indicates single or double precision.
10070 int is_double
= extract32(size
, 0, 1);
10071 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10072 size
= is_double
? 3 : 2;
10074 case 0x2f: /* FABS */
10075 case 0x6f: /* FNEG */
10076 if (size
== 3 && !is_q
) {
10077 unallocated_encoding(s
);
10081 case 0x1d: /* SCVTF */
10082 case 0x5d: /* UCVTF */
10084 bool is_signed
= (opcode
== 0x1d) ? true : false;
10085 int elements
= is_double
? 2 : is_q
? 4 : 2;
10086 if (is_double
&& !is_q
) {
10087 unallocated_encoding(s
);
10090 if (!fp_access_check(s
)) {
10093 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
10096 case 0x2c: /* FCMGT (zero) */
10097 case 0x2d: /* FCMEQ (zero) */
10098 case 0x2e: /* FCMLT (zero) */
10099 case 0x6c: /* FCMGE (zero) */
10100 case 0x6d: /* FCMLE (zero) */
10101 if (size
== 3 && !is_q
) {
10102 unallocated_encoding(s
);
10105 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10107 case 0x7f: /* FSQRT */
10108 if (size
== 3 && !is_q
) {
10109 unallocated_encoding(s
);
10113 case 0x1a: /* FCVTNS */
10114 case 0x1b: /* FCVTMS */
10115 case 0x3a: /* FCVTPS */
10116 case 0x3b: /* FCVTZS */
10117 case 0x5a: /* FCVTNU */
10118 case 0x5b: /* FCVTMU */
10119 case 0x7a: /* FCVTPU */
10120 case 0x7b: /* FCVTZU */
10121 need_fpstatus
= true;
10123 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10124 if (size
== 3 && !is_q
) {
10125 unallocated_encoding(s
);
10129 case 0x5c: /* FCVTAU */
10130 case 0x1c: /* FCVTAS */
10131 need_fpstatus
= true;
10133 rmode
= FPROUNDING_TIEAWAY
;
10134 if (size
== 3 && !is_q
) {
10135 unallocated_encoding(s
);
10139 case 0x3c: /* URECPE */
10141 unallocated_encoding(s
);
10145 case 0x3d: /* FRECPE */
10146 case 0x7d: /* FRSQRTE */
10147 if (size
== 3 && !is_q
) {
10148 unallocated_encoding(s
);
10151 if (!fp_access_check(s
)) {
10154 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10156 case 0x56: /* FCVTXN, FCVTXN2 */
10158 unallocated_encoding(s
);
10162 case 0x16: /* FCVTN, FCVTN2 */
10163 /* handle_2misc_narrow does a 2*size -> size operation, but these
10164 * instructions encode the source size rather than dest size.
10166 if (!fp_access_check(s
)) {
10169 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
10171 case 0x17: /* FCVTL, FCVTL2 */
10172 if (!fp_access_check(s
)) {
10175 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
10177 case 0x18: /* FRINTN */
10178 case 0x19: /* FRINTM */
10179 case 0x38: /* FRINTP */
10180 case 0x39: /* FRINTZ */
10182 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10184 case 0x59: /* FRINTX */
10185 case 0x79: /* FRINTI */
10186 need_fpstatus
= true;
10187 if (size
== 3 && !is_q
) {
10188 unallocated_encoding(s
);
10192 case 0x58: /* FRINTA */
10194 rmode
= FPROUNDING_TIEAWAY
;
10195 need_fpstatus
= true;
10196 if (size
== 3 && !is_q
) {
10197 unallocated_encoding(s
);
10201 case 0x7c: /* URSQRTE */
10203 unallocated_encoding(s
);
10206 need_fpstatus
= true;
10209 unallocated_encoding(s
);
10215 unallocated_encoding(s
);
10219 if (!fp_access_check(s
)) {
10223 if (need_fpstatus
) {
10224 tcg_fpstatus
= get_fpstatus_ptr();
10226 tcg_fpstatus
= NULL
;
10229 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10230 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10236 /* All 64-bit element operations can be shared with scalar 2misc */
10239 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
10240 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10241 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10243 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10245 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
10246 tcg_rmode
, tcg_fpstatus
);
10248 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10250 tcg_temp_free_i64(tcg_res
);
10251 tcg_temp_free_i64(tcg_op
);
10256 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
10257 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10258 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10261 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10264 /* Special cases for 32 bit elements */
10266 case 0xa: /* CMLT */
10267 /* 32 bit integer comparison against zero, result is
10268 * test ? (2^32 - 1) : 0. We implement via setcond(test)
10271 cond
= TCG_COND_LT
;
10273 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
10274 tcg_gen_neg_i32(tcg_res
, tcg_res
);
10276 case 0x8: /* CMGT, CMGE */
10277 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
10279 case 0x9: /* CMEQ, CMLE */
10280 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
10282 case 0x4: /* CLS */
10284 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
10286 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
10289 case 0x7: /* SQABS, SQNEG */
10291 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
10293 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
10296 case 0xb: /* ABS, NEG */
10298 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10300 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10301 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10302 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
10303 tcg_zero
, tcg_op
, tcg_res
);
10304 tcg_temp_free_i32(tcg_zero
);
10307 case 0x2f: /* FABS */
10308 gen_helper_vfp_abss(tcg_res
, tcg_op
);
10310 case 0x6f: /* FNEG */
10311 gen_helper_vfp_negs(tcg_res
, tcg_op
);
10313 case 0x7f: /* FSQRT */
10314 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
10316 case 0x1a: /* FCVTNS */
10317 case 0x1b: /* FCVTMS */
10318 case 0x1c: /* FCVTAS */
10319 case 0x3a: /* FCVTPS */
10320 case 0x3b: /* FCVTZS */
10322 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10323 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
10324 tcg_shift
, tcg_fpstatus
);
10325 tcg_temp_free_i32(tcg_shift
);
10328 case 0x5a: /* FCVTNU */
10329 case 0x5b: /* FCVTMU */
10330 case 0x5c: /* FCVTAU */
10331 case 0x7a: /* FCVTPU */
10332 case 0x7b: /* FCVTZU */
10334 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10335 gen_helper_vfp_touls(tcg_res
, tcg_op
,
10336 tcg_shift
, tcg_fpstatus
);
10337 tcg_temp_free_i32(tcg_shift
);
10340 case 0x18: /* FRINTN */
10341 case 0x19: /* FRINTM */
10342 case 0x38: /* FRINTP */
10343 case 0x39: /* FRINTZ */
10344 case 0x58: /* FRINTA */
10345 case 0x79: /* FRINTI */
10346 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
10348 case 0x59: /* FRINTX */
10349 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
10351 case 0x7c: /* URSQRTE */
10352 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
10355 g_assert_not_reached();
10358 /* Use helpers for 8 and 16 bit elements */
10360 case 0x5: /* CNT, RBIT */
10361 /* For these two insns size is part of the opcode specifier
10362 * (handled earlier); they always operate on byte elements.
10365 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
10367 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
10370 case 0x7: /* SQABS, SQNEG */
10372 NeonGenOneOpEnvFn
*genfn
;
10373 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
10374 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10375 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10377 genfn
= fns
[size
][u
];
10378 genfn(tcg_res
, cpu_env
, tcg_op
);
10381 case 0x8: /* CMGT, CMGE */
10382 case 0x9: /* CMEQ, CMLE */
10383 case 0xa: /* CMLT */
10385 static NeonGenTwoOpFn
* const fns
[3][2] = {
10386 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
10387 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
10388 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
10390 NeonGenTwoOpFn
*genfn
;
10393 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10395 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
10396 comp
= (opcode
- 0x8) * 2 + u
;
10397 /* ...but LE, LT are implemented as reverse GE, GT */
10398 reverse
= (comp
> 2);
10402 genfn
= fns
[comp
][size
];
10404 genfn(tcg_res
, tcg_zero
, tcg_op
);
10406 genfn(tcg_res
, tcg_op
, tcg_zero
);
10408 tcg_temp_free_i32(tcg_zero
);
10411 case 0xb: /* ABS, NEG */
10413 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10415 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
10417 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
10419 tcg_temp_free_i32(tcg_zero
);
10422 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
10424 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
10428 case 0x4: /* CLS, CLZ */
10431 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
10433 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
10437 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
10439 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
10444 g_assert_not_reached();
10448 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10450 tcg_temp_free_i32(tcg_res
);
10451 tcg_temp_free_i32(tcg_op
);
10455 clear_vec_high(s
, rd
);
10459 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10460 tcg_temp_free_i32(tcg_rmode
);
10462 if (need_fpstatus
) {
10463 tcg_temp_free_ptr(tcg_fpstatus
);
10467 /* AdvSIMD scalar x indexed element
10468 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10469 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10470 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10471 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10472 * AdvSIMD vector x indexed element
10473 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10474 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10475 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10476 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10478 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
10480 /* This encoding has two kinds of instruction:
10481 * normal, where we perform elt x idxelt => elt for each
10482 * element in the vector
10483 * long, where we perform elt x idxelt and generate a result of
10484 * double the width of the input element
10485 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10487 bool is_scalar
= extract32(insn
, 28, 1);
10488 bool is_q
= extract32(insn
, 30, 1);
10489 bool u
= extract32(insn
, 29, 1);
10490 int size
= extract32(insn
, 22, 2);
10491 int l
= extract32(insn
, 21, 1);
10492 int m
= extract32(insn
, 20, 1);
10493 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10494 int rm
= extract32(insn
, 16, 4);
10495 int opcode
= extract32(insn
, 12, 4);
10496 int h
= extract32(insn
, 11, 1);
10497 int rn
= extract32(insn
, 5, 5);
10498 int rd
= extract32(insn
, 0, 5);
10499 bool is_long
= false;
10500 bool is_fp
= false;
10505 case 0x0: /* MLA */
10506 case 0x4: /* MLS */
10507 if (!u
|| is_scalar
) {
10508 unallocated_encoding(s
);
10512 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10513 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10514 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10516 unallocated_encoding(s
);
10521 case 0x3: /* SQDMLAL, SQDMLAL2 */
10522 case 0x7: /* SQDMLSL, SQDMLSL2 */
10523 case 0xb: /* SQDMULL, SQDMULL2 */
10526 case 0xc: /* SQDMULH */
10527 case 0xd: /* SQRDMULH */
10529 unallocated_encoding(s
);
10533 case 0x8: /* MUL */
10534 if (u
|| is_scalar
) {
10535 unallocated_encoding(s
);
10539 case 0x1: /* FMLA */
10540 case 0x5: /* FMLS */
10542 unallocated_encoding(s
);
10546 case 0x9: /* FMUL, FMULX */
10547 if (!extract32(size
, 1, 1)) {
10548 unallocated_encoding(s
);
10554 unallocated_encoding(s
);
10559 /* low bit of size indicates single/double */
10560 size
= extract32(size
, 0, 1) ? 3 : 2;
10562 index
= h
<< 1 | l
;
10565 unallocated_encoding(s
);
10574 index
= h
<< 2 | l
<< 1 | m
;
10577 index
= h
<< 1 | l
;
10581 unallocated_encoding(s
);
10586 if (!fp_access_check(s
)) {
10591 fpst
= get_fpstatus_ptr();
10597 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10600 assert(is_fp
&& is_q
&& !is_long
);
10602 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
10604 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10605 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10606 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10608 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10611 case 0x5: /* FMLS */
10612 /* As usual for ARM, separate negation for fused multiply-add */
10613 gen_helper_vfp_negd(tcg_op
, tcg_op
);
10615 case 0x1: /* FMLA */
10616 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10617 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10619 case 0x9: /* FMUL, FMULX */
10621 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10623 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10627 g_assert_not_reached();
10630 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10631 tcg_temp_free_i64(tcg_op
);
10632 tcg_temp_free_i64(tcg_res
);
10636 clear_vec_high(s
, rd
);
10639 tcg_temp_free_i64(tcg_idx
);
10640 } else if (!is_long
) {
10641 /* 32 bit floating point, or 16 or 32 bit integer.
10642 * For the 16 bit scalar case we use the usual Neon helpers and
10643 * rely on the fact that 0 op 0 == 0 with no side effects.
10645 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10646 int pass
, maxpasses
;
10651 maxpasses
= is_q
? 4 : 2;
10654 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10656 if (size
== 1 && !is_scalar
) {
10657 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10658 * the index into both halves of the 32 bit tcg_idx and then use
10659 * the usual Neon helpers.
10661 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10664 for (pass
= 0; pass
< maxpasses
; pass
++) {
10665 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10666 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10668 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
10671 case 0x0: /* MLA */
10672 case 0x4: /* MLS */
10673 case 0x8: /* MUL */
10675 static NeonGenTwoOpFn
* const fns
[2][2] = {
10676 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
10677 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
10679 NeonGenTwoOpFn
*genfn
;
10680 bool is_sub
= opcode
== 0x4;
10683 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
10685 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
10687 if (opcode
== 0x8) {
10690 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
10691 genfn
= fns
[size
- 1][is_sub
];
10692 genfn(tcg_res
, tcg_op
, tcg_res
);
10695 case 0x5: /* FMLS */
10696 /* As usual for ARM, separate negation for fused multiply-add */
10697 gen_helper_vfp_negs(tcg_op
, tcg_op
);
10699 case 0x1: /* FMLA */
10700 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10701 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10703 case 0x9: /* FMUL, FMULX */
10705 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10707 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10710 case 0xc: /* SQDMULH */
10712 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
10715 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
10719 case 0xd: /* SQRDMULH */
10721 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
10724 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
10729 g_assert_not_reached();
10733 write_fp_sreg(s
, rd
, tcg_res
);
10735 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10738 tcg_temp_free_i32(tcg_op
);
10739 tcg_temp_free_i32(tcg_res
);
10742 tcg_temp_free_i32(tcg_idx
);
10745 clear_vec_high(s
, rd
);
10748 /* long ops: 16x16->32 or 32x32->64 */
10749 TCGv_i64 tcg_res
[2];
10751 bool satop
= extract32(opcode
, 0, 1);
10752 TCGMemOp memop
= MO_32
;
10759 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10761 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
10763 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10764 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10765 TCGv_i64 tcg_passres
;
10771 passelt
= pass
+ (is_q
* 2);
10774 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
10776 tcg_res
[pass
] = tcg_temp_new_i64();
10778 if (opcode
== 0xa || opcode
== 0xb) {
10779 /* Non-accumulating ops */
10780 tcg_passres
= tcg_res
[pass
];
10782 tcg_passres
= tcg_temp_new_i64();
10785 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
10786 tcg_temp_free_i64(tcg_op
);
10789 /* saturating, doubling */
10790 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10791 tcg_passres
, tcg_passres
);
10794 if (opcode
== 0xa || opcode
== 0xb) {
10798 /* Accumulating op: handle accumulate step */
10799 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10802 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10803 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10805 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10806 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10808 case 0x7: /* SQDMLSL, SQDMLSL2 */
10809 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10811 case 0x3: /* SQDMLAL, SQDMLAL2 */
10812 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10817 g_assert_not_reached();
10819 tcg_temp_free_i64(tcg_passres
);
10821 tcg_temp_free_i64(tcg_idx
);
10824 clear_vec_high(s
, rd
);
10827 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10830 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10833 /* The simplest way to handle the 16x16 indexed ops is to
10834 * duplicate the index into both halves of the 32 bit tcg_idx
10835 * and then use the usual Neon helpers.
10837 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10840 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10841 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10842 TCGv_i64 tcg_passres
;
10845 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10847 read_vec_element_i32(s
, tcg_op
, rn
,
10848 pass
+ (is_q
* 2), MO_32
);
10851 tcg_res
[pass
] = tcg_temp_new_i64();
10853 if (opcode
== 0xa || opcode
== 0xb) {
10854 /* Non-accumulating ops */
10855 tcg_passres
= tcg_res
[pass
];
10857 tcg_passres
= tcg_temp_new_i64();
10860 if (memop
& MO_SIGN
) {
10861 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
10863 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
10866 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10867 tcg_passres
, tcg_passres
);
10869 tcg_temp_free_i32(tcg_op
);
10871 if (opcode
== 0xa || opcode
== 0xb) {
10875 /* Accumulating op: handle accumulate step */
10876 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10879 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10880 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
10883 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10884 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
10887 case 0x7: /* SQDMLSL, SQDMLSL2 */
10888 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10890 case 0x3: /* SQDMLAL, SQDMLAL2 */
10891 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10896 g_assert_not_reached();
10898 tcg_temp_free_i64(tcg_passres
);
10900 tcg_temp_free_i32(tcg_idx
);
10903 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
10908 tcg_res
[1] = tcg_const_i64(0);
10911 for (pass
= 0; pass
< 2; pass
++) {
10912 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10913 tcg_temp_free_i64(tcg_res
[pass
]);
10918 tcg_temp_free_ptr(fpst
);
10923 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10924 * +-----------------+------+-----------+--------+-----+------+------+
10925 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10926 * +-----------------+------+-----------+--------+-----+------+------+
10928 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
10930 int size
= extract32(insn
, 22, 2);
10931 int opcode
= extract32(insn
, 12, 5);
10932 int rn
= extract32(insn
, 5, 5);
10933 int rd
= extract32(insn
, 0, 5);
10935 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
;
10936 CryptoThreeOpEnvFn
*genfn
;
10938 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
10940 unallocated_encoding(s
);
10945 case 0x4: /* AESE */
10947 genfn
= gen_helper_crypto_aese
;
10949 case 0x6: /* AESMC */
10951 genfn
= gen_helper_crypto_aesmc
;
10953 case 0x5: /* AESD */
10955 genfn
= gen_helper_crypto_aese
;
10957 case 0x7: /* AESIMC */
10959 genfn
= gen_helper_crypto_aesmc
;
10962 unallocated_encoding(s
);
10966 if (!fp_access_check(s
)) {
10970 /* Note that we convert the Vx register indexes into the
10971 * index within the vfp.regs[] array, so we can share the
10972 * helper with the AArch32 instructions.
10974 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10975 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10976 tcg_decrypt
= tcg_const_i32(decrypt
);
10978 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
);
10980 tcg_temp_free_i32(tcg_rd_regno
);
10981 tcg_temp_free_i32(tcg_rn_regno
);
10982 tcg_temp_free_i32(tcg_decrypt
);
10985 /* Crypto three-reg SHA
10986 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10987 * +-----------------+------+---+------+---+--------+-----+------+------+
10988 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
10989 * +-----------------+------+---+------+---+--------+-----+------+------+
10991 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
10993 int size
= extract32(insn
, 22, 2);
10994 int opcode
= extract32(insn
, 12, 3);
10995 int rm
= extract32(insn
, 16, 5);
10996 int rn
= extract32(insn
, 5, 5);
10997 int rd
= extract32(insn
, 0, 5);
10998 CryptoThreeOpEnvFn
*genfn
;
10999 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
;
11000 int feature
= ARM_FEATURE_V8_SHA256
;
11003 unallocated_encoding(s
);
11008 case 0: /* SHA1C */
11009 case 1: /* SHA1P */
11010 case 2: /* SHA1M */
11011 case 3: /* SHA1SU0 */
11013 feature
= ARM_FEATURE_V8_SHA1
;
11015 case 4: /* SHA256H */
11016 genfn
= gen_helper_crypto_sha256h
;
11018 case 5: /* SHA256H2 */
11019 genfn
= gen_helper_crypto_sha256h2
;
11021 case 6: /* SHA256SU1 */
11022 genfn
= gen_helper_crypto_sha256su1
;
11025 unallocated_encoding(s
);
11029 if (!arm_dc_feature(s
, feature
)) {
11030 unallocated_encoding(s
);
11034 if (!fp_access_check(s
)) {
11038 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
11039 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
11040 tcg_rm_regno
= tcg_const_i32(rm
<< 1);
11043 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
);
11045 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
11047 gen_helper_crypto_sha1_3reg(cpu_env
, tcg_rd_regno
,
11048 tcg_rn_regno
, tcg_rm_regno
, tcg_opcode
);
11049 tcg_temp_free_i32(tcg_opcode
);
11052 tcg_temp_free_i32(tcg_rd_regno
);
11053 tcg_temp_free_i32(tcg_rn_regno
);
11054 tcg_temp_free_i32(tcg_rm_regno
);
11057 /* Crypto two-reg SHA
11058 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
11059 * +-----------------+------+-----------+--------+-----+------+------+
11060 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
11061 * +-----------------+------+-----------+--------+-----+------+------+
11063 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
11065 int size
= extract32(insn
, 22, 2);
11066 int opcode
= extract32(insn
, 12, 5);
11067 int rn
= extract32(insn
, 5, 5);
11068 int rd
= extract32(insn
, 0, 5);
11069 CryptoTwoOpEnvFn
*genfn
;
11071 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
;
11074 unallocated_encoding(s
);
11079 case 0: /* SHA1H */
11080 feature
= ARM_FEATURE_V8_SHA1
;
11081 genfn
= gen_helper_crypto_sha1h
;
11083 case 1: /* SHA1SU1 */
11084 feature
= ARM_FEATURE_V8_SHA1
;
11085 genfn
= gen_helper_crypto_sha1su1
;
11087 case 2: /* SHA256SU0 */
11088 feature
= ARM_FEATURE_V8_SHA256
;
11089 genfn
= gen_helper_crypto_sha256su0
;
11092 unallocated_encoding(s
);
11096 if (!arm_dc_feature(s
, feature
)) {
11097 unallocated_encoding(s
);
11101 if (!fp_access_check(s
)) {
11105 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
11106 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
11108 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
);
11110 tcg_temp_free_i32(tcg_rd_regno
);
11111 tcg_temp_free_i32(tcg_rn_regno
);
11114 /* C3.6 Data processing - SIMD, inc Crypto
11116 * As the decode gets a little complex we are using a table based
11117 * approach for this part of the decode.
11119 static const AArch64DecodeTable data_proc_simd
[] = {
11120 /* pattern , mask , fn */
11121 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
11122 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
11123 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
11124 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
11125 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
11126 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
11127 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
11128 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
11129 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
11130 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
11131 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
11132 { 0x2e000000, 0xbf208400, disas_simd_ext
},
11133 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
11134 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
11135 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
11136 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
11137 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
11138 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
11139 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
11140 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
11141 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
11142 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
11143 { 0x00000000, 0x00000000, NULL
}
11146 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
11148 /* Note that this is called with all non-FP cases from
11149 * table C3-6 so it must UNDEF for entries not specifically
11150 * allocated to instructions in that table.
11152 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
11156 unallocated_encoding(s
);
11160 /* C3.6 Data processing - SIMD and floating point */
11161 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
11163 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
11164 disas_data_proc_fp(s
, insn
);
11166 /* SIMD, including crypto */
11167 disas_data_proc_simd(s
, insn
);
11171 /* C3.1 A64 instruction index by encoding */
11172 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
11176 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
11180 s
->fp_access_checked
= false;
11182 switch (extract32(insn
, 25, 4)) {
11183 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
11184 unallocated_encoding(s
);
11186 case 0x8: case 0x9: /* Data processing - immediate */
11187 disas_data_proc_imm(s
, insn
);
11189 case 0xa: case 0xb: /* Branch, exception generation and system insns */
11190 disas_b_exc_sys(s
, insn
);
11195 case 0xe: /* Loads and stores */
11196 disas_ldst(s
, insn
);
11199 case 0xd: /* Data processing - register */
11200 disas_data_proc_reg(s
, insn
);
11203 case 0xf: /* Data processing - SIMD and floating point */
11204 disas_data_proc_simd_fp(s
, insn
);
11207 assert(FALSE
); /* all 15 cases should be handled above */
11211 /* if we allocated any temporaries, free them here */
11215 static int aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
11216 CPUState
*cpu
, int max_insns
)
11218 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11219 CPUARMState
*env
= cpu
->env_ptr
;
11220 ARMCPU
*arm_cpu
= arm_env_get_cpu(env
);
11223 dc
->pc
= dc
->base
.pc_first
;
11227 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
11228 * there is no secure EL1, so we route exceptions to EL3.
11230 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
11231 !arm_el_is_aa64(env
, 3);
11234 dc
->be_data
= ARM_TBFLAG_BE_DATA(dc
->base
.tb
->flags
) ? MO_BE
: MO_LE
;
11235 dc
->condexec_mask
= 0;
11236 dc
->condexec_cond
= 0;
11237 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, ARM_TBFLAG_MMUIDX(dc
->base
.tb
->flags
));
11238 dc
->tbi0
= ARM_TBFLAG_TBI0(dc
->base
.tb
->flags
);
11239 dc
->tbi1
= ARM_TBFLAG_TBI1(dc
->base
.tb
->flags
);
11240 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
11241 #if !defined(CONFIG_USER_ONLY)
11242 dc
->user
= (dc
->current_el
== 0);
11244 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(dc
->base
.tb
->flags
);
11246 dc
->vec_stride
= 0;
11247 dc
->cp_regs
= arm_cpu
->cp_regs
;
11248 dc
->features
= env
->features
;
11250 /* Single step state. The code-generation logic here is:
11252 * generate code with no special handling for single-stepping (except
11253 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
11254 * this happens anyway because those changes are all system register or
11256 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
11257 * emit code for one insn
11258 * emit code to clear PSTATE.SS
11259 * emit code to generate software step exception for completed step
11260 * end TB (as usual for having generated an exception)
11261 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
11262 * emit code to generate a software step exception
11265 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(dc
->base
.tb
->flags
);
11266 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(dc
->base
.tb
->flags
);
11267 dc
->is_ldex
= false;
11268 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
11270 /* Bound the number of insns to execute to those left on the page. */
11271 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
11273 /* If architectural single step active, limit to 1. */
11274 if (dc
->ss_active
) {
11277 max_insns
= MIN(max_insns
, bound
);
11279 init_tmp_a64_array(dc
);
11284 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
11286 tcg_clear_temp_count();
11289 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
11291 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11293 tcg_gen_insn_start(dc
->pc
, 0, 0);
11294 dc
->insn_start
= tcg_last_op();
11297 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
11298 const CPUBreakpoint
*bp
)
11300 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11302 if (bp
->flags
& BP_CPU
) {
11303 gen_a64_set_pc_im(dc
->pc
);
11304 gen_helper_check_breakpoints(cpu_env
);
11305 /* End the TB early; it likely won't be executed */
11306 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
11308 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
11309 /* The address covered by the breakpoint must be
11310 included in [tb->pc, tb->pc + tb->size) in order
11311 to for it to be properly cleared -- thus we
11312 increment the PC here so that the logic setting
11313 tb->size below does the right thing. */
11315 dc
->base
.is_jmp
= DISAS_NORETURN
;
11321 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
11323 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11324 CPUARMState
*env
= cpu
->env_ptr
;
11326 if (dc
->ss_active
&& !dc
->pstate_ss
) {
11327 /* Singlestep state is Active-pending.
11328 * If we're in this state at the start of a TB then either
11329 * a) we just took an exception to an EL which is being debugged
11330 * and this is the first insn in the exception handler
11331 * b) debug exceptions were masked and we just unmasked them
11332 * without changing EL (eg by clearing PSTATE.D)
11333 * In either case we're going to take a swstep exception in the
11334 * "did not step an insn" case, and so the syndrome ISV and EX
11335 * bits should be zero.
11337 assert(dc
->base
.num_insns
== 1);
11338 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
11339 default_exception_el(dc
));
11340 dc
->base
.is_jmp
= DISAS_NORETURN
;
11342 disas_a64_insn(env
, dc
);
11345 dc
->base
.pc_next
= dc
->pc
;
11346 translator_loop_temp_check(&dc
->base
);
11349 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
11351 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11353 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
11354 /* Note that this means single stepping WFI doesn't halt the CPU.
11355 * For conditional branch insns this is harmless unreachable code as
11356 * gen_goto_tb() has already handled emitting the debug exception
11357 * (and thus a tb-jump is not possible when singlestepping).
11359 switch (dc
->base
.is_jmp
) {
11361 gen_a64_set_pc_im(dc
->pc
);
11365 if (dc
->base
.singlestep_enabled
) {
11366 gen_exception_internal(EXCP_DEBUG
);
11368 gen_step_complete_exception(dc
);
11371 case DISAS_NORETURN
:
11375 switch (dc
->base
.is_jmp
) {
11377 case DISAS_TOO_MANY
:
11378 gen_goto_tb(dc
, 1, dc
->pc
);
11382 gen_a64_set_pc_im(dc
->pc
);
11385 tcg_gen_lookup_and_goto_ptr();
11388 tcg_gen_exit_tb(0);
11390 case DISAS_NORETURN
:
11394 gen_a64_set_pc_im(dc
->pc
);
11395 gen_helper_wfe(cpu_env
);
11398 gen_a64_set_pc_im(dc
->pc
);
11399 gen_helper_yield(cpu_env
);
11403 /* This is a special case because we don't want to just halt the CPU
11404 * if trying to debug across a WFI.
11406 TCGv_i32 tmp
= tcg_const_i32(4);
11408 gen_a64_set_pc_im(dc
->pc
);
11409 gen_helper_wfi(cpu_env
, tmp
);
11410 tcg_temp_free_i32(tmp
);
11411 /* The helper doesn't necessarily throw an exception, but we
11412 * must go back to the main loop to check for interrupts anyway.
11414 tcg_gen_exit_tb(0);
11420 /* Functions above can change dc->pc, so re-align db->pc_next */
11421 dc
->base
.pc_next
= dc
->pc
;
11424 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
11427 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11429 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
11430 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
11433 const TranslatorOps aarch64_translator_ops
= {
11434 .init_disas_context
= aarch64_tr_init_disas_context
,
11435 .tb_start
= aarch64_tr_tb_start
,
11436 .insn_start
= aarch64_tr_insn_start
,
11437 .breakpoint_check
= aarch64_tr_breakpoint_check
,
11438 .translate_insn
= aarch64_tr_translate_insn
,
11439 .tb_stop
= aarch64_tr_tb_stop
,
11440 .disas_log
= aarch64_tr_disas_log
,