hw/display/g364fb.c

   1 /*
   2  * QEMU G364 framebuffer Emulator.
   3  *
   4  * Copyright (c) 2007-2011 Herve Poussineau
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "hw/hw.h"
  21 #include "qemu/error-report.h"
  22 #include "ui/console.h"
  23 #include "ui/pixel_ops.h"
  24 #include "trace.h"
  25 #include "hw/sysbus.h"
  26
  27 typedef struct G364State {
  28     /* hardware */
  29     uint8_t *vram;
  30     uint32_t vram_size;
  31     qemu_irq irq;
  32     MemoryRegion mem_vram;
  33     MemoryRegion mem_ctrl;
  34     /* registers */
  35     uint8_t color_palette[256][3];
  36     uint8_t cursor_palette[3][3];
  37     uint16_t cursor[512];
  38     uint32_t cursor_position;
  39     uint32_t ctla;
  40     uint32_t top_of_screen;
  41     uint32_t width, height; /* in pixels */
  42     /* display refresh support */
  43     QemuConsole *con;
  44     int depth;
  45     int blanked;
  46 } G364State;
  47
  48 #define REG_BOOT     0x000000
  49 #define REG_DISPLAY  0x000118
  50 #define REG_VDISPLAY 0x000150
  51 #define REG_CTLA     0x000300
  52 #define REG_TOP      0x000400
  53 #define REG_CURS_PAL 0x000508
  54 #define REG_CURS_POS 0x000638
  55 #define REG_CLR_PAL  0x000800
  56 #define REG_CURS_PAT 0x001000
  57 #define REG_RESET    0x100000
  58
  59 #define CTLA_FORCE_BLANK 0x00000400
  60 #define CTLA_NO_CURSOR   0x00800000
  61
  62 #define G364_PAGE_SIZE 4096
  63
  64 static inline int check_dirty(G364State *s, ram_addr_t page)
  65 {
  66     return memory_region_get_dirty(&s->mem_vram, page, G364_PAGE_SIZE,
  67                                    DIRTY_MEMORY_VGA);
  68 }
  69
  70 static inline void reset_dirty(G364State *s,
  71                                ram_addr_t page_min, ram_addr_t page_max)
  72 {
  73     memory_region_reset_dirty(&s->mem_vram,
  74                               page_min,
  75                               page_max + G364_PAGE_SIZE - page_min - 1,
  76                               DIRTY_MEMORY_VGA);
  77 }
  78
  79 static void g364fb_draw_graphic8(G364State *s)
  80 {
  81     DisplaySurface *surface = qemu_console_surface(s->con);
  82     int i, w;
  83     uint8_t *vram;
  84     uint8_t *data_display, *dd;
  85     ram_addr_t page, page_min, page_max;
  86     int x, y;
  87     int xmin, xmax;
  88     int ymin, ymax;
  89     int xcursor, ycursor;
  90     unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b);
  91
  92     switch (surface_bits_per_pixel(surface)) {
  93         case 8:
  94             rgb_to_pixel = rgb_to_pixel8;
  95             w = 1;
  96             break;
  97         case 15:
  98             rgb_to_pixel = rgb_to_pixel15;
  99             w = 2;
 100             break;
 101         case 16:
 102             rgb_to_pixel = rgb_to_pixel16;
 103             w = 2;
 104             break;
 105         case 32:
 106             rgb_to_pixel = rgb_to_pixel32;
 107             w = 4;
 108             break;
 109         default:
 110             hw_error("g364: unknown host depth %d",
 111                      surface_bits_per_pixel(surface));
 112             return;
 113     }
 114
 115     page = 0;
 116     page_min = (ram_addr_t)-1;
 117     page_max = 0;
 118
 119     x = y = 0;
 120     xmin = s->width;
 121     xmax = 0;
 122     ymin = s->height;
 123     ymax = 0;
 124
 125     if (!(s->ctla & CTLA_NO_CURSOR)) {
 126         xcursor = s->cursor_position >> 12;
 127         ycursor = s->cursor_position & 0xfff;
 128     } else {
 129         xcursor = ycursor = -65;
 130     }
 131
 132     vram = s->vram + s->top_of_screen;
 133     /* XXX: out of range in vram? */
 134     data_display = dd = surface_data(surface);
 135     while (y < s->height) {
 136         if (check_dirty(s, page)) {
 137             if (y < ymin)
 138                 ymin = ymax = y;
 139             if (page_min == (ram_addr_t)-1)
 140                 page_min = page;
 141             page_max = page;
 142             if (x < xmin)
 143                 xmin = x;
 144             for (i = 0; i < G364_PAGE_SIZE; i++) {
 145                 uint8_t index;
 146                 unsigned int color;
 147                 if (unlikely((y >= ycursor && y < ycursor + 64) &&
 148                     (x >= xcursor && x < xcursor + 64))) {
 149                     /* pointer area */
 150                     int xdiff = x - xcursor;
 151                     uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8];
 152                     int op = (curs >> ((xdiff & 7) * 2)) & 3;
 153                     if (likely(op == 0)) {
 154                         /* transparent */
 155                         index = *vram;
 156                         color = (*rgb_to_pixel)(
 157                             s->color_palette[index][0],
 158                             s->color_palette[index][1],
 159                             s->color_palette[index][2]);
 160                     } else {
 161                         /* get cursor color */
 162                         index = op - 1;
 163                         color = (*rgb_to_pixel)(
 164                             s->cursor_palette[index][0],
 165                             s->cursor_palette[index][1],
 166                             s->cursor_palette[index][2]);
 167                     }
 168                 } else {
 169                     /* normal area */
 170                     index = *vram;
 171                     color = (*rgb_to_pixel)(
 172                         s->color_palette[index][0],
 173                         s->color_palette[index][1],
 174                         s->color_palette[index][2]);
 175                 }
 176                 memcpy(dd, &color, w);
 177                 dd += w;
 178                 x++;
 179                 vram++;
 180                 if (x == s->width) {
 181                     xmax = s->width - 1;
 182                     y++;
 183                     if (y == s->height) {
 184                         ymax = s->height - 1;
 185                         goto done;
 186                     }
 187                     data_display = dd = data_display + surface_stride(surface);
 188                     xmin = 0;
 189                     x = 0;
 190                 }
 191             }
 192             if (x > xmax)
 193                 xmax = x;
 194             if (y > ymax)
 195                 ymax = y;
 196         } else {
 197             int dy;
 198             if (page_min != (ram_addr_t)-1) {
 199                 reset_dirty(s, page_min, page_max);
 200                 page_min = (ram_addr_t)-1;
 201                 page_max = 0;
 202                 dpy_gfx_update(s->con, xmin, ymin,
 203                                xmax - xmin + 1, ymax - ymin + 1);
 204                 xmin = s->width;
 205                 xmax = 0;
 206                 ymin = s->height;
 207                 ymax = 0;
 208             }
 209             x += G364_PAGE_SIZE;
 210             dy = x / s->width;
 211             x = x % s->width;
 212             y += dy;
 213             vram += G364_PAGE_SIZE;
 214             data_display += dy * surface_stride(surface);
 215             dd = data_display + x * w;
 216         }
 217         page += G364_PAGE_SIZE;
 218     }
 219
 220 done:
 221     if (page_min != (ram_addr_t)-1) {
 222         dpy_gfx_update(s->con, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
 223         reset_dirty(s, page_min, page_max);
 224     }
 225 }
 226
 227 static void g364fb_draw_blank(G364State *s)
 228 {
 229     DisplaySurface *surface = qemu_console_surface(s->con);
 230     int i, w;
 231     uint8_t *d;
 232
 233     if (s->blanked) {
 234         /* Screen is already blank. No need to redraw it */
 235         return;
 236     }
 237
 238     w = s->width * surface_bytes_per_pixel(surface);
 239     d = surface_data(surface);
 240     for (i = 0; i < s->height; i++) {
 241         memset(d, 0, w);
 242         d += surface_stride(surface);
 243     }
 244
 245     dpy_gfx_update(s->con, 0, 0, s->width, s->height);
 246     s->blanked = 1;
 247 }
 248
 249 static void g364fb_update_display(void *opaque)
 250 {
 251     G364State *s = opaque;
 252     DisplaySurface *surface = qemu_console_surface(s->con);
 253
 254     qemu_flush_coalesced_mmio_buffer();
 255
 256     if (s->width == 0 || s->height == 0)
 257         return;
 258
 259     if (s->width != surface_width(surface) ||
 260         s->height != surface_height(surface)) {
 261         qemu_console_resize(s->con, s->width, s->height);
 262     }
 263
 264     memory_region_sync_dirty_bitmap(&s->mem_vram);
 265     if (s->ctla & CTLA_FORCE_BLANK) {
 266         g364fb_draw_blank(s);
 267     } else if (s->depth == 8) {
 268         g364fb_draw_graphic8(s);
 269     } else {
 270         error_report("g364: unknown guest depth %d", s->depth);
 271     }
 272
 273     qemu_irq_raise(s->irq);
 274 }
 275
 276 static inline void g364fb_invalidate_display(void *opaque)
 277 {
 278     G364State *s = opaque;
 279
 280     s->blanked = 0;
 281     memory_region_set_dirty(&s->mem_vram, 0, s->vram_size);
 282 }
 283
 284 static void g364fb_reset(G364State *s)
 285 {
 286     qemu_irq_lower(s->irq);
 287
 288     memset(s->color_palette, 0, sizeof(s->color_palette));
 289     memset(s->cursor_palette, 0, sizeof(s->cursor_palette));
 290     memset(s->cursor, 0, sizeof(s->cursor));
 291     s->cursor_position = 0;
 292     s->ctla = 0;
 293     s->top_of_screen = 0;
 294     s->width = s->height = 0;
 295     memset(s->vram, 0, s->vram_size);
 296     g364fb_invalidate_display(s);
 297 }
 298
 299 /* called for accesses to io ports */
 300 static uint64_t g364fb_ctrl_read(void *opaque,
 301                                  hwaddr addr,
 302                                  unsigned int size)
 303 {
 304     G364State *s = opaque;
 305     uint32_t val;
 306
 307     if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
 308         /* cursor pattern */
 309         int idx = (addr - REG_CURS_PAT) >> 3;
 310         val = s->cursor[idx];
 311     } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
 312         /* cursor palette */
 313         int idx = (addr - REG_CURS_PAL) >> 3;
 314         val = ((uint32_t)s->cursor_palette[idx][0] << 16);
 315         val |= ((uint32_t)s->cursor_palette[idx][1] << 8);
 316         val |= ((uint32_t)s->cursor_palette[idx][2] << 0);
 317     } else {
 318         switch (addr) {
 319             case REG_DISPLAY:
 320                 val = s->width / 4;
 321                 break;
 322             case REG_VDISPLAY:
 323                 val = s->height * 2;
 324                 break;
 325             case REG_CTLA:
 326                 val = s->ctla;
 327                 break;
 328             default:
 329             {
 330                 error_report("g364: invalid read at [" TARGET_FMT_plx "]",
 331                              addr);
 332                 val = 0;
 333                 break;
 334             }
 335         }
 336     }
 337
 338     trace_g364fb_read(addr, val);
 339
 340     return val;
 341 }
 342
 343 static void g364fb_update_depth(G364State *s)
 344 {
 345     static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 };
 346     s->depth = depths[(s->ctla & 0x00700000) >> 20];
 347 }
 348
 349 static void g364_invalidate_cursor_position(G364State *s)
 350 {
 351     DisplaySurface *surface = qemu_console_surface(s->con);
 352     int ymin, ymax, start, end;
 353
 354     /* invalidate only near the cursor */
 355     ymin = s->cursor_position & 0xfff;
 356     ymax = MIN(s->height, ymin + 64);
 357     start = ymin * surface_stride(surface);
 358     end = (ymax + 1) * surface_stride(surface);
 359
 360     memory_region_set_dirty(&s->mem_vram, start, end - start);
 361 }
 362
 363 static void g364fb_ctrl_write(void *opaque,
 364                               hwaddr addr,
 365                               uint64_t val,
 366                               unsigned int size)
 367 {
 368     G364State *s = opaque;
 369
 370     trace_g364fb_write(addr, val);
 371
 372     if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) {
 373         /* color palette */
 374         int idx = (addr - REG_CLR_PAL) >> 3;
 375         s->color_palette[idx][0] = (val >> 16) & 0xff;
 376         s->color_palette[idx][1] = (val >> 8) & 0xff;
 377         s->color_palette[idx][2] = val & 0xff;
 378         g364fb_invalidate_display(s);
 379     } else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
 380         /* cursor pattern */
 381         int idx = (addr - REG_CURS_PAT) >> 3;
 382         s->cursor[idx] = val;
 383         g364fb_invalidate_display(s);
 384     } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
 385         /* cursor palette */
 386         int idx = (addr - REG_CURS_PAL) >> 3;
 387         s->cursor_palette[idx][0] = (val >> 16) & 0xff;
 388         s->cursor_palette[idx][1] = (val >> 8) & 0xff;
 389         s->cursor_palette[idx][2] = val & 0xff;
 390         g364fb_invalidate_display(s);
 391     } else {
 392         switch (addr) {
 393         case REG_BOOT: /* Boot timing */
 394         case 0x00108: /* Line timing: half sync */
 395         case 0x00110: /* Line timing: back porch */
 396         case 0x00120: /* Line timing: short display */
 397         case 0x00128: /* Frame timing: broad pulse */
 398         case 0x00130: /* Frame timing: v sync */
 399         case 0x00138: /* Frame timing: v preequalise */
 400         case 0x00140: /* Frame timing: v postequalise */
 401         case 0x00148: /* Frame timing: v blank */
 402         case 0x00158: /* Line timing: line time */
 403         case 0x00160: /* Frame store: line start */
 404         case 0x00168: /* vram cycle: mem init */
 405         case 0x00170: /* vram cycle: transfer delay */
 406         case 0x00200: /* vram cycle: mask register */
 407             /* ignore */
 408             break;
 409         case REG_TOP:
 410             s->top_of_screen = val;
 411             g364fb_invalidate_display(s);
 412             break;
 413         case REG_DISPLAY:
 414             s->width = val * 4;
 415             break;
 416         case REG_VDISPLAY:
 417             s->height = val / 2;
 418             break;
 419         case REG_CTLA:
 420             s->ctla = val;
 421             g364fb_update_depth(s);
 422             g364fb_invalidate_display(s);
 423             break;
 424         case REG_CURS_POS:
 425             g364_invalidate_cursor_position(s);
 426             s->cursor_position = val;
 427             g364_invalidate_cursor_position(s);
 428             break;
 429         case REG_RESET:
 430             g364fb_reset(s);
 431             break;
 432         default:
 433             error_report("g364: invalid write of 0x%" PRIx64
 434                          " at [" TARGET_FMT_plx "]", val, addr);
 435             break;
 436         }
 437     }
 438     qemu_irq_lower(s->irq);
 439 }
 440
 441 static const MemoryRegionOps g364fb_ctrl_ops = {
 442     .read = g364fb_ctrl_read,
 443     .write = g364fb_ctrl_write,
 444     .endianness = DEVICE_LITTLE_ENDIAN,
 445     .impl.min_access_size = 4,
 446     .impl.max_access_size = 4,
 447 };
 448
 449 static int g364fb_post_load(void *opaque, int version_id)
 450 {
 451     G364State *s = opaque;
 452
 453     /* force refresh */
 454     g364fb_update_depth(s);
 455     g364fb_invalidate_display(s);
 456
 457     return 0;
 458 }
 459
 460 static const VMStateDescription vmstate_g364fb = {
 461     .name = "g364fb",
 462     .version_id = 1,
 463     .minimum_version_id = 1,
 464     .post_load = g364fb_post_load,
 465     .fields = (VMStateField[]) {
 466         VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, 0, vram_size),
 467         VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3),
 468         VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9),
 469         VMSTATE_UINT16_ARRAY(cursor, G364State, 512),
 470         VMSTATE_UINT32(cursor_position, G364State),
 471         VMSTATE_UINT32(ctla, G364State),
 472         VMSTATE_UINT32(top_of_screen, G364State),
 473         VMSTATE_UINT32(width, G364State),
 474         VMSTATE_UINT32(height, G364State),
 475         VMSTATE_END_OF_LIST()
 476     }
 477 };
 478
 479 static const GraphicHwOps g364fb_ops = {
 480     .invalidate  = g364fb_invalidate_display,
 481     .gfx_update  = g364fb_update_display,
 482 };
 483
 484 static void g364fb_init(DeviceState *dev, G364State *s)
 485 {
 486     s->vram = g_malloc0(s->vram_size);
 487
 488     s->con = graphic_console_init(dev, 0, &g364fb_ops, s);
 489
 490     memory_region_init_io(&s->mem_ctrl, NULL, &g364fb_ctrl_ops, s, "ctrl", 0x180000);
 491     memory_region_init_ram_ptr(&s->mem_vram, NULL, "vram",
 492                                s->vram_size, s->vram);
 493     vmstate_register_ram(&s->mem_vram, dev);
 494     memory_region_set_log(&s->mem_vram, true, DIRTY_MEMORY_VGA);
 495 }
 496
 497 #define TYPE_G364 "sysbus-g364"
 498 #define G364(obj) OBJECT_CHECK(G364SysBusState, (obj), TYPE_G364)
 499
 500 typedef struct {
 501     SysBusDevice parent_obj;
 502
 503     G364State g364;
 504 } G364SysBusState;
 505
 506 static int g364fb_sysbus_init(SysBusDevice *sbd)
 507 {
 508     DeviceState *dev = DEVICE(sbd);
 509     G364SysBusState *sbs = G364(dev);
 510     G364State *s = &sbs->g364;
 511
 512     g364fb_init(dev, s);
 513     sysbus_init_irq(sbd, &s->irq);
 514     sysbus_init_mmio(sbd, &s->mem_ctrl);
 515     sysbus_init_mmio(sbd, &s->mem_vram);
 516
 517     return 0;
 518 }
 519
 520 static void g364fb_sysbus_reset(DeviceState *d)
 521 {
 522     G364SysBusState *s = G364(d);
 523
 524     g364fb_reset(&s->g364);
 525 }
 526
 527 static Property g364fb_sysbus_properties[] = {
 528     DEFINE_PROP_UINT32("vram_size", G364SysBusState, g364.vram_size,
 529     8 * 1024 * 1024),
 530     DEFINE_PROP_END_OF_LIST(),
 531 };
 532
 533 static void g364fb_sysbus_class_init(ObjectClass *klass, void *data)
 534 {
 535     DeviceClass *dc = DEVICE_CLASS(klass);
 536     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 537
 538     k->init = g364fb_sysbus_init;
 539     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
 540     dc->desc = "G364 framebuffer";
 541     dc->reset = g364fb_sysbus_reset;
 542     dc->vmsd = &vmstate_g364fb;
 543     dc->props = g364fb_sysbus_properties;
 544 }
 545
 546 static const TypeInfo g364fb_sysbus_info = {
 547     .name          = TYPE_G364,
 548     .parent        = TYPE_SYS_BUS_DEVICE,
 549     .instance_size = sizeof(G364SysBusState),
 550     .class_init    = g364fb_sysbus_class_init,
 551 };
 552
 553 static void g364fb_register_types(void)
 554 {
 555     type_register_static(&g364fb_sysbus_info);
 556 }
 557
 558 type_init(g364fb_register_types)