target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "hw/loader.h"
  27 #endif
  28 #include "hw/arm/arm.h"
  29 #include "sysemu/sysemu.h"
  30 #include "sysemu/kvm.h"
  31 #include "kvm_arm.h"
  32
  33 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  34 {
  35     ARMCPU *cpu = ARM_CPU(cs);
  36
  37     cpu->env.regs[15] = value;
  38 }
  39
  40 static bool arm_cpu_has_work(CPUState *cs)
  41 {
  42     ARMCPU *cpu = ARM_CPU(cs);
  43
  44     return !cpu->powered_off
  45         && cs->interrupt_request &
  46         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  47          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  48          | CPU_INTERRUPT_EXITTB);
  49 }
  50
  51 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  52 {
  53     /* Reset a single ARMCPRegInfo register */
  54     ARMCPRegInfo *ri = value;
  55     ARMCPU *cpu = opaque;
  56
  57     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
  58         return;
  59     }
  60
  61     if (ri->resetfn) {
  62         ri->resetfn(&cpu->env, ri);
  63         return;
  64     }
  65
  66     /* A zero offset is never possible as it would be regs[0]
  67      * so we use it to indicate that reset is being handled elsewhere.
  68      * This is basically only used for fields in non-core coprocessors
  69      * (like the pxa2xx ones).
  70      */
  71     if (!ri->fieldoffset) {
  72         return;
  73     }
  74
  75     if (cpreg_field_is_64bit(ri)) {
  76         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  77     } else {
  78         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  79     }
  80 }
  81
  82 static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
  83 {
  84     /* Purely an assertion check: we've already done reset once,
  85      * so now check that running the reset for the cpreg doesn't
  86      * change its value. This traps bugs where two different cpregs
  87      * both try to reset the same state field but to different values.
  88      */
  89     ARMCPRegInfo *ri = value;
  90     ARMCPU *cpu = opaque;
  91     uint64_t oldvalue, newvalue;
  92
  93     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
  94         return;
  95     }
  96
  97     oldvalue = read_raw_cp_reg(&cpu->env, ri);
  98     cp_reg_reset(key, value, opaque);
  99     newvalue = read_raw_cp_reg(&cpu->env, ri);
 100     assert(oldvalue == newvalue);
 101 }
 102
 103 /* CPUClass::reset() */
 104 static void arm_cpu_reset(CPUState *s)
 105 {
 106     ARMCPU *cpu = ARM_CPU(s);
 107     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
 108     CPUARMState *env = &cpu->env;
 109
 110     acc->parent_reset(s);
 111
 112     memset(env, 0, offsetof(CPUARMState, features));
 113     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
 114     g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
 115
 116     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
 117     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
 118     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
 119     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
 120
 121     cpu->powered_off = cpu->start_powered_off;
 122     s->halted = cpu->start_powered_off;
 123
 124     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 125         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 126     }
 127
 128     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 129         /* 64 bit CPUs always start in 64 bit mode */
 130         env->aarch64 = 1;
 131 #if defined(CONFIG_USER_ONLY)
 132         env->pstate = PSTATE_MODE_EL0t;
 133         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 134         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 135         /* and to the FP/Neon instructions */
 136         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
 137 #else
 138         /* Reset into the highest available EL */
 139         if (arm_feature(env, ARM_FEATURE_EL3)) {
 140             env->pstate = PSTATE_MODE_EL3h;
 141         } else if (arm_feature(env, ARM_FEATURE_EL2)) {
 142             env->pstate = PSTATE_MODE_EL2h;
 143         } else {
 144             env->pstate = PSTATE_MODE_EL1h;
 145         }
 146         env->pc = cpu->rvbar;
 147 #endif
 148     } else {
 149 #if defined(CONFIG_USER_ONLY)
 150         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 151         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
 152 #endif
 153     }
 154
 155 #if defined(CONFIG_USER_ONLY)
 156     env->uncached_cpsr = ARM_CPU_MODE_USR;
 157     /* For user mode we must enable access to coprocessors */
 158     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 159     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 160         env->cp15.c15_cpar = 3;
 161     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 162         env->cp15.c15_cpar = 1;
 163     }
 164 #else
 165     /* SVC mode with interrupts disabled.  */
 166     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 167     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 168     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 169      * clear at reset. Initial SP and PC are loaded from ROM.
 170      */
 171     if (IS_M(env)) {
 172         uint32_t initial_msp; /* Loaded from 0x0 */
 173         uint32_t initial_pc; /* Loaded from 0x4 */
 174         uint8_t *rom;
 175
 176         env->daif &= ~PSTATE_I;
 177         rom = rom_ptr(0);
 178         if (rom) {
 179             /* Address zero is covered by ROM which hasn't yet been
 180              * copied into physical memory.
 181              */
 182             initial_msp = ldl_p(rom);
 183             initial_pc = ldl_p(rom + 4);
 184         } else {
 185             /* Address zero not covered by a ROM blob, or the ROM blob
 186              * is in non-modifiable memory and this is a second reset after
 187              * it got copied into memory. In the latter case, rom_ptr
 188              * will return a NULL pointer and we should use ldl_phys instead.
 189              */
 190             initial_msp = ldl_phys(s->as, 0);
 191             initial_pc = ldl_phys(s->as, 4);
 192         }
 193
 194         env->regs[13] = initial_msp & 0xFFFFFFFC;
 195         env->regs[15] = initial_pc & ~1;
 196         env->thumb = initial_pc & 1;
 197     }
 198
 199     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 200      * executing as AArch32 then check if highvecs are enabled and
 201      * adjust the PC accordingly.
 202      */
 203     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 204         env->regs[15] = 0xFFFF0000;
 205     }
 206
 207     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 208 #endif
 209     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 210     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 211     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 212     set_float_detect_tininess(float_tininess_before_rounding,
 213                               &env->vfp.fp_status);
 214     set_float_detect_tininess(float_tininess_before_rounding,
 215                               &env->vfp.standard_fp_status);
 216     tlb_flush(s, 1);
 217
 218 #ifndef CONFIG_USER_ONLY
 219     if (kvm_enabled()) {
 220         kvm_arm_reset_vcpu(cpu);
 221     }
 222 #endif
 223
 224     hw_breakpoint_update_all(cpu);
 225     hw_watchpoint_update_all(cpu);
 226 }
 227
 228 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 229 {
 230     CPUClass *cc = CPU_GET_CLASS(cs);
 231     CPUARMState *env = cs->env_ptr;
 232     uint32_t cur_el = arm_current_el(env);
 233     bool secure = arm_is_secure(env);
 234     uint32_t target_el;
 235     uint32_t excp_idx;
 236     bool ret = false;
 237
 238     if (interrupt_request & CPU_INTERRUPT_FIQ) {
 239         excp_idx = EXCP_FIQ;
 240         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 241         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 242             cs->exception_index = excp_idx;
 243             env->exception.target_el = target_el;
 244             cc->do_interrupt(cs);
 245             ret = true;
 246         }
 247     }
 248     if (interrupt_request & CPU_INTERRUPT_HARD) {
 249         excp_idx = EXCP_IRQ;
 250         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 251         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 252             cs->exception_index = excp_idx;
 253             env->exception.target_el = target_el;
 254             cc->do_interrupt(cs);
 255             ret = true;
 256         }
 257     }
 258     if (interrupt_request & CPU_INTERRUPT_VIRQ) {
 259         excp_idx = EXCP_VIRQ;
 260         target_el = 1;
 261         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 262             cs->exception_index = excp_idx;
 263             env->exception.target_el = target_el;
 264             cc->do_interrupt(cs);
 265             ret = true;
 266         }
 267     }
 268     if (interrupt_request & CPU_INTERRUPT_VFIQ) {
 269         excp_idx = EXCP_VFIQ;
 270         target_el = 1;
 271         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 272             cs->exception_index = excp_idx;
 273             env->exception.target_el = target_el;
 274             cc->do_interrupt(cs);
 275             ret = true;
 276         }
 277     }
 278
 279     return ret;
 280 }
 281
 282 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 283 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 284 {
 285     CPUClass *cc = CPU_GET_CLASS(cs);
 286     ARMCPU *cpu = ARM_CPU(cs);
 287     CPUARMState *env = &cpu->env;
 288     bool ret = false;
 289
 290
 291     if (interrupt_request & CPU_INTERRUPT_FIQ
 292         && !(env->daif & PSTATE_F)) {
 293         cs->exception_index = EXCP_FIQ;
 294         cc->do_interrupt(cs);
 295         ret = true;
 296     }
 297     /* ARMv7-M interrupt return works by loading a magic value
 298      * into the PC.  On real hardware the load causes the
 299      * return to occur.  The qemu implementation performs the
 300      * jump normally, then does the exception return when the
 301      * CPU tries to execute code at the magic address.
 302      * This will cause the magic PC value to be pushed to
 303      * the stack if an interrupt occurred at the wrong time.
 304      * We avoid this by disabling interrupts when
 305      * pc contains a magic address.
 306      */
 307     if (interrupt_request & CPU_INTERRUPT_HARD
 308         && !(env->daif & PSTATE_I)
 309         && (env->regs[15] < 0xfffffff0)) {
 310         cs->exception_index = EXCP_IRQ;
 311         cc->do_interrupt(cs);
 312         ret = true;
 313     }
 314     return ret;
 315 }
 316 #endif
 317
 318 #ifndef CONFIG_USER_ONLY
 319 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 320 {
 321     ARMCPU *cpu = opaque;
 322     CPUARMState *env = &cpu->env;
 323     CPUState *cs = CPU(cpu);
 324     static const int mask[] = {
 325         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 326         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 327         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 328         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 329     };
 330
 331     switch (irq) {
 332     case ARM_CPU_VIRQ:
 333     case ARM_CPU_VFIQ:
 334         assert(arm_feature(env, ARM_FEATURE_EL2));
 335         /* fall through */
 336     case ARM_CPU_IRQ:
 337     case ARM_CPU_FIQ:
 338         if (level) {
 339             cpu_interrupt(cs, mask[irq]);
 340         } else {
 341             cpu_reset_interrupt(cs, mask[irq]);
 342         }
 343         break;
 344     default:
 345         g_assert_not_reached();
 346     }
 347 }
 348
 349 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 350 {
 351 #ifdef CONFIG_KVM
 352     ARMCPU *cpu = opaque;
 353     CPUState *cs = CPU(cpu);
 354     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 355
 356     switch (irq) {
 357     case ARM_CPU_IRQ:
 358         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 359         break;
 360     case ARM_CPU_FIQ:
 361         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 362         break;
 363     default:
 364         g_assert_not_reached();
 365     }
 366     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 367     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 368 #endif
 369 }
 370
 371 static bool arm_cpu_is_big_endian(CPUState *cs)
 372 {
 373     ARMCPU *cpu = ARM_CPU(cs);
 374     CPUARMState *env = &cpu->env;
 375     int cur_el;
 376
 377     cpu_synchronize_state(cs);
 378
 379     /* In 32bit guest endianness is determined by looking at CPSR's E bit */
 380     if (!is_a64(env)) {
 381         return (env->uncached_cpsr & CPSR_E) ? 1 : 0;
 382     }
 383
 384     cur_el = arm_current_el(env);
 385
 386     if (cur_el == 0) {
 387         return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
 388     }
 389
 390     return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
 391 }
 392
 393 #endif
 394
 395 static inline void set_feature(CPUARMState *env, int feature)
 396 {
 397     env->features |= 1ULL << feature;
 398 }
 399
 400 static inline void unset_feature(CPUARMState *env, int feature)
 401 {
 402     env->features &= ~(1ULL << feature);
 403 }
 404
 405 static int
 406 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
 407 {
 408   return print_insn_arm(pc | 1, info);
 409 }
 410
 411 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
 412 {
 413     ARMCPU *ac = ARM_CPU(cpu);
 414     CPUARMState *env = &ac->env;
 415
 416     if (is_a64(env)) {
 417         /* We might not be compiled with the A64 disassembler
 418          * because it needs a C++ compiler. Leave print_insn
 419          * unset in this case to use the caller default behaviour.
 420          */
 421 #if defined(CONFIG_ARM_A64_DIS)
 422         info->print_insn = print_insn_arm_a64;
 423 #endif
 424     } else if (env->thumb) {
 425         info->print_insn = print_insn_thumb1;
 426     } else {
 427         info->print_insn = print_insn_arm;
 428     }
 429     if (env->bswap_code) {
 430 #ifdef TARGET_WORDS_BIGENDIAN
 431         info->endian = BFD_ENDIAN_LITTLE;
 432 #else
 433         info->endian = BFD_ENDIAN_BIG;
 434 #endif
 435     }
 436 }
 437
 438 #define ARM_CPUS_PER_CLUSTER 8
 439
 440 static void arm_cpu_initfn(Object *obj)
 441 {
 442     CPUState *cs = CPU(obj);
 443     ARMCPU *cpu = ARM_CPU(obj);
 444     static bool inited;
 445     uint32_t Aff1, Aff0;
 446
 447     cs->env_ptr = &cpu->env;
 448     cpu_exec_init(cs, &error_abort);
 449     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 450                                          g_free, g_free);
 451
 452     /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
 453      * We don't support setting cluster ID ([16..23]) (known as Aff2
 454      * in later ARM ARM versions), or any of the higher affinity level fields,
 455      * so these bits always RAZ.
 456      */
 457     Aff1 = cs->cpu_index / ARM_CPUS_PER_CLUSTER;
 458     Aff0 = cs->cpu_index % ARM_CPUS_PER_CLUSTER;
 459     cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0;
 460
 461 #ifndef CONFIG_USER_ONLY
 462     /* Our inbound IRQ and FIQ lines */
 463     if (kvm_enabled()) {
 464         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 465          * the same interface as non-KVM CPUs.
 466          */
 467         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 468     } else {
 469         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 470     }
 471
 472     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 473                                                 arm_gt_ptimer_cb, cpu);
 474     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 475                                                 arm_gt_vtimer_cb, cpu);
 476     cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 477                                                 arm_gt_htimer_cb, cpu);
 478     cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 479                                                 arm_gt_stimer_cb, cpu);
 480     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 481                        ARRAY_SIZE(cpu->gt_timer_outputs));
 482 #endif
 483
 484     /* DTB consumers generally don't in fact care what the 'compatible'
 485      * string is, so always provide some string and trust that a hypothetical
 486      * picky DTB consumer will also provide a helpful error message.
 487      */
 488     cpu->dtb_compatible = "qemu,unknown";
 489     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 490     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 491
 492     if (tcg_enabled()) {
 493         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 494         if (!inited) {
 495             inited = true;
 496             arm_translate_init();
 497         }
 498     }
 499 }
 500
 501 static Property arm_cpu_reset_cbar_property =
 502             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 503
 504 static Property arm_cpu_reset_hivecs_property =
 505             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 506
 507 static Property arm_cpu_rvbar_property =
 508             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 509
 510 static Property arm_cpu_has_el3_property =
 511             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 512
 513 static Property arm_cpu_has_mpu_property =
 514             DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
 515
 516 static Property arm_cpu_pmsav7_dregion_property =
 517             DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16);
 518
 519 static void arm_cpu_post_init(Object *obj)
 520 {
 521     ARMCPU *cpu = ARM_CPU(obj);
 522
 523     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 524         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 525         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 526                                  &error_abort);
 527     }
 528
 529     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 530         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 531                                  &error_abort);
 532     }
 533
 534     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 535         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 536                                  &error_abort);
 537     }
 538
 539     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
 540         /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
 541          * prevent "has_el3" from existing on CPUs which cannot support EL3.
 542          */
 543         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
 544                                  &error_abort);
 545     }
 546
 547     if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
 548         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
 549                                  &error_abort);
 550         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
 551             qdev_property_add_static(DEVICE(obj),
 552                                      &arm_cpu_pmsav7_dregion_property,
 553                                      &error_abort);
 554         }
 555     }
 556
 557 }
 558
 559 static void arm_cpu_finalizefn(Object *obj)
 560 {
 561     ARMCPU *cpu = ARM_CPU(obj);
 562     g_hash_table_destroy(cpu->cp_regs);
 563 }
 564
 565 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 566 {
 567     CPUState *cs = CPU(dev);
 568     ARMCPU *cpu = ARM_CPU(dev);
 569     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 570     CPUARMState *env = &cpu->env;
 571
 572     /* Some features automatically imply others: */
 573     if (arm_feature(env, ARM_FEATURE_V8)) {
 574         set_feature(env, ARM_FEATURE_V7);
 575         set_feature(env, ARM_FEATURE_ARM_DIV);
 576         set_feature(env, ARM_FEATURE_LPAE);
 577     }
 578     if (arm_feature(env, ARM_FEATURE_V7)) {
 579         set_feature(env, ARM_FEATURE_VAPA);
 580         set_feature(env, ARM_FEATURE_THUMB2);
 581         set_feature(env, ARM_FEATURE_MPIDR);
 582         if (!arm_feature(env, ARM_FEATURE_M)) {
 583             set_feature(env, ARM_FEATURE_V6K);
 584         } else {
 585             set_feature(env, ARM_FEATURE_V6);
 586         }
 587     }
 588     if (arm_feature(env, ARM_FEATURE_V6K)) {
 589         set_feature(env, ARM_FEATURE_V6);
 590         set_feature(env, ARM_FEATURE_MVFR);
 591     }
 592     if (arm_feature(env, ARM_FEATURE_V6)) {
 593         set_feature(env, ARM_FEATURE_V5);
 594         if (!arm_feature(env, ARM_FEATURE_M)) {
 595             set_feature(env, ARM_FEATURE_AUXCR);
 596         }
 597     }
 598     if (arm_feature(env, ARM_FEATURE_V5)) {
 599         set_feature(env, ARM_FEATURE_V4T);
 600     }
 601     if (arm_feature(env, ARM_FEATURE_M)) {
 602         set_feature(env, ARM_FEATURE_THUMB_DIV);
 603     }
 604     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 605         set_feature(env, ARM_FEATURE_THUMB_DIV);
 606     }
 607     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 608         set_feature(env, ARM_FEATURE_VFP3);
 609         set_feature(env, ARM_FEATURE_VFP_FP16);
 610     }
 611     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 612         set_feature(env, ARM_FEATURE_VFP);
 613     }
 614     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 615         set_feature(env, ARM_FEATURE_V7MP);
 616         set_feature(env, ARM_FEATURE_PXN);
 617     }
 618     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 619         set_feature(env, ARM_FEATURE_CBAR);
 620     }
 621     if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 622         !arm_feature(env, ARM_FEATURE_M)) {
 623         set_feature(env, ARM_FEATURE_THUMB_DSP);
 624     }
 625
 626     if (cpu->reset_hivecs) {
 627             cpu->reset_sctlr |= (1 << 13);
 628     }
 629
 630     if (!cpu->has_el3) {
 631         /* If the has_el3 CPU property is disabled then we need to disable the
 632          * feature.
 633          */
 634         unset_feature(env, ARM_FEATURE_EL3);
 635
 636         /* Disable the security extension feature bits in the processor feature
 637          * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
 638          */
 639         cpu->id_pfr1 &= ~0xf0;
 640         cpu->id_aa64pfr0 &= ~0xf000;
 641     }
 642
 643     if (!cpu->has_mpu) {
 644         unset_feature(env, ARM_FEATURE_MPU);
 645     }
 646
 647     if (arm_feature(env, ARM_FEATURE_MPU) &&
 648         arm_feature(env, ARM_FEATURE_V7)) {
 649         uint32_t nr = cpu->pmsav7_dregion;
 650
 651         if (nr > 0xff) {
 652             error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32 "\n", nr);
 653             return;
 654         }
 655
 656         if (nr) {
 657             env->pmsav7.drbar = g_new0(uint32_t, nr);
 658             env->pmsav7.drsr = g_new0(uint32_t, nr);
 659             env->pmsav7.dracr = g_new0(uint32_t, nr);
 660         }
 661     }
 662
 663     register_cp_regs_for_features(cpu);
 664     arm_cpu_register_gdb_regs_for_features(cpu);
 665
 666     init_cpreg_list(cpu);
 667
 668     qemu_init_vcpu(cs);
 669     cpu_reset(cs);
 670
 671     acc->parent_realize(dev, errp);
 672 }
 673
 674 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 675 {
 676     ObjectClass *oc;
 677     char *typename;
 678     char **cpuname;
 679
 680     if (!cpu_model) {
 681         return NULL;
 682     }
 683
 684     cpuname = g_strsplit(cpu_model, ",", 1);
 685     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
 686     oc = object_class_by_name(typename);
 687     g_strfreev(cpuname);
 688     g_free(typename);
 689     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 690         object_class_is_abstract(oc)) {
 691         return NULL;
 692     }
 693     return oc;
 694 }
 695
 696 /* CPU models. These are not needed for the AArch64 linux-user build. */
 697 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 698
 699 static void arm926_initfn(Object *obj)
 700 {
 701     ARMCPU *cpu = ARM_CPU(obj);
 702
 703     cpu->dtb_compatible = "arm,arm926";
 704     set_feature(&cpu->env, ARM_FEATURE_V5);
 705     set_feature(&cpu->env, ARM_FEATURE_VFP);
 706     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 707     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 708     cpu->midr = 0x41069265;
 709     cpu->reset_fpsid = 0x41011090;
 710     cpu->ctr = 0x1dd20d2;
 711     cpu->reset_sctlr = 0x00090078;
 712 }
 713
 714 static void arm946_initfn(Object *obj)
 715 {
 716     ARMCPU *cpu = ARM_CPU(obj);
 717
 718     cpu->dtb_compatible = "arm,arm946";
 719     set_feature(&cpu->env, ARM_FEATURE_V5);
 720     set_feature(&cpu->env, ARM_FEATURE_MPU);
 721     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 722     cpu->midr = 0x41059461;
 723     cpu->ctr = 0x0f004006;
 724     cpu->reset_sctlr = 0x00000078;
 725 }
 726
 727 static void arm1026_initfn(Object *obj)
 728 {
 729     ARMCPU *cpu = ARM_CPU(obj);
 730
 731     cpu->dtb_compatible = "arm,arm1026";
 732     set_feature(&cpu->env, ARM_FEATURE_V5);
 733     set_feature(&cpu->env, ARM_FEATURE_VFP);
 734     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 735     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 736     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 737     cpu->midr = 0x4106a262;
 738     cpu->reset_fpsid = 0x410110a0;
 739     cpu->ctr = 0x1dd20d2;
 740     cpu->reset_sctlr = 0x00090078;
 741     cpu->reset_auxcr = 1;
 742     {
 743         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 744         ARMCPRegInfo ifar = {
 745             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 746             .access = PL1_RW,
 747             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 748             .resetvalue = 0
 749         };
 750         define_one_arm_cp_reg(cpu, &ifar);
 751     }
 752 }
 753
 754 static void arm1136_r2_initfn(Object *obj)
 755 {
 756     ARMCPU *cpu = ARM_CPU(obj);
 757     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 758      * older core than plain "arm1136". In particular this does not
 759      * have the v6K features.
 760      * These ID register values are correct for 1136 but may be wrong
 761      * for 1136_r2 (in particular r0p2 does not actually implement most
 762      * of the ID registers).
 763      */
 764
 765     cpu->dtb_compatible = "arm,arm1136";
 766     set_feature(&cpu->env, ARM_FEATURE_V6);
 767     set_feature(&cpu->env, ARM_FEATURE_VFP);
 768     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 769     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 770     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 771     cpu->midr = 0x4107b362;
 772     cpu->reset_fpsid = 0x410120b4;
 773     cpu->mvfr0 = 0x11111111;
 774     cpu->mvfr1 = 0x00000000;
 775     cpu->ctr = 0x1dd20d2;
 776     cpu->reset_sctlr = 0x00050078;
 777     cpu->id_pfr0 = 0x111;
 778     cpu->id_pfr1 = 0x1;
 779     cpu->id_dfr0 = 0x2;
 780     cpu->id_afr0 = 0x3;
 781     cpu->id_mmfr0 = 0x01130003;
 782     cpu->id_mmfr1 = 0x10030302;
 783     cpu->id_mmfr2 = 0x01222110;
 784     cpu->id_isar0 = 0x00140011;
 785     cpu->id_isar1 = 0x12002111;
 786     cpu->id_isar2 = 0x11231111;
 787     cpu->id_isar3 = 0x01102131;
 788     cpu->id_isar4 = 0x141;
 789     cpu->reset_auxcr = 7;
 790 }
 791
 792 static void arm1136_initfn(Object *obj)
 793 {
 794     ARMCPU *cpu = ARM_CPU(obj);
 795
 796     cpu->dtb_compatible = "arm,arm1136";
 797     set_feature(&cpu->env, ARM_FEATURE_V6K);
 798     set_feature(&cpu->env, ARM_FEATURE_V6);
 799     set_feature(&cpu->env, ARM_FEATURE_VFP);
 800     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 801     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 802     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 803     cpu->midr = 0x4117b363;
 804     cpu->reset_fpsid = 0x410120b4;
 805     cpu->mvfr0 = 0x11111111;
 806     cpu->mvfr1 = 0x00000000;
 807     cpu->ctr = 0x1dd20d2;
 808     cpu->reset_sctlr = 0x00050078;
 809     cpu->id_pfr0 = 0x111;
 810     cpu->id_pfr1 = 0x1;
 811     cpu->id_dfr0 = 0x2;
 812     cpu->id_afr0 = 0x3;
 813     cpu->id_mmfr0 = 0x01130003;
 814     cpu->id_mmfr1 = 0x10030302;
 815     cpu->id_mmfr2 = 0x01222110;
 816     cpu->id_isar0 = 0x00140011;
 817     cpu->id_isar1 = 0x12002111;
 818     cpu->id_isar2 = 0x11231111;
 819     cpu->id_isar3 = 0x01102131;
 820     cpu->id_isar4 = 0x141;
 821     cpu->reset_auxcr = 7;
 822 }
 823
 824 static void arm1176_initfn(Object *obj)
 825 {
 826     ARMCPU *cpu = ARM_CPU(obj);
 827
 828     cpu->dtb_compatible = "arm,arm1176";
 829     set_feature(&cpu->env, ARM_FEATURE_V6K);
 830     set_feature(&cpu->env, ARM_FEATURE_VFP);
 831     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 832     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 833     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 834     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 835     set_feature(&cpu->env, ARM_FEATURE_EL3);
 836     cpu->midr = 0x410fb767;
 837     cpu->reset_fpsid = 0x410120b5;
 838     cpu->mvfr0 = 0x11111111;
 839     cpu->mvfr1 = 0x00000000;
 840     cpu->ctr = 0x1dd20d2;
 841     cpu->reset_sctlr = 0x00050078;
 842     cpu->id_pfr0 = 0x111;
 843     cpu->id_pfr1 = 0x11;
 844     cpu->id_dfr0 = 0x33;
 845     cpu->id_afr0 = 0;
 846     cpu->id_mmfr0 = 0x01130003;
 847     cpu->id_mmfr1 = 0x10030302;
 848     cpu->id_mmfr2 = 0x01222100;
 849     cpu->id_isar0 = 0x0140011;
 850     cpu->id_isar1 = 0x12002111;
 851     cpu->id_isar2 = 0x11231121;
 852     cpu->id_isar3 = 0x01102131;
 853     cpu->id_isar4 = 0x01141;
 854     cpu->reset_auxcr = 7;
 855 }
 856
 857 static void arm11mpcore_initfn(Object *obj)
 858 {
 859     ARMCPU *cpu = ARM_CPU(obj);
 860
 861     cpu->dtb_compatible = "arm,arm11mpcore";
 862     set_feature(&cpu->env, ARM_FEATURE_V6K);
 863     set_feature(&cpu->env, ARM_FEATURE_VFP);
 864     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 865     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 866     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 867     cpu->midr = 0x410fb022;
 868     cpu->reset_fpsid = 0x410120b4;
 869     cpu->mvfr0 = 0x11111111;
 870     cpu->mvfr1 = 0x00000000;
 871     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 872     cpu->id_pfr0 = 0x111;
 873     cpu->id_pfr1 = 0x1;
 874     cpu->id_dfr0 = 0;
 875     cpu->id_afr0 = 0x2;
 876     cpu->id_mmfr0 = 0x01100103;
 877     cpu->id_mmfr1 = 0x10020302;
 878     cpu->id_mmfr2 = 0x01222000;
 879     cpu->id_isar0 = 0x00100011;
 880     cpu->id_isar1 = 0x12002111;
 881     cpu->id_isar2 = 0x11221011;
 882     cpu->id_isar3 = 0x01102131;
 883     cpu->id_isar4 = 0x141;
 884     cpu->reset_auxcr = 1;
 885 }
 886
 887 static void cortex_m3_initfn(Object *obj)
 888 {
 889     ARMCPU *cpu = ARM_CPU(obj);
 890     set_feature(&cpu->env, ARM_FEATURE_V7);
 891     set_feature(&cpu->env, ARM_FEATURE_M);
 892     cpu->midr = 0x410fc231;
 893 }
 894
 895 static void cortex_m4_initfn(Object *obj)
 896 {
 897     ARMCPU *cpu = ARM_CPU(obj);
 898
 899     set_feature(&cpu->env, ARM_FEATURE_V7);
 900     set_feature(&cpu->env, ARM_FEATURE_M);
 901     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 902     cpu->midr = 0x410fc240; /* r0p0 */
 903 }
 904 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 905 {
 906     CPUClass *cc = CPU_CLASS(oc);
 907
 908 #ifndef CONFIG_USER_ONLY
 909     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 910 #endif
 911
 912     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
 913 }
 914
 915 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
 916     /* Dummy the TCM region regs for the moment */
 917     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
 918       .access = PL1_RW, .type = ARM_CP_CONST },
 919     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
 920       .access = PL1_RW, .type = ARM_CP_CONST },
 921     REGINFO_SENTINEL
 922 };
 923
 924 static void cortex_r5_initfn(Object *obj)
 925 {
 926     ARMCPU *cpu = ARM_CPU(obj);
 927
 928     set_feature(&cpu->env, ARM_FEATURE_V7);
 929     set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
 930     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 931     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 932     set_feature(&cpu->env, ARM_FEATURE_MPU);
 933     cpu->midr = 0x411fc153; /* r1p3 */
 934     cpu->id_pfr0 = 0x0131;
 935     cpu->id_pfr1 = 0x001;
 936     cpu->id_dfr0 = 0x010400;
 937     cpu->id_afr0 = 0x0;
 938     cpu->id_mmfr0 = 0x0210030;
 939     cpu->id_mmfr1 = 0x00000000;
 940     cpu->id_mmfr2 = 0x01200000;
 941     cpu->id_mmfr3 = 0x0211;
 942     cpu->id_isar0 = 0x2101111;
 943     cpu->id_isar1 = 0x13112111;
 944     cpu->id_isar2 = 0x21232141;
 945     cpu->id_isar3 = 0x01112131;
 946     cpu->id_isar4 = 0x0010142;
 947     cpu->id_isar5 = 0x0;
 948     cpu->mp_is_up = true;
 949     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
 950 }
 951
 952 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 953     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 954       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 955     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 956       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 957     REGINFO_SENTINEL
 958 };
 959
 960 static void cortex_a8_initfn(Object *obj)
 961 {
 962     ARMCPU *cpu = ARM_CPU(obj);
 963
 964     cpu->dtb_compatible = "arm,cortex-a8";
 965     set_feature(&cpu->env, ARM_FEATURE_V7);
 966     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 967     set_feature(&cpu->env, ARM_FEATURE_NEON);
 968     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 969     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 970     set_feature(&cpu->env, ARM_FEATURE_EL3);
 971     cpu->midr = 0x410fc080;
 972     cpu->reset_fpsid = 0x410330c0;
 973     cpu->mvfr0 = 0x11110222;
 974     cpu->mvfr1 = 0x00011100;
 975     cpu->ctr = 0x82048004;
 976     cpu->reset_sctlr = 0x00c50078;
 977     cpu->id_pfr0 = 0x1031;
 978     cpu->id_pfr1 = 0x11;
 979     cpu->id_dfr0 = 0x400;
 980     cpu->id_afr0 = 0;
 981     cpu->id_mmfr0 = 0x31100003;
 982     cpu->id_mmfr1 = 0x20000000;
 983     cpu->id_mmfr2 = 0x01202000;
 984     cpu->id_mmfr3 = 0x11;
 985     cpu->id_isar0 = 0x00101111;
 986     cpu->id_isar1 = 0x12112111;
 987     cpu->id_isar2 = 0x21232031;
 988     cpu->id_isar3 = 0x11112131;
 989     cpu->id_isar4 = 0x00111142;
 990     cpu->dbgdidr = 0x15141000;
 991     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 992     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 993     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 994     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 995     cpu->reset_auxcr = 2;
 996     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 997 }
 998
 999 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1000     /* power_control should be set to maximum latency. Again,
1001      * default to 0 and set by private hook
1002      */
1003     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1004       .access = PL1_RW, .resetvalue = 0,
1005       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1006     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1007       .access = PL1_RW, .resetvalue = 0,
1008       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1009     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1010       .access = PL1_RW, .resetvalue = 0,
1011       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1012     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1013       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1014     /* TLB lockdown control */
1015     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1016       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1017     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1018       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1019     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1020       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1021     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1022       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1023     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1024       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1025     REGINFO_SENTINEL
1026 };
1027
1028 static void cortex_a9_initfn(Object *obj)
1029 {
1030     ARMCPU *cpu = ARM_CPU(obj);
1031
1032     cpu->dtb_compatible = "arm,cortex-a9";
1033     set_feature(&cpu->env, ARM_FEATURE_V7);
1034     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1035     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
1036     set_feature(&cpu->env, ARM_FEATURE_NEON);
1037     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1038     set_feature(&cpu->env, ARM_FEATURE_EL3);
1039     /* Note that A9 supports the MP extensions even for
1040      * A9UP and single-core A9MP (which are both different
1041      * and valid configurations; we don't model A9UP).
1042      */
1043     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1044     set_feature(&cpu->env, ARM_FEATURE_CBAR);
1045     cpu->midr = 0x410fc090;
1046     cpu->reset_fpsid = 0x41033090;
1047     cpu->mvfr0 = 0x11110222;
1048     cpu->mvfr1 = 0x01111111;
1049     cpu->ctr = 0x80038003;
1050     cpu->reset_sctlr = 0x00c50078;
1051     cpu->id_pfr0 = 0x1031;
1052     cpu->id_pfr1 = 0x11;
1053     cpu->id_dfr0 = 0x000;
1054     cpu->id_afr0 = 0;
1055     cpu->id_mmfr0 = 0x00100103;
1056     cpu->id_mmfr1 = 0x20000000;
1057     cpu->id_mmfr2 = 0x01230000;
1058     cpu->id_mmfr3 = 0x00002111;
1059     cpu->id_isar0 = 0x00101111;
1060     cpu->id_isar1 = 0x13112111;
1061     cpu->id_isar2 = 0x21232041;
1062     cpu->id_isar3 = 0x11112131;
1063     cpu->id_isar4 = 0x00111142;
1064     cpu->dbgdidr = 0x35141000;
1065     cpu->clidr = (1 << 27) | (1 << 24) | 3;
1066     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
1067     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
1068     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1069 }
1070
1071 #ifndef CONFIG_USER_ONLY
1072 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1073 {
1074     /* Linux wants the number of processors from here.
1075      * Might as well set the interrupt-controller bit too.
1076      */
1077     return ((smp_cpus - 1) << 24) | (1 << 23);
1078 }
1079 #endif
1080
1081 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1082 #ifndef CONFIG_USER_ONLY
1083     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1084       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1085       .writefn = arm_cp_write_ignore, },
1086 #endif
1087     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1088       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1089     REGINFO_SENTINEL
1090 };
1091
1092 static void cortex_a15_initfn(Object *obj)
1093 {
1094     ARMCPU *cpu = ARM_CPU(obj);
1095
1096     cpu->dtb_compatible = "arm,cortex-a15";
1097     set_feature(&cpu->env, ARM_FEATURE_V7);
1098     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1099     set_feature(&cpu->env, ARM_FEATURE_NEON);
1100     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1101     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1102     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1103     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1104     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1105     set_feature(&cpu->env, ARM_FEATURE_LPAE);
1106     set_feature(&cpu->env, ARM_FEATURE_EL3);
1107     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1108     cpu->midr = 0x412fc0f1;
1109     cpu->reset_fpsid = 0x410430f0;
1110     cpu->mvfr0 = 0x10110222;
1111     cpu->mvfr1 = 0x11111111;
1112     cpu->ctr = 0x8444c004;
1113     cpu->reset_sctlr = 0x00c50078;
1114     cpu->id_pfr0 = 0x00001131;
1115     cpu->id_pfr1 = 0x00011011;
1116     cpu->id_dfr0 = 0x02010555;
1117     cpu->id_afr0 = 0x00000000;
1118     cpu->id_mmfr0 = 0x10201105;
1119     cpu->id_mmfr1 = 0x20000000;
1120     cpu->id_mmfr2 = 0x01240000;
1121     cpu->id_mmfr3 = 0x02102211;
1122     cpu->id_isar0 = 0x02101110;
1123     cpu->id_isar1 = 0x13112111;
1124     cpu->id_isar2 = 0x21232041;
1125     cpu->id_isar3 = 0x11112131;
1126     cpu->id_isar4 = 0x10011142;
1127     cpu->dbgdidr = 0x3515f021;
1128     cpu->clidr = 0x0a200023;
1129     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1130     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1131     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1132     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1133 }
1134
1135 static void ti925t_initfn(Object *obj)
1136 {
1137     ARMCPU *cpu = ARM_CPU(obj);
1138     set_feature(&cpu->env, ARM_FEATURE_V4T);
1139     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1140     cpu->midr = ARM_CPUID_TI925T;
1141     cpu->ctr = 0x5109149;
1142     cpu->reset_sctlr = 0x00000070;
1143 }
1144
1145 static void sa1100_initfn(Object *obj)
1146 {
1147     ARMCPU *cpu = ARM_CPU(obj);
1148
1149     cpu->dtb_compatible = "intel,sa1100";
1150     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1151     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1152     cpu->midr = 0x4401A11B;
1153     cpu->reset_sctlr = 0x00000070;
1154 }
1155
1156 static void sa1110_initfn(Object *obj)
1157 {
1158     ARMCPU *cpu = ARM_CPU(obj);
1159     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1160     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1161     cpu->midr = 0x6901B119;
1162     cpu->reset_sctlr = 0x00000070;
1163 }
1164
1165 static void pxa250_initfn(Object *obj)
1166 {
1167     ARMCPU *cpu = ARM_CPU(obj);
1168
1169     cpu->dtb_compatible = "marvell,xscale";
1170     set_feature(&cpu->env, ARM_FEATURE_V5);
1171     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1172     cpu->midr = 0x69052100;
1173     cpu->ctr = 0xd172172;
1174     cpu->reset_sctlr = 0x00000078;
1175 }
1176
1177 static void pxa255_initfn(Object *obj)
1178 {
1179     ARMCPU *cpu = ARM_CPU(obj);
1180
1181     cpu->dtb_compatible = "marvell,xscale";
1182     set_feature(&cpu->env, ARM_FEATURE_V5);
1183     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1184     cpu->midr = 0x69052d00;
1185     cpu->ctr = 0xd172172;
1186     cpu->reset_sctlr = 0x00000078;
1187 }
1188
1189 static void pxa260_initfn(Object *obj)
1190 {
1191     ARMCPU *cpu = ARM_CPU(obj);
1192
1193     cpu->dtb_compatible = "marvell,xscale";
1194     set_feature(&cpu->env, ARM_FEATURE_V5);
1195     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1196     cpu->midr = 0x69052903;
1197     cpu->ctr = 0xd172172;
1198     cpu->reset_sctlr = 0x00000078;
1199 }
1200
1201 static void pxa261_initfn(Object *obj)
1202 {
1203     ARMCPU *cpu = ARM_CPU(obj);
1204
1205     cpu->dtb_compatible = "marvell,xscale";
1206     set_feature(&cpu->env, ARM_FEATURE_V5);
1207     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1208     cpu->midr = 0x69052d05;
1209     cpu->ctr = 0xd172172;
1210     cpu->reset_sctlr = 0x00000078;
1211 }
1212
1213 static void pxa262_initfn(Object *obj)
1214 {
1215     ARMCPU *cpu = ARM_CPU(obj);
1216
1217     cpu->dtb_compatible = "marvell,xscale";
1218     set_feature(&cpu->env, ARM_FEATURE_V5);
1219     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1220     cpu->midr = 0x69052d06;
1221     cpu->ctr = 0xd172172;
1222     cpu->reset_sctlr = 0x00000078;
1223 }
1224
1225 static void pxa270a0_initfn(Object *obj)
1226 {
1227     ARMCPU *cpu = ARM_CPU(obj);
1228
1229     cpu->dtb_compatible = "marvell,xscale";
1230     set_feature(&cpu->env, ARM_FEATURE_V5);
1231     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1232     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1233     cpu->midr = 0x69054110;
1234     cpu->ctr = 0xd172172;
1235     cpu->reset_sctlr = 0x00000078;
1236 }
1237
1238 static void pxa270a1_initfn(Object *obj)
1239 {
1240     ARMCPU *cpu = ARM_CPU(obj);
1241
1242     cpu->dtb_compatible = "marvell,xscale";
1243     set_feature(&cpu->env, ARM_FEATURE_V5);
1244     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1245     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1246     cpu->midr = 0x69054111;
1247     cpu->ctr = 0xd172172;
1248     cpu->reset_sctlr = 0x00000078;
1249 }
1250
1251 static void pxa270b0_initfn(Object *obj)
1252 {
1253     ARMCPU *cpu = ARM_CPU(obj);
1254
1255     cpu->dtb_compatible = "marvell,xscale";
1256     set_feature(&cpu->env, ARM_FEATURE_V5);
1257     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1258     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1259     cpu->midr = 0x69054112;
1260     cpu->ctr = 0xd172172;
1261     cpu->reset_sctlr = 0x00000078;
1262 }
1263
1264 static void pxa270b1_initfn(Object *obj)
1265 {
1266     ARMCPU *cpu = ARM_CPU(obj);
1267
1268     cpu->dtb_compatible = "marvell,xscale";
1269     set_feature(&cpu->env, ARM_FEATURE_V5);
1270     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1271     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1272     cpu->midr = 0x69054113;
1273     cpu->ctr = 0xd172172;
1274     cpu->reset_sctlr = 0x00000078;
1275 }
1276
1277 static void pxa270c0_initfn(Object *obj)
1278 {
1279     ARMCPU *cpu = ARM_CPU(obj);
1280
1281     cpu->dtb_compatible = "marvell,xscale";
1282     set_feature(&cpu->env, ARM_FEATURE_V5);
1283     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1284     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1285     cpu->midr = 0x69054114;
1286     cpu->ctr = 0xd172172;
1287     cpu->reset_sctlr = 0x00000078;
1288 }
1289
1290 static void pxa270c5_initfn(Object *obj)
1291 {
1292     ARMCPU *cpu = ARM_CPU(obj);
1293
1294     cpu->dtb_compatible = "marvell,xscale";
1295     set_feature(&cpu->env, ARM_FEATURE_V5);
1296     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1297     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1298     cpu->midr = 0x69054117;
1299     cpu->ctr = 0xd172172;
1300     cpu->reset_sctlr = 0x00000078;
1301 }
1302
1303 #ifdef CONFIG_USER_ONLY
1304 static void arm_any_initfn(Object *obj)
1305 {
1306     ARMCPU *cpu = ARM_CPU(obj);
1307     set_feature(&cpu->env, ARM_FEATURE_V8);
1308     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1309     set_feature(&cpu->env, ARM_FEATURE_NEON);
1310     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1311     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1312     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1313     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1314     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1315     set_feature(&cpu->env, ARM_FEATURE_CRC);
1316     cpu->midr = 0xffffffff;
1317 }
1318 #endif
1319
1320 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1321
1322 typedef struct ARMCPUInfo {
1323     const char *name;
1324     void (*initfn)(Object *obj);
1325     void (*class_init)(ObjectClass *oc, void *data);
1326 } ARMCPUInfo;
1327
1328 static const ARMCPUInfo arm_cpus[] = {
1329 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1330     { .name = "arm926",      .initfn = arm926_initfn },
1331     { .name = "arm946",      .initfn = arm946_initfn },
1332     { .name = "arm1026",     .initfn = arm1026_initfn },
1333     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1334      * older core than plain "arm1136". In particular this does not
1335      * have the v6K features.
1336      */
1337     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1338     { .name = "arm1136",     .initfn = arm1136_initfn },
1339     { .name = "arm1176",     .initfn = arm1176_initfn },
1340     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1341     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1342                              .class_init = arm_v7m_class_init },
1343     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
1344                              .class_init = arm_v7m_class_init },
1345     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
1346     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1347     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1348     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1349     { .name = "ti925t",      .initfn = ti925t_initfn },
1350     { .name = "sa1100",      .initfn = sa1100_initfn },
1351     { .name = "sa1110",      .initfn = sa1110_initfn },
1352     { .name = "pxa250",      .initfn = pxa250_initfn },
1353     { .name = "pxa255",      .initfn = pxa255_initfn },
1354     { .name = "pxa260",      .initfn = pxa260_initfn },
1355     { .name = "pxa261",      .initfn = pxa261_initfn },
1356     { .name = "pxa262",      .initfn = pxa262_initfn },
1357     /* "pxa270" is an alias for "pxa270-a0" */
1358     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1359     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1360     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1361     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1362     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1363     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1364     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1365 #ifdef CONFIG_USER_ONLY
1366     { .name = "any",         .initfn = arm_any_initfn },
1367 #endif
1368 #endif
1369     { .name = NULL }
1370 };
1371
1372 static Property arm_cpu_properties[] = {
1373     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1374     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1375     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1376     DEFINE_PROP_END_OF_LIST()
1377 };
1378
1379 #ifdef CONFIG_USER_ONLY
1380 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
1381                                     int mmu_idx)
1382 {
1383     ARMCPU *cpu = ARM_CPU(cs);
1384     CPUARMState *env = &cpu->env;
1385
1386     env->exception.vaddress = address;
1387     if (rw == 2) {
1388         cs->exception_index = EXCP_PREFETCH_ABORT;
1389     } else {
1390         cs->exception_index = EXCP_DATA_ABORT;
1391     }
1392     return 1;
1393 }
1394 #endif
1395
1396 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1397 {
1398     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1399     CPUClass *cc = CPU_CLASS(acc);
1400     DeviceClass *dc = DEVICE_CLASS(oc);
1401
1402     acc->parent_realize = dc->realize;
1403     dc->realize = arm_cpu_realizefn;
1404     dc->props = arm_cpu_properties;
1405
1406     acc->parent_reset = cc->reset;
1407     cc->reset = arm_cpu_reset;
1408
1409     cc->class_by_name = arm_cpu_class_by_name;
1410     cc->has_work = arm_cpu_has_work;
1411     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1412     cc->dump_state = arm_cpu_dump_state;
1413     cc->set_pc = arm_cpu_set_pc;
1414     cc->gdb_read_register = arm_cpu_gdb_read_register;
1415     cc->gdb_write_register = arm_cpu_gdb_write_register;
1416 #ifdef CONFIG_USER_ONLY
1417     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1418 #else
1419     cc->do_interrupt = arm_cpu_do_interrupt;
1420     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1421     cc->vmsd = &vmstate_arm_cpu;
1422     cc->virtio_is_big_endian = arm_cpu_is_big_endian;
1423 #endif
1424     cc->gdb_num_core_regs = 26;
1425     cc->gdb_core_xml_file = "arm-core.xml";
1426     cc->gdb_stop_before_watchpoint = true;
1427     cc->debug_excp_handler = arm_debug_excp_handler;
1428
1429     cc->disas_set_info = arm_disas_set_info;
1430 }
1431
1432 static void cpu_register(const ARMCPUInfo *info)
1433 {
1434     TypeInfo type_info = {
1435         .parent = TYPE_ARM_CPU,
1436         .instance_size = sizeof(ARMCPU),
1437         .instance_init = info->initfn,
1438         .class_size = sizeof(ARMCPUClass),
1439         .class_init = info->class_init,
1440     };
1441
1442     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1443     type_register(&type_info);
1444     g_free((void *)type_info.name);
1445 }
1446
1447 static const TypeInfo arm_cpu_type_info = {
1448     .name = TYPE_ARM_CPU,
1449     .parent = TYPE_CPU,
1450     .instance_size = sizeof(ARMCPU),
1451     .instance_init = arm_cpu_initfn,
1452     .instance_post_init = arm_cpu_post_init,
1453     .instance_finalize = arm_cpu_finalizefn,
1454     .abstract = true,
1455     .class_size = sizeof(ARMCPUClass),
1456     .class_init = arm_cpu_class_init,
1457 };
1458
1459 static void arm_cpu_register_types(void)
1460 {
1461     const ARMCPUInfo *info = arm_cpus;
1462
1463     type_register_static(&arm_cpu_type_info);
1464
1465     while (info->name) {
1466         cpu_register(info);
1467         info++;
1468     }
1469 }
1470
1471 type_init(arm_cpu_register_types)