hw/timer/imx_gpt.c

   1 /*
   2  * IMX GPT Timer
   3  *
   4  * Copyright (c) 2008 OK Labs
   5  * Copyright (c) 2011 NICTA Pty Ltd
   6  * Originally written by Hans Jiang
   7  * Updated by Peter Chubb
   8  * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
   9  *
  10  * This code is licensed under GPL version 2 or later.  See
  11  * the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include "hw/timer/imx_gpt.h"
  16 #include "hw/misc/imx_ccm.h"
  17 #include "qemu/main-loop.h"
  18
  19 /*
  20  * Define to 1 for debug messages
  21  */
  22 #define DEBUG_TIMER 0
  23 #if DEBUG_TIMER
  24
  25 static char const *imx_gpt_reg_name(uint32_t reg)
  26 {
  27     switch (reg) {
  28     case 0:
  29         return "CR";
  30     case 1:
  31         return "PR";
  32     case 2:
  33         return "SR";
  34     case 3:
  35         return "IR";
  36     case 4:
  37         return "OCR1";
  38     case 5:
  39         return "OCR2";
  40     case 6:
  41         return "OCR3";
  42     case 7:
  43         return "ICR1";
  44     case 8:
  45         return "ICR2";
  46     case 9:
  47         return "CNT";
  48     default:
  49         return "[?]";
  50     }
  51 }
  52
  53 #  define DPRINTF(fmt, args...) \
  54           do { printf("%s: " fmt , __func__, ##args); } while (0)
  55 #else
  56 #  define DPRINTF(fmt, args...) do {} while (0)
  57 #endif
  58
  59 /*
  60  * Define to 1 for messages about attempts to
  61  * access unimplemented registers or similar.
  62  */
  63 #define DEBUG_IMPLEMENTATION 1
  64 #if DEBUG_IMPLEMENTATION
  65 #  define IPRINTF(fmt, args...) \
  66           do { fprintf(stderr, "%s: " fmt, __func__, ##args); } while (0)
  67 #else
  68 #  define IPRINTF(fmt, args...) do {} while (0)
  69 #endif
  70
  71 static const VMStateDescription vmstate_imx_timer_gpt = {
  72     .name = TYPE_IMX_GPT,
  73     .version_id = 3,
  74     .minimum_version_id = 3,
  75     .fields = (VMStateField[]) {
  76         VMSTATE_UINT32(cr, IMXGPTState),
  77         VMSTATE_UINT32(pr, IMXGPTState),
  78         VMSTATE_UINT32(sr, IMXGPTState),
  79         VMSTATE_UINT32(ir, IMXGPTState),
  80         VMSTATE_UINT32(ocr1, IMXGPTState),
  81         VMSTATE_UINT32(ocr2, IMXGPTState),
  82         VMSTATE_UINT32(ocr3, IMXGPTState),
  83         VMSTATE_UINT32(icr1, IMXGPTState),
  84         VMSTATE_UINT32(icr2, IMXGPTState),
  85         VMSTATE_UINT32(cnt, IMXGPTState),
  86         VMSTATE_UINT32(next_timeout, IMXGPTState),
  87         VMSTATE_UINT32(next_int, IMXGPTState),
  88         VMSTATE_UINT32(freq, IMXGPTState),
  89         VMSTATE_PTIMER(timer, IMXGPTState),
  90         VMSTATE_END_OF_LIST()
  91     }
  92 };
  93
  94 static const IMXClk imx_gpt_clocks[] = {
  95     NOCLK,    /* 000 No clock source */
  96     IPG,      /* 001 ipg_clk, 532MHz*/
  97     IPG,      /* 010 ipg_clk_highfreq */
  98     NOCLK,    /* 011 not defined */
  99     CLK_32k,  /* 100 ipg_clk_32k */
 100     NOCLK,    /* 101 not defined */
 101     NOCLK,    /* 110 not defined */
 102     NOCLK,    /* 111 not defined */
 103 };
 104
 105 static void imx_gpt_set_freq(IMXGPTState *s)
 106 {
 107     uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3);
 108     uint32_t freq = imx_clock_frequency(s->ccm, imx_gpt_clocks[clksrc])
 109                     / (1 + s->pr);
 110     s->freq = freq;
 111
 112     DPRINTF("Setting clksrc %d to frequency %d\n", clksrc, freq);
 113
 114     if (freq) {
 115         ptimer_set_freq(s->timer, freq);
 116     }
 117 }
 118
 119 static void imx_gpt_update_int(IMXGPTState *s)
 120 {
 121     if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) {
 122         qemu_irq_raise(s->irq);
 123     } else {
 124         qemu_irq_lower(s->irq);
 125     }
 126 }
 127
 128 static uint32_t imx_gpt_update_count(IMXGPTState *s)
 129 {
 130     s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer);
 131
 132     return s->cnt;
 133 }
 134
 135 static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg,
 136                                           uint32_t timeout)
 137 {
 138     if ((count < reg) && (timeout > reg)) {
 139         timeout = reg;
 140     }
 141
 142     return timeout;
 143 }
 144
 145 static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event)
 146 {
 147     uint32_t timeout = GPT_TIMER_MAX;
 148     uint32_t count = 0;
 149     long long limit;
 150
 151     if (!(s->cr & GPT_CR_EN)) {
 152         /* if not enabled just return */
 153         return;
 154     }
 155
 156     if (event) {
 157         /* This is a timer event  */
 158
 159         if ((s->cr & GPT_CR_FRR)  && (s->next_timeout != GPT_TIMER_MAX)) {
 160             /*
 161              * if we are in free running mode and we have not reached
 162              * the GPT_TIMER_MAX limit, then update the count
 163              */
 164             count = imx_gpt_update_count(s);
 165         }
 166     } else {
 167         /* not a timer event, then just update the count */
 168
 169         count = imx_gpt_update_count(s);
 170     }
 171
 172     /* now, find the next timeout related to count */
 173
 174     if (s->ir & GPT_IR_OF1IE) {
 175         timeout = imx_gpt_find_limit(count, s->ocr1, timeout);
 176     }
 177     if (s->ir & GPT_IR_OF2IE) {
 178         timeout = imx_gpt_find_limit(count, s->ocr2, timeout);
 179     }
 180     if (s->ir & GPT_IR_OF3IE) {
 181         timeout = imx_gpt_find_limit(count, s->ocr3, timeout);
 182     }
 183
 184     /* find the next set of interrupts to raise for next timer event */
 185
 186     s->next_int = 0;
 187     if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) {
 188         s->next_int |= GPT_SR_OF1;
 189     }
 190     if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) {
 191         s->next_int |= GPT_SR_OF2;
 192     }
 193     if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) {
 194         s->next_int |= GPT_SR_OF3;
 195     }
 196     if ((s->ir & GPT_IR_ROVIE) && (timeout == GPT_TIMER_MAX)) {
 197         s->next_int |= GPT_SR_ROV;
 198     }
 199
 200     /* the new range to count down from */
 201     limit = timeout - imx_gpt_update_count(s);
 202
 203     if (limit < 0) {
 204         /*
 205          * if we reach here, then QEMU is running too slow and we pass the
 206          * timeout limit while computing it. Let's deliver the interrupt
 207          * and compute a new limit.
 208          */
 209         s->sr |= s->next_int;
 210
 211         imx_gpt_compute_next_timeout(s, event);
 212
 213         imx_gpt_update_int(s);
 214     } else {
 215         /* New timeout value */
 216         s->next_timeout = timeout;
 217
 218         /* reset the limit to the computed range */
 219         ptimer_set_limit(s->timer, limit, 1);
 220     }
 221 }
 222
 223 static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size)
 224 {
 225     IMXGPTState *s = IMX_GPT(opaque);
 226     uint32_t reg_value = 0;
 227     uint32_t reg = offset >> 2;
 228
 229     switch (reg) {
 230     case 0: /* Control Register */
 231         reg_value = s->cr;
 232         break;
 233
 234     case 1: /* prescaler */
 235         reg_value = s->pr;
 236         break;
 237
 238     case 2: /* Status Register */
 239         reg_value = s->sr;
 240         break;
 241
 242     case 3: /* Interrupt Register */
 243         reg_value = s->ir;
 244         break;
 245
 246     case 4: /* Output Compare Register 1 */
 247         reg_value = s->ocr1;
 248         break;
 249
 250     case 5: /* Output Compare Register 2 */
 251         reg_value = s->ocr2;
 252         break;
 253
 254     case 6: /* Output Compare Register 3 */
 255         reg_value = s->ocr3;
 256         break;
 257
 258     case 7: /* input Capture Register 1 */
 259         qemu_log_mask(LOG_UNIMP, "icr1 feature is not implemented\n");
 260         reg_value = s->icr1;
 261         break;
 262
 263     case 8: /* input Capture Register 2 */
 264         qemu_log_mask(LOG_UNIMP, "icr2 feature is not implemented\n");
 265         reg_value = s->icr2;
 266         break;
 267
 268     case 9: /* cnt */
 269         imx_gpt_update_count(s);
 270         reg_value = s->cnt;
 271         break;
 272
 273     default:
 274         IPRINTF("Bad offset %x\n", reg);
 275         break;
 276     }
 277
 278     DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(reg), reg_value);
 279
 280     return reg_value;
 281 }
 282
 283 static void imx_gpt_reset(DeviceState *dev)
 284 {
 285     IMXGPTState *s = IMX_GPT(dev);
 286
 287     /* stop timer */
 288     ptimer_stop(s->timer);
 289
 290     /*
 291      * Soft reset doesn't touch some bits; hard reset clears them
 292      */
 293     s->cr &= ~(GPT_CR_EN|GPT_CR_ENMOD|GPT_CR_STOPEN|GPT_CR_DOZEN|
 294                GPT_CR_WAITEN|GPT_CR_DBGEN);
 295     s->sr = 0;
 296     s->pr = 0;
 297     s->ir = 0;
 298     s->cnt = 0;
 299     s->ocr1 = GPT_TIMER_MAX;
 300     s->ocr2 = GPT_TIMER_MAX;
 301     s->ocr3 = GPT_TIMER_MAX;
 302     s->icr1 = 0;
 303     s->icr2 = 0;
 304
 305     s->next_timeout = GPT_TIMER_MAX;
 306     s->next_int = 0;
 307
 308     /* compute new freq */
 309     imx_gpt_set_freq(s);
 310
 311     /* reset the limit to GPT_TIMER_MAX */
 312     ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1);
 313
 314     /* if the timer is still enabled, restart it */
 315     if (s->freq && (s->cr & GPT_CR_EN)) {
 316         ptimer_run(s->timer, 1);
 317     }
 318 }
 319
 320 static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value,
 321                           unsigned size)
 322 {
 323     IMXGPTState *s = IMX_GPT(opaque);
 324     uint32_t oldreg;
 325     uint32_t reg = offset >> 2;
 326
 327     DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(reg),
 328             (uint32_t)value);
 329
 330     switch (reg) {
 331     case 0:
 332         oldreg = s->cr;
 333         s->cr = value & ~0x7c14;
 334         if (s->cr & GPT_CR_SWR) { /* force reset */
 335             /* handle the reset */
 336             imx_gpt_reset(DEVICE(s));
 337         } else {
 338             /* set our freq, as the source might have changed */
 339             imx_gpt_set_freq(s);
 340
 341             if ((oldreg ^ s->cr) & GPT_CR_EN) {
 342                 if (s->cr & GPT_CR_EN) {
 343                     if (s->cr & GPT_CR_ENMOD) {
 344                         s->next_timeout = GPT_TIMER_MAX;
 345                         ptimer_set_count(s->timer, GPT_TIMER_MAX);
 346                         imx_gpt_compute_next_timeout(s, false);
 347                     }
 348                     ptimer_run(s->timer, 1);
 349                 } else {
 350                     /* stop timer */
 351                     ptimer_stop(s->timer);
 352                 }
 353             }
 354         }
 355         break;
 356
 357     case 1: /* Prescaler */
 358         s->pr = value & 0xfff;
 359         imx_gpt_set_freq(s);
 360         break;
 361
 362     case 2: /* SR */
 363         s->sr &= ~(value & 0x3f);
 364         imx_gpt_update_int(s);
 365         break;
 366
 367     case 3: /* IR -- interrupt register */
 368         s->ir = value & 0x3f;
 369         imx_gpt_update_int(s);
 370
 371         imx_gpt_compute_next_timeout(s, false);
 372
 373         break;
 374
 375     case 4: /* OCR1 -- output compare register */
 376         s->ocr1 = value;
 377
 378         /* In non-freerun mode, reset count when this register is written */
 379         if (!(s->cr & GPT_CR_FRR)) {
 380             s->next_timeout = GPT_TIMER_MAX;
 381             ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1);
 382         }
 383
 384         /* compute the new timeout */
 385         imx_gpt_compute_next_timeout(s, false);
 386
 387         break;
 388
 389     case 5: /* OCR2 -- output compare register */
 390         s->ocr2 = value;
 391
 392         /* compute the new timeout */
 393         imx_gpt_compute_next_timeout(s, false);
 394
 395         break;
 396
 397     case 6: /* OCR3 -- output compare register */
 398         s->ocr3 = value;
 399
 400         /* compute the new timeout */
 401         imx_gpt_compute_next_timeout(s, false);
 402
 403         break;
 404
 405     default:
 406         IPRINTF("Bad offset %x\n", reg);
 407         break;
 408     }
 409 }
 410
 411 static void imx_gpt_timeout(void *opaque)
 412 {
 413     IMXGPTState *s = IMX_GPT(opaque);
 414
 415     DPRINTF("\n");
 416
 417     s->sr |= s->next_int;
 418     s->next_int = 0;
 419
 420     imx_gpt_compute_next_timeout(s, true);
 421
 422     imx_gpt_update_int(s);
 423
 424     if (s->freq && (s->cr & GPT_CR_EN)) {
 425         ptimer_run(s->timer, 1);
 426     }
 427 }
 428
 429 static const MemoryRegionOps imx_gpt_ops = {
 430     .read = imx_gpt_read,
 431     .write = imx_gpt_write,
 432     .endianness = DEVICE_NATIVE_ENDIAN,
 433 };
 434
 435
 436 static void imx_gpt_realize(DeviceState *dev, Error **errp)
 437 {
 438     IMXGPTState *s = IMX_GPT(dev);
 439     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 440     QEMUBH *bh;
 441
 442     sysbus_init_irq(sbd, &s->irq);
 443     memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT,
 444                           0x00001000);
 445     sysbus_init_mmio(sbd, &s->iomem);
 446
 447     bh = qemu_bh_new(imx_gpt_timeout, s);
 448     s->timer = ptimer_init(bh);
 449 }
 450
 451 static void imx_gpt_class_init(ObjectClass *klass, void *data)
 452 {
 453     DeviceClass *dc = DEVICE_CLASS(klass);
 454
 455     dc->realize = imx_gpt_realize;
 456     dc->reset = imx_gpt_reset;
 457     dc->vmsd = &vmstate_imx_timer_gpt;
 458     dc->desc = "i.MX general timer";
 459 }
 460
 461 static const TypeInfo imx_gpt_info = {
 462     .name = TYPE_IMX_GPT,
 463     .parent = TYPE_SYS_BUS_DEVICE,
 464     .instance_size = sizeof(IMXGPTState),
 465     .class_init = imx_gpt_class_init,
 466 };
 467
 468 static void imx_gpt_register_types(void)
 469 {
 470     type_register_static(&imx_gpt_info);
 471 }
 472
 473 type_init(imx_gpt_register_types)