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ppc: Convert PPC UIC to a QOM device
[qemu/ar7.git] / hw / ppc / ppc4xx_devs.c
blobffe4cf43e88637e47f345da102ecda56dd5c831f
1 /*
2 * QEMU PowerPC 4xx embedded processors shared devices emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "sysemu/reset.h"
28 #include "cpu.h"
29 #include "hw/irq.h"
30 #include "hw/ppc/ppc.h"
31 #include "hw/ppc/ppc4xx.h"
32 #include "hw/boards.h"
33 #include "hw/intc/ppc-uic.h"
34 #include "hw/qdev-properties.h"
35 #include "qemu/log.h"
36 #include "exec/address-spaces.h"
37 #include "qemu/error-report.h"
38 #include "qapi/error.h"
39
40 /*#define DEBUG_UIC*/
41
42 #ifdef DEBUG_UIC
43 # define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
44 #else
45 # define LOG_UIC(...) do { } while (0)
46 #endif
47
48 static void ppc4xx_reset(void *opaque)
49 {
50 PowerPCCPU *cpu = opaque;
51
52 cpu_reset(CPU(cpu));
53 }
54
55 /*****************************************************************************/
56 /* Generic PowerPC 4xx processor instantiation */
57 PowerPCCPU *ppc4xx_init(const char *cpu_type,
58 clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
59 uint32_t sysclk)
60 {
61 PowerPCCPU *cpu;
62 CPUPPCState *env;
63
64 /* init CPUs */
65 cpu = POWERPC_CPU(cpu_create(cpu_type));
66 env = &cpu->env;
67
68 cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
69 cpu_clk->opaque = env;
70 /* Set time-base frequency to sysclk */
71 tb_clk->cb = ppc_40x_timers_init(env, sysclk, PPC_INTERRUPT_PIT);
72 tb_clk->opaque = env;
73 ppc_dcr_init(env, NULL, NULL);
74 /* Register qemu callbacks */
75 qemu_register_reset(ppc4xx_reset, cpu);
76
77 return cpu;
78 }
79
80 /*****************************************************************************/
81 /* "Universal" Interrupt controller */
82
83 qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
84 uint32_t dcr_base, int has_ssr, int has_vr)
85 {
86 DeviceState *uicdev = qdev_new(TYPE_PPC_UIC);
87 SysBusDevice *uicsbd = SYS_BUS_DEVICE(uicdev);
88 qemu_irq *uic_irqs;
89 int i;
90
91 qdev_prop_set_uint32(uicdev, "dcr-base", dcr_base);
92 qdev_prop_set_bit(uicdev, "use-vectors", has_vr);
93 object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(env_cpu(env)),
94 &error_fatal);
95 sysbus_realize_and_unref(uicsbd, &error_fatal);
96
97 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, irqs[PPCUIC_OUTPUT_INT]);
98 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, irqs[PPCUIC_OUTPUT_CINT]);
99
100 /*
101 * Return an allocated array of the UIC's input IRQ lines.
102 * This is an ugly temporary API to retain compatibility with
103 * the ppcuic_init() interface from the pre-QOM-conversion UIC.
104 * None of the callers free this array, so it is leaked -- but
105 * so was the array allocated by qemu_allocate_irqs() in the
106 * old code.
107 *
108 * The callers should just instantiate the UIC and wire it up
109 * themselves rather than passing qemu_irq* in and out of this function.
110 */
111 uic_irqs = g_new0(qemu_irq, UIC_MAX_IRQ);
112 for (i = 0; i < UIC_MAX_IRQ; i++) {
113 uic_irqs[i] = qdev_get_gpio_in(uicdev, i);
114 }
115 return uic_irqs;
116 }
117
118 /*****************************************************************************/
119 /* SDRAM controller */
120 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
121 struct ppc4xx_sdram_t {
122 uint32_t addr;
123 int nbanks;
124 MemoryRegion containers[4]; /* used for clipping */
125 MemoryRegion *ram_memories;
126 hwaddr ram_bases[4];
127 hwaddr ram_sizes[4];
128 uint32_t besr0;
129 uint32_t besr1;
130 uint32_t bear;
131 uint32_t cfg;
132 uint32_t status;
133 uint32_t rtr;
134 uint32_t pmit;
135 uint32_t bcr[4];
136 uint32_t tr;
137 uint32_t ecccfg;
138 uint32_t eccesr;
139 qemu_irq irq;
140 };
141
142 enum {
143 SDRAM0_CFGADDR = 0x010,
144 SDRAM0_CFGDATA = 0x011,
145 };
146
147 /* XXX: TOFIX: some patches have made this code become inconsistent:
148 * there are type inconsistencies, mixing hwaddr, target_ulong
149 * and uint32_t
150 */
151 static uint32_t sdram_bcr (hwaddr ram_base,
152 hwaddr ram_size)
153 {
154 uint32_t bcr;
155
156 switch (ram_size) {
157 case 4 * MiB:
158 bcr = 0x00000000;
159 break;
160 case 8 * MiB:
161 bcr = 0x00020000;
162 break;
163 case 16 * MiB:
164 bcr = 0x00040000;
165 break;
166 case 32 * MiB:
167 bcr = 0x00060000;
168 break;
169 case 64 * MiB:
170 bcr = 0x00080000;
171 break;
172 case 128 * MiB:
173 bcr = 0x000A0000;
174 break;
175 case 256 * MiB:
176 bcr = 0x000C0000;
177 break;
178 default:
179 printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__,
180 ram_size);
181 return 0x00000000;
182 }
183 bcr |= ram_base & 0xFF800000;
184 bcr |= 1;
185
186 return bcr;
187 }
188
189 static inline hwaddr sdram_base(uint32_t bcr)
190 {
191 return bcr & 0xFF800000;
192 }
193
194 static target_ulong sdram_size (uint32_t bcr)
195 {
196 target_ulong size;
197 int sh;
198
199 sh = (bcr >> 17) & 0x7;
200 if (sh == 7)
201 size = -1;
202 else
203 size = (4 * MiB) << sh;
204
205 return size;
206 }
207
208 static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
209 uint32_t bcr, int enabled)
210 {
211 if (sdram->bcr[i] & 0x00000001) {
212 /* Unmap RAM */
213 #ifdef DEBUG_SDRAM
214 printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
215 __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
216 #endif
217 memory_region_del_subregion(get_system_memory(),
218 &sdram->containers[i]);
219 memory_region_del_subregion(&sdram->containers[i],
220 &sdram->ram_memories[i]);
221 object_unparent(OBJECT(&sdram->containers[i]));
222 }
223 sdram->bcr[i] = bcr & 0xFFDEE001;
224 if (enabled && (bcr & 0x00000001)) {
225 #ifdef DEBUG_SDRAM
226 printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
227 __func__, sdram_base(bcr), sdram_size(bcr));
228 #endif
229 memory_region_init(&sdram->containers[i], NULL, "sdram-containers",
230 sdram_size(bcr));
231 memory_region_add_subregion(&sdram->containers[i], 0,
232 &sdram->ram_memories[i]);
233 memory_region_add_subregion(get_system_memory(),
234 sdram_base(bcr),
235 &sdram->containers[i]);
236 }
237 }
238
239 static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
240 {
241 int i;
242
243 for (i = 0; i < sdram->nbanks; i++) {
244 if (sdram->ram_sizes[i] != 0) {
245 sdram_set_bcr(sdram, i, sdram_bcr(sdram->ram_bases[i],
246 sdram->ram_sizes[i]), 1);
247 } else {
248 sdram_set_bcr(sdram, i, 0x00000000, 0);
249 }
250 }
251 }
252
253 static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
254 {
255 int i;
256
257 for (i = 0; i < sdram->nbanks; i++) {
258 #ifdef DEBUG_SDRAM
259 printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
260 __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
261 #endif
262 memory_region_del_subregion(get_system_memory(),
263 &sdram->ram_memories[i]);
264 }
265 }
266
267 static uint32_t dcr_read_sdram (void *opaque, int dcrn)
268 {
269 ppc4xx_sdram_t *sdram;
270 uint32_t ret;
271
272 sdram = opaque;
273 switch (dcrn) {
274 case SDRAM0_CFGADDR:
275 ret = sdram->addr;
276 break;
277 case SDRAM0_CFGDATA:
278 switch (sdram->addr) {
279 case 0x00: /* SDRAM_BESR0 */
280 ret = sdram->besr0;
281 break;
282 case 0x08: /* SDRAM_BESR1 */
283 ret = sdram->besr1;
284 break;
285 case 0x10: /* SDRAM_BEAR */
286 ret = sdram->bear;
287 break;
288 case 0x20: /* SDRAM_CFG */
289 ret = sdram->cfg;
290 break;
291 case 0x24: /* SDRAM_STATUS */
292 ret = sdram->status;
293 break;
294 case 0x30: /* SDRAM_RTR */
295 ret = sdram->rtr;
296 break;
297 case 0x34: /* SDRAM_PMIT */
298 ret = sdram->pmit;
299 break;
300 case 0x40: /* SDRAM_B0CR */
301 ret = sdram->bcr[0];
302 break;
303 case 0x44: /* SDRAM_B1CR */
304 ret = sdram->bcr[1];
305 break;
306 case 0x48: /* SDRAM_B2CR */
307 ret = sdram->bcr[2];
308 break;
309 case 0x4C: /* SDRAM_B3CR */
310 ret = sdram->bcr[3];
311 break;
312 case 0x80: /* SDRAM_TR */
313 ret = -1; /* ? */
314 break;
315 case 0x94: /* SDRAM_ECCCFG */
316 ret = sdram->ecccfg;
317 break;
318 case 0x98: /* SDRAM_ECCESR */
319 ret = sdram->eccesr;
320 break;
321 default: /* Error */
322 ret = -1;
323 break;
324 }
325 break;
326 default:
327 /* Avoid gcc warning */
328 ret = 0x00000000;
329 break;
330 }
331
332 return ret;
333 }
334
335 static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val)
336 {
337 ppc4xx_sdram_t *sdram;
338
339 sdram = opaque;
340 switch (dcrn) {
341 case SDRAM0_CFGADDR:
342 sdram->addr = val;
343 break;
344 case SDRAM0_CFGDATA:
345 switch (sdram->addr) {
346 case 0x00: /* SDRAM_BESR0 */
347 sdram->besr0 &= ~val;
348 break;
349 case 0x08: /* SDRAM_BESR1 */
350 sdram->besr1 &= ~val;
351 break;
352 case 0x10: /* SDRAM_BEAR */
353 sdram->bear = val;
354 break;
355 case 0x20: /* SDRAM_CFG */
356 val &= 0xFFE00000;
357 if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
358 #ifdef DEBUG_SDRAM
359 printf("%s: enable SDRAM controller\n", __func__);
360 #endif
361 /* validate all RAM mappings */
362 sdram_map_bcr(sdram);
363 sdram->status &= ~0x80000000;
364 } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
365 #ifdef DEBUG_SDRAM
366 printf("%s: disable SDRAM controller\n", __func__);
367 #endif
368 /* invalidate all RAM mappings */
369 sdram_unmap_bcr(sdram);
370 sdram->status |= 0x80000000;
371 }
372 if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
373 sdram->status |= 0x40000000;
374 else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
375 sdram->status &= ~0x40000000;
376 sdram->cfg = val;
377 break;
378 case 0x24: /* SDRAM_STATUS */
379 /* Read-only register */
380 break;
381 case 0x30: /* SDRAM_RTR */
382 sdram->rtr = val & 0x3FF80000;
383 break;
384 case 0x34: /* SDRAM_PMIT */
385 sdram->pmit = (val & 0xF8000000) | 0x07C00000;
386 break;
387 case 0x40: /* SDRAM_B0CR */
388 sdram_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000);
389 break;
390 case 0x44: /* SDRAM_B1CR */
391 sdram_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000);
392 break;
393 case 0x48: /* SDRAM_B2CR */
394 sdram_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000);
395 break;
396 case 0x4C: /* SDRAM_B3CR */
397 sdram_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000);
398 break;
399 case 0x80: /* SDRAM_TR */
400 sdram->tr = val & 0x018FC01F;
401 break;
402 case 0x94: /* SDRAM_ECCCFG */
403 sdram->ecccfg = val & 0x00F00000;
404 break;
405 case 0x98: /* SDRAM_ECCESR */
406 val &= 0xFFF0F000;
407 if (sdram->eccesr == 0 && val != 0)
408 qemu_irq_raise(sdram->irq);
409 else if (sdram->eccesr != 0 && val == 0)
410 qemu_irq_lower(sdram->irq);
411 sdram->eccesr = val;
412 break;
413 default: /* Error */
414 break;
415 }
416 break;
417 }
418 }
419
420 static void sdram_reset (void *opaque)
421 {
422 ppc4xx_sdram_t *sdram;
423
424 sdram = opaque;
425 sdram->addr = 0x00000000;
426 sdram->bear = 0x00000000;
427 sdram->besr0 = 0x00000000; /* No error */
428 sdram->besr1 = 0x00000000; /* No error */
429 sdram->cfg = 0x00000000;
430 sdram->ecccfg = 0x00000000; /* No ECC */
431 sdram->eccesr = 0x00000000; /* No error */
432 sdram->pmit = 0x07C00000;
433 sdram->rtr = 0x05F00000;
434 sdram->tr = 0x00854009;
435 /* We pre-initialize RAM banks */
436 sdram->status = 0x00000000;
437 sdram->cfg = 0x00800000;
438 }
439
440 void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
441 MemoryRegion *ram_memories,
442 hwaddr *ram_bases,
443 hwaddr *ram_sizes,
444 int do_init)
445 {
446 ppc4xx_sdram_t *sdram;
447
448 sdram = g_malloc0(sizeof(ppc4xx_sdram_t));
449 sdram->irq = irq;
450 sdram->nbanks = nbanks;
451 sdram->ram_memories = ram_memories;
452 memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr));
453 memcpy(sdram->ram_bases, ram_bases,
454 nbanks * sizeof(hwaddr));
455 memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr));
456 memcpy(sdram->ram_sizes, ram_sizes,
457 nbanks * sizeof(hwaddr));
458 qemu_register_reset(&sdram_reset, sdram);
459 ppc_dcr_register(env, SDRAM0_CFGADDR,
460 sdram, &dcr_read_sdram, &dcr_write_sdram);
461 ppc_dcr_register(env, SDRAM0_CFGDATA,
462 sdram, &dcr_read_sdram, &dcr_write_sdram);
463 if (do_init)
464 sdram_map_bcr(sdram);
465 }
466
467 /*
468 * Split RAM between SDRAM banks.
469 *
470 * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1]
471 * and must be 0-terminated.
472 *
473 * The 4xx SDRAM controller supports a small number of banks, and each bank
474 * must be one of a small set of sizes. The number of banks and the supported
475 * sizes varies by SoC.
476 */
477 void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
478 MemoryRegion ram_memories[],
479 hwaddr ram_bases[], hwaddr ram_sizes[],
480 const ram_addr_t sdram_bank_sizes[])
481 {
482 ram_addr_t size_left = memory_region_size(ram);
483 ram_addr_t base = 0;
484 ram_addr_t bank_size;
485 int i;
486 int j;
487
488 for (i = 0; i < nr_banks; i++) {
489 for (j = 0; sdram_bank_sizes[j] != 0; j++) {
490 bank_size = sdram_bank_sizes[j];
491 if (bank_size <= size_left) {
492 char name[32];
493
494 ram_bases[i] = base;
495 ram_sizes[i] = bank_size;
496 base += bank_size;
497 size_left -= bank_size;
498 snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
499 memory_region_init_alias(&ram_memories[i], NULL, name, ram,
500 ram_bases[i], ram_sizes[i]);
501 break;
502 }
503 }
504 if (!size_left) {
505 /* No need to use the remaining banks. */
506 break;
507 }
508 }
509
510 if (size_left) {
511 ram_addr_t used_size = memory_region_size(ram) - size_left;
512 GString *s = g_string_new(NULL);
513
514 for (i = 0; sdram_bank_sizes[i]; i++) {
515 g_string_append_printf(s, "%" PRIi64 "%s",
516 sdram_bank_sizes[i] / MiB,
517 sdram_bank_sizes[i + 1] ? ", " : "");
518 }
519 error_report("at most %d bank%s of %s MiB each supported",
520 nr_banks, nr_banks == 1 ? "" : "s", s->str);
521 error_printf("Possible valid RAM size: %" PRIi64 " MiB \n",
522 used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB);
523
524 g_string_free(s, true);
525 exit(EXIT_FAILURE);
526 }
527 }
528
529 /*****************************************************************************/
530 /* MAL */
531
532 enum {
533 MAL0_CFG = 0x180,
534 MAL0_ESR = 0x181,
535 MAL0_IER = 0x182,
536 MAL0_TXCASR = 0x184,
537 MAL0_TXCARR = 0x185,
538 MAL0_TXEOBISR = 0x186,
539 MAL0_TXDEIR = 0x187,
540 MAL0_RXCASR = 0x190,
541 MAL0_RXCARR = 0x191,
542 MAL0_RXEOBISR = 0x192,
543 MAL0_RXDEIR = 0x193,
544 MAL0_TXCTP0R = 0x1A0,
545 MAL0_RXCTP0R = 0x1C0,
546 MAL0_RCBS0 = 0x1E0,
547 MAL0_RCBS1 = 0x1E1,
548 };
549
550 typedef struct ppc4xx_mal_t ppc4xx_mal_t;
551 struct ppc4xx_mal_t {
552 qemu_irq irqs[4];
553 uint32_t cfg;
554 uint32_t esr;
555 uint32_t ier;
556 uint32_t txcasr;
557 uint32_t txcarr;
558 uint32_t txeobisr;
559 uint32_t txdeir;
560 uint32_t rxcasr;
561 uint32_t rxcarr;
562 uint32_t rxeobisr;
563 uint32_t rxdeir;
564 uint32_t *txctpr;
565 uint32_t *rxctpr;
566 uint32_t *rcbs;
567 uint8_t txcnum;
568 uint8_t rxcnum;
569 };
570
571 static void ppc4xx_mal_reset(void *opaque)
572 {
573 ppc4xx_mal_t *mal;
574
575 mal = opaque;
576 mal->cfg = 0x0007C000;
577 mal->esr = 0x00000000;
578 mal->ier = 0x00000000;
579 mal->rxcasr = 0x00000000;
580 mal->rxdeir = 0x00000000;
581 mal->rxeobisr = 0x00000000;
582 mal->txcasr = 0x00000000;
583 mal->txdeir = 0x00000000;
584 mal->txeobisr = 0x00000000;
585 }
586
587 static uint32_t dcr_read_mal(void *opaque, int dcrn)
588 {
589 ppc4xx_mal_t *mal;
590 uint32_t ret;
591
592 mal = opaque;
593 switch (dcrn) {
594 case MAL0_CFG:
595 ret = mal->cfg;
596 break;
597 case MAL0_ESR:
598 ret = mal->esr;
599 break;
600 case MAL0_IER:
601 ret = mal->ier;
602 break;
603 case MAL0_TXCASR:
604 ret = mal->txcasr;
605 break;
606 case MAL0_TXCARR:
607 ret = mal->txcarr;
608 break;
609 case MAL0_TXEOBISR:
610 ret = mal->txeobisr;
611 break;
612 case MAL0_TXDEIR:
613 ret = mal->txdeir;
614 break;
615 case MAL0_RXCASR:
616 ret = mal->rxcasr;
617 break;
618 case MAL0_RXCARR:
619 ret = mal->rxcarr;
620 break;
621 case MAL0_RXEOBISR:
622 ret = mal->rxeobisr;
623 break;
624 case MAL0_RXDEIR:
625 ret = mal->rxdeir;
626 break;
627 default:
628 ret = 0;
629 break;
630 }
631 if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
632 ret = mal->txctpr[dcrn - MAL0_TXCTP0R];
633 }
634 if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {
635 ret = mal->rxctpr[dcrn - MAL0_RXCTP0R];
636 }
637 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
638 ret = mal->rcbs[dcrn - MAL0_RCBS0];
639 }
640
641 return ret;
642 }
643
644 static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
645 {
646 ppc4xx_mal_t *mal;
647
648 mal = opaque;
649 switch (dcrn) {
650 case MAL0_CFG:
651 if (val & 0x80000000) {
652 ppc4xx_mal_reset(mal);
653 }
654 mal->cfg = val & 0x00FFC087;
655 break;
656 case MAL0_ESR:
657 /* Read/clear */
658 mal->esr &= ~val;
659 break;
660 case MAL0_IER:
661 mal->ier = val & 0x0000001F;
662 break;
663 case MAL0_TXCASR:
664 mal->txcasr = val & 0xF0000000;
665 break;
666 case MAL0_TXCARR:
667 mal->txcarr = val & 0xF0000000;
668 break;
669 case MAL0_TXEOBISR:
670 /* Read/clear */
671 mal->txeobisr &= ~val;
672 break;
673 case MAL0_TXDEIR:
674 /* Read/clear */
675 mal->txdeir &= ~val;
676 break;
677 case MAL0_RXCASR:
678 mal->rxcasr = val & 0xC0000000;
679 break;
680 case MAL0_RXCARR:
681 mal->rxcarr = val & 0xC0000000;
682 break;
683 case MAL0_RXEOBISR:
684 /* Read/clear */
685 mal->rxeobisr &= ~val;
686 break;
687 case MAL0_RXDEIR:
688 /* Read/clear */
689 mal->rxdeir &= ~val;
690 break;
691 }
692 if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
693 mal->txctpr[dcrn - MAL0_TXCTP0R] = val;
694 }
695 if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {
696 mal->rxctpr[dcrn - MAL0_RXCTP0R] = val;
697 }
698 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
699 mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF;
700 }
701 }
702
703 void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
704 qemu_irq irqs[4])
705 {
706 ppc4xx_mal_t *mal;
707 int i;
708
709 assert(txcnum <= 32 && rxcnum <= 32);
710 mal = g_malloc0(sizeof(*mal));
711 mal->txcnum = txcnum;
712 mal->rxcnum = rxcnum;
713 mal->txctpr = g_new0(uint32_t, txcnum);
714 mal->rxctpr = g_new0(uint32_t, rxcnum);
715 mal->rcbs = g_new0(uint32_t, rxcnum);
716 for (i = 0; i < 4; i++) {
717 mal->irqs[i] = irqs[i];
718 }
719 qemu_register_reset(&ppc4xx_mal_reset, mal);
720 ppc_dcr_register(env, MAL0_CFG,
721 mal, &dcr_read_mal, &dcr_write_mal);
722 ppc_dcr_register(env, MAL0_ESR,
723 mal, &dcr_read_mal, &dcr_write_mal);
724 ppc_dcr_register(env, MAL0_IER,
725 mal, &dcr_read_mal, &dcr_write_mal);
726 ppc_dcr_register(env, MAL0_TXCASR,
727 mal, &dcr_read_mal, &dcr_write_mal);
728 ppc_dcr_register(env, MAL0_TXCARR,
729 mal, &dcr_read_mal, &dcr_write_mal);
730 ppc_dcr_register(env, MAL0_TXEOBISR,
731 mal, &dcr_read_mal, &dcr_write_mal);
732 ppc_dcr_register(env, MAL0_TXDEIR,
733 mal, &dcr_read_mal, &dcr_write_mal);
734 ppc_dcr_register(env, MAL0_RXCASR,
735 mal, &dcr_read_mal, &dcr_write_mal);
736 ppc_dcr_register(env, MAL0_RXCARR,
737 mal, &dcr_read_mal, &dcr_write_mal);
738 ppc_dcr_register(env, MAL0_RXEOBISR,
739 mal, &dcr_read_mal, &dcr_write_mal);
740 ppc_dcr_register(env, MAL0_RXDEIR,
741 mal, &dcr_read_mal, &dcr_write_mal);
742 for (i = 0; i < txcnum; i++) {
743 ppc_dcr_register(env, MAL0_TXCTP0R + i,
744 mal, &dcr_read_mal, &dcr_write_mal);
745 }
746 for (i = 0; i < rxcnum; i++) {
747 ppc_dcr_register(env, MAL0_RXCTP0R + i,
748 mal, &dcr_read_mal, &dcr_write_mal);
749 }
750 for (i = 0; i < rxcnum; i++) {
751 ppc_dcr_register(env, MAL0_RCBS0 + i,
752 mal, &dcr_read_mal, &dcr_write_mal);
753 }
754 }
AR7 emulation for QEMU