hw/arm/realview.c

   1 /*
   2  * ARM RealView Baseboard System emulation.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "hw/sysbus.h"
  11 #include "hw/arm/arm.h"
  12 #include "hw/arm/primecell.h"
  13 #include "hw/devices.h"
  14 #include "hw/pci/pci.h"
  15 #include "net/net.h"
  16 #include "sysemu/sysemu.h"
  17 #include "hw/boards.h"
  18 #include "hw/i2c/i2c.h"
  19 #include "sysemu/block-backend.h"
  20 #include "exec/address-spaces.h"
  21 #include "qemu/error-report.h"
  22
  23 #define SMP_BOOT_ADDR 0xe0000000
  24 #define SMP_BOOTREG_ADDR 0x10000030
  25
  26 /* Board init.  */
  27
  28 static struct arm_boot_info realview_binfo = {
  29     .smp_loader_start = SMP_BOOT_ADDR,
  30     .smp_bootreg_addr = SMP_BOOTREG_ADDR,
  31 };
  32
  33 /* The following two lists must be consistent.  */
  34 enum realview_board_type {
  35     BOARD_EB,
  36     BOARD_EB_MPCORE,
  37     BOARD_PB_A8,
  38     BOARD_PBX_A9,
  39 };
  40
  41 static const int realview_board_id[] = {
  42     0x33b,
  43     0x33b,
  44     0x769,
  45     0x76d
  46 };
  47
  48 static void realview_init(MachineState *machine,
  49                           enum realview_board_type board_type)
  50 {
  51     ARMCPU *cpu = NULL;
  52     CPUARMState *env;
  53     ObjectClass *cpu_oc;
  54     MemoryRegion *sysmem = get_system_memory();
  55     MemoryRegion *ram_lo;
  56     MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
  57     MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
  58     MemoryRegion *ram_hack = g_new(MemoryRegion, 1);
  59     DeviceState *dev, *sysctl, *gpio2, *pl041;
  60     SysBusDevice *busdev;
  61     qemu_irq pic[64];
  62     qemu_irq mmc_irq[2];
  63     PCIBus *pci_bus = NULL;
  64     NICInfo *nd;
  65     I2CBus *i2c;
  66     int n;
  67     int done_nic = 0;
  68     qemu_irq cpu_irq[4];
  69     int is_mpcore = 0;
  70     int is_pb = 0;
  71     uint32_t proc_id = 0;
  72     uint32_t sys_id;
  73     ram_addr_t low_ram_size;
  74     ram_addr_t ram_size = machine->ram_size;
  75     hwaddr periphbase = 0;
  76
  77     switch (board_type) {
  78     case BOARD_EB:
  79         break;
  80     case BOARD_EB_MPCORE:
  81         is_mpcore = 1;
  82         periphbase = 0x10100000;
  83         break;
  84     case BOARD_PB_A8:
  85         is_pb = 1;
  86         break;
  87     case BOARD_PBX_A9:
  88         is_mpcore = 1;
  89         is_pb = 1;
  90         periphbase = 0x1f000000;
  91         break;
  92     }
  93
  94     cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model);
  95     if (!cpu_oc) {
  96         fprintf(stderr, "Unable to find CPU definition\n");
  97         exit(1);
  98     }
  99
 100     for (n = 0; n < smp_cpus; n++) {
 101         Object *cpuobj = object_new(object_class_get_name(cpu_oc));
 102         Error *err = NULL;
 103
 104         /* By default A9,A15 and ARM1176 CPUs have EL3 enabled.  This board
 105          * does not currently support EL3 so the CPU EL3 property is disabled
 106          * before realization.
 107          */
 108         if (object_property_find(cpuobj, "has_el3", NULL)) {
 109             object_property_set_bool(cpuobj, false, "has_el3", &err);
 110             if (err) {
 111                 error_report_err(err);
 112                 exit(1);
 113             }
 114         }
 115
 116         if (is_pb && is_mpcore) {
 117             object_property_set_int(cpuobj, periphbase, "reset-cbar", &err);
 118             if (err) {
 119                 error_report_err(err);
 120                 exit(1);
 121             }
 122         }
 123
 124         object_property_set_bool(cpuobj, true, "realized", &err);
 125         if (err) {
 126             error_report_err(err);
 127             exit(1);
 128         }
 129
 130         cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ);
 131     }
 132     cpu = ARM_CPU(first_cpu);
 133     env = &cpu->env;
 134     if (arm_feature(env, ARM_FEATURE_V7)) {
 135         if (is_mpcore) {
 136             proc_id = 0x0c000000;
 137         } else {
 138             proc_id = 0x0e000000;
 139         }
 140     } else if (arm_feature(env, ARM_FEATURE_V6K)) {
 141         proc_id = 0x06000000;
 142     } else if (arm_feature(env, ARM_FEATURE_V6)) {
 143         proc_id = 0x04000000;
 144     } else {
 145         proc_id = 0x02000000;
 146     }
 147
 148     if (is_pb && ram_size > 0x20000000) {
 149         /* Core tile RAM.  */
 150         ram_lo = g_new(MemoryRegion, 1);
 151         low_ram_size = ram_size - 0x20000000;
 152         ram_size = 0x20000000;
 153         memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size,
 154                                &error_fatal);
 155         vmstate_register_ram_global(ram_lo);
 156         memory_region_add_subregion(sysmem, 0x20000000, ram_lo);
 157     }
 158
 159     memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size,
 160                            &error_fatal);
 161     vmstate_register_ram_global(ram_hi);
 162     low_ram_size = ram_size;
 163     if (low_ram_size > 0x10000000)
 164       low_ram_size = 0x10000000;
 165     /* SDRAM at address zero.  */
 166     memory_region_init_alias(ram_alias, NULL, "realview.alias",
 167                              ram_hi, 0, low_ram_size);
 168     memory_region_add_subregion(sysmem, 0, ram_alias);
 169     if (is_pb) {
 170         /* And again at a high address.  */
 171         memory_region_add_subregion(sysmem, 0x70000000, ram_hi);
 172     } else {
 173         ram_size = low_ram_size;
 174     }
 175
 176     sys_id = is_pb ? 0x01780500 : 0xc1400400;
 177     sysctl = qdev_create(NULL, "realview_sysctl");
 178     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 179     qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
 180     qdev_init_nofail(sysctl);
 181     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
 182
 183     if (is_mpcore) {
 184         dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore");
 185         qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 186         qdev_init_nofail(dev);
 187         busdev = SYS_BUS_DEVICE(dev);
 188         sysbus_mmio_map(busdev, 0, periphbase);
 189         for (n = 0; n < smp_cpus; n++) {
 190             sysbus_connect_irq(busdev, n, cpu_irq[n]);
 191         }
 192         sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL);
 193         /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */
 194         realview_binfo.gic_cpu_if_addr = periphbase + 0x100;
 195     } else {
 196         uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
 197         /* For now just create the nIRQ GIC, and ignore the others.  */
 198         dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]);
 199     }
 200     for (n = 0; n < 64; n++) {
 201         pic[n] = qdev_get_gpio_in(dev, n);
 202     }
 203
 204     pl041 = qdev_create(NULL, "pl041");
 205     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 206     qdev_init_nofail(pl041);
 207     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
 208     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]);
 209
 210     sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
 211     sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);
 212
 213     sysbus_create_simple("pl011", 0x10009000, pic[12]);
 214     sysbus_create_simple("pl011", 0x1000a000, pic[13]);
 215     sysbus_create_simple("pl011", 0x1000b000, pic[14]);
 216     sysbus_create_simple("pl011", 0x1000c000, pic[15]);
 217
 218     /* DMA controller is optional, apparently.  */
 219     sysbus_create_simple("pl081", 0x10030000, pic[24]);
 220
 221     sysbus_create_simple("sp804", 0x10011000, pic[4]);
 222     sysbus_create_simple("sp804", 0x10012000, pic[5]);
 223
 224     sysbus_create_simple("pl061", 0x10013000, pic[6]);
 225     sysbus_create_simple("pl061", 0x10014000, pic[7]);
 226     gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]);
 227
 228     sysbus_create_simple("pl111", 0x10020000, pic[23]);
 229
 230     dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
 231     /* Wire up MMC card detect and read-only signals. These have
 232      * to go to both the PL061 GPIO and the sysctl register.
 233      * Note that the PL181 orders these lines (readonly,inserted)
 234      * and the PL061 has them the other way about. Also the card
 235      * detect line is inverted.
 236      */
 237     mmc_irq[0] = qemu_irq_split(
 238         qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
 239         qdev_get_gpio_in(gpio2, 1));
 240     mmc_irq[1] = qemu_irq_split(
 241         qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
 242         qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
 243     qdev_connect_gpio_out(dev, 0, mmc_irq[0]);
 244     qdev_connect_gpio_out(dev, 1, mmc_irq[1]);
 245
 246     sysbus_create_simple("pl031", 0x10017000, pic[10]);
 247
 248     if (!is_pb) {
 249         dev = qdev_create(NULL, "realview_pci");
 250         busdev = SYS_BUS_DEVICE(dev);
 251         qdev_init_nofail(dev);
 252         sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */
 253         sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */
 254         sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */
 255         sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */
 256         sysbus_mmio_map(busdev, 4, 0x63000000); /* PCI memory window 1 */
 257         sysbus_mmio_map(busdev, 5, 0x64000000); /* PCI memory window 2 */
 258         sysbus_mmio_map(busdev, 6, 0x68000000); /* PCI memory window 3 */
 259         sysbus_connect_irq(busdev, 0, pic[48]);
 260         sysbus_connect_irq(busdev, 1, pic[49]);
 261         sysbus_connect_irq(busdev, 2, pic[50]);
 262         sysbus_connect_irq(busdev, 3, pic[51]);
 263         pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
 264         if (usb_enabled()) {
 265             pci_create_simple(pci_bus, -1, "pci-ohci");
 266         }
 267         n = drive_get_max_bus(IF_SCSI);
 268         while (n >= 0) {
 269             pci_create_simple(pci_bus, -1, "lsi53c895a");
 270             n--;
 271         }
 272     }
 273     for(n = 0; n < nb_nics; n++) {
 274         nd = &nd_table[n];
 275
 276         if (!done_nic && (!nd->model ||
 277                     strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) {
 278             if (is_pb) {
 279                 lan9118_init(nd, 0x4e000000, pic[28]);
 280             } else {
 281                 smc91c111_init(nd, 0x4e000000, pic[28]);
 282             }
 283             done_nic = 1;
 284         } else {
 285             if (pci_bus) {
 286                 pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL);
 287             }
 288         }
 289     }
 290
 291     dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
 292     i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
 293     i2c_create_slave(i2c, "ds1338", 0x68);
 294
 295     /* Memory map for RealView Emulation Baseboard:  */
 296     /* 0x10000000 System registers.  */
 297     /*  0x10001000 System controller.  */
 298     /* 0x10002000 Two-Wire Serial Bus.  */
 299     /* 0x10003000 Reserved.  */
 300     /*  0x10004000 AACI.  */
 301     /*  0x10005000 MCI.  */
 302     /* 0x10006000 KMI0.  */
 303     /* 0x10007000 KMI1.  */
 304     /*  0x10008000 Character LCD. (EB) */
 305     /* 0x10009000 UART0.  */
 306     /* 0x1000a000 UART1.  */
 307     /* 0x1000b000 UART2.  */
 308     /* 0x1000c000 UART3.  */
 309     /*  0x1000d000 SSPI.  */
 310     /*  0x1000e000 SCI.  */
 311     /* 0x1000f000 Reserved.  */
 312     /*  0x10010000 Watchdog.  */
 313     /* 0x10011000 Timer 0+1.  */
 314     /* 0x10012000 Timer 2+3.  */
 315     /*  0x10013000 GPIO 0.  */
 316     /*  0x10014000 GPIO 1.  */
 317     /*  0x10015000 GPIO 2.  */
 318     /*  0x10002000 Two-Wire Serial Bus - DVI. (PB) */
 319     /* 0x10017000 RTC.  */
 320     /*  0x10018000 DMC.  */
 321     /*  0x10019000 PCI controller config.  */
 322     /*  0x10020000 CLCD.  */
 323     /* 0x10030000 DMA Controller.  */
 324     /* 0x10040000 GIC1. (EB) */
 325     /*  0x10050000 GIC2. (EB) */
 326     /*  0x10060000 GIC3. (EB) */
 327     /*  0x10070000 GIC4. (EB) */
 328     /*  0x10080000 SMC.  */
 329     /* 0x1e000000 GIC1. (PB) */
 330     /*  0x1e001000 GIC2. (PB) */
 331     /*  0x1e002000 GIC3. (PB) */
 332     /*  0x1e003000 GIC4. (PB) */
 333     /*  0x40000000 NOR flash.  */
 334     /*  0x44000000 DoC flash.  */
 335     /*  0x48000000 SRAM.  */
 336     /*  0x4c000000 Configuration flash.  */
 337     /* 0x4e000000 Ethernet.  */
 338     /*  0x4f000000 USB.  */
 339     /*  0x50000000 PISMO.  */
 340     /*  0x54000000 PISMO.  */
 341     /*  0x58000000 PISMO.  */
 342     /*  0x5c000000 PISMO.  */
 343     /* 0x60000000 PCI.  */
 344     /* 0x60000000 PCI Self Config.  */
 345     /* 0x61000000 PCI Config.  */
 346     /* 0x62000000 PCI IO.  */
 347     /* 0x63000000 PCI mem 0.  */
 348     /* 0x64000000 PCI mem 1.  */
 349     /* 0x68000000 PCI mem 2.  */
 350
 351     /* ??? Hack to map an additional page of ram for the secondary CPU
 352        startup code.  I guess this works on real hardware because the
 353        BootROM happens to be in ROM/flash or in memory that isn't clobbered
 354        until after Linux boots the secondary CPUs.  */
 355     memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000,
 356                            &error_fatal);
 357     vmstate_register_ram_global(ram_hack);
 358     memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack);
 359
 360     realview_binfo.ram_size = ram_size;
 361     realview_binfo.kernel_filename = machine->kernel_filename;
 362     realview_binfo.kernel_cmdline = machine->kernel_cmdline;
 363     realview_binfo.initrd_filename = machine->initrd_filename;
 364     realview_binfo.nb_cpus = smp_cpus;
 365     realview_binfo.board_id = realview_board_id[board_type];
 366     realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
 367     arm_load_kernel(ARM_CPU(first_cpu), &realview_binfo);
 368 }
 369
 370 static void realview_eb_init(MachineState *machine)
 371 {
 372     if (!machine->cpu_model) {
 373         machine->cpu_model = "arm926";
 374     }
 375     realview_init(machine, BOARD_EB);
 376 }
 377
 378 static void realview_eb_mpcore_init(MachineState *machine)
 379 {
 380     if (!machine->cpu_model) {
 381         machine->cpu_model = "arm11mpcore";
 382     }
 383     realview_init(machine, BOARD_EB_MPCORE);
 384 }
 385
 386 static void realview_pb_a8_init(MachineState *machine)
 387 {
 388     if (!machine->cpu_model) {
 389         machine->cpu_model = "cortex-a8";
 390     }
 391     realview_init(machine, BOARD_PB_A8);
 392 }
 393
 394 static void realview_pbx_a9_init(MachineState *machine)
 395 {
 396     if (!machine->cpu_model) {
 397         machine->cpu_model = "cortex-a9";
 398     }
 399     realview_init(machine, BOARD_PBX_A9);
 400 }
 401
 402 static void realview_eb_class_init(ObjectClass *oc, void *data)
 403 {
 404     MachineClass *mc = MACHINE_CLASS(oc);
 405
 406     mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)";
 407     mc->init = realview_eb_init;
 408     mc->block_default_type = IF_SCSI;
 409 }
 410
 411 static const TypeInfo realview_eb_type = {
 412     .name = MACHINE_TYPE_NAME("realview-eb"),
 413     .parent = TYPE_MACHINE,
 414     .class_init = realview_eb_class_init,
 415 };
 416
 417 static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data)
 418 {
 419     MachineClass *mc = MACHINE_CLASS(oc);
 420
 421     mc->desc = "ARM RealView Emulation Baseboard (ARM11MPCore)";
 422     mc->init = realview_eb_mpcore_init;
 423     mc->block_default_type = IF_SCSI;
 424     mc->max_cpus = 4;
 425 }
 426
 427 static const TypeInfo realview_eb_mpcore_type = {
 428     .name = MACHINE_TYPE_NAME("realview-eb-mpcore"),
 429     .parent = TYPE_MACHINE,
 430     .class_init = realview_eb_mpcore_class_init,
 431 };
 432
 433 static void realview_pb_a8_class_init(ObjectClass *oc, void *data)
 434 {
 435     MachineClass *mc = MACHINE_CLASS(oc);
 436
 437     mc->desc = "ARM RealView Platform Baseboard for Cortex-A8";
 438     mc->init = realview_pb_a8_init;
 439 }
 440
 441 static const TypeInfo realview_pb_a8_type = {
 442     .name = MACHINE_TYPE_NAME("realview-pb-a8"),
 443     .parent = TYPE_MACHINE,
 444     .class_init = realview_pb_a8_class_init,
 445 };
 446
 447 static void realview_pbx_a9_class_init(ObjectClass *oc, void *data)
 448 {
 449     MachineClass *mc = MACHINE_CLASS(oc);
 450
 451     mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9";
 452     mc->init = realview_pbx_a9_init;
 453     mc->block_default_type = IF_SCSI;
 454     mc->max_cpus = 4;
 455 }
 456
 457 static const TypeInfo realview_pbx_a9_type = {
 458     .name = MACHINE_TYPE_NAME("realview-pbx-a9"),
 459     .parent = TYPE_MACHINE,
 460     .class_init = realview_pbx_a9_class_init,
 461 };
 462
 463 static void realview_machine_init(void)
 464 {
 465     type_register_static(&realview_eb_type);
 466     type_register_static(&realview_eb_mpcore_type);
 467     type_register_static(&realview_pb_a8_type);
 468     type_register_static(&realview_pbx_a9_type);
 469 }
 470
 471 machine_init(realview_machine_init)