hw/arm/pxa2xx_pic.c

   1 /*
   2  * Intel XScale PXA Programmable Interrupt Controller.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Copyright (c) 2006 Thorsten Zitterell
   6  * Written by Andrzej Zaborowski <balrog@zabor.org>
   7  *
   8  * This code is licensed under the GPL.
   9  */
  10
  11 #include "hw/hw.h"
  12 #include "hw/arm/pxa.h"
  13 #include "hw/sysbus.h"
  14
  15 #define ICIP    0x00    /* Interrupt Controller IRQ Pending register */
  16 #define ICMR    0x04    /* Interrupt Controller Mask register */
  17 #define ICLR    0x08    /* Interrupt Controller Level register */
  18 #define ICFP    0x0c    /* Interrupt Controller FIQ Pending register */
  19 #define ICPR    0x10    /* Interrupt Controller Pending register */
  20 #define ICCR    0x14    /* Interrupt Controller Control register */
  21 #define ICHP    0x18    /* Interrupt Controller Highest Priority register */
  22 #define IPR0    0x1c    /* Interrupt Controller Priority register 0 */
  23 #define IPR31   0x98    /* Interrupt Controller Priority register 31 */
  24 #define ICIP2   0x9c    /* Interrupt Controller IRQ Pending register 2 */
  25 #define ICMR2   0xa0    /* Interrupt Controller Mask register 2 */
  26 #define ICLR2   0xa4    /* Interrupt Controller Level register 2 */
  27 #define ICFP2   0xa8    /* Interrupt Controller FIQ Pending register 2 */
  28 #define ICPR2   0xac    /* Interrupt Controller Pending register 2 */
  29 #define IPR32   0xb0    /* Interrupt Controller Priority register 32 */
  30 #define IPR39   0xcc    /* Interrupt Controller Priority register 39 */
  31
  32 #define PXA2XX_PIC_SRCS 40
  33
  34 #define TYPE_PXA2XX_PIC "pxa2xx_pic"
  35 #define PXA2XX_PIC(obj) \
  36     OBJECT_CHECK(PXA2xxPICState, (obj), TYPE_PXA2XX_PIC)
  37
  38 typedef struct {
  39     /*< private >*/
  40     SysBusDevice parent_obj;
  41     /*< public >*/
  42
  43     MemoryRegion iomem;
  44     ARMCPU *cpu;
  45     uint32_t int_enabled[2];
  46     uint32_t int_pending[2];
  47     uint32_t is_fiq[2];
  48     uint32_t int_idle;
  49     uint32_t priority[PXA2XX_PIC_SRCS];
  50 } PXA2xxPICState;
  51
  52 static void pxa2xx_pic_update(void *opaque)
  53 {
  54     uint32_t mask[2];
  55     PXA2xxPICState *s = (PXA2xxPICState *) opaque;
  56     CPUState *cpu = CPU(s->cpu);
  57
  58     if (cpu->halted) {
  59         mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
  60         mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);
  61         if (mask[0] || mask[1]) {
  62             cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
  63         }
  64     }
  65
  66     mask[0] = s->int_pending[0] & s->int_enabled[0];
  67     mask[1] = s->int_pending[1] & s->int_enabled[1];
  68
  69     if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) {
  70         cpu_interrupt(cpu, CPU_INTERRUPT_FIQ);
  71     } else {
  72         cpu_reset_interrupt(cpu, CPU_INTERRUPT_FIQ);
  73     }
  74
  75     if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) {
  76         cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
  77     } else {
  78         cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
  79     }
  80 }
  81
  82 /* Note: Here level means state of the signal on a pin, not
  83  * IRQ/FIQ distinction as in PXA Developer Manual.  */
  84 static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
  85 {
  86     PXA2xxPICState *s = (PXA2xxPICState *) opaque;
  87     int int_set = (irq >= 32);
  88     irq &= 31;
  89
  90     if (level)
  91         s->int_pending[int_set] |= 1 << irq;
  92     else
  93         s->int_pending[int_set] &= ~(1 << irq);
  94
  95     pxa2xx_pic_update(opaque);
  96 }
  97
  98 static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
  99     int i, int_set, irq;
 100     uint32_t bit, mask[2];
 101     uint32_t ichp = 0x003f003f; /* Both IDs invalid */
 102
 103     mask[0] = s->int_pending[0] & s->int_enabled[0];
 104     mask[1] = s->int_pending[1] & s->int_enabled[1];
 105
 106     for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) {
 107         irq = s->priority[i] & 0x3f;
 108         if ((s->priority[i] & (1U << 31)) && irq < PXA2XX_PIC_SRCS) {
 109             /* Source peripheral ID is valid.  */
 110             bit = 1 << (irq & 31);
 111             int_set = (irq >= 32);
 112
 113             if (mask[int_set] & bit & s->is_fiq[int_set]) {
 114                 /* FIQ asserted */
 115                 ichp &= 0xffff0000;
 116                 ichp |= (1 << 15) | irq;
 117             }
 118
 119             if (mask[int_set] & bit & ~s->is_fiq[int_set]) {
 120                 /* IRQ asserted */
 121                 ichp &= 0x0000ffff;
 122                 ichp |= (1U << 31) | (irq << 16);
 123             }
 124         }
 125     }
 126
 127     return ichp;
 128 }
 129
 130 static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
 131                                     unsigned size)
 132 {
 133     PXA2xxPICState *s = (PXA2xxPICState *) opaque;
 134
 135     switch (offset) {
 136     case ICIP:  /* IRQ Pending register */
 137         return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0];
 138     case ICIP2: /* IRQ Pending register 2 */
 139         return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1];
 140     case ICMR:  /* Mask register */
 141         return s->int_enabled[0];
 142     case ICMR2: /* Mask register 2 */
 143         return s->int_enabled[1];
 144     case ICLR:  /* Level register */
 145         return s->is_fiq[0];
 146     case ICLR2: /* Level register 2 */
 147         return s->is_fiq[1];
 148     case ICCR:  /* Idle mask */
 149         return (s->int_idle == 0);
 150     case ICFP:  /* FIQ Pending register */
 151         return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0];
 152     case ICFP2: /* FIQ Pending register 2 */
 153         return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1];
 154     case ICPR:  /* Pending register */
 155         return s->int_pending[0];
 156     case ICPR2: /* Pending register 2 */
 157         return s->int_pending[1];
 158     case IPR0  ... IPR31:
 159         return s->priority[0  + ((offset - IPR0 ) >> 2)];
 160     case IPR32 ... IPR39:
 161         return s->priority[32 + ((offset - IPR32) >> 2)];
 162     case ICHP:  /* Highest Priority register */
 163         return pxa2xx_pic_highest(s);
 164     default:
 165         printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset);
 166         return 0;
 167     }
 168 }
 169
 170 static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
 171                                  uint64_t value, unsigned size)
 172 {
 173     PXA2xxPICState *s = (PXA2xxPICState *) opaque;
 174
 175     switch (offset) {
 176     case ICMR:  /* Mask register */
 177         s->int_enabled[0] = value;
 178         break;
 179     case ICMR2: /* Mask register 2 */
 180         s->int_enabled[1] = value;
 181         break;
 182     case ICLR:  /* Level register */
 183         s->is_fiq[0] = value;
 184         break;
 185     case ICLR2: /* Level register 2 */
 186         s->is_fiq[1] = value;
 187         break;
 188     case ICCR:  /* Idle mask */
 189         s->int_idle = (value & 1) ? 0 : ~0;
 190         break;
 191     case IPR0  ... IPR31:
 192         s->priority[0  + ((offset - IPR0 ) >> 2)] = value & 0x8000003f;
 193         break;
 194     case IPR32 ... IPR39:
 195         s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
 196         break;
 197     default:
 198         printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset);
 199         return;
 200     }
 201     pxa2xx_pic_update(opaque);
 202 }
 203
 204 /* Interrupt Controller Coprocessor Space Register Mapping */
 205 static const int pxa2xx_cp_reg_map[0x10] = {
 206     [0x0 ... 0xf] = -1,
 207     [0x0] = ICIP,
 208     [0x1] = ICMR,
 209     [0x2] = ICLR,
 210     [0x3] = ICFP,
 211     [0x4] = ICPR,
 212     [0x5] = ICHP,
 213     [0x6] = ICIP2,
 214     [0x7] = ICMR2,
 215     [0x8] = ICLR2,
 216     [0x9] = ICFP2,
 217     [0xa] = ICPR2,
 218 };
 219
 220 static uint64_t pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri)
 221 {
 222     int offset = pxa2xx_cp_reg_map[ri->crn];
 223     return pxa2xx_pic_mem_read(ri->opaque, offset, 4);
 224 }
 225
 226 static void pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri,
 227                                 uint64_t value)
 228 {
 229     int offset = pxa2xx_cp_reg_map[ri->crn];
 230     pxa2xx_pic_mem_write(ri->opaque, offset, value, 4);
 231 }
 232
 233 #define REGINFO_FOR_PIC_CP(NAME, CRN) \
 234     { .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \
 235       .access = PL1_RW, .type = ARM_CP_IO, \
 236       .readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write }
 237
 238 static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
 239     REGINFO_FOR_PIC_CP("ICIP", 0),
 240     REGINFO_FOR_PIC_CP("ICMR", 1),
 241     REGINFO_FOR_PIC_CP("ICLR", 2),
 242     REGINFO_FOR_PIC_CP("ICFP", 3),
 243     REGINFO_FOR_PIC_CP("ICPR", 4),
 244     REGINFO_FOR_PIC_CP("ICHP", 5),
 245     REGINFO_FOR_PIC_CP("ICIP2", 6),
 246     REGINFO_FOR_PIC_CP("ICMR2", 7),
 247     REGINFO_FOR_PIC_CP("ICLR2", 8),
 248     REGINFO_FOR_PIC_CP("ICFP2", 9),
 249     REGINFO_FOR_PIC_CP("ICPR2", 0xa),
 250     REGINFO_SENTINEL
 251 };
 252
 253 static const MemoryRegionOps pxa2xx_pic_ops = {
 254     .read = pxa2xx_pic_mem_read,
 255     .write = pxa2xx_pic_mem_write,
 256     .endianness = DEVICE_NATIVE_ENDIAN,
 257 };
 258
 259 static int pxa2xx_pic_post_load(void *opaque, int version_id)
 260 {
 261     pxa2xx_pic_update(opaque);
 262     return 0;
 263 }
 264
 265 DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
 266 {
 267     DeviceState *dev = qdev_create(NULL, TYPE_PXA2XX_PIC);
 268     PXA2xxPICState *s = PXA2XX_PIC(dev);
 269
 270     s->cpu = cpu;
 271
 272     s->int_pending[0] = 0;
 273     s->int_pending[1] = 0;
 274     s->int_enabled[0] = 0;
 275     s->int_enabled[1] = 0;
 276     s->is_fiq[0] = 0;
 277     s->is_fiq[1] = 0;
 278
 279     qdev_init_nofail(dev);
 280
 281     qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
 282
 283     /* Enable IC memory-mapped registers access.  */
 284     memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_pic_ops, s,
 285                           "pxa2xx-pic", 0x00100000);
 286     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 287     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 288
 289     /* Enable IC coprocessor access.  */
 290     define_arm_cp_regs_with_opaque(cpu, pxa_pic_cp_reginfo, s);
 291
 292     return dev;
 293 }
 294
 295 static VMStateDescription vmstate_pxa2xx_pic_regs = {
 296     .name = "pxa2xx_pic",
 297     .version_id = 0,
 298     .minimum_version_id = 0,
 299     .post_load = pxa2xx_pic_post_load,
 300     .fields = (VMStateField[]) {
 301         VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
 302         VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2),
 303         VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2),
 304         VMSTATE_UINT32(int_idle, PXA2xxPICState),
 305         VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS),
 306         VMSTATE_END_OF_LIST(),
 307     },
 308 };
 309
 310 static int pxa2xx_pic_initfn(SysBusDevice *dev)
 311 {
 312     return 0;
 313 }
 314
 315 static void pxa2xx_pic_class_init(ObjectClass *klass, void *data)
 316 {
 317     DeviceClass *dc = DEVICE_CLASS(klass);
 318     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 319
 320     k->init = pxa2xx_pic_initfn;
 321     dc->desc = "PXA2xx PIC";
 322     dc->vmsd = &vmstate_pxa2xx_pic_regs;
 323 }
 324
 325 static const TypeInfo pxa2xx_pic_info = {
 326     .name          = TYPE_PXA2XX_PIC,
 327     .parent        = TYPE_SYS_BUS_DEVICE,
 328     .instance_size = sizeof(PXA2xxPICState),
 329     .class_init    = pxa2xx_pic_class_init,
 330 };
 331
 332 static void pxa2xx_pic_register_types(void)
 333 {
 334     type_register_static(&pxa2xx_pic_info);
 335 }
 336
 337 type_init(pxa2xx_pic_register_types)